From 31736b4c8e0d37517b862021df181a9f93ae701b Mon Sep 17 00:00:00 2001 From: Mariya Podchishchaeva Date: Mon, 22 Nov 2021 11:11:17 +0300 Subject: [PATCH 1/4] [SYCL][FPGA] Update __builtin_intel_fpga_mem According to https://github.com/intel/llvm/pull/4980 this built-in should take four more constant integer parameters with following default values: ``` const int32_t AnchorID = -1 const int32_t TargetAnchor = 0 const int32_t Type = 0 const int32_t Cycle = 0 ``` The old variant is still allowed for backward compatibility. In case some parameters are not provided - default value will be emitted in annotation string. --- clang/lib/CodeGen/CGBuiltin.cpp | 27 +++++++++++++++-- clang/lib/Sema/SemaChecking.cpp | 26 +++++++++++++++-- .../CodeGenSYCL/intel-fpga-mem-builtin.cpp | 29 +++++++++++++++++-- .../test/SemaSYCL/intel-fpga-mem-builtin.cpp | 23 +++++++++++++-- 4 files changed, 95 insertions(+), 10 deletions(-) diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index a0de1bb01aac2..ede40d01b99a7 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -20402,6 +20402,7 @@ RValue CodeGenFunction::EmitIntelFPGAMemBuiltin(const CallExpr *E) { // Arguments const Expr *PtrArg = E->getArg(0); Value *PtrVal = EmitScalarExpr(PtrArg); + ASTContext &Ctx = getContext(); // Create the pointer annotation Function *F = @@ -20410,15 +20411,37 @@ RValue CodeGenFunction::EmitIntelFPGAMemBuiltin(const CallExpr *E) { llvm::raw_svector_ostream Out(AnnotStr); Optional Params = - E->getArg(1)->getIntegerConstantExpr(getContext()); + E->getArg(1)->getIntegerConstantExpr(Ctx); assert(Params.hasValue() && "Constant arg isn't actually constant?"); Out << "{params:" << toString(*Params, 10) << "}"; Optional CacheSize = - E->getArg(2)->getIntegerConstantExpr(getContext()); + E->getArg(2)->getIntegerConstantExpr(Ctx); assert(CacheSize.hasValue() && "Constant arg isn't actually constant?"); Out << "{cache-size:" << toString(*CacheSize, 10) << "}"; + // There is four optional arguments with following default values: + // const int32_t AnchorID = -1 + // const int32_t TargetAnchor = 0 + // const int32_t Type = 0 + // const int32_t Cycle = 0 + // Emit default values or use provided. + auto AddOptionalArgValue = [&E, &Ctx, &Out](int DefaultValue, + unsigned NumOfArg, + StringRef StringToAdd) { + Optional IntVal = + (E->getNumArgs() > NumOfArg) + ? E->getArg(NumOfArg)->getIntegerConstantExpr(Ctx) + : APSInt::get(DefaultValue); + assert(IntVal.hasValue() && "Constant arg isn't actually constant?"); + Out << "{" << StringToAdd << ":" << toString(*IntVal, 10) << "}"; + }; + + AddOptionalArgValue(-1, 3, "anchor-id"); + AddOptionalArgValue(0, 4, "target-anchor"); + AddOptionalArgValue(0, 5, "type"); + AddOptionalArgValue(0, 6, "cycle"); + llvm::Value *Ann = EmitAnnotationCall(F, PtrVal, AnnotStr, SourceLocation()); cast(Ann)->addFnAttr(llvm::Attribute::ReadNone); diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 5bed658c6d585..17864eea4faf6 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -4720,9 +4720,23 @@ bool Sema::CheckIntelFPGARegBuiltinFunctionCall(unsigned BuiltinID, } bool Sema::CheckIntelFPGAMemBuiltinFunctionCall(CallExpr *TheCall) { - // Make sure we have exactly 3 arguments - if (checkArgCount(*this, TheCall, 3)) - return true; + const unsigned MinNumArgs = 3; + const unsigned MaxNumArgs = 7; + unsigned NumArgs = TheCall->getNumArgs(); + + // Make sure we have minimum number of provided arguments. + if (NumArgs < MinNumArgs) + return Diag(TheCall->getEndLoc(), + diag::err_typecheck_call_too_few_args_at_least) + << 0 /* function call */ << MinNumArgs << NumArgs + << TheCall->getSourceRange(); + + // Make sure we don't have too many arguments. + if (NumArgs > MaxNumArgs) + return Diag(TheCall->getEndLoc(), + diag::err_typecheck_call_too_many_args_at_most) + << 0 /*function call*/ << MaxNumArgs << NumArgs + << TheCall->getSourceRange(); Expr *PointerArg = TheCall->getArg(0); QualType PointerArgType = PointerArg->getType(); @@ -4758,6 +4772,12 @@ bool Sema::CheckIntelFPGAMemBuiltinFunctionCall(CallExpr *TheCall) { return Diag(TheCall->getArg(2)->getBeginLoc(), diag::err_intel_fpga_mem_arg_mismatch) << 1; + // The last four optional arguments must be signed integers. + for (unsigned I = MinNumArgs; I != NumArgs; ++I) { + if (SemaBuiltinConstantArg(TheCall, I, Result)) + return true; + } + // Set the return type to be the same as the type of the first argument // (pointer argument) TheCall->setType(PointerArgType); diff --git a/clang/test/CodeGenSYCL/intel-fpga-mem-builtin.cpp b/clang/test/CodeGenSYCL/intel-fpga-mem-builtin.cpp index fe6833e189d6f..c3aad52f9181b 100644 --- a/clang/test/CodeGenSYCL/intel-fpga-mem-builtin.cpp +++ b/clang/test/CodeGenSYCL/intel-fpga-mem-builtin.cpp @@ -9,8 +9,13 @@ struct State { float y; }; -// CHECK: [[ANN1:@.str[\.]*[0-9]*]] = {{.*}}{params:384}{cache-size:0} -// CHECK: [[ANN2:@.str[\.]*[0-9]*]] = {{.*}}{params:384}{cache-size:127} +// CHECK: [[ANN1:@.str[\.]*[0-9]*]] = {{.*}}{params:384}{cache-size:0}{anchor-id:-1}{target-anchor:0}{type:0}{cycle:0} +// CHECK: [[ANN2:@.str[\.]*[0-9]*]] = {{.*}}{params:384}{cache-size:127}{anchor-id:-1}{target-anchor:0}{type:0}{cycle:0} +// CHECK: [[ANN3:@.str[\.]*[0-9]*]] = {{.*}}{params:384}{cache-size:127}{anchor-id:10}{target-anchor:20}{type:30}{cycle:40} +// CHECK: [[ANN4:@.str[\.]*[0-9]*]] = {{.*}}{params:384}{cache-size:127}{anchor-id:11}{target-anchor:12}{type:0}{cycle:0} +// CHECK: [[ANN5:@.str[\.]*[0-9]*]] = {{.*}}{params:384}{cache-size:127}{anchor-id:100}{target-anchor:0}{type:0}{cycle:0} +// CHECK: [[ANN6:@.str[\.]*[0-9]*]] = {{.*}}{params:384}{cache-size:128}{anchor-id:4}{target-anchor:5}{type:6}{cycle:0} + // CHECK: define {{.*}}spir_func void @{{.*}}(float addrspace(4)* %A, i32 addrspace(4)* %B, [[STRUCT]] addrspace(4)* %C, [[STRUCT]] addrspace(4)*{{.*}}%D) void foo(float *A, int *B, State *C, State &D) { @@ -65,6 +70,26 @@ void foo(float *A, int *B, State *C, State &D) { // CHECK-DAG: [[PTR8:%[0-9]+]] = call double addrspace(4)* @llvm.ptr.annotation{{.*}}[[F]]{{.*}}[[ANN2]]{{.*}}[[ATT:#[0-9]+]] // CHECK-DAG: store double addrspace(4)* [[PTR8]], double addrspace(4)* addrspace(4)* [[f]] f = __builtin_intel_fpga_mem(&F, PARAM_1 | PARAM_2, 127); + + // CHECK-DAG: [[A3:%[0-9]+]] = load float addrspace(4)*, float addrspace(4)* addrspace(4)* [[Aaddr]] + // CHECK-DAG: [[PTR9:%[0-9]+]] = call float addrspace(4)* @llvm.ptr.annotation{{.*}}[[A3]]{{.*}}[[ANN3]]{{.*}}[[ATT:#[0-9]+]] + // CHECK-DAG: store float addrspace(4)* [[PTR9]], float addrspace(4)* addrspace(4)* %x + x = __builtin_intel_fpga_mem(A, PARAM_1 | PARAM_2, 127, 10, 20, 30, 40); + + // CHECK-DAG: [[A4:%[0-9]+]] = load float addrspace(4)*, float addrspace(4)* addrspace(4)* [[Aaddr]] + // CHECK-DAG: [[PTR10:%[0-9]+]] = call float addrspace(4)* @llvm.ptr.annotation{{.*}}[[A4]]{{.*}}[[ANN4]]{{.*}}[[ATT:#[0-9]+]] + // CHECK-DAG: store float addrspace(4)* [[PTR10]], float addrspace(4)* addrspace(4)* %x + x = __builtin_intel_fpga_mem(A, PARAM_1 | PARAM_2, 127, 11, 12); + + // CHECK-DAG: [[B3:%[0-9]+]] = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(4)* [[Baddr]] + // CHECK-DAG: [[PTR11:%[0-9]+]] = call i32 addrspace(4)* @llvm.ptr.annotation{{.*}}[[B3]]{{.*}}[[ANN5]]{{.*}}[[ATT:#[0-9]+]] + // CHECK-DAG: store i32 addrspace(4)* [[PTR11]], i32 addrspace(4)* addrspace(4)* %y + y = __builtin_intel_fpga_mem(B, PARAM_1 | PARAM_2, 127, 100); + + // CHECK-DAG: [[D1:%[0-9]+]] = load [[STRUCT]] addrspace(4)*, [[STRUCT]] addrspace(4)* addrspace(4)* [[Daddr]] + // CHECK-DAG: [[PTR12:%[0-9]+]] = call [[STRUCT]] addrspace(4)* @llvm.ptr.annotation{{.*}}[[D1]]{{.*}}[[ANN6]]{{.*}}[[ATT:#[0-9]+]] + // CHECK-DAG: store [[STRUCT]] addrspace(4)* [[PTR12]], [[STRUCT]] addrspace(4)* addrspace(4)* %z + z = __builtin_intel_fpga_mem(&D, PARAM_1 | PARAM_2, 128, 4, 5, 6); } // CHECK-DAG: attributes [[ATT]] = { readnone } diff --git a/clang/test/SemaSYCL/intel-fpga-mem-builtin.cpp b/clang/test/SemaSYCL/intel-fpga-mem-builtin.cpp index 77d7ad6920865..1a9f3c43252b2 100644 --- a/clang/test/SemaSYCL/intel-fpga-mem-builtin.cpp +++ b/clang/test/SemaSYCL/intel-fpga-mem-builtin.cpp @@ -29,9 +29,7 @@ void foo(float *A, int *B, State *C) { x = __builtin_intel_fpga_mem(A, PARAM_1 | PARAM_2, -1); // expected-error@-1{{builtin parameter must be a non-negative integer constant}} x = __builtin_intel_fpga_mem(A, PARAM_1 | PARAM_2); - // expected-error@-1{{too few arguments to function call, expected 3, have 2}} - x = __builtin_intel_fpga_mem(A, PARAM_1 | PARAM_2, 1, 1); - // expected-error@-1{{too many arguments to function call, expected 3, have 4}} + // expected-error@-1{{too few arguments to function call, expected at least 3, have 2}} y = __builtin_intel_fpga_mem(B, 0, i); // expected-error@-1{{argument to '__builtin_intel_fpga_mem' must be a constant integer}} z = __builtin_intel_fpga_mem(C, i, 0); @@ -53,6 +51,25 @@ void foo(float *A, int *B, State *C) { struct outer *iii; struct outer *iv = __builtin_intel_fpga_mem(iii, 0, 0); // expected-error@-1{{illegal field in type pointed to by pointer argument to __builtin_intel_fpga_mem; only pointers to a first class lvalue or to an rvalue are allowed}} + + // Up to 7 parameters is ok. + x = __builtin_intel_fpga_mem(A, PARAM_1 | PARAM_2, 1, 1); + x = __builtin_intel_fpga_mem(A, PARAM_1 | PARAM_2, 1, 1, 10); + x = __builtin_intel_fpga_mem(A, PARAM_1 | PARAM_2, 1, 1, 10, 20); + x = __builtin_intel_fpga_mem(A, PARAM_1 | PARAM_2, 1, 1, -1, 10, 20); + + z = __builtin_intel_fpga_mem(A, PARAM_1 | PARAM_2, 1, B, -1, 1, 1); + // expected-error@-1{{argument to '__builtin_intel_fpga_mem' must be a constant integer}} + z = __builtin_intel_fpga_mem(A, PARAM_1 | PARAM_2, 1, 1, U, 10, 20); + // expected-error@-1{{argument to '__builtin_intel_fpga_mem' must be a constant integer}} + z = __builtin_intel_fpga_mem(A, PARAM_1 | PARAM_2, 1, 1, -1, C, 300); + // expected-error@-1{{argument to '__builtin_intel_fpga_mem' must be a constant integer}} + z = __builtin_intel_fpga_mem(A, PARAM_1 | PARAM_2, 1, 1, -1, 1, i); + // expected-error@-1{{argument to '__builtin_intel_fpga_mem' must be a constant integer}} + + y = __builtin_intel_fpga_mem(A, PARAM_1 | PARAM_2, 1, 1, -1, 10, 20, 30); + // expected-error@-1{{too many arguments to function call, expected at most 7, have 8}} + } template From 4ba6244e0deb3a96a08c20b22fec2bf087dcba70 Mon Sep 17 00:00:00 2001 From: Mariya Podchishchaeva Date: Tue, 23 Nov 2021 16:22:58 +0300 Subject: [PATCH 2/4] Apply clang-format --- clang/lib/CodeGen/CGBuiltin.cpp | 6 ++---- clang/test/CodeGenSYCL/intel-fpga-mem-builtin.cpp | 1 - clang/test/SemaSYCL/intel-fpga-mem-builtin.cpp | 1 - 3 files changed, 2 insertions(+), 6 deletions(-) diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index ede40d01b99a7..da264cae8164b 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -20410,13 +20410,11 @@ RValue CodeGenFunction::EmitIntelFPGAMemBuiltin(const CallExpr *E) { SmallString<256> AnnotStr; llvm::raw_svector_ostream Out(AnnotStr); - Optional Params = - E->getArg(1)->getIntegerConstantExpr(Ctx); + Optional Params = E->getArg(1)->getIntegerConstantExpr(Ctx); assert(Params.hasValue() && "Constant arg isn't actually constant?"); Out << "{params:" << toString(*Params, 10) << "}"; - Optional CacheSize = - E->getArg(2)->getIntegerConstantExpr(Ctx); + Optional CacheSize = E->getArg(2)->getIntegerConstantExpr(Ctx); assert(CacheSize.hasValue() && "Constant arg isn't actually constant?"); Out << "{cache-size:" << toString(*CacheSize, 10) << "}"; diff --git a/clang/test/CodeGenSYCL/intel-fpga-mem-builtin.cpp b/clang/test/CodeGenSYCL/intel-fpga-mem-builtin.cpp index c3aad52f9181b..779a84c7e55a0 100644 --- a/clang/test/CodeGenSYCL/intel-fpga-mem-builtin.cpp +++ b/clang/test/CodeGenSYCL/intel-fpga-mem-builtin.cpp @@ -16,7 +16,6 @@ struct State { // CHECK: [[ANN5:@.str[\.]*[0-9]*]] = {{.*}}{params:384}{cache-size:127}{anchor-id:100}{target-anchor:0}{type:0}{cycle:0} // CHECK: [[ANN6:@.str[\.]*[0-9]*]] = {{.*}}{params:384}{cache-size:128}{anchor-id:4}{target-anchor:5}{type:6}{cycle:0} - // CHECK: define {{.*}}spir_func void @{{.*}}(float addrspace(4)* %A, i32 addrspace(4)* %B, [[STRUCT]] addrspace(4)* %C, [[STRUCT]] addrspace(4)*{{.*}}%D) void foo(float *A, int *B, State *C, State &D) { float *x; diff --git a/clang/test/SemaSYCL/intel-fpga-mem-builtin.cpp b/clang/test/SemaSYCL/intel-fpga-mem-builtin.cpp index 1a9f3c43252b2..0f543019897e8 100644 --- a/clang/test/SemaSYCL/intel-fpga-mem-builtin.cpp +++ b/clang/test/SemaSYCL/intel-fpga-mem-builtin.cpp @@ -69,7 +69,6 @@ void foo(float *A, int *B, State *C) { y = __builtin_intel_fpga_mem(A, PARAM_1 | PARAM_2, 1, 1, -1, 10, 20, 30); // expected-error@-1{{too many arguments to function call, expected at most 7, have 8}} - } template From 6136f23c7000a6a6359e86d2f9fb110391bb1cbc Mon Sep 17 00:00:00 2001 From: Mariya Podchishchaeva Date: Tue, 30 Nov 2021 16:58:22 +0300 Subject: [PATCH 3/4] Apply CR suggestions --- clang/lib/CodeGen/CGBuiltin.cpp | 2 +- clang/lib/Sema/SemaChecking.cpp | 4 ++-- clang/test/CodeGenSYCL/intel-fpga-mem-builtin.cpp | 10 ++++++++-- clang/test/SemaSYCL/intel-fpga-mem-builtin.cpp | 3 +++ 4 files changed, 14 insertions(+), 5 deletions(-) diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index c356c3130180b..d0e7516343032 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -20465,7 +20465,7 @@ RValue CodeGenFunction::EmitIntelFPGAMemBuiltin(const CallExpr *E) { assert(CacheSize.hasValue() && "Constant arg isn't actually constant?"); Out << "{cache-size:" << toString(*CacheSize, 10) << "}"; - // There is four optional arguments with following default values: + // There are four optional arguments with the following default values: // const int32_t AnchorID = -1 // const int32_t TargetAnchor = 0 // const int32_t Type = 0 diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 84cd443d4d3c9..f87c1778ec444 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -4863,7 +4863,7 @@ bool Sema::CheckIntelFPGAMemBuiltinFunctionCall(CallExpr *TheCall) { const unsigned MaxNumArgs = 7; unsigned NumArgs = TheCall->getNumArgs(); - // Make sure we have minimum number of provided arguments. + // Make sure we have the minimum number of provided arguments. if (NumArgs < MinNumArgs) return Diag(TheCall->getEndLoc(), diag::err_typecheck_call_too_few_args_at_least) @@ -4911,7 +4911,7 @@ bool Sema::CheckIntelFPGAMemBuiltinFunctionCall(CallExpr *TheCall) { return Diag(TheCall->getArg(2)->getBeginLoc(), diag::err_intel_fpga_mem_arg_mismatch) << 1; - // The last four optional arguments must be signed integers. + // The last four optional arguments must be signed constant integers. for (unsigned I = MinNumArgs; I != NumArgs; ++I) { if (SemaBuiltinConstantArg(TheCall, I, Result)) return true; diff --git a/clang/test/CodeGenSYCL/intel-fpga-mem-builtin.cpp b/clang/test/CodeGenSYCL/intel-fpga-mem-builtin.cpp index 779a84c7e55a0..8670ed6c7fc54 100644 --- a/clang/test/CodeGenSYCL/intel-fpga-mem-builtin.cpp +++ b/clang/test/CodeGenSYCL/intel-fpga-mem-builtin.cpp @@ -3,6 +3,9 @@ #define PARAM_1 1U << 7 #define PARAM_2 1U << 8 +// This test checks that using of __builtin_intel_fpga_mem results in correct +// generation of annotations in LLVM IR. + // CHECK: [[STRUCT:%.*]] = type { i32, float } struct State { int x; @@ -14,7 +17,7 @@ struct State { // CHECK: [[ANN3:@.str[\.]*[0-9]*]] = {{.*}}{params:384}{cache-size:127}{anchor-id:10}{target-anchor:20}{type:30}{cycle:40} // CHECK: [[ANN4:@.str[\.]*[0-9]*]] = {{.*}}{params:384}{cache-size:127}{anchor-id:11}{target-anchor:12}{type:0}{cycle:0} // CHECK: [[ANN5:@.str[\.]*[0-9]*]] = {{.*}}{params:384}{cache-size:127}{anchor-id:100}{target-anchor:0}{type:0}{cycle:0} -// CHECK: [[ANN6:@.str[\.]*[0-9]*]] = {{.*}}{params:384}{cache-size:128}{anchor-id:4}{target-anchor:5}{type:6}{cycle:0} +// CHECK: [[ANN6:@.str[\.]*[0-9]*]] = {{.*}}{params:384}{cache-size:128}{anchor-id:4}{target-anchor:7}{type:8}{cycle:0} // CHECK: define {{.*}}spir_func void @{{.*}}(float addrspace(4)* %A, i32 addrspace(4)* %B, [[STRUCT]] addrspace(4)* %C, [[STRUCT]] addrspace(4)*{{.*}}%D) void foo(float *A, int *B, State *C, State &D) { @@ -85,10 +88,13 @@ void foo(float *A, int *B, State *C, State &D) { // CHECK-DAG: store i32 addrspace(4)* [[PTR11]], i32 addrspace(4)* addrspace(4)* %y y = __builtin_intel_fpga_mem(B, PARAM_1 | PARAM_2, 127, 100); + constexpr TestVal1 = 7; + constexpr TestVal2 = 8; + // CHECK-DAG: [[D1:%[0-9]+]] = load [[STRUCT]] addrspace(4)*, [[STRUCT]] addrspace(4)* addrspace(4)* [[Daddr]] // CHECK-DAG: [[PTR12:%[0-9]+]] = call [[STRUCT]] addrspace(4)* @llvm.ptr.annotation{{.*}}[[D1]]{{.*}}[[ANN6]]{{.*}}[[ATT:#[0-9]+]] // CHECK-DAG: store [[STRUCT]] addrspace(4)* [[PTR12]], [[STRUCT]] addrspace(4)* addrspace(4)* %z - z = __builtin_intel_fpga_mem(&D, PARAM_1 | PARAM_2, 128, 4, 5, 6); + z = __builtin_intel_fpga_mem(&D, PARAM_1 | PARAM_2, 128, 4, TestVal1, TestVal2); } // CHECK-DAG: attributes [[ATT]] = { readnone } diff --git a/clang/test/SemaSYCL/intel-fpga-mem-builtin.cpp b/clang/test/SemaSYCL/intel-fpga-mem-builtin.cpp index 0f543019897e8..11afe6fc20989 100644 --- a/clang/test/SemaSYCL/intel-fpga-mem-builtin.cpp +++ b/clang/test/SemaSYCL/intel-fpga-mem-builtin.cpp @@ -4,6 +4,9 @@ #define PARAM_1 1U << 7 #define PARAM_2 1U << 8 +// This test makes sure that the compiler checks the semantics of +// __builtin_intel_fpga_mem built-in function arguments correctly. + #ifdef __SYCL_DEVICE_ONLY__ static_assert(__has_builtin(__builtin_intel_fpga_mem), ""); struct State { From 591695017907743d1998527c641c6b8047d81f5f Mon Sep 17 00:00:00 2001 From: Mariya Podchishchaeva Date: Tue, 30 Nov 2021 19:36:07 +0300 Subject: [PATCH 4/4] Fix tests --- clang/test/CodeGenSYCL/intel-fpga-mem-builtin.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/clang/test/CodeGenSYCL/intel-fpga-mem-builtin.cpp b/clang/test/CodeGenSYCL/intel-fpga-mem-builtin.cpp index 8670ed6c7fc54..3cd793c19f482 100644 --- a/clang/test/CodeGenSYCL/intel-fpga-mem-builtin.cpp +++ b/clang/test/CodeGenSYCL/intel-fpga-mem-builtin.cpp @@ -88,8 +88,8 @@ void foo(float *A, int *B, State *C, State &D) { // CHECK-DAG: store i32 addrspace(4)* [[PTR11]], i32 addrspace(4)* addrspace(4)* %y y = __builtin_intel_fpga_mem(B, PARAM_1 | PARAM_2, 127, 100); - constexpr TestVal1 = 7; - constexpr TestVal2 = 8; + constexpr int TestVal1 = 7; + constexpr int TestVal2 = 8; // CHECK-DAG: [[D1:%[0-9]+]] = load [[STRUCT]] addrspace(4)*, [[STRUCT]] addrspace(4)* addrspace(4)* [[Daddr]] // CHECK-DAG: [[PTR12:%[0-9]+]] = call [[STRUCT]] addrspace(4)* @llvm.ptr.annotation{{.*}}[[D1]]{{.*}}[[ANN6]]{{.*}}[[ATT:#[0-9]+]]