From 05e4fa392d239b6f6fb52c3b4daca5fc11102191 Mon Sep 17 00:00:00 2001
From: Max Korbel <max.korbel@intel.com>
Date: Mon, 9 Sep 2024 17:11:38 -0700
Subject: [PATCH] Add tests that configurator modules build (#88)

---
 .pubignore                  |  2 ++
 README.md                   |  2 +-
 doc/README.md               |  4 ++--
 test/configurator_test.dart | 24 ++++++++++++++++++++++++
 4 files changed, 29 insertions(+), 3 deletions(-)

diff --git a/.pubignore b/.pubignore
index 7e2fe825..025146a4 100644
--- a/.pubignore
+++ b/.pubignore
@@ -16,6 +16,8 @@ tmp*
 *.vcd
 .vscode/*
 confapp/.vscode/*
+*tracker.json
+*tracker.log
 
 # Exceptions
 !.vscode/extensions.json
diff --git a/README.md b/README.md
index de8710db..9e99a033 100644
--- a/README.md
+++ b/README.md
@@ -9,7 +9,7 @@
 
 # ROHD Hardware Component Libary
 
-A hardware component library developed with [ROHD](https://github.com/intel/rohd). This library aims to collect a set of reusable, configurable components that can be leveraged in other designs. These components are also intended as good examples of ROHD hardware implementations.
+A hardware component library developed with [ROHD](https://intel.github.io/rohd-website/). This library aims to collect a set of reusable, configurable components that can be leveraged in other designs. These components are also intended as good examples of ROHD hardware implementations.
 
 Check out the [generator web app](https://intel.github.io/rohd-hcl/confapp/), which lets you explore some of the available components, configure them, and generate SystemVerilog.
 
diff --git a/doc/README.md b/doc/README.md
index 1ea46548..6796bda2 100644
--- a/doc/README.md
+++ b/doc/README.md
@@ -8,8 +8,8 @@ Some in-development items will have opened issues, as well. Feel free to create
 - Encoders & Decoders
   - [1-hot to Binary](./components/onehot.md)
   - [Binary to 1-hot](./components/onehot.md)
-  - Gray to Binary
-  - Binary to Gray
+  - [Binary to Gray](./components/binary_gray.md#binary-to-gray)
+  - [Gray to Binary](./components/binary_gray.md#gray-to-binary)
   - Priority
   - PLAs
 - Arbiters
diff --git a/test/configurator_test.dart b/test/configurator_test.dart
index 4a4c2328..01316bf4 100644
--- a/test/configurator_test.dart
+++ b/test/configurator_test.dart
@@ -6,11 +6,21 @@
 //
 // 2023 December 6
 
+import 'package:rohd/rohd.dart';
 import 'package:rohd_hcl/rohd_hcl.dart';
+import 'package:rohd_hcl/src/component_config/components/component_registry.dart';
 import 'package:test/test.dart';
 
 import '../confapp/test/example_component.dart';
 
+/// A module that just wraps a hierarchy around a given module.
+class Wrapper extends Module {
+  Wrapper(Module m) {
+    final mOut = m.outputs.values.first;
+    addOutput('dummy', width: mOut.width) <= mOut;
+  }
+}
+
 void main() {
   test('to and from json', () {
     final cfg = ExampleConfigurator();
@@ -274,4 +284,18 @@ void main() {
     final sv = await cfg.generateSV();
     expect(sv, contains('swizzle'));
   });
+
+  group('configurator builds', () {
+    for (final componentConfigurator in componentRegistry) {
+      test(componentConfigurator.name, () async {
+        // generates verilog stand-alone
+        await componentConfigurator.generateSV();
+
+        // generates within a wrapping module (check for input/output rules)
+        final mod = Wrapper(componentConfigurator.createModule());
+        await mod.build();
+        mod.generateSynth();
+      });
+    }
+  });
 }