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PCIe: add flit mode support
Signed-off-by: Aaron Li <aaron.li@intel.com>
1 parent 1a070ca commit 24fa716

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3 files changed

+191
-3
lines changed

3 files changed

+191
-3
lines changed

‎teeio-validator/include/pcie.h‎

Lines changed: 112 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/**
22
* Copyright Notice:
3-
* Copyright 2023-2024 Intel. All rights reserved.
3+
* Copyright 2023-2025 Intel. All rights reserved.
44
* License: BSD 3-Clause License.
55
**/
66

@@ -224,6 +224,115 @@ typedef struct
224224
// PCIE_SEL_IDE_STREAM_REG_BLOCK sel_ide_stream_block; // number of elements is dynamic
225225
} PCIE_IDE_ECAP;
226226

227+
// 7.5.3.1 PCI Express Capability List Register (Offset 00h)
228+
typedef union
229+
{
230+
struct
231+
{
232+
uint8_t id;
233+
uint8_t next_cap_offset;
234+
};
235+
uint16_t raw;
236+
} PCIE_CAP_LIST;
237+
238+
// 7.5.3.2 PCI Express Capabilities Register (Offset 02h)
239+
typedef union
240+
{
241+
struct
242+
{
243+
uint16_t cap_version : 4;
244+
uint16_t dev_port_type : 4;
245+
uint16_t slot_impl : 1;
246+
uint16_t interrupt_msg_number : 5;
247+
uint16_t undefined : 1;
248+
uint16_t flit_mode_supported : 1;
249+
};
250+
uint16_t raw;
251+
} PCIE_CAP;
252+
253+
// 7.5.3.6 Link Capabilities Register (Offset 0Ch)
254+
typedef union
255+
{
256+
struct
257+
{
258+
uint32_t max_link_speed : 4;
259+
uint32_t max_link_width : 6;
260+
uint32_t aspm_support : 2;
261+
uint32_t l0s_exit_latency : 3;
262+
uint32_t l1_exit_latency : 3;
263+
uint32_t clock_power_management : 1;
264+
uint32_t surprise_down_error_reporting : 1;
265+
uint32_t dll_active_reporting : 1;
266+
uint32_t link_bandwidth_notification : 1;
267+
uint32_t aspm_optionality : 1;
268+
uint32_t rsvd : 1;
269+
uint32_t port_number : 8;
270+
};
271+
uint32_t raw;
272+
} PCIE_LINK_CAP;
273+
274+
// 7.5.3.7 Link Control Register (Offset 10h)
275+
typedef union
276+
{
277+
struct
278+
{
279+
uint16_t aspm_control : 2;
280+
uint16_t ptm_propagation_delay_adaption_interpretation_b : 1;
281+
uint16_t read_completion_boundary : 1;
282+
uint16_t link_disable : 1;
283+
uint16_t retrain_link : 1;
284+
uint16_t common_clock_config : 1;
285+
uint16_t extended_synch : 1;
286+
uint16_t enable_clock_power_management : 1;
287+
uint16_t hardware_autonomous_width_disable : 1;
288+
uint16_t link_bandwidth_management_interrupt_enable : 1;
289+
uint16_t link_autonomous_bandwidth_interrupt_enable : 1;
290+
uint16_t sris_clocking : 1;
291+
uint16_t flit_mode_disable : 1;
292+
uint16_t drs_signaling_control : 2;
293+
};
294+
uint16_t raw;
295+
} PCIE_LINK_CTRL;
296+
297+
// 7.5.3.8 Link Status Register (Offset 12h)
298+
typedef union
299+
{
300+
struct
301+
{
302+
uint16_t current_link_speed : 4;
303+
uint16_t negotiated_link_width : 6;
304+
uint16_t undefined : 1;
305+
uint16_t link_training : 1;
306+
uint16_t slot_clock_config : 1;
307+
uint16_t data_link_layer_active : 1;
308+
uint16_t link_bandwidth_management_status : 1;
309+
uint16_t link_autonomous_bandwidth_status : 1;
310+
};
311+
uint16_t raw;
312+
} PCIE_LINK_STATUS;
313+
314+
// 7.5.3.20 Link Status 2 Register (Offset 32h)
315+
typedef union
316+
{
317+
struct
318+
{
319+
uint16_t current_deemphasis_level : 1;
320+
uint16_t equalization_8gt_complete : 1;
321+
uint16_t equalization_8gt_phase1_successful : 1;
322+
uint16_t equalization_8gt_phase2_successful : 1;
323+
uint16_t equalization_8gt_phase3_successful : 1;
324+
uint16_t link_equalization_request_8gt : 1;
325+
uint16_t retimer_presence_detected : 1;
326+
uint16_t two_retimers_presence_detected : 1;
327+
uint16_t crosslink_resolution : 2;
328+
uint16_t flit_mode_status : 1;
329+
uint16_t rsvdz : 1;
330+
uint16_t downstream_component_presence : 3;
331+
uint16_t drs_message_received : 1;
332+
};
333+
uint16_t raw;
334+
} PCIE_LINK_STATUS2;
335+
227336
#pragma pack(0)
228337

229338
// 6.33.3 IDE Key Management
@@ -272,6 +381,8 @@ enum PCIE_IDE_STREAM_KEY_SUB_STREAM_ENUM {
272381
#define IDE_STREAM_STATUS_SECURE 2
273382
#define IDE_STREAM_STATUS_INSECURE 0
274383

384+
#define PCIE_CAPABILITY_ID 0x10
385+
275386
#define PCIE_CONFIG_SPACE_SIZE 0x1000
276387
#define PCIE_EXT_CAP_START 0x100
277388

‎teeio-validator/include/pcie_ide_lib.h‎

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/**
22
* Copyright Notice:
3-
* Copyright 2024 Intel. All rights reserved.
3+
* Copyright 2024-2025 Intel. All rights reserved.
44
* License: BSD 3-Clause License.
55
**/
66

@@ -20,6 +20,11 @@
2020
*/
2121
int open_configuration_space(char *bdf);
2222

23+
/**
24+
* get offset of cap in cap list
25+
*/
26+
uint32_t get_cap_offset(int fd, uint32_t cap_id);
27+
2328
/**
2429
* get offset of ext in ecap
2530
*/
@@ -40,6 +45,11 @@ bool scan_devices_at_bus(
4045
ide_common_test_switch_internal_conn_context_t* conn,
4146
uint8_t bus);
4247

48+
/**
49+
* Check if the PCIE Flit Mode is enabled on the given port context
50+
*/
51+
bool pcie_check_flit_mode_enabled(ide_common_test_port_context_t *port_context);
52+
4353
/**
4454
* Initialize rootcomplex port
4555
* root_port and upper_port is the same port

‎teeio-validator/library/pcie_ide_lib/pcie_ide.c‎

Lines changed: 68 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/**
22
* Copyright Notice:
3-
* Copyright 2023-2024 Intel. All rights reserved.
3+
* Copyright 2023-2025 Intel. All rights reserved.
44
* License: BSD 3-Clause License.
55
*/
66

@@ -103,6 +103,41 @@ int open_configuration_space(char *bdf)
103103
return fd;
104104
}
105105

106+
107+
uint32_t get_cap_offset(int fd, uint32_t cap_id)
108+
{
109+
uint32_t walker = 0;
110+
uint32_t cap_header = 0;
111+
uint32_t offset = 0;
112+
113+
// get capability start from Type 0/1 header
114+
uint16_t data16;
115+
data16 = device_pci_read_16(0x34, fd);
116+
walker = data16 & 0xFF; // CAPABILITY_POINTER
117+
118+
if (cap_id != PCIE_CAPABILITY_ID)
119+
{
120+
TEEIO_DEBUG((TEEIO_DEBUG_ERROR, "Not supported cap id: 0x%x\n", cap_id));
121+
return 0;
122+
}
123+
124+
while (walker < PCIE_EXT_CAP_START && walker != 0)
125+
{
126+
cap_header = device_pci_read_32(walker, fd);
127+
128+
if (((PCIE_CAP_LIST *)&cap_header)->id == cap_id)
129+
{
130+
offset = walker;
131+
break;
132+
}
133+
134+
walker = ((PCIE_CAP_LIST *)&cap_header)->next_cap_offset;
135+
}
136+
137+
return offset;
138+
}
139+
140+
106141
uint32_t get_extended_cap_offset(int fd, uint32_t ext_id)
107142
{
108143
uint32_t ext_cap_start = 0x100; // defined by PCIe Specification
@@ -476,6 +511,38 @@ bool find_free_rp_stream_index_and_ide_id(ide_common_test_port_context_t* port_c
476511
return true;
477512
}
478513

514+
// Check if the PCIE Flit Mode is enabled on the given port context
515+
bool pcie_check_flit_mode_enabled(ide_common_test_port_context_t *port_context)
516+
{
517+
int fd = port_context->cfg_space_fd;
518+
uint32_t pcie_cap_offset = get_cap_offset(fd, PCIE_CAPABILITY_ID);
519+
uint32_t offset;
520+
521+
TEEIO_DEBUG((TEEIO_DEBUG_INFO, "%s: PCIE Capability Offset: 0x%02x\n", port_context->port->bdf, pcie_cap_offset));
522+
offset = pcie_cap_offset + 0x02;
523+
PCIE_CAP pcie_cap;
524+
pcie_cap.raw = device_pci_read_16(offset, fd);
525+
TEEIO_DEBUG((TEEIO_DEBUG_INFO, "%s: PCIE Capability: 0x%04x\n", port_context->port->bdf, pcie_cap));
526+
if (pcie_cap.flit_mode_supported) {
527+
TEEIO_DEBUG((TEEIO_DEBUG_INFO, "%s: PCIE Flit Mode Supported\n", port_context->port->bdf));
528+
} else {
529+
TEEIO_DEBUG((TEEIO_DEBUG_INFO, "%s: PCIE Flit Mode Not Supported\n", port_context->port->bdf));
530+
return false;
531+
}
532+
533+
offset = pcie_cap_offset + 0x32;
534+
PCIE_LINK_STATUS2 pcie_link_status2;
535+
pcie_link_status2.raw = device_pci_read_16(offset, fd);
536+
TEEIO_DEBUG((TEEIO_DEBUG_INFO, "%s: PCIE Link Status2: 0x%04x\n", port_context->port->bdf, pcie_link_status2.raw));
537+
if (pcie_link_status2.flit_mode_status) {
538+
TEEIO_DEBUG((TEEIO_DEBUG_INFO, "%s: PCIE Flit Mode Enabled\n", port_context->port->bdf));
539+
return true;
540+
} else {
541+
TEEIO_DEBUG((TEEIO_DEBUG_INFO, "%s: PCIE Flit Mode Not Enabled\n", port_context->port->bdf));
542+
return false;
543+
}
544+
}
545+
479546
bool populate_rid_assoc_reg_block(
480547
PCIE_SEL_IDE_RID_ASSOC_REG_BLOCK *rid_assoc_reg_block,
481548
uint8_t bus, uint8_t device, uint8_t func)

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