diff --git a/docs/website/docs/community/blog/posts/linalg-tutorial.md b/docs/website/docs/community/blog/posts/linalg-tutorial.md
index 3548ecb5ef4c..281b9143f564 100644
--- a/docs/website/docs/community/blog/posts/linalg-tutorial.md
+++ b/docs/website/docs/community/blog/posts/linalg-tutorial.md
@@ -185,12 +185,12 @@ iree-compile --iree-hal-target-backends=llvm-cpu prog.mlir -o /tmp/prog.vmfb
       `--device=` to `iree-run-module` below.
     * To cross-compile, explore `--iree-llvmcpu-target-triple=`.
     * To enable higher CPU performance by enabling CPU features:
-      * On x86, explore `--iree-llvmcpu-target-cpu=` (e.g.
-        `--iree-llvmcpu-target-cpu=znver4` to target AMD Zen4).
-      * On other architectures, explore `--iree-llvmcpu-target-cpu-features=`.
-      * To optimize for running on the same machine that the compilation ran
-        on, pass  `--iree-llvmcpu-target-cpu=host`. That works regardless of
-        CPU architecture.
+        * On x86, explore `--iree-llvmcpu-target-cpu=` (e.g.
+          `--iree-llvmcpu-target-cpu=znver4` to target AMD Zen4).
+        * On other architectures, explore `--iree-llvmcpu-target-cpu-features=`.
+        * To optimize for running on the same machine that the compilation ran
+          on, pass  `--iree-llvmcpu-target-cpu=host`. That works regardless of
+          CPU architecture.
     * Check out
       [these docs](../../../developers/general/developer-tips.md) for
       more useful `iree-compile` flags.
diff --git a/docs/website/docs/community/blog/posts/microkernels.md b/docs/website/docs/community/blog/posts/microkernels.md
index 1bbcb91e416b..f56b71303db9 100644
--- a/docs/website/docs/community/blog/posts/microkernels.md
+++ b/docs/website/docs/community/blog/posts/microkernels.md
@@ -152,6 +152,10 @@ subgraph Part3["Part 3: Linking with microkernels, optimizing, producing object
   object
   vmfb
 end
+
+style Part1 stroke:#FDD835,stroke-width:2px
+style Part2 stroke:#039BE5,stroke-width:2px
+style Part3 stroke:#43A047,stroke-width:2px
 ```
 
 ## 🟨 Part 1: MLIR code generation