diff --git a/.github/ISSUE_TEMPLATE.md b/.github/ISSUE_TEMPLATE.md deleted file mode 100644 index e6877ba7dd509d..00000000000000 --- a/.github/ISSUE_TEMPLATE.md +++ /dev/null @@ -1,20 +0,0 @@ -反馈bug/问题模板，提建议请删除 - -## 1.关于你要提交的问题 - -Q：是否搜索了issue (使用 "x" 选择) -* [ ] 没有类似的issue - -## 2. 详细叙述 - -### (1) 具体问题 - -A： - -### (2) 路由器型号和固件版本 - -A： - -### (3) 详细日志 - -A： diff --git a/.github/ISSUE_TEMPLATE/bug-report.yml b/.github/ISSUE_TEMPLATE/bug-report.yml new file mode 100644 index 00000000000000..7375f5511c4a13 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/bug-report.yml @@ -0,0 +1,32 @@ +name: 问题描述 +description: 反馈问题模板 +body: + - type: textarea + id: description + attributes: + label: 详细叙述 + description: 详细叙述问题 + validations: + required: true + - type: checkboxes + id: duplicate_issue + attributes: + label: 重复 issue + description: 是否搜索了 issues + options: + - label: 没有类似的 issue + required: true + - type: input + id: model_name + attributes: + label: 具体型号 + description: 硬件型号 + validations: + required: true + - type: textarea + id: details_log + attributes: + label: 详细日志 + description: make V=s -j1 时的问题日志 + validations: + required: true diff --git a/.github/ISSUE_TEMPLATE/config.yml b/.github/ISSUE_TEMPLATE/config.yml new file mode 100644 index 00000000000000..9dd2f5671a5044 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/config.yml @@ -0,0 +1,6 @@ +--- +blank_issues_enabled: false +contact_links: + - name: discussion + url: https://github.com/coolsnowwolf/lede/discussions + about: Please ask and answer questions here. diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md index b9b4232d7c773e..3f000a7666d3b8 100644 --- a/.github/PULL_REQUEST_TEMPLATE.md +++ b/.github/PULL_REQUEST_TEMPLATE.md @@ -1,2 +1,4 @@ -Q：你知道这是`pull request`吗？(使用 "x" 选择) -* [ ] 我知道 +# Pull Request 规则，创建时请删除 + +- 禁止有关 "GitHub Actions" 的提交 +- 禁止使用 users.noreply.github.com 提交 diff --git a/README.md b/README.md index 765aa066faffd3..985e7c8f1b98dc 100644 --- a/README.md +++ b/README.md @@ -1,9 +1,11 @@ # 欢迎来到 Lean 的 LEDE 源码仓库 -I18N: [English](README_EN.md) | [简体中文](README.md) +I18N: [English](README_EN.md) | [简体中文](README.md) | [日本語](README_JA.md) ## 官方讨论群 + 如有技术问题需要讨论或者交流，欢迎加入以下群： + 1. QQ 讨论群： Op固件技术研究群 ,号码 891659613 ，加群链接：[点击加入](https://jq.qq.com/?_wv=1027&k=XL8SK5aC "Op固件技术研究群") 2. TG 讨论群： OP 编译官方大群 ，加群链接：[点击加入](https://t.me/JhKgAA6Hx1 "OP 编译官方大群") @@ -15,7 +17,6 @@ I18N: [English](README_EN.md) | [简体中文](README.md) [![r1](doc/r1.jpg)](https://item.taobao.com/item.htm?id=721197662185) - ## 注意 1. **不要用 root 用户进行编译** @@ -33,11 +34,11 @@ I18N: [English](README_EN.md) | [简体中文](README.md) sudo apt full-upgrade -y sudo apt install -y ack antlr3 asciidoc autoconf automake autopoint binutils bison build-essential \ bzip2 ccache cmake cpio curl device-tree-compiler fastjar flex gawk gettext gcc-multilib g++-multilib \ - git gperf haveged help2man intltool libc6-dev-i386 libelf-dev libglib2.0-dev libgmp3-dev libltdl-dev \ - libmpc-dev libmpfr-dev libncurses5-dev libncursesw5-dev libreadline-dev libssl-dev libtool lrzsz \ - mkisofs msmtp nano ninja-build p7zip p7zip-full patch pkgconf python2.7 python3 python3-pyelftools \ - libpython3-dev qemu-utils rsync scons squashfs-tools subversion swig texinfo uglifyjs upx-ucl unzip \ - vim wget xmlto xxd zlib1g-dev python3-setuptools + git gperf haveged help2man intltool libc6-dev-i386 libelf-dev libfuse-dev libglib2.0-dev libgmp3-dev \ + libltdl-dev libmpc-dev libmpfr-dev libncurses5-dev libncursesw5-dev libpython3-dev libreadline-dev \ + libssl-dev libtool lrzsz mkisofs msmtp ninja-build p7zip p7zip-full patch pkgconf python2.7 python3 \ + python3-pyelftools python3-setuptools qemu-utils rsync scons squashfs-tools subversion swig texinfo \ + uglifyjs upx-ucl unzip vim wget xmlto xxd zlib1g-dev ``` 3. 下载源代码，更新 feeds 并选择配置 @@ -77,14 +78,14 @@ make V=s -j$(nproc) 如果需要重新配置： ```bash -rm -rf ./tmp && rm -rf .config +rm -rf .config make menuconfig make V=s -j$(nproc) ``` 编译完成后输出路径：bin/targets -### 如果你使用 WSL/WSL2 进行编译 +### 使用 WSL/WSL2 进行编译 由于 WSL 的 PATH 中包含带有空格的 Windows 路径，有可能会导致编译失败，请在 `make` 前面加上： @@ -95,7 +96,7 @@ PATH=/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin 由于默认情况下，装载到 WSL 发行版的 NTFS 格式的驱动器将不区分大小写，因此大概率在 WSL/WSL2 的编译检查中会返回以下错误： ```txt -Build dependency: OpenWrt can only be built on a case-sensitive filesystem +Build dependency: OpenWrt can only be built on a case-sensitive filesystem ``` 一个比较简洁的解决方法是，在 `git clone` 前先创建 Repository 目录，并为其启用大小写敏感： @@ -152,8 +153,6 @@ PS > git clone git@github.com:coolsnowwolf/lede.git 4. 存档版本仓库地址： - - ## 捐贈 如果你觉得此项目对你有帮助，可以捐助我们，以鼓励项目能持续发展，更加完善 diff --git a/README_EN.md b/README_EN.md index 32e32921d383dc..9705f50edbf96c 100644 --- a/README_EN.md +++ b/README_EN.md @@ -1,6 +1,6 @@ # Welcome to Lean's git source of OpenWrt and packages -I18N: [English](README_EN.md) | [简体中文](README.md) +I18N: [English](README_EN.md) | [简体中文](README.md) | [日本語](README_JA.md) ## Official Channels + +ディスカッションや共有したい技術的な質問がある場合は、以下のチャンネルにお気軽にご参加ください: +1. QQ グループ: *OpenWRT ファームウェア技術研究グループ*、グループ番号は `891659613` です。グループに参加する: [リンク](https://jq.qq.com/?_wv=1027&k=XL8SK5aC "Op固件技术研究群")。 + - [クリックして QQ クライアントをダウンロードする](https://im.qq.com/pcqq)。 +2. Telegram グループ: *OpenWRT ファームウェア技術研究グループ*。グループに参加する: [リンク](https://t.me/JhKgAA6Hx1 "OP 编译官方大群")。 +3. Rockchip **RK3568** コンパイル済みファームウェアリリース (H68K を含む): [クリックしてダウンロード](https://github.com/coolsnowwolf/lede/releases/tag/20220716)。 + +
+ + + +
+ +4. Rockchip **RK3588**コンパイル済みファームウェアリリース（H68K を含む）: [クリックしてダウンロード](https://github.com/coolsnowwolf/lede/releases/tag/20230609)。 + + +## 注意 + +1. **OpenWRT を決して `root` としてコンパイルしないこと** +2. 中国本土にお住まいの方は、ぜひ **REAL** インターネットをご覧ください。 +3. デフォルトのログイン IP は `192.168.1.1` で、パスワードは `password` です。 + +## コンパイル方法 + + +1. Linuxディストリビューションをインストールし、Debian 11 または Ubuntu LTS を推奨します。 +2. 依存関係をインストールする: + + ```bash + sudo apt update -y + sudo apt full-upgrade -y + sudo apt install -y ack antlr3 asciidoc autoconf automake autopoint binutils bison build-essential \ + bzip2 ccache cmake cpio curl device-tree-compiler fastjar flex gawk gettext gcc-multilib g++-multilib \ + git gperf haveged help2man intltool libc6-dev-i386 libelf-dev libglib2.0-dev libgmp3-dev libltdl-dev \ + libmpc-dev libmpfr-dev libncurses5-dev libncursesw5-dev libreadline-dev libssl-dev libtool lrzsz \ + mkisofs msmtp nano ninja-build p7zip p7zip-full patch pkgconf python2.7 python3 python3-pyelftools \ + libpython3-dev qemu-utils rsync scons squashfs-tools subversion swig texinfo uglifyjs upx-ucl unzip \ + vim wget xmlto xxd zlib1g-dev python3-setuptools + ``` + + + +3. ソースコードをクローンし、`feeds` を更新し、設定する: + + ```bash + git clone https://github.com/coolsnowwolf/lede + cd lede + ./scripts/feeds update -a + ./scripts/feeds install -a + make menuconfig + ``` + +4. ライブラリのダウンロードとファームウェアのコンパイル + > (`-j` はスレッドカウント、最初のビルドはシングルスレッドを推奨): + + ```bash + make -j8 download V=s + make -j1 V=s + ``` + + + +これらのコマンドは、ソースコードを正常にコンパイルするためのものです。 +R23 のソースコードは IPK を含めてすべて含まれています。 + +このソースコードはご自由にお使いいただけますが、再配布の際はこの GitHub リポジトリをリンクしてください。 +ご協力ありがとうございました！ + + + +リビルド: + +```bash +cd lede +git pull +./scripts/feeds update -a +./scripts/feeds install -a +make defconfig +make download -j8 +make V=s -j$(nproc) +``` + +再設定が必要な場合: + +```bash +rm -rf ./tmp && rm -rf .config +make menuconfig +make V=s -j$(nproc) +``` + +ビルドの成果物は `bin/targets` ディレクトリに出力されます。 + +### WSL/WSL2 をビルド環境として使用している場合 + + +WSL の `PATH` には、Windows のパスが空白で含まれている可能性があり、コンパイルに失敗することがあります。コンパイルする前に、ローカルの環境プロファイルに以下の行を追加してください: + +```bash +# 例えば、~/.bashrc などのプロファイルを更新した後、再読み込みを行う。 +cat << EOF >> ~/.bashrc +export PATH="/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:$PATH" +EOF +source ~/.bashrc +``` + + + +WSL ディストリビューションにマウントされた NTFS フォーマットのドライブは、デフォルトで大文字と小文字が区別されません。このため、WSL/WSL2 でコンパイルすると、次のようなエラーが発生します: + +```txt +Build dependency: OpenWrt can only be built on a case-sensitive filesystem +``` + +単純な解決策は、`git clone` の前に大文字小文字を区別してリポジトリ用のディレクトリを作成することです: + +```powershell +# 管理者としてターミナルを開く +PS > fsutil.exe file setCaseSensitiveInfo enable +# 大文字と小文字を区別して、このリポジトリを ディレクトリにクローンする +PS > git clone git@github.com:coolsnowwolf/lede.git +``` + +> すでに `git clone` されたディレクトリでは、`fsutil.exe` は有効になりません。大文字小文字の区別はディレクトリの新しい変更に対してのみ有効になります。 + +### macOS コンパイル + + +1. AppStore から Xcode をインストールする +2. Homebrew をインストールする: + ```bash + /usr/bin/ruby -e "$(curl -fsSL https://raw.githubusercontent.com/Homebrew/install/master/install)" + ``` +3. Homebrew でツールチェーン、依存関係、パッケージをインストールする: + ```bash + brew unlink awk + brew install coreutils diffutils findutils gawk gnu-getopt gnu-tar grep make ncurses pkg-config wget quilt xz + brew install gcc@11 + ``` +4. システム環境のアップデート: + ```bash + echo 'export PATH="/usr/local/opt/coreutils/libexec/gnubin:$PATH"' >> ~/.bashrc + echo 'export PATH="/usr/local/opt/findutils/libexec/gnubin:$PATH"' >> ~/.bashrc + echo 'export PATH="/usr/local/opt/gnu-getopt/bin:$PATH"' >> ~/.bashrc + echo 'export PATH="/usr/local/opt/gnu-tar/libexec/gnubin:$PATH"' >> ~/.bashrc + echo 'export PATH="/usr/local/opt/grep/libexec/gnubin:$PATH"' >> ~/.bashrc + echo 'export PATH="/usr/local/opt/gnu-sed/libexec/gnubin:$PATH"' >> ~/.bashrc + echo 'export PATH="/usr/local/opt/make/libexec/gnubin:$PATH"' >> ~/.bashrc + ``` +5. シェルプロファイル `source ~/.bashrc && bash` を再読み込みすれば、Linux のように普通にコンパイルできます。 + +## 宣言 + +1. このソースコードには、HTTPS トラフィックを監視／キャプチャできるバックドアやクローズドソースアプリケーションは含まれていません。SSL セキュリティはサイバーセキュリティの最後の城です。安全性はファームウェアがすべきことです。 +2. OpenWRT の開発を学びたいが、何から始めたらいいかわからないですか？自己学習のモチベーションが上がらない？基礎知識が足りない？ズオ氏の初心者 OpenWRT トレーニングコースで一緒に OpenWRT 開発を学びましょう。お申し込みは[こちら](http://forgotfun.org/2018/04/openwrt-training-2018.html)をクリックしてください。 +3. QCA IPQ60xx オープンソースリポジトリ: +4. OpenWRT アーカイブリポジトリ: + +## ソフトウェアルーター入門 + +Yingku R2 - N95/N300 Mini Four-Network HomeLab Server + +(紹介ページ - Yingku Technology (support AliPay Huabei)): + +[先行販売リンク](https://item.taobao.com/item.htm?ft=t&id=719159813003) +
+ + + +
+
+ +## 寄付 + + +このプロジェクトがあなたのお役に立てたのであれば、このプロジェクトの発展を支援するための寄付をご検討ください。 + +
+ +
+
diff --git a/include/kernel-5.10 b/include/kernel-5.10 index 1c4497eb424327..0a36292558efbf 100644 --- a/include/kernel-5.10 +++ b/include/kernel-5.10 @@ -1,2 +1,2 @@ -LINUX_VERSION-5.10 = .199 -LINUX_KERNEL_HASH-5.10.199 = a0ea77a1f5eeb1387d62e7a8df585ffc53758e4da153d98224ccd833bd2624c1 +LINUX_VERSION-5.10 = .205 +LINUX_KERNEL_HASH-5.10.205 = c55217a80d74f81b83116289a8bfe4302293390b45aeabb76f64814920788863 diff --git a/include/kernel-5.15 b/include/kernel-5.15 index 6c2be5b3546a30..2948d10bdc34b5 100644 --- a/include/kernel-5.15 +++ b/include/kernel-5.15 @@ -1,2 +1,2 @@ -LINUX_VERSION-5.15 = .138 -LINUX_KERNEL_HASH-5.15.138 = af84e54164e1c01f59764ba528448ed36b377d22aafbd81b4b0cf47792ef4aaa +LINUX_VERSION-5.15 = .145 +LINUX_KERNEL_HASH-5.15.145 = b2a49d87605f3a9491581150315e22337c1afb599efc1e2737481be3a2d6d620 diff --git a/include/kernel-5.4 b/include/kernel-5.4 index 6fb2fe85c6642d..a6b44269ca33d2 100644 --- a/include/kernel-5.4 +++ b/include/kernel-5.4 @@ -1,2 +1,2 @@ -LINUX_VERSION-5.4 = .260 -LINUX_KERNEL_HASH-5.4.260 = 9830820714c8f5985c50071cc9e1b40533ee81a4f6c704916c7148d16e54ebfe +LINUX_VERSION-5.4 = .265 +LINUX_KERNEL_HASH-5.4.265 = 4dae99e49f466d4689e128ec023754908147159d7462019a83c7da1f25df9b15 diff --git a/include/kernel-6.1 b/include/kernel-6.1 index 1dd947e7bc0ccb..b42886811e3be7 100644 --- a/include/kernel-6.1 +++ b/include/kernel-6.1 @@ -1,2 +1,2 @@ -LINUX_VERSION-6.1 = .62 -LINUX_KERNEL_HASH-6.1.62 = b9fd616facd6becfceef88b9be718d0f16625cab3fe81d11384802a7091e85ec +LINUX_VERSION-6.1 = .69 +LINUX_KERNEL_HASH-6.1.69 = 7e3d2694d18ce502068cc88a430da809abbd17d0773268524ebece442612b541 diff --git a/include/u-boot.mk b/include/u-boot.mk index 8945e8e2b8f568..d824d97ff23a75 100644 --- a/include/u-boot.mk +++ b/include/u-boot.mk @@ -16,7 +16,7 @@ PKG_FLAGS:=nonshared PKG_LICENSE:=GPL-2.0 GPL-2.0+ PKG_LICENSE_FILES:=Licenses/README -PKG_BUILD_PARALLEL:=1 +PKG_BUILD_PARALLEL ?= 1 export GCC_HONOUR_COPTS=s diff --git a/package/base-files/files/lib/functions/system.sh b/package/base-files/files/lib/functions/system.sh index 2cf592a24fbe22..c34bca33cd54d0 100644 --- a/package/base-files/files/lib/functions/system.sh +++ b/package/base-files/files/lib/functions/system.sh @@ -61,11 +61,21 @@ find_mtd_chardev() { echo "${INDEX:+$PREFIX$INDEX}" } +get_mac_ascii() { + local part="$1" + local key="$2" + local mac_dirty + + mac_dirty=$(strings "$part" | sed -n 's/^'"$key"'=//p') + + # "canonicalize" mac + [ -n "$mac_dirty" ] && macaddr_canonicalize "$mac_dirty" +} + mtd_get_mac_ascii() { local mtdname="$1" local key="$2" local part - local mac_dirty part=$(find_mtd_part "$mtdname") if [ -z "$part" ]; then @@ -73,10 +83,7 @@ mtd_get_mac_ascii() { return fi - mac_dirty=$(strings "$part" | sed -n 's/^'"$key"'=//p') - - # "canonicalize" mac - [ -n "$mac_dirty" ] && macaddr_canonicalize "$mac_dirty" + get_mac_ascii "$part" "$key" } mtd_get_mac_text() { @@ -144,6 +151,19 @@ mtd_get_part_size() { done < /proc/mtd } +mmc_get_mac_ascii() { + local part_name="$1" + local key="$2" + local part + + part=$(find_mmc_part "$part_name") + if [ -z "$part" ]; then + echo "mmc_get_mac_ascii: partition $part_name not found!" >&2 + fi + + get_mac_ascii "$part" "$key" +} + mmc_get_mac_binary() { local part_name="$1" local offset="$2" diff --git a/package/kernel/linux/modules/usb.mk b/package/kernel/linux/modules/usb.mk index 6429d58a08dd3a..e0bebc46d27022 100644 --- a/package/kernel/linux/modules/usb.mk +++ b/package/kernel/linux/modules/usb.mk @@ -549,6 +549,7 @@ define KernelPackage/usb-audio CONFIG_SND_USB_AUDIO $(call AddDepends/usb) $(call AddDepends/sound) + DEPENDS += +LINUX_6_1:kmod-media-core FILES:= \ $(LINUX_DIR)/sound/usb/snd-usbmidi-lib.ko \ $(LINUX_DIR)/sound/usb/snd-usb-audio.ko diff --git a/package/kernel/linux/modules/video.mk b/package/kernel/linux/modules/video.mk index 9ae9c92712fdc8..ae2cc36f25033a 100644 --- a/package/kernel/linux/modules/video.mk +++ b/package/kernel/linux/modules/video.mk @@ -240,6 +240,24 @@ endef $(eval $(call KernelPackage,fb-tft-ili9486)) +define KernelPackage/media-core + SUBMENU:=$(VIDEO_MENU) + TITLE=Multimedia support + HIDDEN:=1 + KCONFIG:= \ + CONFIG_MEDIA_SUPPORT \ + CONFIG_MEDIA_CONTROLLER=y \ + CONFIG_MEDIA_CAMERA_SUPPORT=y + FILES:=$(LINUX_DIR)/drivers/media/mc/mc.ko + AUTOLOAD:=$(call AutoProbe,mc) +endef + +define KernelPackage/media-core/description + Kernel modules for media controller support +endef + +$(eval $(call KernelPackage,media-core)) + define KernelPackage/multimedia-input SUBMENU:=$(VIDEO_MENU) TITLE:=Multimedia input support @@ -541,13 +559,12 @@ $(eval $(call KernelPackage,drm-nouveau)) define KernelPackage/video-core SUBMENU:=$(VIDEO_MENU) TITLE=Video4Linux support - DEPENDS:=+PACKAGE_kmod-i2c-core:kmod-i2c-core + DEPENDS:=+PACKAGE_kmod-i2c-core:kmod-i2c-core \ + +LINUX_6_1:kmod-media-core KCONFIG:= \ - CONFIG_MEDIA_SUPPORT \ - CONFIG_MEDIA_CAMERA_SUPPORT=y \ CONFIG_VIDEO_DEV \ CONFIG_V4L_PLATFORM_DRIVERS=y - FILES:=$(LINUX_DIR)/drivers/media/mc/mc.ko@ge6.1 \ + FILES:= \ $(LINUX_DIR)/drivers/media/$(V4L2_DIR)/videodev.ko AUTOLOAD:=$(call AutoLoad,60, videodev v4l2-common) endef diff --git a/package/kernel/mac80211/patches/ath10k/911-ath10k-disable-caldata-prefetch-for-sdio-bus.patch b/package/kernel/mac80211/patches/ath10k/911-ath10k-disable-caldata-prefetch-for-sdio-bus.patch index 1fd8117e6a3345..8ca8f3b55b6a6e 100644 --- a/package/kernel/mac80211/patches/ath10k/911-ath10k-disable-caldata-prefetch-for-sdio-bus.patch +++ b/package/kernel/mac80211/patches/ath10k/911-ath10k-disable-caldata-prefetch-for-sdio-bus.patch @@ -1,12 +1,12 @@ --- a/drivers/net/wireless/ath/ath10k/debug.c +++ b/drivers/net/wireless/ath/ath10k/debug.c -@@ -1260,6 +1260,9 @@ static int ath10k_debug_cal_data_fetch(struct ath10k *ar) - if (ar->hw_params.cal_data_len == 0) - return -EOPNOTSUPP; - +@@ -1260,6 +1260,9 @@ static int ath10k_debug_cal_data_fetch(s + if (ar->hw_params.cal_data_len == 0) + return -EOPNOTSUPP; + + if (ar->hif.bus == ATH10K_BUS_SDIO) + return -EINVAL; + - hi_addr = host_interest_item_address(HI_ITEM(hi_board_data)); - - ret = ath10k_hif_diag_read(ar, hi_addr, &addr, sizeof(addr)); + hi_addr = host_interest_item_address(HI_ITEM(hi_board_data)); + + ret = ath10k_hif_diag_read(ar, hi_addr, &addr, sizeof(addr)); diff --git a/package/kernel/mac80211/patches/ath10k/974-ath10k_add-LED-and-GPIO-controlling-support-for-various-chipsets.patch b/package/kernel/mac80211/patches/ath10k/974-ath10k_add-LED-and-GPIO-controlling-support-for-various-chipsets.patch index 1c1630c05199d9..fd5b4481170e14 100644 --- a/package/kernel/mac80211/patches/ath10k/974-ath10k_add-LED-and-GPIO-controlling-support-for-various-chipsets.patch +++ b/package/kernel/mac80211/patches/ath10k/974-ath10k_add-LED-and-GPIO-controlling-support-for-various-chipsets.patch @@ -202,7 +202,7 @@ v13: err_spectral_destroy: ath10k_spectral_destroy(ar); err_debug_destroy: -@@ -3537,6 +3556,8 @@ void ath10k_core_unregister(struct ath10 +@@ -3538,6 +3557,8 @@ void ath10k_core_unregister(struct ath10 if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags)) return; diff --git a/package/kernel/mac80211/patches/ath10k/988-ath10k-always-use-mac80211-loss-detection.patch b/package/kernel/mac80211/patches/ath10k/988-ath10k-always-use-mac80211-loss-detection.patch index f025fea63b7ad6..f4b1ded15e5c8c 100644 --- a/package/kernel/mac80211/patches/ath10k/988-ath10k-always-use-mac80211-loss-detection.patch +++ b/package/kernel/mac80211/patches/ath10k/988-ath10k-always-use-mac80211-loss-detection.patch @@ -18,7 +18,7 @@ Signed-off-by: David Bauer --- a/drivers/net/wireless/ath/ath10k/mac.c +++ b/drivers/net/wireless/ath/ath10k/mac.c -@@ -10080,7 +10080,6 @@ int ath10k_mac_register(struct ath10k *a +@@ -10081,7 +10081,6 @@ int ath10k_mac_register(struct ath10k *a ieee80211_hw_set(ar->hw, CHANCTX_STA_CSA); ieee80211_hw_set(ar->hw, QUEUE_CONTROL); ieee80211_hw_set(ar->hw, SUPPORTS_TX_FRAG); diff --git a/package/kernel/mac80211/patches/ath11k/0085-wifi-ath11k-fix-memory-leak-in-WMI-firmware-stats.patch b/package/kernel/mac80211/patches/ath11k/0085-wifi-ath11k-fix-memory-leak-in-WMI-firmware-stats.patch new file mode 100644 index 00000000000000..dde30b962d4f87 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0085-wifi-ath11k-fix-memory-leak-in-WMI-firmware-stats.patch @@ -0,0 +1,51 @@ +From 6aafa1c2d3e3fea2ebe84c018003f2a91722e607 Mon Sep 17 00:00:00 2001 +From: P Praneesh +Date: Tue, 6 Jun 2023 14:41:28 +0530 +Subject: [PATCH] wifi: ath11k: fix memory leak in WMI firmware stats + +Memory allocated for firmware pdev, vdev and beacon statistics +are not released during rmmod. + +Fix it by calling ath11k_fw_stats_free() function before hardware +unregister. + +While at it, avoid calling ath11k_fw_stats_free() while processing +the firmware stats received in the WMI event because the local list +is getting spliced and reinitialised and hence there are no elements +in the list after splicing. + +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: P Praneesh +Signed-off-by: Aditya Kumar Singh +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230606091128.14202-1-quic_adisi@quicinc.com +--- + drivers/net/wireless/ath/ath11k/mac.c | 1 + + drivers/net/wireless/ath/ath11k/wmi.c | 5 +++++ + 2 files changed, 6 insertions(+) + +--- a/drivers/net/wireless/ath/ath11k/mac.c ++++ b/drivers/net/wireless/ath/ath11k/mac.c +@@ -9792,6 +9792,7 @@ void ath11k_mac_destroy(struct ath11k_ba + if (!ar) + continue; + ++ ath11k_fw_stats_free(&ar->fw_stats); + ieee80211_free_hw(ar->hw); + pdev->ar = NULL; + } +--- a/drivers/net/wireless/ath/ath11k/wmi.c ++++ b/drivers/net/wireless/ath/ath11k/wmi.c +@@ -8119,6 +8119,11 @@ complete: + rcu_read_unlock(); + spin_unlock_bh(&ar->data_lock); + ++ /* Since the stats's pdev, vdev and beacon list are spliced and reinitialised ++ * at this point, no need to free the individual list. ++ */ ++ return; ++ + free: + ath11k_fw_stats_free(&stats); + } diff --git a/package/kernel/mac80211/patches/ath11k/0086-wifi-ath11k-Add-missing-check-for-ioremap.patch b/package/kernel/mac80211/patches/ath11k/0086-wifi-ath11k-Add-missing-check-for-ioremap.patch new file mode 100644 index 00000000000000..e536c3bd644567 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0086-wifi-ath11k-Add-missing-check-for-ioremap.patch @@ -0,0 +1,38 @@ +From 16e0077e14a73866e9b0f4a6bf4ad3d4a5cb0f2a Mon Sep 17 00:00:00 2001 +From: Jiasheng Jiang +Date: Tue, 13 Jun 2023 12:19:40 +0300 +Subject: [PATCH] wifi: ath11k: Add missing check for ioremap + +Add check for ioremap() and return the error if it fails in order to +guarantee the success of ioremap(), same as in +ath11k_qmi_load_file_target_mem(). + +Fixes: 6ac04bdc5edb ("ath11k: Use reserved host DDR addresses from DT for PCI devices") +Signed-off-by: Jiasheng Jiang +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230608022858.27405-1-jiasheng@iscas.ac.cn +--- + drivers/net/wireless/ath/ath11k/qmi.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/net/wireless/ath/ath11k/qmi.c ++++ b/drivers/net/wireless/ath/ath11k/qmi.c +@@ -2061,6 +2061,9 @@ static int ath11k_qmi_assign_target_mem_ + ab->qmi.target_mem[idx].iaddr = + ioremap(ab->qmi.target_mem[idx].paddr, + ab->qmi.target_mem[i].size); ++ if (!ab->qmi.target_mem[idx].iaddr) ++ return -EIO; ++ + ab->qmi.target_mem[idx].size = ab->qmi.target_mem[i].size; + host_ddr_sz = ab->qmi.target_mem[i].size; + ab->qmi.target_mem[idx].type = ab->qmi.target_mem[i].type; +@@ -2086,6 +2089,8 @@ static int ath11k_qmi_assign_target_mem_ + ab->qmi.target_mem[idx].iaddr = + ioremap(ab->qmi.target_mem[idx].paddr, + ab->qmi.target_mem[i].size); ++ if (!ab->qmi.target_mem[idx].iaddr) ++ return -EIO; + } else { + ab->qmi.target_mem[idx].paddr = + ATH11K_QMI_CALDB_ADDRESS; diff --git a/package/kernel/mac80211/patches/ath11k/0087-wifi-ath11k-Add-missing-ops-config-for-IPQ5018-in.patch b/package/kernel/mac80211/patches/ath11k/0087-wifi-ath11k-Add-missing-ops-config-for-IPQ5018-in.patch new file mode 100644 index 00000000000000..fa539ef4591236 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0087-wifi-ath11k-Add-missing-ops-config-for-IPQ5018-in.patch @@ -0,0 +1,30 @@ +From 469ddb20cae61cad9c4f208a4c8682305905a511 Mon Sep 17 00:00:00 2001 +From: Ziyang Huang +Date: Thu, 15 Jun 2023 14:41:47 +0300 +Subject: [PATCH] wifi: ath11k: Add missing ops config for IPQ5018 in + ath11k_ahb_probe() + +Without this patch, the IPQ5018 WiFi will fail and print the following +logs: + + [ 11.033179] ath11k c000000.wifi: unsupported device type 7 + [ 11.033223] ath11k: probe of c000000.wifi failed with error -95 + +Fixes: 25edca7bb18a ("wifi: ath11k: add ipq5018 device support") +Signed-off-by: Ziyang Huang +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/TYZPR01MB5556D7AA10ABEDDDD2D8F39EC953A@TYZPR01MB5556.apcprd01.prod.exchangelabs.com +--- + drivers/net/wireless/ath/ath11k/ahb.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/net/wireless/ath/ath11k/ahb.c ++++ b/drivers/net/wireless/ath/ath11k/ahb.c +@@ -1127,6 +1127,7 @@ static int ath11k_ahb_probe(struct platf + switch (hw_rev) { + case ATH11K_HW_IPQ8074: + case ATH11K_HW_IPQ6018_HW10: ++ case ATH11K_HW_IPQ5018_HW10: + hif_ops = &ath11k_ahb_hif_ops_ipq8074; + pci_ops = NULL; + break; diff --git a/package/kernel/mac80211/patches/ath11k/0088-wifi-ath11k-Restart-firmware-after-cold-boot-calibration.patch b/package/kernel/mac80211/patches/ath11k/0088-wifi-ath11k-Restart-firmware-after-cold-boot-calibration.patch new file mode 100644 index 00000000000000..4a9385218042c6 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0088-wifi-ath11k-Restart-firmware-after-cold-boot-calibration.patch @@ -0,0 +1,47 @@ +From 80c5390e1f5e5b16d820512265530ef26073d8e0 Mon Sep 17 00:00:00 2001 +From: Ziyang Huang +Date: Thu, 15 Jun 2023 14:41:48 +0300 +Subject: [PATCH] wifi: ath11k: Restart firmware after cold boot calibration + for IPQ5018 + +Restart is required after cold boot calibration on IPQ5018. Otherwise, +we get the following exception: + + [ 14.412829] qcom-q6-mpd cd00000.remoteproc: fatal error received: err_smem_ver.2.1: + [ 14.412829] QC Image Version : QC_IMAGE_VERSION_STRING=WLAN.HK.2.6.0.1-00974-QCAHKSWPL_SILICONZ-1 + [ 14.412829] Image Variant : IMAGE_VARIANT_STRING=5018.wlanfw2.map_spr_spr_evalQ + [ 14.412829] DALSysLogEvent.c:174 Assertion 0 failed param0 :zero,param1 :zero,param2 :zero + [ 14.412829] Thread ID : 0x00000048 Thread name : WLAN RT0 Process ID : 0x00000001 Process name :wlan0 + [ 14.412829] + [ 14.412829] Registers: + [ 14.412829] SP : 0x4c81c120 + [ 14.412829] FP : 0x4c81c138 + [ 14.412829] PC : 0xb022c590 + [ 14.412829] SSR : 0x00000000 + [ 14.412829] BADVA : 0x00000000 + [ 14.412829] LR : 0xb0008490 + [ 14.412829] + [ 14.412829] StackDump + [ 14.412829] from:0x4c81c120 + [ 14.412829] to: 0x00000000: + [ 14.412829] + [ 14.463006] remoteproc remoteproc0: crash detected in cd00000.remoteproc: type fatal error + +Fixes: 8dfe875aa24a ("wifi: ath11k: update hw params for IPQ5018") +Signed-off-by: Ziyang Huang +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/TYZPR01MB55566969818BD4B49E770445C953A@TYZPR01MB5556.apcprd01.prod.exchangelabs.com +--- + drivers/net/wireless/ath/ath11k/core.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/net/wireless/ath/ath11k/core.c ++++ b/drivers/net/wireless/ath/ath11k/core.c +@@ -668,6 +668,7 @@ static const struct ath11k_hw_params ath + .hal_params = &ath11k_hw_hal_params_ipq8074, + .single_pdev_only = false, + .cold_boot_calib = true, ++ .cbcal_restart_fw = true, + .fix_l1ss = true, + .supports_dynamic_smps_6ghz = false, + .alloc_cacheable_memory = true, diff --git a/package/kernel/mac80211/patches/ath11k/0089-wifi-ath11k-Add-missing-hw_ops-get_ring_selector-for.patch b/package/kernel/mac80211/patches/ath11k/0089-wifi-ath11k-Add-missing-hw_ops-get_ring_selector-for.patch new file mode 100644 index 00000000000000..cb6667f14ad915 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0089-wifi-ath11k-Add-missing-hw_ops-get_ring_selector-for.patch @@ -0,0 +1,58 @@ +From ce282d8de71f07f0056ea319541141152c65f552 Mon Sep 17 00:00:00 2001 +From: Ziyang Huang +Date: Thu, 15 Jun 2023 14:41:48 +0300 +Subject: [PATCH] wifi: ath11k: Add missing hw_ops->get_ring_selector() for + IPQ5018 + +During sending data after clients connected, hw_ops->get_ring_selector() +will be called. But for IPQ5018, this member isn't set, and the +following NULL pointer exception will be occurred: + + [ 38.840478] 8<--- cut here --- + [ 38.840517] Unable to handle kernel NULL pointer dereference at virtual address 00000000 + ... + [ 38.923161] PC is at 0x0 + [ 38.927930] LR is at ath11k_dp_tx+0x70/0x730 [ath11k] + ... + [ 39.063264] Process hostapd (pid: 1034, stack limit = 0x801ceb3d) + [ 39.068994] Stack: (0x856a9a68 to 0x856aa000) + ... + [ 39.438467] [<7f323804>] (ath11k_dp_tx [ath11k]) from [<7f314e6c>] (ath11k_mac_op_tx+0x80/0x190 [ath11k]) + [ 39.446607] [<7f314e6c>] (ath11k_mac_op_tx [ath11k]) from [<7f17dbe0>] (ieee80211_handle_wake_tx_queue+0x7c/0xc0 [mac80211]) + [ 39.456162] [<7f17dbe0>] (ieee80211_handle_wake_tx_queue [mac80211]) from [<7f174450>] (ieee80211_probereq_get+0x584/0x704 [mac80211]) + [ 39.467443] [<7f174450>] (ieee80211_probereq_get [mac80211]) from [<7f178c40>] (ieee80211_tx_prepare_skb+0x1f8/0x248 [mac80211]) + [ 39.479334] [<7f178c40>] (ieee80211_tx_prepare_skb [mac80211]) from [<7f179e28>] (__ieee80211_subif_start_xmit+0x32c/0x3d4 [mac80211]) + [ 39.491053] [<7f179e28>] (__ieee80211_subif_start_xmit [mac80211]) from [<7f17af08>] (ieee80211_tx_control_port+0x19c/0x288 [mac80211]) + [ 39.502946] [<7f17af08>] (ieee80211_tx_control_port [mac80211]) from [<7f0fc704>] (nl80211_tx_control_port+0x174/0x1d4 [cfg80211]) + [ 39.515017] [<7f0fc704>] (nl80211_tx_control_port [cfg80211]) from [<808ceac4>] (genl_rcv_msg+0x154/0x340) + [ 39.526814] [<808ceac4>] (genl_rcv_msg) from [<808cdb74>] (netlink_rcv_skb+0xb8/0x11c) + [ 39.536446] [<808cdb74>] (netlink_rcv_skb) from [<808ce1d0>] (genl_rcv+0x28/0x34) + [ 39.544344] [<808ce1d0>] (genl_rcv) from [<808cd234>] (netlink_unicast+0x174/0x274) + [ 39.551895] [<808cd234>] (netlink_unicast) from [<808cd510>] (netlink_sendmsg+0x1dc/0x440) + [ 39.559362] [<808cd510>] (netlink_sendmsg) from [<808596e0>] (____sys_sendmsg+0x1a8/0x1fc) + [ 39.567697] [<808596e0>] (____sys_sendmsg) from [<8085b1a8>] (___sys_sendmsg+0xa4/0xdc) + [ 39.575941] [<8085b1a8>] (___sys_sendmsg) from [<8085b310>] (sys_sendmsg+0x44/0x74) + [ 39.583841] [<8085b310>] (sys_sendmsg) from [<80300060>] (ret_fast_syscall+0x0/0x40) + ... + [ 39.620734] Code: bad PC value + [ 39.625869] ---[ end trace 8aef983ad3cbc032 ]--- + +Fixes: ba60f2793d3a ("wifi: ath11k: initialize hw_ops for IPQ5018") +Signed-off-by: Ziyang Huang +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/TYZPR01MB5556D6E3F63EAB5129D11420C953A@TYZPR01MB5556.apcprd01.prod.exchangelabs.com +--- + drivers/net/wireless/ath/ath11k/hw.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/wireless/ath/ath11k/hw.c ++++ b/drivers/net/wireless/ath/ath11k/hw.c +@@ -1178,7 +1178,7 @@ const struct ath11k_hw_ops ipq5018_ops = + .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, + .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid, + .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2, +- ++ .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector, + }; + + #define ATH11K_TX_RING_MASK_0 BIT(0) diff --git a/package/kernel/mac80211/patches/ath11k/0090-Revert-wifi-ath11k-Enable-threaded-NAPI.patch b/package/kernel/mac80211/patches/ath11k/0090-Revert-wifi-ath11k-Enable-threaded-NAPI.patch new file mode 100644 index 00000000000000..313c18c557fdc7 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0090-Revert-wifi-ath11k-Enable-threaded-NAPI.patch @@ -0,0 +1,44 @@ +From d265ebe41c911314bd273c218a37088835959fa1 Mon Sep 17 00:00:00 2001 +From: Kalle Valo +Date: Thu, 20 Jul 2023 18:14:44 +0300 +Subject: [PATCH] Revert "wifi: ath11k: Enable threaded NAPI" + +This reverts commit 13aa2fb692d3717767303817f35b3e650109add3. + +This commit broke QCN9074 initialisation: + +[ 358.960477] ath11k_pci 0000:04:00.0: ce desc not available for wmi command 36866 +[ 358.960481] ath11k_pci 0000:04:00.0: failed to send WMI_STA_POWERSAVE_PARAM_CMDID +[ 358.960484] ath11k_pci 0000:04:00.0: could not set uapsd params -105 + +As there's no fix available let's just revert it to get QCN9074 working again. + +Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217536 +Signed-off-by: Kalle Valo +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230720151444.2016637-1-kvalo@kernel.org +--- + drivers/net/wireless/ath/ath11k/ahb.c | 1 - + drivers/net/wireless/ath/ath11k/pcic.c | 1 - + 2 files changed, 2 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/ahb.c ++++ b/drivers/net/wireless/ath/ath11k/ahb.c +@@ -376,7 +376,6 @@ static void ath11k_ahb_ext_irq_enable(st + struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; + + if (!irq_grp->napi_enabled) { +- dev_set_threaded(&irq_grp->napi_ndev, true); + napi_enable(&irq_grp->napi); + irq_grp->napi_enabled = true; + } +--- a/drivers/net/wireless/ath/ath11k/pcic.c ++++ b/drivers/net/wireless/ath/ath11k/pcic.c +@@ -466,7 +466,6 @@ void ath11k_pcic_ext_irq_enable(struct a + struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; + + if (!irq_grp->napi_enabled) { +- dev_set_threaded(&irq_grp->napi_ndev, true); + napi_enable(&irq_grp->napi); + irq_grp->napi_enabled = true; + } diff --git a/package/kernel/mac80211/patches/ath11k/0091-wifi-ath11k-Split-coldboot-calibration-hw_param.patch b/package/kernel/mac80211/patches/ath11k/0091-wifi-ath11k-Split-coldboot-calibration-hw_param.patch new file mode 100644 index 00000000000000..47053546860ddf --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0091-wifi-ath11k-Split-coldboot-calibration-hw_param.patch @@ -0,0 +1,180 @@ +From 011e5a3052a22d3758d17442bf0c04c68bf79bea Mon Sep 17 00:00:00 2001 +From: Seevalamuthu Mariappan +Date: Wed, 26 Jul 2023 19:40:30 +0530 +Subject: [PATCH 3/5] wifi: ath11k: Split coldboot calibration hw_param + +QCN9074 enables coldboot calibration only in Factory Test Mode (FTM). +Hence, split cold_boot_calib to two hw_params for mission and FTM +mode. + +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Seevalamuthu Mariappan +Signed-off-by: Raj Kumar Bhagat +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230726141032.3061-2-quic_rajkbhag@quicinc.com +--- + drivers/net/wireless/ath/ath11k/ahb.c | 3 +-- + drivers/net/wireless/ath/ath11k/core.c | 36 ++++++++++++++++++++------ + drivers/net/wireless/ath/ath11k/core.h | 1 + + drivers/net/wireless/ath/ath11k/hw.h | 3 ++- + drivers/net/wireless/ath/ath11k/qmi.c | 6 ++--- + 5 files changed, 35 insertions(+), 14 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/ahb.c ++++ b/drivers/net/wireless/ath/ath11k/ahb.c +@@ -422,8 +422,7 @@ static int ath11k_ahb_fwreset_from_cold_ + { + int timeout; + +- if (ath11k_cold_boot_cal == 0 || ab->qmi.cal_done || +- ab->hw_params.cold_boot_calib == 0 || ++ if (!ath11k_core_coldboot_cal_support(ab) || ab->qmi.cal_done || + ab->hw_params.cbcal_restart_fw == 0) + return 0; + +--- a/drivers/net/wireless/ath/ath11k/core.c ++++ b/drivers/net/wireless/ath/ath11k/core.c +@@ -86,7 +86,8 @@ static const struct ath11k_hw_params ath + .supports_shadow_regs = false, + .idle_ps = false, + .supports_sta_ps = false, +- .cold_boot_calib = true, ++ .coldboot_cal_mm = true, ++ .coldboot_cal_ftm = true, + .cbcal_restart_fw = true, + .fw_mem_mode = 0, + .num_vdevs = 16 + 1, +@@ -167,7 +168,8 @@ static const struct ath11k_hw_params ath + .supports_shadow_regs = false, + .idle_ps = false, + .supports_sta_ps = false, +- .cold_boot_calib = true, ++ .coldboot_cal_mm = true, ++ .coldboot_cal_ftm = true, + .cbcal_restart_fw = true, + .fw_mem_mode = 0, + .num_vdevs = 16 + 1, +@@ -248,7 +250,8 @@ static const struct ath11k_hw_params ath + .supports_shadow_regs = true, + .idle_ps = true, + .supports_sta_ps = true, +- .cold_boot_calib = false, ++ .coldboot_cal_mm = false, ++ .coldboot_cal_ftm = false, + .cbcal_restart_fw = false, + .fw_mem_mode = 0, + .num_vdevs = 16 + 1, +@@ -332,7 +335,8 @@ static const struct ath11k_hw_params ath + .supports_shadow_regs = false, + .idle_ps = false, + .supports_sta_ps = false, +- .cold_boot_calib = false, ++ .coldboot_cal_mm = false, ++ .coldboot_cal_ftm = false, + .cbcal_restart_fw = false, + .fw_mem_mode = 2, + .num_vdevs = 8, +@@ -413,7 +417,8 @@ static const struct ath11k_hw_params ath + .supports_shadow_regs = true, + .idle_ps = true, + .supports_sta_ps = true, +- .cold_boot_calib = false, ++ .coldboot_cal_mm = false, ++ .coldboot_cal_ftm = false, + .cbcal_restart_fw = false, + .fw_mem_mode = 0, + .num_vdevs = 16 + 1, +@@ -495,7 +500,8 @@ static const struct ath11k_hw_params ath + .supports_shadow_regs = true, + .idle_ps = true, + .supports_sta_ps = true, +- .cold_boot_calib = false, ++ .coldboot_cal_mm = false, ++ .coldboot_cal_ftm = false, + .cbcal_restart_fw = false, + .fw_mem_mode = 0, + .num_vdevs = 16 + 1, +@@ -578,7 +584,8 @@ static const struct ath11k_hw_params ath + .supports_shadow_regs = true, + .idle_ps = true, + .supports_sta_ps = true, +- .cold_boot_calib = true, ++ .coldboot_cal_mm = true, ++ .coldboot_cal_ftm = true, + .cbcal_restart_fw = false, + .fw_mem_mode = 0, + .num_vdevs = 16 + 1, +@@ -667,7 +674,8 @@ static const struct ath11k_hw_params ath + .supports_suspend = false, + .hal_params = &ath11k_hw_hal_params_ipq8074, + .single_pdev_only = false, +- .cold_boot_calib = true, ++ .coldboot_cal_mm = true, ++ .coldboot_cal_ftm = true, + .cbcal_restart_fw = true, + .fix_l1ss = true, + .supports_dynamic_smps_6ghz = false, +@@ -749,6 +757,18 @@ void ath11k_fw_stats_free(struct ath11k_ + ath11k_fw_stats_bcn_free(&stats->bcn); + } + ++bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab) ++{ ++ if (!ath11k_cold_boot_cal) ++ return false; ++ ++ if (ath11k_ftm_mode) ++ return ab->hw_params.coldboot_cal_ftm; ++ ++ else ++ return ab->hw_params.coldboot_cal_mm; ++} ++ + int ath11k_core_suspend(struct ath11k_base *ab) + { + int ret; +--- a/drivers/net/wireless/ath/ath11k/core.h ++++ b/drivers/net/wireless/ath/ath11k/core.h +@@ -1186,6 +1186,7 @@ void ath11k_core_halt(struct ath11k *ar) + int ath11k_core_resume(struct ath11k_base *ab); + int ath11k_core_suspend(struct ath11k_base *ab); + void ath11k_core_pre_reconfigure_recovery(struct ath11k_base *ab); ++bool ath11k_core_coldboot_cal_support(struct ath11k_base *ab); + + const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab, + const char *filename); +--- a/drivers/net/wireless/ath/ath11k/hw.h ++++ b/drivers/net/wireless/ath/ath11k/hw.h +@@ -187,7 +187,8 @@ struct ath11k_hw_params { + bool supports_shadow_regs; + bool idle_ps; + bool supports_sta_ps; +- bool cold_boot_calib; ++ bool coldboot_cal_mm; ++ bool coldboot_cal_ftm; + bool cbcal_restart_fw; + int fw_mem_mode; + u32 num_vdevs; +--- a/drivers/net/wireless/ath/ath11k/qmi.c ++++ b/drivers/net/wireless/ath/ath11k/qmi.c +@@ -2082,7 +2082,7 @@ static int ath11k_qmi_assign_target_mem_ + return -EINVAL; + } + +- if (ath11k_cold_boot_cal && ab->hw_params.cold_boot_calib) { ++ if (ath11k_core_coldboot_cal_support(ab)) { + if (hremote_node) { + ab->qmi.target_mem[idx].paddr = + res.start + host_ddr_sz; +@@ -3212,8 +3212,8 @@ static void ath11k_qmi_driver_event_work + break; + } + +- if (ath11k_cold_boot_cal && ab->qmi.cal_done == 0 && +- ab->hw_params.cold_boot_calib) { ++ if (ab->qmi.cal_done == 0 && ++ ath11k_core_coldboot_cal_support(ab)) { + ath11k_qmi_process_coldboot_calibration(ab); + } else { + clear_bit(ATH11K_FLAG_CRASH_FLUSH, diff --git a/package/kernel/mac80211/patches/ath11k/0092-wifi-ath11k-Add-coldboot-calibration-support-for-QCN.patch b/package/kernel/mac80211/patches/ath11k/0092-wifi-ath11k-Add-coldboot-calibration-support-for-QCN.patch new file mode 100644 index 00000000000000..31b11ddee4bbdf --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0092-wifi-ath11k-Add-coldboot-calibration-support-for-QCN.patch @@ -0,0 +1,176 @@ +From bdfc967bf5fcd762473a01d39edb81f1165ba290 Mon Sep 17 00:00:00 2001 +From: Anilkumar Kolli +Date: Wed, 26 Jul 2023 19:40:31 +0530 +Subject: [PATCH 4/5] wifi: ath11k: Add coldboot calibration support for + QCN9074 + +QCN9074 supports 6 GHz, which has increased number of channels +compared to 5 GHz/2 GHz. So, to support coldboot calibration in +QCN9074 ATH11K_COLD_BOOT_FW_RESET_DELAY extended to 60 seconds. To +avoid code redundancy, fwreset_from_cold_boot moved to QMI and made +common for both ahb and pci. Coldboot calibration is enabled only in +FTM mode for QCN9074. QCN9074 requires firmware restart after coldboot, +hence enable cbcal_restart_fw in hw_params. + +This support can be enabled/disabled using hw params for different +hardware. Currently it is not enabled for QCA6390. + +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Anilkumar Kolli +Signed-off-by: Seevalamuthu Mariappan +Signed-off-by: Raj Kumar Bhagat +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230726141032.3061-3-quic_rajkbhag@quicinc.com +--- + drivers/net/wireless/ath/ath11k/ahb.c | 28 ++------------------------ + drivers/net/wireless/ath/ath11k/core.c | 4 ++-- + drivers/net/wireless/ath/ath11k/pci.c | 2 ++ + drivers/net/wireless/ath/ath11k/qmi.c | 28 ++++++++++++++++++++++++++ + drivers/net/wireless/ath/ath11k/qmi.h | 3 ++- + 5 files changed, 36 insertions(+), 29 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/ahb.c ++++ b/drivers/net/wireless/ath/ath11k/ahb.c +@@ -14,6 +14,7 @@ + #include "ahb.h" + #include "debug.h" + #include "hif.h" ++#include "qmi.h" + #include + #include "pcic.h" + #include +@@ -418,31 +419,6 @@ static void ath11k_ahb_power_down(struct + rproc_shutdown(ab_ahb->tgt_rproc); + } + +-static int ath11k_ahb_fwreset_from_cold_boot(struct ath11k_base *ab) +-{ +- int timeout; +- +- if (!ath11k_core_coldboot_cal_support(ab) || ab->qmi.cal_done || +- ab->hw_params.cbcal_restart_fw == 0) +- return 0; +- +- ath11k_dbg(ab, ATH11K_DBG_AHB, "wait for cold boot done\n"); +- timeout = wait_event_timeout(ab->qmi.cold_boot_waitq, +- (ab->qmi.cal_done == 1), +- ATH11K_COLD_BOOT_FW_RESET_DELAY); +- if (timeout <= 0) { +- ath11k_cold_boot_cal = 0; +- ath11k_warn(ab, "Coldboot Calibration failed timed out\n"); +- } +- +- /* reset the firmware */ +- ath11k_ahb_power_down(ab); +- ath11k_ahb_power_up(ab); +- +- ath11k_dbg(ab, ATH11K_DBG_AHB, "exited from cold boot mode\n"); +- return 0; +-} +- + static void ath11k_ahb_init_qmi_ce_config(struct ath11k_base *ab) + { + struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; +@@ -1225,7 +1201,7 @@ static int ath11k_ahb_probe(struct platf + goto err_ce_free; + } + +- ath11k_ahb_fwreset_from_cold_boot(ab); ++ ath11k_qmi_fwreset_from_cold_boot(ab); + + return 0; + +--- a/drivers/net/wireless/ath/ath11k/core.c ++++ b/drivers/net/wireless/ath/ath11k/core.c +@@ -336,8 +336,8 @@ static const struct ath11k_hw_params ath + .idle_ps = false, + .supports_sta_ps = false, + .coldboot_cal_mm = false, +- .coldboot_cal_ftm = false, +- .cbcal_restart_fw = false, ++ .coldboot_cal_ftm = true, ++ .cbcal_restart_fw = true, + .fw_mem_mode = 2, + .num_vdevs = 8, + .num_peers = 128, +--- a/drivers/net/wireless/ath/ath11k/pci.c ++++ b/drivers/net/wireless/ath/ath11k/pci.c +@@ -15,6 +15,7 @@ + #include "mhi.h" + #include "debug.h" + #include "pcic.h" ++#include "qmi.h" + + #define ATH11K_PCI_BAR_NUM 0 + #define ATH11K_PCI_DMA_MASK 32 +@@ -897,6 +898,7 @@ unsupported_wcn6855_soc: + ath11k_err(ab, "failed to init core: %d\n", ret); + goto err_irq_affinity_cleanup; + } ++ ath11k_qmi_fwreset_from_cold_boot(ab); + return 0; + + err_irq_affinity_cleanup: +--- a/drivers/net/wireless/ath/ath11k/qmi.c ++++ b/drivers/net/wireless/ath/ath11k/qmi.c +@@ -9,6 +9,7 @@ + #include "qmi.h" + #include "core.h" + #include "debug.h" ++#include "hif.h" + #include + #include + #include +@@ -2842,6 +2843,33 @@ int ath11k_qmi_firmware_start(struct ath + return 0; + } + ++int ath11k_qmi_fwreset_from_cold_boot(struct ath11k_base *ab) ++{ ++ int timeout; ++ ++ if (!ath11k_core_coldboot_cal_support(ab) || ab->qmi.cal_done || ++ ab->hw_params.cbcal_restart_fw == 0) ++ return 0; ++ ++ ath11k_dbg(ab, ATH11K_DBG_QMI, "wait for cold boot done\n"); ++ ++ timeout = wait_event_timeout(ab->qmi.cold_boot_waitq, ++ (ab->qmi.cal_done == 1), ++ ATH11K_COLD_BOOT_FW_RESET_DELAY); ++ ++ if (timeout <= 0) { ++ ath11k_warn(ab, "Coldboot Calibration timed out\n"); ++ return -ETIMEDOUT; ++ } ++ ++ /* reset the firmware */ ++ ath11k_hif_power_down(ab); ++ ath11k_hif_power_up(ab); ++ ath11k_dbg(ab, ATH11K_DBG_QMI, "exit wait for cold boot done\n"); ++ return 0; ++} ++EXPORT_SYMBOL(ath11k_qmi_fwreset_from_cold_boot); ++ + static int ath11k_qmi_process_coldboot_calibration(struct ath11k_base *ab) + { + int timeout; +--- a/drivers/net/wireless/ath/ath11k/qmi.h ++++ b/drivers/net/wireless/ath/ath11k/qmi.h +@@ -37,7 +37,7 @@ + + #define QMI_WLANFW_MAX_DATA_SIZE_V01 6144 + #define ATH11K_FIRMWARE_MODE_OFF 4 +-#define ATH11K_COLD_BOOT_FW_RESET_DELAY (40 * HZ) ++#define ATH11K_COLD_BOOT_FW_RESET_DELAY (60 * HZ) + + #define ATH11K_QMI_DEVICE_BAR_SIZE 0x200000 + +@@ -519,5 +519,6 @@ void ath11k_qmi_msg_recv_work(struct wor + void ath11k_qmi_deinit_service(struct ath11k_base *ab); + int ath11k_qmi_init_service(struct ath11k_base *ab); + void ath11k_qmi_free_resource(struct ath11k_base *ab); ++int ath11k_qmi_fwreset_from_cold_boot(struct ath11k_base *ab); + + #endif diff --git a/package/kernel/mac80211/patches/ath11k/0093-wifi-ath11k-Remove-cal_done-check-during-probe.patch b/package/kernel/mac80211/patches/ath11k/0093-wifi-ath11k-Remove-cal_done-check-during-probe.patch new file mode 100644 index 00000000000000..513ea3f0b9af44 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0093-wifi-ath11k-Remove-cal_done-check-during-probe.patch @@ -0,0 +1,33 @@ +From 13329d0cb7212b058bd8451a99d215a8f97645ea Mon Sep 17 00:00:00 2001 +From: Seevalamuthu Mariappan +Date: Wed, 26 Jul 2023 19:40:32 +0530 +Subject: [PATCH] wifi: ath11k: Remove cal_done check during probe + +In some race conditions, calibration done QMI message is received even +before host wait starts for calibration to be done. +Due to this, resetting firmware was not performed after calibration. + +Hence, remove cal_done check in ath11k_qmi_fwreset_from_cold_boot() +as this is called only from probe. + +Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.7.0.1-01744-QCAHKSWPL_SILICONZ-1 + +Signed-off-by: Seevalamuthu Mariappan +Signed-off-by: Raj Kumar Bhagat +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230726141032.3061-4-quic_rajkbhag@quicinc.com +--- + drivers/net/wireless/ath/ath11k/qmi.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/wireless/ath/ath11k/qmi.c ++++ b/drivers/net/wireless/ath/ath11k/qmi.c +@@ -2847,7 +2847,7 @@ int ath11k_qmi_fwreset_from_cold_boot(st + { + int timeout; + +- if (!ath11k_core_coldboot_cal_support(ab) || ab->qmi.cal_done || ++ if (!ath11k_core_coldboot_cal_support(ab) || + ab->hw_params.cbcal_restart_fw == 0) + return 0; + diff --git a/package/kernel/mac80211/patches/ath11k/0094-wifi-ath11k-mhi-add-a-warning-message-for-MHI_CB_EE.patch b/package/kernel/mac80211/patches/ath11k/0094-wifi-ath11k-mhi-add-a-warning-message-for-MHI_CB_EE.patch new file mode 100644 index 00000000000000..e1286c9537ce7f --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0094-wifi-ath11k-mhi-add-a-warning-message-for-MHI_CB_EE.patch @@ -0,0 +1,34 @@ +From 4a93b554cf9fa64faa7cf164c0d32fc3ce67108b Mon Sep 17 00:00:00 2001 +From: Arowa Suliman +Date: Sat, 26 Aug 2023 08:42:42 +0300 +Subject: [PATCH] wifi: ath11k: mhi: add a warning message for MHI_CB_EE_RDDM + crash + +Currently, the ath11k driver does not print a crash signature when a +MHI_CB_EE_RDDM crash happens. Checked by triggering a simulated crash using the +command and checking dmesg for logs: + +echo assert > /sys/kernel/debug/ath11k/../simulate_fw_crash + +Add a warning when firmware crash MHI_CB_EE_RDDM happens. + +Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-03125-QCAHSPSWPL_V1_V2_SILICONZ_LITE-3.6510.23 + +Signed-off-by: Arowa Suliman +Reviewed-by: Jeff Johnson +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230714001126.463127-1-arowa@chromium.org +--- + drivers/net/wireless/ath/ath11k/mhi.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/net/wireless/ath/ath11k/mhi.c ++++ b/drivers/net/wireless/ath/ath11k/mhi.c +@@ -333,6 +333,7 @@ static void ath11k_mhi_op_status_cb(stru + ath11k_warn(ab, "firmware crashed: MHI_CB_SYS_ERROR\n"); + break; + case MHI_CB_EE_RDDM: ++ ath11k_warn(ab, "firmware crashed: MHI_CB_EE_RDDM\n"); + if (!(test_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags))) + queue_work(ab->workqueue_aux, &ab->reset_work); + break; diff --git a/package/kernel/mac80211/patches/ath11k/0095-wifi-ath11k-add-chip-id-board-name-while-searching-b.patch b/package/kernel/mac80211/patches/ath11k/0095-wifi-ath11k-add-chip-id-board-name-while-searching-b.patch new file mode 100644 index 00000000000000..662e28f4ef8d18 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0095-wifi-ath11k-add-chip-id-board-name-while-searching-b.patch @@ -0,0 +1,214 @@ +From 1133af5aea588a58043244a4ecb5ce511b310356 Mon Sep 17 00:00:00 2001 +From: Wen Gong +Date: Wed, 30 Aug 2023 02:02:26 -0400 +Subject: [PATCH] wifi: ath11k: add chip id board name while searching + board-2.bin for WCN6855 + +Sometimes board-2.bin does not have the board data which matched the +parameters such as bus type, vendor, device, subsystem-vendor, +subsystem-device, qmi-chip-id and qmi-board-id, then wlan will load fail. + +Hence add another type which only matches the bus type and qmi-chip-id, +then the ratio of missing board data reduced. + +Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-03125-QCAHSPSWPL_V1_V2_SILICONZ_LITE-3.6510.23 + +Signed-off-by: Wen Gong +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230830060226.18664-1-quic_wgong@quicinc.com +--- + drivers/net/wireless/ath/ath11k/core.c | 108 ++++++++++++++++++++----- + 1 file changed, 87 insertions(+), 21 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/core.c ++++ b/drivers/net/wireless/ath/ath11k/core.c +@@ -985,9 +985,15 @@ int ath11k_core_check_dt(struct ath11k_b + return 0; + } + ++enum ath11k_bdf_name_type { ++ ATH11K_BDF_NAME_FULL, ++ ATH11K_BDF_NAME_BUS_NAME, ++ ATH11K_BDF_NAME_CHIP_ID, ++}; ++ + static int __ath11k_core_create_board_name(struct ath11k_base *ab, char *name, + size_t name_len, bool with_variant, +- bool bus_type_mode) ++ enum ath11k_bdf_name_type name_type) + { + /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */ + char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = { 0 }; +@@ -998,11 +1004,8 @@ static int __ath11k_core_create_board_na + + switch (ab->id.bdf_search) { + case ATH11K_BDF_SEARCH_BUS_AND_BOARD: +- if (bus_type_mode) +- scnprintf(name, name_len, +- "bus=%s", +- ath11k_bus_str(ab->hif.bus)); +- else ++ switch (name_type) { ++ case ATH11K_BDF_NAME_FULL: + scnprintf(name, name_len, + "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x,qmi-chip-id=%d,qmi-board-id=%d%s", + ath11k_bus_str(ab->hif.bus), +@@ -1012,6 +1015,19 @@ static int __ath11k_core_create_board_na + ab->qmi.target.chip_id, + ab->qmi.target.board_id, + variant); ++ break; ++ case ATH11K_BDF_NAME_BUS_NAME: ++ scnprintf(name, name_len, ++ "bus=%s", ++ ath11k_bus_str(ab->hif.bus)); ++ break; ++ case ATH11K_BDF_NAME_CHIP_ID: ++ scnprintf(name, name_len, ++ "bus=%s,qmi-chip-id=%d", ++ ath11k_bus_str(ab->hif.bus), ++ ab->qmi.target.chip_id); ++ break; ++ } + break; + default: + scnprintf(name, name_len, +@@ -1030,19 +1046,29 @@ static int __ath11k_core_create_board_na + static int ath11k_core_create_board_name(struct ath11k_base *ab, char *name, + size_t name_len) + { +- return __ath11k_core_create_board_name(ab, name, name_len, true, false); ++ return __ath11k_core_create_board_name(ab, name, name_len, true, ++ ATH11K_BDF_NAME_FULL); + } + + static int ath11k_core_create_fallback_board_name(struct ath11k_base *ab, char *name, + size_t name_len) + { +- return __ath11k_core_create_board_name(ab, name, name_len, false, false); ++ return __ath11k_core_create_board_name(ab, name, name_len, false, ++ ATH11K_BDF_NAME_FULL); + } + + static int ath11k_core_create_bus_type_board_name(struct ath11k_base *ab, char *name, + size_t name_len) + { +- return __ath11k_core_create_board_name(ab, name, name_len, false, true); ++ return __ath11k_core_create_board_name(ab, name, name_len, false, ++ ATH11K_BDF_NAME_BUS_NAME); ++} ++ ++static int ath11k_core_create_chip_id_board_name(struct ath11k_base *ab, char *name, ++ size_t name_len) ++{ ++ return __ath11k_core_create_board_name(ab, name, name_len, false, ++ ATH11K_BDF_NAME_CHIP_ID); + } + + const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab, +@@ -1289,16 +1315,21 @@ int ath11k_core_fetch_board_data_api_1(s + #define BOARD_NAME_SIZE 200 + int ath11k_core_fetch_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd) + { +- char boardname[BOARD_NAME_SIZE], fallback_boardname[BOARD_NAME_SIZE]; ++ char *boardname = NULL, *fallback_boardname = NULL, *chip_id_boardname = NULL; + char *filename, filepath[100]; +- int ret; ++ int ret = 0; + + filename = ATH11K_BOARD_API2_FILE; ++ boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL); ++ if (!boardname) { ++ ret = -ENOMEM; ++ goto exit; ++ } + +- ret = ath11k_core_create_board_name(ab, boardname, sizeof(boardname)); ++ ret = ath11k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE); + if (ret) { + ath11k_err(ab, "failed to create board name: %d", ret); +- return ret; ++ goto exit; + } + + ab->bd_api = 2; +@@ -1307,13 +1338,19 @@ int ath11k_core_fetch_bdf(struct ath11k_ + ATH11K_BD_IE_BOARD_NAME, + ATH11K_BD_IE_BOARD_DATA); + if (!ret) +- goto success; ++ goto exit; ++ ++ fallback_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL); ++ if (!fallback_boardname) { ++ ret = -ENOMEM; ++ goto exit; ++ } + + ret = ath11k_core_create_fallback_board_name(ab, fallback_boardname, +- sizeof(fallback_boardname)); ++ BOARD_NAME_SIZE); + if (ret) { + ath11k_err(ab, "failed to create fallback board name: %d", ret); +- return ret; ++ goto exit; + } + + ret = ath11k_core_fetch_board_data_api_n(ab, bd, fallback_boardname, +@@ -1321,7 +1358,28 @@ int ath11k_core_fetch_bdf(struct ath11k_ + ATH11K_BD_IE_BOARD_NAME, + ATH11K_BD_IE_BOARD_DATA); + if (!ret) +- goto success; ++ goto exit; ++ ++ chip_id_boardname = kzalloc(BOARD_NAME_SIZE, GFP_KERNEL); ++ if (!chip_id_boardname) { ++ ret = -ENOMEM; ++ goto exit; ++ } ++ ++ ret = ath11k_core_create_chip_id_board_name(ab, chip_id_boardname, ++ BOARD_NAME_SIZE); ++ if (ret) { ++ ath11k_err(ab, "failed to create chip id board name: %d", ret); ++ goto exit; ++ } ++ ++ ret = ath11k_core_fetch_board_data_api_n(ab, bd, chip_id_boardname, ++ ATH11K_BD_IE_BOARD, ++ ATH11K_BD_IE_BOARD_NAME, ++ ATH11K_BD_IE_BOARD_DATA); ++ ++ if (!ret) ++ goto exit; + + ab->bd_api = 1; + ret = ath11k_core_fetch_board_data_api_1(ab, bd, ATH11K_DEFAULT_BOARD_FILE); +@@ -1334,14 +1392,22 @@ int ath11k_core_fetch_bdf(struct ath11k_ + ath11k_err(ab, "failed to fetch board data for %s from %s\n", + fallback_boardname, filepath); + ++ ath11k_err(ab, "failed to fetch board data for %s from %s\n", ++ chip_id_boardname, filepath); ++ + ath11k_err(ab, "failed to fetch board.bin from %s\n", + ab->hw_params.fw.dir); +- return ret; + } + +-success: +- ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", ab->bd_api); +- return 0; ++exit: ++ kfree(boardname); ++ kfree(fallback_boardname); ++ kfree(chip_id_boardname); ++ ++ if (!ret) ++ ath11k_dbg(ab, ATH11K_DBG_BOOT, "using board api %d\n", ab->bd_api); ++ ++ return ret; + } + + int ath11k_core_fetch_regdb(struct ath11k_base *ab, struct ath11k_board_data *bd) diff --git a/package/kernel/mac80211/patches/ath11k/0096-wifi-ath11k-fix-boot-failure-with-one-MSI-vector.patch b/package/kernel/mac80211/patches/ath11k/0096-wifi-ath11k-fix-boot-failure-with-one-MSI-vector.patch new file mode 100644 index 00000000000000..9101a1ea1ce557 --- /dev/null +++ b/package/kernel/mac80211/patches/ath11k/0096-wifi-ath11k-fix-boot-failure-with-one-MSI-vector.patch @@ -0,0 +1,103 @@ +From 39564b475ac5a589e6c22c43a08cbd283c295d2c Mon Sep 17 00:00:00 2001 +From: Baochen Qiang +Date: Thu, 7 Sep 2023 09:56:06 +0800 +Subject: [PATCH] wifi: ath11k: fix boot failure with one MSI vector + +Commit 5b32b6dd96633 ("ath11k: Remove core PCI references from +PCI common code") breaks with one MSI vector because it moves +affinity setting after IRQ request, see below log: + +[ 1417.278835] ath11k_pci 0000:02:00.0: failed to receive control response completion, polling.. +[ 1418.302829] ath11k_pci 0000:02:00.0: Service connect timeout +[ 1418.302833] ath11k_pci 0000:02:00.0: failed to connect to HTT: -110 +[ 1418.303669] ath11k_pci 0000:02:00.0: failed to start core: -110 + +The detail is, if do affinity request after IRQ activated, +which is done in request_irq(), kernel caches that request and +returns success directly. Later when a subsequent MHI interrupt is +fired, kernel will do the real affinity setting work, as a result, +changs the MSI vector. However at that time host has configured +old vector to hardware, so host never receives CE or DP interrupts. + +Fix it by setting affinity before registering MHI controller +where host is, for the first time, doing IRQ request. + +Tested-on: WCN6855 hw2.0 PCI WLAN.HSP.1.1-03125-QCAHSPSWPL_V1_V2_SILICONZ_LITE-3 +Tested-on: WCN6855 hw2.1 PCI WLAN.HSP.1.1-03125-QCAHSPSWPL_V1_V2_SILICONZ_LITE-3.6510.23 +Tested-on: WCN6750 hw1.0 AHB WLAN.MSL.1.0.1-01160-QCAMSLSWPLZ-1 + +Fixes: 5b32b6dd9663 ("ath11k: Remove core PCI references from PCI common code") +Signed-off-by: Baochen Qiang +Acked-by: Jeff Johnson +Signed-off-by: Kalle Valo +Link: https://lore.kernel.org/r/20230907015606.16297-1-quic_bqiang@quicinc.com +--- + drivers/net/wireless/ath/ath11k/pci.c | 24 ++++++++++++------------ + 1 file changed, 12 insertions(+), 12 deletions(-) + +--- a/drivers/net/wireless/ath/ath11k/pci.c ++++ b/drivers/net/wireless/ath/ath11k/pci.c +@@ -852,10 +852,16 @@ unsupported_wcn6855_soc: + if (ret) + goto err_pci_disable_msi; + ++ ret = ath11k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0)); ++ if (ret) { ++ ath11k_err(ab, "failed to set irq affinity %d\n", ret); ++ goto err_pci_disable_msi; ++ } ++ + ret = ath11k_mhi_register(ab_pci); + if (ret) { + ath11k_err(ab, "failed to register mhi: %d\n", ret); +- goto err_pci_disable_msi; ++ goto err_irq_affinity_cleanup; + } + + ret = ath11k_hal_srng_init(ab); +@@ -876,12 +882,6 @@ unsupported_wcn6855_soc: + goto err_ce_free; + } + +- ret = ath11k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0)); +- if (ret) { +- ath11k_err(ab, "failed to set irq affinity %d\n", ret); +- goto err_free_irq; +- } +- + /* kernel may allocate a dummy vector before request_irq and + * then allocate a real vector when request_irq is called. + * So get msi_data here again to avoid spurious interrupt +@@ -890,20 +890,17 @@ unsupported_wcn6855_soc: + ret = ath11k_pci_config_msi_data(ab_pci); + if (ret) { + ath11k_err(ab, "failed to config msi_data: %d\n", ret); +- goto err_irq_affinity_cleanup; ++ goto err_free_irq; + } + + ret = ath11k_core_init(ab); + if (ret) { + ath11k_err(ab, "failed to init core: %d\n", ret); +- goto err_irq_affinity_cleanup; ++ goto err_free_irq; + } + ath11k_qmi_fwreset_from_cold_boot(ab); + return 0; + +-err_irq_affinity_cleanup: +- ath11k_pci_set_irq_affinity_hint(ab_pci, NULL); +- + err_free_irq: + ath11k_pcic_free_irq(ab); + +@@ -916,6 +913,9 @@ err_hal_srng_deinit: + err_mhi_unregister: + ath11k_mhi_unregister(ab_pci); + ++err_irq_affinity_cleanup: ++ ath11k_pci_set_irq_affinity_hint(ab_pci, NULL); ++ + err_pci_disable_msi: + ath11k_pci_free_msi(ab_pci); + diff --git a/package/kernel/mac80211/patches/ath11k/100-wifi-ath11k-use-unique-QRTR-instance-ID.patch b/package/kernel/mac80211/patches/ath11k/100-wifi-ath11k-use-unique-QRTR-instance-ID.patch index 39d5a61d5a1ed8..30472b322987d1 100644 --- a/package/kernel/mac80211/patches/ath11k/100-wifi-ath11k-use-unique-QRTR-instance-ID.patch +++ b/package/kernel/mac80211/patches/ath11k/100-wifi-ath11k-use-unique-QRTR-instance-ID.patch @@ -93,7 +93,7 @@ Signed-off-by: Robert Marko default: return "UNKNOWN"; } -@@ -336,27 +366,14 @@ static void ath11k_mhi_op_status_cb(stru +@@ -337,27 +367,14 @@ static void ath11k_mhi_op_status_cb(stru if (!(test_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags))) queue_work(ab->workqueue_aux, &ab->reset_work); break; @@ -138,7 +138,7 @@ Signed-off-by: Robert Marko int ath11k_mhi_register(struct ath11k_pci *ar_pci); --- a/drivers/net/wireless/ath/ath11k/pci.c +++ b/drivers/net/wireless/ath/ath11k/pci.c -@@ -370,13 +370,20 @@ static void ath11k_pci_sw_reset(struct a +@@ -371,13 +371,20 @@ static void ath11k_pci_sw_reset(struct a static void ath11k_pci_init_qmi_ce_config(struct ath11k_base *ab) { struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; diff --git a/package/kernel/mac80211/patches/ath11k/901-wifi-ath11k-pci-fix-compilation-in-5.16-and-older.patch b/package/kernel/mac80211/patches/ath11k/901-wifi-ath11k-pci-fix-compilation-in-5.16-and-older.patch index 72156563899370..9a0ca80090da8d 100644 --- a/package/kernel/mac80211/patches/ath11k/901-wifi-ath11k-pci-fix-compilation-in-5.16-and-older.patch +++ b/package/kernel/mac80211/patches/ath11k/901-wifi-ath11k-pci-fix-compilation-in-5.16-and-older.patch @@ -15,7 +15,7 @@ Signed-off-by: Robert Marko --- a/drivers/net/wireless/ath/ath11k/pci.c +++ b/drivers/net/wireless/ath/ath11k/pci.c -@@ -458,7 +458,11 @@ static int ath11k_pci_alloc_msi(struct a +@@ -459,7 +459,11 @@ static int ath11k_pci_alloc_msi(struct a pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO, &ab->pci.msi.addr_lo); diff --git a/package/kernel/mac80211/patches/ath11k/902-ath11k-Disable-coldboot-calibration-for-IPQ8074.patch b/package/kernel/mac80211/patches/ath11k/902-ath11k-Disable-coldboot-calibration-for-IPQ8074.patch index 5454fa75e4c62d..0c92fa914f7cd3 100644 --- a/package/kernel/mac80211/patches/ath11k/902-ath11k-Disable-coldboot-calibration-for-IPQ8074.patch +++ b/package/kernel/mac80211/patches/ath11k/902-ath11k-Disable-coldboot-calibration-for-IPQ8074.patch @@ -13,12 +13,14 @@ Signed-off-by: Robert Marko --- a/drivers/net/wireless/ath/ath11k/core.c +++ b/drivers/net/wireless/ath/ath11k/core.c -@@ -86,7 +86,7 @@ static const struct ath11k_hw_params ath +@@ -86,8 +86,8 @@ static const struct ath11k_hw_params ath .supports_shadow_regs = false, .idle_ps = false, .supports_sta_ps = false, -- .cold_boot_calib = true, -+ .cold_boot_calib = false, +- .coldboot_cal_mm = true, +- .coldboot_cal_ftm = true, ++ .coldboot_cal_mm = false, ++ .coldboot_cal_ftm = false, .cbcal_restart_fw = true, .fw_mem_mode = 0, .num_vdevs = 16 + 1, diff --git a/package/kernel/mac80211/patches/ath11k/903-ath11k-support-setting-FW-memory-mode-via-DT.patch b/package/kernel/mac80211/patches/ath11k/903-ath11k-support-setting-FW-memory-mode-via-DT.patch index 22c2493ca9d1e0..71373b2136f76a 100644 --- a/package/kernel/mac80211/patches/ath11k/903-ath11k-support-setting-FW-memory-mode-via-DT.patch +++ b/package/kernel/mac80211/patches/ath11k/903-ath11k-support-setting-FW-memory-mode-via-DT.patch @@ -31,7 +31,7 @@ Signed-off-by: Robert Marko { .hw_rev = ATH11K_HW_IPQ8074, .name = "ipq8074 hw2.0", -@@ -1953,7 +1953,8 @@ static void ath11k_core_reset(struct wor +@@ -2040,7 +2040,8 @@ static void ath11k_core_reset(struct wor static int ath11k_init_hw_params(struct ath11k_base *ab) { const struct ath11k_hw_params *hw_params = NULL; @@ -41,7 +41,7 @@ Signed-off-by: Robert Marko for (i = 0; i < ARRAY_SIZE(ath11k_hw_params); i++) { hw_params = &ath11k_hw_params[i]; -@@ -1969,7 +1970,30 @@ static int ath11k_init_hw_params(struct +@@ -2056,7 +2057,31 @@ static int ath11k_init_hw_params(struct ab->hw_params = *hw_params; @@ -62,7 +62,8 @@ Signed-off-by: Robert Marko + ab->hw_params.fw_mem_mode = 2; + ab->hw_params.num_vdevs = 8; + ab->hw_params.num_peers = 128; -+ ab->hw_params.cold_boot_calib = false; ++ ab->hw_params.coldboot_cal_mm = false; ++ ab->hw_params.coldboot_cal_ftm = false; + } else + ath11k_info(ab, "Unsupported FW memory mode: %u\n", fw_mem_mode); + } diff --git a/package/kernel/mac80211/patches/ath9k/500-ath9k_eeprom_debugfs.patch b/package/kernel/mac80211/patches/ath9k/500-ath9k_eeprom_debugfs.patch index b32535738e165b..e2bbb4a1b1db58 100644 --- a/package/kernel/mac80211/patches/ath9k/500-ath9k_eeprom_debugfs.patch +++ b/package/kernel/mac80211/patches/ath9k/500-ath9k_eeprom_debugfs.patch @@ -54,7 +54,7 @@ int ath9k_init_debug(struct ath_hw *ah) { struct ath_common *common = ath9k_hw_common(ah); -@@ -1432,6 +1480,8 @@ int ath9k_init_debug(struct ath_hw *ah) +@@ -1432,6 +1479,8 @@ int ath9k_init_debug(struct ath_hw *ah) ath9k_tx99_init_debug(sc); ath9k_cmn_spectral_init_debug(&sc->spec_priv, sc->debug.debugfs_phy); diff --git a/package/kernel/mac80211/patches/ath9k/512-ath9k_channelbw_debugfs.patch b/package/kernel/mac80211/patches/ath9k/512-ath9k_channelbw_debugfs.patch index a871e458a4e7e9..0c8b6920c4fa70 100644 --- a/package/kernel/mac80211/patches/ath9k/512-ath9k_channelbw_debugfs.patch +++ b/package/kernel/mac80211/patches/ath9k/512-ath9k_channelbw_debugfs.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/ath/ath9k/debug.c +++ b/drivers/net/wireless/ath/ath9k/debug.c -@@ -1461,6 +1461,52 @@ static const struct file_operations fops +@@ -1460,6 +1460,52 @@ static const struct file_operations fops .owner = THIS_MODULE }; @@ -53,7 +53,7 @@ int ath9k_init_debug(struct ath_hw *ah) { struct ath_common *common = ath9k_hw_common(ah); -@@ -1482,6 +1528,8 @@ int ath9k_init_debug(struct ath_hw *ah) +@@ -1481,6 +1527,8 @@ int ath9k_init_debug(struct ath_hw *ah) debugfs_create_file("eeprom", S_IRUSR, sc->debug.debugfs_phy, sc, &fops_eeprom); diff --git a/package/kernel/mac80211/patches/ath9k/530-ath9k_extra_leds.patch b/package/kernel/mac80211/patches/ath9k/530-ath9k_extra_leds.patch index 74506657e0f26c..1fe00410228073 100644 --- a/package/kernel/mac80211/patches/ath9k/530-ath9k_extra_leds.patch +++ b/package/kernel/mac80211/patches/ath9k/530-ath9k_extra_leds.patch @@ -192,7 +192,7 @@ #endif --- a/drivers/net/wireless/ath/ath9k/debug.c +++ b/drivers/net/wireless/ath/ath9k/debug.c -@@ -1506,6 +1506,61 @@ static const struct file_operations fops +@@ -1505,6 +1505,61 @@ static const struct file_operations fops .llseek = default_llseek, }; @@ -254,7 +254,7 @@ int ath9k_init_debug(struct ath_hw *ah) { -@@ -1530,6 +1585,10 @@ int ath9k_init_debug(struct ath_hw *ah) +@@ -1529,6 +1584,10 @@ int ath9k_init_debug(struct ath_hw *ah) &fops_eeprom); debugfs_create_file("chanbw", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy, sc, &fops_chanbw); diff --git a/package/kernel/mac80211/patches/ath9k/542-ath9k_debugfs_diag.patch b/package/kernel/mac80211/patches/ath9k/542-ath9k_debugfs_diag.patch index e09bbc08eafb4b..70f7ee36592c2b 100644 --- a/package/kernel/mac80211/patches/ath9k/542-ath9k_debugfs_diag.patch +++ b/package/kernel/mac80211/patches/ath9k/542-ath9k_debugfs_diag.patch @@ -1,6 +1,6 @@ --- a/drivers/net/wireless/ath/ath9k/debug.c +++ b/drivers/net/wireless/ath/ath9k/debug.c -@@ -1562,6 +1562,50 @@ static const struct file_operations fops +@@ -1561,6 +1561,50 @@ static const struct file_operations fops #endif @@ -51,7 +51,7 @@ int ath9k_init_debug(struct ath_hw *ah) { struct ath_common *common = ath9k_hw_common(ah); -@@ -1589,6 +1633,8 @@ int ath9k_init_debug(struct ath_hw *ah) +@@ -1588,6 +1632,8 @@ int ath9k_init_debug(struct ath_hw *ah) debugfs_create_file("gpio_led", S_IWUSR, sc->debug.debugfs_phy, sc, &fops_gpio_led); #endif diff --git a/package/kernel/mac80211/patches/build/099-netlink-range.patch b/package/kernel/mac80211/patches/build/099-netlink-range.patch index 9f0efa664423bf..0df2b38fa1ea0e 100644 --- a/package/kernel/mac80211/patches/build/099-netlink-range.patch +++ b/package/kernel/mac80211/patches/build/099-netlink-range.patch @@ -1,91 +1,91 @@ ---- a/net/wireless/nl80211.c -+++ b/net/wireless/nl80211.c -@@ -421,8 +421,13 @@ static const struct nla_policy - nl80211_fils_discovery_policy[NL80211_FILS_DISCOVERY_ATTR_MAX + 1] = { - [NL80211_FILS_DISCOVERY_ATTR_INT_MIN] = NLA_POLICY_MAX(NLA_U32, 10000), - [NL80211_FILS_DISCOVERY_ATTR_INT_MAX] = NLA_POLICY_MAX(NLA_U32, 10000), -+#if LINUX_VERSION_IS_GEQ(5,10,0) - [NL80211_FILS_DISCOVERY_ATTR_TMPL] = - NLA_POLICY_BINARY_RANGE(NL80211_FILS_DISCOVERY_TMPL_MIN_LEN, IEEE80211_MAX_DATA_LEN), -+#else -+ [NL80211_FILS_DISCOVERY_ATTR_TMPL] = { .type = NLA_BINARY, -+ .len = IEEE80211_MAX_DATA_LEN }, -+#endif - }; - - static const struct nla_policy -@@ -533,7 +538,11 @@ static const struct nla_policy nl80211_policy[NUM_NL80211_ATTR] = { - [NL80211_ATTR_MPATH_NEXT_HOP] = NLA_POLICY_ETH_ADDR_COMPAT, - - /* allow 3 for NUL-termination, we used to declare this NLA_STRING */ -+#if LINUX_VERSION_IS_GEQ(5,10,0) - [NL80211_ATTR_REG_ALPHA2] = NLA_POLICY_BINARY_RANGE(2, 3), -+#else -+ [NL80211_ATTR_REG_ALPHA2] = { .type = NLA_STRING, .len = 2 }, -+#endif - [NL80211_ATTR_REG_RULES] = { .type = NLA_NESTED }, - - [NL80211_ATTR_BSS_CTS_PROT] = { .type = NLA_U8 }, -@@ -679,14 +688,24 @@ static const struct nla_policy nl80211_policy[NUM_NL80211_ATTR] = { - * The value of the Length field of the Supported Operating - * Classes element is between 2 and 253. - */ -+#if LINUX_VERSION_IS_GEQ(5,10,0) - [NL80211_ATTR_STA_SUPPORTED_OPER_CLASSES] = - NLA_POLICY_BINARY_RANGE(2, 253), -+#else -+ [NL80211_ATTR_STA_SUPPORTED_OPER_CLASSES] = -+ { .type = NLA_BINARY }, -+#endif - [NL80211_ATTR_HANDLE_DFS] = { .type = NLA_FLAG }, - [NL80211_ATTR_OPMODE_NOTIF] = { .type = NLA_U8 }, - [NL80211_ATTR_VENDOR_ID] = { .type = NLA_U32 }, - [NL80211_ATTR_VENDOR_SUBCMD] = { .type = NLA_U32 }, - [NL80211_ATTR_VENDOR_DATA] = { .type = NLA_BINARY }, -+#if LINUX_VERSION_IS_GEQ(5,10,0) - [NL80211_ATTR_QOS_MAP] = NLA_POLICY_BINARY_RANGE(IEEE80211_QOS_MAP_LEN_MIN, IEEE80211_QOS_MAP_LEN_MAX), -+#else -+ [NL80211_ATTR_QOS_MAP] = { .type = NLA_BINARY, -+ .len = IEEE80211_QOS_MAP_LEN_MAX }, -+#endif - [NL80211_ATTR_MAC_HINT] = NLA_POLICY_EXACT_LEN_WARN(ETH_ALEN), - [NL80211_ATTR_WIPHY_FREQ_HINT] = { .type = NLA_U32 }, - [NL80211_ATTR_TDLS_PEER_CAPABILITY] = { .type = NLA_U32 }, -@@ -741,9 +760,14 @@ static const struct nla_policy nl80211_policy[NUM_NL80211_ATTR] = { - [NL80211_ATTR_TXQ_LIMIT] = { .type = NLA_U32 }, - [NL80211_ATTR_TXQ_MEMORY_LIMIT] = { .type = NLA_U32 }, - [NL80211_ATTR_TXQ_QUANTUM] = { .type = NLA_U32 }, -+#if LINUX_VERSION_IS_GEQ(5,10,0) - [NL80211_ATTR_HE_CAPABILITY] = - NLA_POLICY_VALIDATE_FN(NLA_BINARY, validate_he_capa, - NL80211_HE_MAX_CAPABILITY_LEN), -+#else -+ [NL80211_ATTR_HE_CAPABILITY] = { .type = NLA_BINARY, -+ .len = NL80211_HE_MAX_CAPABILITY_LEN }, -+#endif - [NL80211_ATTR_FTM_RESPONDER] = - NLA_POLICY_NESTED(nl80211_ftm_responder_policy), - [NL80211_ATTR_TIMEOUT] = NLA_POLICY_MIN(NLA_U32, 1), -@@ -16409,9 +16433,11 @@ static const struct genl_ops nl80211_ops[] = { - /* can be retrieved by unprivileged users */ - .internal_flags = IFLAGS(NL80211_FLAG_NEED_WIPHY), - }, -+#if LINUX_VERSION_IS_GEQ(5,10,0) - }; - - static const struct genl_small_ops nl80211_small_ops[] = { -+#endif - { - .cmd = NL80211_CMD_SET_WIPHY, - .validate = GENL_DONT_VALIDATE_STRICT | GENL_DONT_VALIDATE_DUMP, -@@ -17248,8 +17274,10 @@ static struct genl_family nl80211_fam __genl_ro_after_init = { - .module = THIS_MODULE, - .ops = nl80211_ops, - .n_ops = ARRAY_SIZE(nl80211_ops), -+#if LINUX_VERSION_IS_GEQ(5,10,0) - .small_ops = nl80211_small_ops, - .n_small_ops = ARRAY_SIZE(nl80211_small_ops), -+#endif - #if LINUX_VERSION_IS_GEQ(6,1,0) - .resv_start_op = NL80211_CMD_REMOVE_LINK_STA + 1, - #endif +--- a/net/wireless/nl80211.c ++++ b/net/wireless/nl80211.c +@@ -421,8 +421,13 @@ static const struct nla_policy + nl80211_fils_discovery_policy[NL80211_FILS_DISCOVERY_ATTR_MAX + 1] = { + [NL80211_FILS_DISCOVERY_ATTR_INT_MIN] = NLA_POLICY_MAX(NLA_U32, 10000), + [NL80211_FILS_DISCOVERY_ATTR_INT_MAX] = NLA_POLICY_MAX(NLA_U32, 10000), ++#if LINUX_VERSION_IS_GEQ(5,10,0) + [NL80211_FILS_DISCOVERY_ATTR_TMPL] = + NLA_POLICY_BINARY_RANGE(NL80211_FILS_DISCOVERY_TMPL_MIN_LEN, IEEE80211_MAX_DATA_LEN), ++#else ++ [NL80211_FILS_DISCOVERY_ATTR_TMPL] = { .type = NLA_BINARY, ++ .len = IEEE80211_MAX_DATA_LEN }, ++#endif + }; + + static const struct nla_policy +@@ -533,7 +538,11 @@ static const struct nla_policy nl80211_p + [NL80211_ATTR_MPATH_NEXT_HOP] = NLA_POLICY_ETH_ADDR_COMPAT, + + /* allow 3 for NUL-termination, we used to declare this NLA_STRING */ ++#if LINUX_VERSION_IS_GEQ(5,10,0) + [NL80211_ATTR_REG_ALPHA2] = NLA_POLICY_BINARY_RANGE(2, 3), ++#else ++ [NL80211_ATTR_REG_ALPHA2] = { .type = NLA_STRING, .len = 2 }, ++#endif + [NL80211_ATTR_REG_RULES] = { .type = NLA_NESTED }, + + [NL80211_ATTR_BSS_CTS_PROT] = { .type = NLA_U8 }, +@@ -679,14 +688,24 @@ static const struct nla_policy nl80211_p + * The value of the Length field of the Supported Operating + * Classes element is between 2 and 253. + */ ++#if LINUX_VERSION_IS_GEQ(5,10,0) + [NL80211_ATTR_STA_SUPPORTED_OPER_CLASSES] = + NLA_POLICY_BINARY_RANGE(2, 253), ++#else ++ [NL80211_ATTR_STA_SUPPORTED_OPER_CLASSES] = ++ { .type = NLA_BINARY }, ++#endif + [NL80211_ATTR_HANDLE_DFS] = { .type = NLA_FLAG }, + [NL80211_ATTR_OPMODE_NOTIF] = { .type = NLA_U8 }, + [NL80211_ATTR_VENDOR_ID] = { .type = NLA_U32 }, + [NL80211_ATTR_VENDOR_SUBCMD] = { .type = NLA_U32 }, + [NL80211_ATTR_VENDOR_DATA] = { .type = NLA_BINARY }, ++#if LINUX_VERSION_IS_GEQ(5,10,0) + [NL80211_ATTR_QOS_MAP] = NLA_POLICY_BINARY_RANGE(IEEE80211_QOS_MAP_LEN_MIN, IEEE80211_QOS_MAP_LEN_MAX), ++#else ++ [NL80211_ATTR_QOS_MAP] = { .type = NLA_BINARY, ++ .len = IEEE80211_QOS_MAP_LEN_MAX }, ++#endif + [NL80211_ATTR_MAC_HINT] = NLA_POLICY_EXACT_LEN_WARN(ETH_ALEN), + [NL80211_ATTR_WIPHY_FREQ_HINT] = { .type = NLA_U32 }, + [NL80211_ATTR_TDLS_PEER_CAPABILITY] = { .type = NLA_U32 }, +@@ -741,9 +760,14 @@ static const struct nla_policy nl80211_p + [NL80211_ATTR_TXQ_LIMIT] = { .type = NLA_U32 }, + [NL80211_ATTR_TXQ_MEMORY_LIMIT] = { .type = NLA_U32 }, + [NL80211_ATTR_TXQ_QUANTUM] = { .type = NLA_U32 }, ++#if LINUX_VERSION_IS_GEQ(5,10,0) + [NL80211_ATTR_HE_CAPABILITY] = + NLA_POLICY_VALIDATE_FN(NLA_BINARY, validate_he_capa, + NL80211_HE_MAX_CAPABILITY_LEN), ++#else ++ [NL80211_ATTR_HE_CAPABILITY] = { .type = NLA_BINARY, ++ .len = NL80211_HE_MAX_CAPABILITY_LEN }, ++#endif + [NL80211_ATTR_FTM_RESPONDER] = + NLA_POLICY_NESTED(nl80211_ftm_responder_policy), + [NL80211_ATTR_TIMEOUT] = NLA_POLICY_MIN(NLA_U32, 1), +@@ -16392,9 +16416,11 @@ static const struct genl_ops nl80211_ops + /* can be retrieved by unprivileged users */ + .internal_flags = IFLAGS(NL80211_FLAG_NEED_WIPHY), + }, ++#if LINUX_VERSION_IS_GEQ(5,10,0) + }; + + static const struct genl_small_ops nl80211_small_ops[] = { ++#endif + { + .cmd = NL80211_CMD_SET_WIPHY, + .validate = GENL_DONT_VALIDATE_STRICT | GENL_DONT_VALIDATE_DUMP, +@@ -17231,8 +17257,10 @@ static struct genl_family nl80211_fam __ + .module = THIS_MODULE, + .ops = nl80211_ops, + .n_ops = ARRAY_SIZE(nl80211_ops), ++#if LINUX_VERSION_IS_GEQ(5,10,0) + .small_ops = nl80211_small_ops, + .n_small_ops = ARRAY_SIZE(nl80211_small_ops), ++#endif + #if LINUX_VERSION_IS_GEQ(6,1,0) + .resv_start_op = NL80211_CMD_REMOVE_LINK_STA + 1, + #endif diff --git a/package/kernel/mac80211/patches/subsys/401-mac80211-allow-vht-on-2g.patch b/package/kernel/mac80211/patches/subsys/401-mac80211-allow-vht-on-2g.patch index bc929c43509968..5d8742ba9521ac 100644 --- a/package/kernel/mac80211/patches/subsys/401-mac80211-allow-vht-on-2g.patch +++ b/package/kernel/mac80211/patches/subsys/401-mac80211-allow-vht-on-2g.patch @@ -12,7 +12,7 @@ have_80mhz = true; --- a/net/mac80211/util.c +++ b/net/mac80211/util.c -@@ -1981,7 +1981,8 @@ static int ieee80211_build_preq_ies_band +@@ -1955,7 +1955,8 @@ static int ieee80211_build_preq_ies_band /* Check if any channel in this sband supports at least 80 MHz */ for (i = 0; i < sband->n_channels; i++) { if (sband->channels[i].flags & (IEEE80211_CHAN_DISABLED | diff --git a/package/kernel/mac80211/patches/subsys/500-mac80211_configure_antenna_gain.patch b/package/kernel/mac80211/patches/subsys/500-mac80211_configure_antenna_gain.patch index 58a590682a3502..bc5e7e76cb27ce 100644 --- a/package/kernel/mac80211/patches/subsys/500-mac80211_configure_antenna_gain.patch +++ b/package/kernel/mac80211/patches/subsys/500-mac80211_configure_antenna_gain.patch @@ -129,7 +129,7 @@ local->hw.max_mtu = IEEE80211_MAX_DATA_LEN; --- a/net/wireless/nl80211.c +++ b/net/wireless/nl80211.c -@@ -799,6 +799,7 @@ static const struct nla_policy nl80211_p +@@ -823,6 +823,7 @@ static const struct nla_policy nl80211_p [NL80211_ATTR_MLD_ADDR] = NLA_POLICY_EXACT_LEN(ETH_ALEN), [NL80211_ATTR_MLO_SUPPORT] = { .type = NLA_FLAG }, [NL80211_ATTR_MAX_NUM_AKM_SUITES] = { .type = NLA_REJECT }, @@ -137,7 +137,7 @@ }; /* policy for the key attributes */ -@@ -3511,6 +3512,22 @@ static int nl80211_set_wiphy(struct sk_b +@@ -3535,6 +3536,22 @@ static int nl80211_set_wiphy(struct sk_b if (result) goto out; } diff --git a/package/kernel/mac80211/patches/subsys/800-rework-eth_hw_addr_set.patch b/package/kernel/mac80211/patches/subsys/800-rework-eth_hw_addr_set.patch index e9211db1cd5d84..20f857f2d542ee 100644 --- a/package/kernel/mac80211/patches/subsys/800-rework-eth_hw_addr_set.patch +++ b/package/kernel/mac80211/patches/subsys/800-rework-eth_hw_addr_set.patch @@ -1,6 +1,6 @@ --- a/backport-include/linux/etherdevice.h +++ b/backport-include/linux/etherdevice.h -@@ -39,7 +39,7 @@ +@@ -39,7 +39,7 @@ static inline void u64_to_ether_addr(u64 } #endif /* LINUX_VERSION_IS_LESS(4,11,0) */ diff --git a/package/wwan/driver/fibocom_QMI_WWAN/src/qmi_wwan_f.c b/package/wwan/driver/fibocom_QMI_WWAN/src/qmi_wwan_f.c index 8995e83270c2af..48efef7283509f 100755 --- a/package/wwan/driver/fibocom_QMI_WWAN/src/qmi_wwan_f.c +++ b/package/wwan/driver/fibocom_QMI_WWAN/src/qmi_wwan_f.c @@ -2096,8 +2096,8 @@ static int qmi_wwan_reset_resume(struct usb_interface *intf) static int rmnet_usb_bind(struct usbnet *dev, struct usb_interface *intf) { - dev_err(&intf->dev, "rmnet_usb_bind\n"); int status = qmi_wwan_bind(dev, intf); + dev_err(&intf->dev, "rmnet_usb_bind\n"); if (!status) { struct qmi_wwan_state *info = (void *)&dev->data; diff --git a/target/linux/armvirt/patches-5.15/701-dpaa2-eth-do-not-hold-rtnl_lock.patch b/target/linux/armvirt/patches-5.15/701-dpaa2-eth-do-not-hold-rtnl_lock.patch index 447266fa1438dc..0f6bdd10795744 100644 --- a/target/linux/armvirt/patches-5.15/701-dpaa2-eth-do-not-hold-rtnl_lock.patch +++ b/target/linux/armvirt/patches-5.15/701-dpaa2-eth-do-not-hold-rtnl_lock.patch @@ -27,7 +27,7 @@ Signed-off-by: Russell King --- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c +++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c -@@ -4217,12 +4217,10 @@ static irqreturn_t dpni_irq0_handler_thr +@@ -4215,12 +4215,10 @@ static irqreturn_t dpni_irq0_handler_thr dpaa2_eth_set_mac_addr(netdev_priv(net_dev)); dpaa2_eth_update_tx_fqids(priv); diff --git a/target/linux/ath79/patches-5.10/401-mtd-nor-support-mtd-name-from-device-tree.patch b/target/linux/ath79/patches-5.10/401-mtd-nor-support-mtd-name-from-device-tree.patch index d2aecdb9d52f67..fa5e19cd4116e1 100644 --- a/target/linux/ath79/patches-5.10/401-mtd-nor-support-mtd-name-from-device-tree.patch +++ b/target/linux/ath79/patches-5.10/401-mtd-nor-support-mtd-name-from-device-tree.patch @@ -10,7 +10,7 @@ Signed-off-by: Abhimanyu Vishwakarma --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c -@@ -3161,6 +3161,7 @@ int spi_nor_scan(struct spi_nor *nor, co +@@ -3162,6 +3162,7 @@ int spi_nor_scan(struct spi_nor *nor, co struct device *dev = nor->dev; struct mtd_info *mtd = &nor->mtd; struct device_node *np = spi_nor_get_flash_node(nor); @@ -18,7 +18,7 @@ Signed-off-by: Abhimanyu Vishwakarma int ret; int i; -@@ -3215,7 +3216,12 @@ int spi_nor_scan(struct spi_nor *nor, co +@@ -3216,7 +3217,12 @@ int spi_nor_scan(struct spi_nor *nor, co if (ret) return ret; diff --git a/target/linux/ath79/patches-5.10/910-unaligned_access_hacks.patch b/target/linux/ath79/patches-5.10/910-unaligned_access_hacks.patch index 6e92b626934c41..dea246e954d495 100644 --- a/target/linux/ath79/patches-5.10/910-unaligned_access_hacks.patch +++ b/target/linux/ath79/patches-5.10/910-unaligned_access_hacks.patch @@ -339,7 +339,7 @@ SVN-Revision: 35130 list_for_each_entry(p, head, list) { --- a/net/ipv4/tcp_output.c +++ b/net/ipv4/tcp_output.c -@@ -609,48 +609,53 @@ static void tcp_options_write(__be32 *pt +@@ -608,48 +608,53 @@ static void tcp_options_write(__be32 *pt u16 options = opts->options; /* mungable copy */ if (unlikely(OPTION_MD5 & options)) { @@ -416,7 +416,7 @@ SVN-Revision: 35130 } if (unlikely(opts->num_sack_blocks)) { -@@ -658,16 +663,17 @@ static void tcp_options_write(__be32 *pt +@@ -657,16 +662,17 @@ static void tcp_options_write(__be32 *pt tp->duplicate_sack : tp->selective_acks; int this_sack; @@ -440,7 +440,7 @@ SVN-Revision: 35130 } tp->rx_opt.dsack = 0; -@@ -680,13 +686,14 @@ static void tcp_options_write(__be32 *pt +@@ -679,13 +685,14 @@ static void tcp_options_write(__be32 *pt if (foc->exp) { len = TCPOLEN_EXP_FASTOPEN_BASE + foc->len; @@ -579,15 +579,15 @@ SVN-Revision: 35130 * XXX skbs on the gro_list have all been parsed and pulled --- a/include/net/addrconf.h +++ b/include/net/addrconf.h -@@ -47,7 +47,7 @@ struct prefix_info { +@@ -52,7 +52,7 @@ struct prefix_info { __be32 reserved2; struct in6_addr prefix; -}; +} __attribute__((packed, aligned(2))); - #include - #include + /* rfc4861 4.6.2: IPv6 PIO is 32 bytes in size */ + static_assert(sizeof(struct prefix_info) == 32); --- a/include/net/inet_ecn.h +++ b/include/net/inet_ecn.h @@ -140,9 +140,9 @@ static inline int IP6_ECN_set_ce(struct @@ -740,7 +740,7 @@ SVN-Revision: 35130 EXPORT_SYMBOL(xfrm_parse_spi); --- a/net/ipv4/tcp_input.c +++ b/net/ipv4/tcp_input.c -@@ -4134,14 +4134,16 @@ static bool tcp_parse_aligned_timestamp( +@@ -4151,14 +4151,16 @@ static bool tcp_parse_aligned_timestamp( { const __be32 *ptr = (const __be32 *)(th + 1); diff --git a/target/linux/ath79/patches-5.15/910-unaligned_access_hacks.patch b/target/linux/ath79/patches-5.15/900-unaligned_access_hacks.patch similarity index 99% rename from target/linux/ath79/patches-5.15/910-unaligned_access_hacks.patch rename to target/linux/ath79/patches-5.15/900-unaligned_access_hacks.patch index 84723add3b8aaf..7bd6ae8b5606a9 100644 --- a/target/linux/ath79/patches-5.15/910-unaligned_access_hacks.patch +++ b/target/linux/ath79/patches-5.15/900-unaligned_access_hacks.patch @@ -589,15 +589,15 @@ SVN-Revision: 35130 * XXX skbs on the gro_list have all been parsed and pulled --- a/include/net/addrconf.h +++ b/include/net/addrconf.h -@@ -47,7 +47,7 @@ struct prefix_info { +@@ -52,7 +52,7 @@ struct prefix_info { __be32 reserved2; struct in6_addr prefix; -}; +} __attribute__((packed, aligned(2))); - #include - #include + /* rfc4861 4.6.2: IPv6 PIO is 32 bytes in size */ + static_assert(sizeof(struct prefix_info) == 32); --- a/include/net/inet_ecn.h +++ b/include/net/inet_ecn.h @@ -138,9 +138,9 @@ static inline int IP6_ECN_set_ce(struct @@ -750,7 +750,7 @@ SVN-Revision: 35130 EXPORT_SYMBOL(xfrm_parse_spi); --- a/net/ipv4/tcp_input.c +++ b/net/ipv4/tcp_input.c -@@ -4171,14 +4171,16 @@ static bool tcp_parse_aligned_timestamp( +@@ -4175,14 +4175,16 @@ static bool tcp_parse_aligned_timestamp( { const __be32 *ptr = (const __be32 *)(th + 1); diff --git a/target/linux/ath79/patches-5.4/0036-GPIO-add-named-gpio-exports.patch b/target/linux/ath79/patches-5.4/0036-GPIO-add-named-gpio-exports.patch index a7f1a48bd94734..e213b850e1bbff 100644 --- a/target/linux/ath79/patches-5.4/0036-GPIO-add-named-gpio-exports.patch +++ b/target/linux/ath79/patches-5.4/0036-GPIO-add-named-gpio-exports.patch @@ -93,7 +93,7 @@ Signed-off-by: John Crispin +module_platform_driver(gpio_export_driver); --- a/drivers/gpio/gpiolib-sysfs.c +++ b/drivers/gpio/gpiolib-sysfs.c -@@ -571,7 +571,7 @@ static struct class gpio_class = { +@@ -574,7 +574,7 @@ static struct class gpio_class = { * * Returns zero on success, else an error. */ @@ -102,7 +102,7 @@ Signed-off-by: John Crispin { struct gpio_chip *chip; struct gpio_device *gdev; -@@ -633,6 +633,8 @@ int gpiod_export(struct gpio_desc *desc, +@@ -636,6 +636,8 @@ int gpiod_export(struct gpio_desc *desc, offset = gpio_chip_hwgpio(desc); if (chip->names && chip->names[offset]) ioname = chip->names[offset]; @@ -111,7 +111,7 @@ Signed-off-by: John Crispin dev = device_create_with_groups(&gpio_class, &gdev->dev, MKDEV(0, 0), data, gpio_groups, -@@ -654,6 +656,12 @@ err_unlock: +@@ -657,6 +659,12 @@ err_unlock: gpiod_dbg(desc, "%s: status %d\n", __func__, status); return status; } diff --git a/target/linux/ath79/patches-5.4/910-unaligned_access_hacks.patch b/target/linux/ath79/patches-5.4/910-unaligned_access_hacks.patch index f8dfb4f81177b5..0179f756810c06 100644 --- a/target/linux/ath79/patches-5.4/910-unaligned_access_hacks.patch +++ b/target/linux/ath79/patches-5.4/910-unaligned_access_hacks.patch @@ -545,15 +545,15 @@ * XXX skbs on the gro_list have all been parsed and pulled --- a/include/net/addrconf.h +++ b/include/net/addrconf.h -@@ -47,7 +47,7 @@ struct prefix_info { +@@ -52,7 +52,7 @@ struct prefix_info { __be32 reserved2; struct in6_addr prefix; -}; +} __attribute__((packed, aligned(2))); - #include - #include + /* rfc4861 4.6.2: IPv6 PIO is 32 bytes in size */ + static_assert(sizeof(struct prefix_info) == 32); --- a/include/net/inet_ecn.h +++ b/include/net/inet_ecn.h @@ -140,9 +140,9 @@ static inline int IP6_ECN_set_ce(struct @@ -706,7 +706,7 @@ EXPORT_SYMBOL(xfrm_parse_spi); --- a/net/ipv4/tcp_input.c +++ b/net/ipv4/tcp_input.c -@@ -4017,14 +4017,16 @@ static bool tcp_parse_aligned_timestamp( +@@ -4021,14 +4021,16 @@ static bool tcp_parse_aligned_timestamp( { const __be32 *ptr = (const __be32 *)(th + 1); diff --git a/target/linux/bcm27xx/patches-5.15/950-0056-amba_pl011-Don-t-use-DT-aliases-for-numbering.patch b/target/linux/bcm27xx/patches-5.15/950-0056-amba_pl011-Don-t-use-DT-aliases-for-numbering.patch index 3c90882138f221..14f4ee66eff33f 100644 --- a/target/linux/bcm27xx/patches-5.15/950-0056-amba_pl011-Don-t-use-DT-aliases-for-numbering.patch +++ b/target/linux/bcm27xx/patches-5.15/950-0056-amba_pl011-Don-t-use-DT-aliases-for-numbering.patch @@ -14,7 +14,7 @@ use the same logic. --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c -@@ -2756,7 +2756,12 @@ static int pl011_setup_port(struct devic +@@ -2752,7 +2752,12 @@ static int pl011_setup_port(struct devic if (IS_ERR(base)) return PTR_ERR(base); diff --git a/target/linux/bcm27xx/patches-5.15/950-0057-amba_pl011-Round-input-clock-up.patch b/target/linux/bcm27xx/patches-5.15/950-0057-amba_pl011-Round-input-clock-up.patch index 632862908d92b5..416df594accef6 100644 --- a/target/linux/bcm27xx/patches-5.15/950-0057-amba_pl011-Round-input-clock-up.patch +++ b/target/linux/bcm27xx/patches-5.15/950-0057-amba_pl011-Round-input-clock-up.patch @@ -26,7 +26,7 @@ Signed-off-by: Phil Elwell --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c -@@ -1730,6 +1730,23 @@ static void pl011_put_poll_char(struct u +@@ -1726,6 +1726,23 @@ static void pl011_put_poll_char(struct u #endif /* CONFIG_CONSOLE_POLL */ @@ -50,7 +50,7 @@ Signed-off-by: Phil Elwell static int pl011_hwinit(struct uart_port *port) { struct uart_amba_port *uap = -@@ -1746,7 +1763,7 @@ static int pl011_hwinit(struct uart_port +@@ -1742,7 +1759,7 @@ static int pl011_hwinit(struct uart_port if (retval) return retval; @@ -59,7 +59,7 @@ Signed-off-by: Phil Elwell /* Clear pending error and receive interrupts */ pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | -@@ -2452,7 +2469,7 @@ static int pl011_console_setup(struct co +@@ -2448,7 +2465,7 @@ static int pl011_console_setup(struct co plat->init(); } @@ -68,7 +68,7 @@ Signed-off-by: Phil Elwell if (uap->vendor->fixed_options) { baud = uap->fixed_baud; -@@ -2669,6 +2686,7 @@ static struct uart_driver amba_reg = { +@@ -2665,6 +2682,7 @@ static struct uart_driver amba_reg = { .cons = AMBA_CONSOLE, }; @@ -76,7 +76,7 @@ Signed-off-by: Phil Elwell static int pl011_probe_dt_alias(int index, struct device *dev) { struct device_node *np; -@@ -2700,6 +2718,7 @@ static int pl011_probe_dt_alias(int inde +@@ -2696,6 +2714,7 @@ static int pl011_probe_dt_alias(int inde return ret; } diff --git a/target/linux/bcm27xx/patches-5.15/950-0058-amba_pl011-Insert-mb-for-correct-FIFO-handling.patch b/target/linux/bcm27xx/patches-5.15/950-0058-amba_pl011-Insert-mb-for-correct-FIFO-handling.patch index beb2c67e39c3ae..90507846024898 100644 --- a/target/linux/bcm27xx/patches-5.15/950-0058-amba_pl011-Insert-mb-for-correct-FIFO-handling.patch +++ b/target/linux/bcm27xx/patches-5.15/950-0058-amba_pl011-Insert-mb-for-correct-FIFO-handling.patch @@ -17,7 +17,7 @@ Signed-off-by: Phil Elwell --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c -@@ -1435,6 +1435,7 @@ static bool pl011_tx_char(struct uart_am +@@ -1431,6 +1431,7 @@ static bool pl011_tx_char(struct uart_am return false; /* unable to transmit character */ pl011_write(c, uap, REG_DR); diff --git a/target/linux/bcm27xx/patches-5.15/950-0059-amba_pl011-Add-cts-event-workaround-DT-property.patch b/target/linux/bcm27xx/patches-5.15/950-0059-amba_pl011-Add-cts-event-workaround-DT-property.patch index 1d4cdbca64755b..7e10f7931cd1d0 100644 --- a/target/linux/bcm27xx/patches-5.15/950-0059-amba_pl011-Add-cts-event-workaround-DT-property.patch +++ b/target/linux/bcm27xx/patches-5.15/950-0059-amba_pl011-Add-cts-event-workaround-DT-property.patch @@ -36,7 +36,7 @@ Signed-off-by: Phil Elwell - reg --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c -@@ -2847,6 +2847,11 @@ static int pl011_probe(struct amba_devic +@@ -2843,6 +2843,11 @@ static int pl011_probe(struct amba_devic if (IS_ERR(uap->clk)) return PTR_ERR(uap->clk); diff --git a/target/linux/bcm27xx/patches-5.15/950-0061-tty-amba-pl011-Avoid-rare-write-when-full-error.patch b/target/linux/bcm27xx/patches-5.15/950-0061-tty-amba-pl011-Avoid-rare-write-when-full-error.patch index 431f588a4c5f59..82dc4f384f4462 100644 --- a/target/linux/bcm27xx/patches-5.15/950-0061-tty-amba-pl011-Avoid-rare-write-when-full-error.patch +++ b/target/linux/bcm27xx/patches-5.15/950-0061-tty-amba-pl011-Avoid-rare-write-when-full-error.patch @@ -29,7 +29,7 @@ Signed-off-by: Phil Elwell --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c -@@ -1496,6 +1496,10 @@ static bool pl011_tx_chars(struct uart_a +@@ -1492,6 +1492,10 @@ static bool pl011_tx_chars(struct uart_a if (likely(from_irq) && count-- == 0) break; diff --git a/target/linux/bcm27xx/patches-5.15/950-0070-MMC-added-alternative-MMC-driver.patch b/target/linux/bcm27xx/patches-5.15/950-0070-MMC-added-alternative-MMC-driver.patch index d7368a0ba4eb1f..2f8829398588e1 100644 --- a/target/linux/bcm27xx/patches-5.15/950-0070-MMC-added-alternative-MMC-driver.patch +++ b/target/linux/bcm27xx/patches-5.15/950-0070-MMC-added-alternative-MMC-driver.patch @@ -244,7 +244,7 @@ bcm2835-mmc: uninitialized_var is no more static inline int mmc_blk_part_switch(struct mmc_card *card, unsigned int part_type); static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq, -@@ -2942,6 +2949,8 @@ static int mmc_blk_probe(struct mmc_card +@@ -2944,6 +2951,8 @@ static int mmc_blk_probe(struct mmc_card { struct mmc_blk_data *md; int ret = 0; @@ -253,7 +253,7 @@ bcm2835-mmc: uninitialized_var is no more /* * Check that the card supports the command class(es) we need. -@@ -2949,7 +2958,16 @@ static int mmc_blk_probe(struct mmc_card +@@ -2951,7 +2960,16 @@ static int mmc_blk_probe(struct mmc_card if (!(card->csd.cmdclass & CCC_BLOCK_READ)) return -ENODEV; @@ -271,7 +271,7 @@ bcm2835-mmc: uninitialized_var is no more card->complete_wq = alloc_workqueue("mmc_complete", WQ_MEM_RECLAIM | WQ_HIGHPRI, 0); -@@ -2964,6 +2982,17 @@ static int mmc_blk_probe(struct mmc_card +@@ -2966,6 +2984,17 @@ static int mmc_blk_probe(struct mmc_card goto out_free; } @@ -291,7 +291,7 @@ bcm2835-mmc: uninitialized_var is no more goto out; --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c -@@ -1812,7 +1812,8 @@ EXPORT_SYMBOL(mmc_erase); +@@ -1817,7 +1817,8 @@ EXPORT_SYMBOL(mmc_erase); int mmc_can_erase(struct mmc_card *card) { diff --git a/target/linux/bcm27xx/patches-5.15/950-0108-sc16is7xx-Don-t-spin-if-no-data-received.patch b/target/linux/bcm27xx/patches-5.15/950-0108-sc16is7xx-Don-t-spin-if-no-data-received.patch index a7d7f211d4339a..711bd0025f3de4 100644 --- a/target/linux/bcm27xx/patches-5.15/950-0108-sc16is7xx-Don-t-spin-if-no-data-received.patch +++ b/target/linux/bcm27xx/patches-5.15/950-0108-sc16is7xx-Don-t-spin-if-no-data-received.patch @@ -12,8 +12,8 @@ Signed-off-by: Phil Elwell --- a/drivers/tty/serial/sc16is7xx.c +++ b/drivers/tty/serial/sc16is7xx.c -@@ -696,6 +696,8 @@ static bool sc16is7xx_port_irq(struct sc - rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG); +@@ -708,6 +708,8 @@ static bool sc16is7xx_port_irq(struct sc + if (rxlen) sc16is7xx_handle_rx(port, rxlen, iir); + else diff --git a/target/linux/bcm27xx/patches-5.15/950-0163-hid-usb-Add-device-quirks-for-Freeway-Airmouse-T3-an.patch b/target/linux/bcm27xx/patches-5.15/950-0163-hid-usb-Add-device-quirks-for-Freeway-Airmouse-T3-an.patch index f00f2e7b23f3f4..0b6ff1a70a23cf 100644 --- a/target/linux/bcm27xx/patches-5.15/950-0163-hid-usb-Add-device-quirks-for-Freeway-Airmouse-T3-an.patch +++ b/target/linux/bcm27xx/patches-5.15/950-0163-hid-usb-Add-device-quirks-for-Freeway-Airmouse-T3-an.patch @@ -33,7 +33,7 @@ Signed-off-by: Jonathan Bell #define USB_VENDOR_ID_BELKIN 0x050d #define USB_DEVICE_ID_FLIP_KVM 0x3201 -@@ -1318,6 +1321,9 @@ +@@ -1322,6 +1325,9 @@ #define USB_VENDOR_ID_XAT 0x2505 #define USB_DEVICE_ID_XAT_CSR 0x0220 @@ -45,7 +45,7 @@ Signed-off-by: Jonathan Bell #define USB_DEVICE_ID_THT_2P_ARCADE 0x75e1 --- a/drivers/hid/hid-quirks.c +++ b/drivers/hid/hid-quirks.c -@@ -41,6 +41,7 @@ static const struct hid_device_id hid_qu +@@ -42,6 +42,7 @@ static const struct hid_device_id hid_qu { HID_USB_DEVICE(USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_CS682), HID_QUIRK_NOGET }, { HID_USB_DEVICE(USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_CS692), HID_QUIRK_NOGET }, { HID_USB_DEVICE(USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_UC100KM), HID_QUIRK_NOGET }, @@ -53,7 +53,7 @@ Signed-off-by: Jonathan Bell { HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_MULTI_TOUCH), HID_QUIRK_MULTI_INPUT }, { HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_PIXART_USB_OPTICAL_MOUSE), HID_QUIRK_ALWAYS_POLL }, { HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_PIXART_USB_OPTICAL_MOUSE2), HID_QUIRK_ALWAYS_POLL }, -@@ -198,6 +199,7 @@ static const struct hid_device_id hid_qu +@@ -200,6 +201,7 @@ static const struct hid_device_id hid_qu { HID_USB_DEVICE(USB_VENDOR_ID_WISEGROUP, USB_DEVICE_ID_QUAD_USB_JOYPAD), HID_QUIRK_NOGET | HID_QUIRK_MULTI_INPUT }, { HID_USB_DEVICE(USB_VENDOR_ID_XIN_MO, USB_DEVICE_ID_XIN_MO_DUAL_ARCADE), HID_QUIRK_MULTI_INPUT }, { HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_GROUP_AUDIO), HID_QUIRK_NOGET }, diff --git a/target/linux/bcm27xx/patches-5.15/950-0231-sc16is7xx-Fix-for-hardware-flow-control.patch b/target/linux/bcm27xx/patches-5.15/950-0231-sc16is7xx-Fix-for-hardware-flow-control.patch index 37bea70db74245..88b3a6125efe77 100644 --- a/target/linux/bcm27xx/patches-5.15/950-0231-sc16is7xx-Fix-for-hardware-flow-control.patch +++ b/target/linux/bcm27xx/patches-5.15/950-0231-sc16is7xx-Fix-for-hardware-flow-control.patch @@ -38,7 +38,7 @@ Signed-off-by: Phil Elwell regcache_cache_bypass(s->regmap, false); /* Put LCR back to the normal mode */ -@@ -842,7 +843,7 @@ static unsigned int sc16is7xx_get_mctrl( +@@ -854,7 +855,7 @@ static unsigned int sc16is7xx_get_mctrl( /* DCD and DSR are not wired and CTS/RTS is handled automatically * so just indicate DSR and CAR asserted */ @@ -47,7 +47,7 @@ Signed-off-by: Phil Elwell } static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl) -@@ -929,14 +930,19 @@ static void sc16is7xx_set_termios(struct +@@ -941,14 +942,19 @@ static void sc16is7xx_set_termios(struct regcache_cache_bypass(s->regmap, true); sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]); sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]); diff --git a/target/linux/bcm27xx/patches-5.15/950-0281-media-i2c-Add-driver-for-Sony-IMX477-sensor.patch b/target/linux/bcm27xx/patches-5.15/950-0281-media-i2c-Add-driver-for-Sony-IMX477-sensor.patch index cd786e47152c5d..4f94a9f11dcc37 100644 --- a/target/linux/bcm27xx/patches-5.15/950-0281-media-i2c-Add-driver-for-Sony-IMX477-sensor.patch +++ b/target/linux/bcm27xx/patches-5.15/950-0281-media-i2c-Add-driver-for-Sony-IMX477-sensor.patch @@ -25,7 +25,7 @@ Signed-off-by: Naushir Patuck --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -17523,6 +17523,14 @@ T: git git://linuxtv.org/media_tree.git +@@ -17526,6 +17526,14 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/i2c/sony,imx412.yaml F: drivers/media/i2c/imx412.c diff --git a/target/linux/bcm27xx/patches-5.15/950-0413-Documentation-devicetree-Add-documentation-for-imx37.patch b/target/linux/bcm27xx/patches-5.15/950-0413-Documentation-devicetree-Add-documentation-for-imx37.patch index 1b9cfd8c002683..8c75f80baa9783 100644 --- a/target/linux/bcm27xx/patches-5.15/950-0413-Documentation-devicetree-Add-documentation-for-imx37.patch +++ b/target/linux/bcm27xx/patches-5.15/950-0413-Documentation-devicetree-Add-documentation-for-imx37.patch @@ -132,7 +132,7 @@ Signed-off-by: David Plowman +... --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -17537,6 +17537,7 @@ M: Raspberry Pi Kernel Maintenance static const struct drm_display_mode innolux_at070tn92_mode = { .clock = 33333, .hdisplay = 800, -@@ -4666,6 +4698,9 @@ static const struct of_device_id platfor +@@ -4667,6 +4699,9 @@ static const struct of_device_id platfor .compatible = "innolux,at043tn24", .data = &innolux_at043tn24, }, { diff --git a/target/linux/bcm27xx/patches-5.15/950-0479-drm-panel-simple-Add-a-timing-for-the-Raspberry-Pi-7.patch b/target/linux/bcm27xx/patches-5.15/950-0479-drm-panel-simple-Add-a-timing-for-the-Raspberry-Pi-7.patch index ee582fea80eeee..72cefe864e313e 100644 --- a/target/linux/bcm27xx/patches-5.15/950-0479-drm-panel-simple-Add-a-timing-for-the-Raspberry-Pi-7.patch +++ b/target/linux/bcm27xx/patches-5.15/950-0479-drm-panel-simple-Add-a-timing-for-the-Raspberry-Pi-7.patch @@ -15,7 +15,7 @@ Signed-off-by: Dave Stevenson --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c -@@ -3765,6 +3765,31 @@ static const struct panel_desc qishenglo +@@ -3766,6 +3766,31 @@ static const struct panel_desc qishenglo .connector_type = DRM_MODE_CONNECTOR_DPI, }; @@ -47,7 +47,7 @@ Signed-off-by: Dave Stevenson static const struct display_timing rocktech_rk070er9427_timing = { .pixelclock = { 26400000, 33300000, 46800000 }, .hactive = { 800, 800, 800 }, -@@ -4845,6 +4870,9 @@ static const struct of_device_id platfor +@@ -4846,6 +4871,9 @@ static const struct of_device_id platfor .compatible = "qishenglong,gopher2b-lcd", .data = &qishenglong_gopher2b_lcd, }, { diff --git a/target/linux/bcm27xx/patches-5.15/950-0520-dt-bindings-media-i2c-Add-IMX519-CMOS-sensor-binding.patch b/target/linux/bcm27xx/patches-5.15/950-0520-dt-bindings-media-i2c-Add-IMX519-CMOS-sensor-binding.patch index ccb0625848e1f7..53c6646cabdccb 100644 --- a/target/linux/bcm27xx/patches-5.15/950-0520-dt-bindings-media-i2c-Add-IMX519-CMOS-sensor-binding.patch +++ b/target/linux/bcm27xx/patches-5.15/950-0520-dt-bindings-media-i2c-Add-IMX519-CMOS-sensor-binding.patch @@ -132,7 +132,7 @@ Signed-off-by: Lee Jackson +... --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -17541,6 +17541,14 @@ F: Documentation/devicetree/bindings/med +@@ -17544,6 +17544,14 @@ F: Documentation/devicetree/bindings/med F: Documentation/devicetree/bindings/media/i2c/imx477.yaml F: drivers/media/i2c/imx477.c diff --git a/target/linux/bcm27xx/patches-5.15/950-0686-drm-panel-simple-add-Geekworm-MZP280-Panel.patch b/target/linux/bcm27xx/patches-5.15/950-0686-drm-panel-simple-add-Geekworm-MZP280-Panel.patch index f668c4db19c7cb..1d450282f2a67b 100644 --- a/target/linux/bcm27xx/patches-5.15/950-0686-drm-panel-simple-add-Geekworm-MZP280-Panel.patch +++ b/target/linux/bcm27xx/patches-5.15/950-0686-drm-panel-simple-add-Geekworm-MZP280-Panel.patch @@ -46,7 +46,7 @@ Acked-by: Maxime Ripard static const struct drm_display_mode giantplus_gpg482739qs5_mode = { .clock = 9000, .hdisplay = 480, -@@ -4708,6 +4734,9 @@ static const struct of_device_id platfor +@@ -4709,6 +4735,9 @@ static const struct of_device_id platfor .compatible = "friendlyarm,hd702e", .data = &friendlyarm_hd702e, }, { diff --git a/target/linux/bcm27xx/patches-5.15/950-0914-mmc-block-Don-t-do-single-sector-reads-during-recove.patch b/target/linux/bcm27xx/patches-5.15/950-0914-mmc-block-Don-t-do-single-sector-reads-during-recove.patch index 5c96783ed7d56b..2741660ee2ae9b 100644 --- a/target/linux/bcm27xx/patches-5.15/950-0914-mmc-block-Don-t-do-single-sector-reads-during-recove.patch +++ b/target/linux/bcm27xx/patches-5.15/950-0914-mmc-block-Don-t-do-single-sector-reads-during-recove.patch @@ -23,7 +23,7 @@ Signed-off-by: Jonathan Bell --- a/drivers/mmc/core/block.c +++ b/drivers/mmc/core/block.c -@@ -1886,7 +1886,11 @@ static void mmc_blk_mq_rw_recovery(struc +@@ -1888,7 +1888,11 @@ static void mmc_blk_mq_rw_recovery(struc return; } diff --git a/target/linux/bcm53xx/patches-5.10/030-v5.11-0002-ARM-dts-BCM5301X-Harmonize-EHCI-OHCI-DT-nodes-name.patch b/target/linux/bcm53xx/patches-5.10/030-v5.11-0002-ARM-dts-BCM5301X-Harmonize-EHCI-OHCI-DT-nodes-name.patch deleted file mode 100644 index d6e5fca967611c..00000000000000 --- a/target/linux/bcm53xx/patches-5.10/030-v5.11-0002-ARM-dts-BCM5301X-Harmonize-EHCI-OHCI-DT-nodes-name.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 74abbfe99f43eb7466d26d9e48fbeb46b8f3d804 Mon Sep 17 00:00:00 2001 -From: Serge Semin -Date: Tue, 20 Oct 2020 14:59:37 +0300 -Subject: [PATCH] ARM: dts: BCM5301X: Harmonize EHCI/OHCI DT nodes name - -In accordance with the Generic EHCI/OHCI bindings the corresponding node -name is suppose to comply with the Generic USB HCD DT schema, which -requires the USB nodes to have the name acceptable by the regexp: -"^usb(@.*)?" . Make sure the "generic-ehci" and "generic-ohci"-compatible -nodes are correctly named. - -Signed-off-by: Serge Semin -Acked-by: Florian Fainelli -Acked-by: Krzysztof Kozlowski -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm5301x.dtsi | 4 ++-- - arch/arm/boot/dts/bcm53573.dtsi | 4 ++-- - 2 files changed, 4 insertions(+), 4 deletions(-) - ---- a/arch/arm/boot/dts/bcm5301x.dtsi -+++ b/arch/arm/boot/dts/bcm5301x.dtsi -@@ -267,7 +267,7 @@ - - interrupt-parent = <&gic>; - -- ehci: ehci@21000 { -+ ehci: usb@21000 { - #usb-cells = <0>; - - compatible = "generic-ehci"; -@@ -289,7 +289,7 @@ - }; - }; - -- ohci: ohci@22000 { -+ ohci: usb@22000 { - #usb-cells = <0>; - - compatible = "generic-ohci"; ---- a/arch/arm/boot/dts/bcm53573.dtsi -+++ b/arch/arm/boot/dts/bcm53573.dtsi -@@ -135,7 +135,7 @@ - #address-cells = <1>; - #size-cells = <1>; - -- ehci: ehci@4000 { -+ ehci: usb@4000 { - compatible = "generic-ehci"; - reg = <0x4000 0x1000>; - interrupt-parent = <&gic>; -@@ -155,7 +155,7 @@ - }; - }; - -- ohci: ohci@d000 { -+ ohci: usb@d000 { - #usb-cells = <0>; - - compatible = "generic-ohci"; diff --git a/target/linux/bcm53xx/patches-5.10/033-v5.16-0019-ARM-dts-BCM53573-Describe-on-SoC-BCM53125-rev-4-swit.patch b/target/linux/bcm53xx/patches-5.10/033-v5.16-0019-ARM-dts-BCM53573-Describe-on-SoC-BCM53125-rev-4-swit.patch deleted file mode 100644 index 3a5438c228241f..00000000000000 --- a/target/linux/bcm53xx/patches-5.10/033-v5.16-0019-ARM-dts-BCM53573-Describe-on-SoC-BCM53125-rev-4-swit.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 9fb90ae6cae7f8fe4fbf626945f32cd9da2c3892 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= -Date: Mon, 20 Sep 2021 16:10:23 +0200 -Subject: [PATCH] ARM: dts: BCM53573: Describe on-SoC BCM53125 rev 4 switch -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -BCM53573 family SoC have Ethernet switch connected to the first Ethernet -controller (accessible over MDIO). - -Signed-off-by: Rafał Miłecki -Signed-off-by: Florian Fainelli ---- - arch/arm/boot/dts/bcm53573.dtsi | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - ---- a/arch/arm/boot/dts/bcm53573.dtsi -+++ b/arch/arm/boot/dts/bcm53573.dtsi -@@ -180,6 +180,24 @@ - - gmac0: ethernet@5000 { - reg = <0x5000 0x1000>; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ switch: switch@1e { -+ compatible = "brcm,bcm53125"; -+ reg = <0x1e>; -+ -+ status = "disabled"; -+ -+ /* ports are defined in board DTS */ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ }; -+ }; - }; - - gmac1: ethernet@b000 { diff --git a/target/linux/bcm53xx/patches-5.10/180-usb-xhci-add-support-for-performing-fake-doorbell.patch b/target/linux/bcm53xx/patches-5.10/180-usb-xhci-add-support-for-performing-fake-doorbell.patch index 359da930237e11..4aec8a8b84a565 100644 --- a/target/linux/bcm53xx/patches-5.10/180-usb-xhci-add-support-for-performing-fake-doorbell.patch +++ b/target/linux/bcm53xx/patches-5.10/180-usb-xhci-add-support-for-performing-fake-doorbell.patch @@ -127,11 +127,11 @@ it on BCM4708 family. /* --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h -@@ -1895,6 +1895,7 @@ struct xhci_hcd { - #define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42) - #define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43) +@@ -1896,6 +1896,7 @@ struct xhci_hcd { #define XHCI_RESET_TO_DEFAULT BIT_ULL(44) -+#define XHCI_FAKE_DOORBELL BIT_ULL(45) + #define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45) + #define XHCI_ZHAOXIN_HOST BIT_ULL(46) ++#define XHCI_FAKE_DOORBELL BIT_ULL(47) unsigned int num_active_eps; unsigned int limit_active_eps; diff --git a/target/linux/bcm53xx/patches-5.10/304-ARM-dts-BCM5301X-Specify-switch-ports-for-remaining-.patch b/target/linux/bcm53xx/patches-5.10/304-ARM-dts-BCM5301X-Specify-switch-ports-for-remaining-.patch index d20fe71d483483..3c133c41a63190 100644 --- a/target/linux/bcm53xx/patches-5.10/304-ARM-dts-BCM5301X-Specify-switch-ports-for-remaining-.patch +++ b/target/linux/bcm53xx/patches-5.10/304-ARM-dts-BCM5301X-Specify-switch-ports-for-remaining-.patch @@ -182,7 +182,7 @@ Signed-off-by: Rafał Miłecki +}; --- a/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts +++ b/arch/arm/boot/dts/bcm4708-linksys-ea6500-v2.dts -@@ -42,3 +42,40 @@ +@@ -43,3 +43,40 @@ &usb3_phy { status = "okay"; }; diff --git a/target/linux/bcm63xx/patches-5.10/143-gpio-fix-device-tree-gpio-hogs-on-dual-role-gpio-pin.patch b/target/linux/bcm63xx/patches-5.10/143-gpio-fix-device-tree-gpio-hogs-on-dual-role-gpio-pin.patch index f5f42df2d81df9..87fc7a2f0f99e8 100644 --- a/target/linux/bcm63xx/patches-5.10/143-gpio-fix-device-tree-gpio-hogs-on-dual-role-gpio-pin.patch +++ b/target/linux/bcm63xx/patches-5.10/143-gpio-fix-device-tree-gpio-hogs-on-dual-role-gpio-pin.patch @@ -116,7 +116,7 @@ Signed-off-by: Jonas Gorski } --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c -@@ -1911,7 +1911,8 @@ int gpiochip_add_pingroup_range(struct g +@@ -1924,7 +1924,8 @@ int gpiochip_add_pingroup_range(struct g list_add_tail(&pin_range->node, &gdev->pin_ranges); @@ -126,7 +126,7 @@ Signed-off-by: Jonas Gorski } EXPORT_SYMBOL_GPL(gpiochip_add_pingroup_range); -@@ -1968,7 +1969,7 @@ int gpiochip_add_pin_range(struct gpio_c +@@ -1981,7 +1982,7 @@ int gpiochip_add_pin_range(struct gpio_c list_add_tail(&pin_range->node, &gdev->pin_ranges); diff --git a/target/linux/bcm63xx/patches-5.10/322-MIPS-BCM63XX-switch-to-IRQ_DOMAIN.patch b/target/linux/bcm63xx/patches-5.10/322-MIPS-BCM63XX-switch-to-IRQ_DOMAIN.patch index b70f28e5a67544..be499f95394798 100644 --- a/target/linux/bcm63xx/patches-5.10/322-MIPS-BCM63XX-switch-to-IRQ_DOMAIN.patch +++ b/target/linux/bcm63xx/patches-5.10/322-MIPS-BCM63XX-switch-to-IRQ_DOMAIN.patch @@ -14,7 +14,7 @@ Signed-off-by: Jonas Gorski --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -319,6 +319,9 @@ config BCM63XX +@@ -320,6 +320,9 @@ config BCM63XX select SYNC_R4K select DMA_NONCOHERENT select IRQ_MIPS_CPU diff --git a/target/linux/generic/backport-5.10/103-v5.13-MIPS-select-CPU_MIPS64-for-remaining-MIPS64-CPUs.patch b/target/linux/generic/backport-5.10/103-v5.13-MIPS-select-CPU_MIPS64-for-remaining-MIPS64-CPUs.patch index e451a49ac2dc1e..aa88f610d39f8e 100644 --- a/target/linux/generic/backport-5.10/103-v5.13-MIPS-select-CPU_MIPS64-for-remaining-MIPS64-CPUs.patch +++ b/target/linux/generic/backport-5.10/103-v5.13-MIPS-select-CPU_MIPS64-for-remaining-MIPS64-CPUs.patch @@ -25,7 +25,7 @@ Signed-off-by: Jason A. Donenfeld --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -2089,7 +2089,7 @@ config CPU_MIPS32 +@@ -2091,7 +2091,7 @@ config CPU_MIPS32 config CPU_MIPS64 bool default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R5 || \ diff --git a/target/linux/generic/backport-5.10/343-netfilter-nft_flow_offload-handle-netdevice-events-f.patch b/target/linux/generic/backport-5.10/343-netfilter-nft_flow_offload-handle-netdevice-events-f.patch index d300af3342586b..82a62b0f2dfd43 100644 --- a/target/linux/generic/backport-5.10/343-netfilter-nft_flow_offload-handle-netdevice-events-f.patch +++ b/target/linux/generic/backport-5.10/343-netfilter-nft_flow_offload-handle-netdevice-events-f.patch @@ -55,7 +55,7 @@ Signed-off-by: Pablo Neira Ayuso --- a/net/netfilter/nft_flow_offload.c +++ b/net/netfilter/nft_flow_offload.c -@@ -237,47 +237,14 @@ static struct nft_expr_type nft_flow_off +@@ -239,47 +239,14 @@ static struct nft_expr_type nft_flow_off .owner = THIS_MODULE, }; diff --git a/target/linux/generic/backport-5.10/610-v5.13-10-netfilter-nftables-update-table-flags-from-the-commi.patch b/target/linux/generic/backport-5.10/610-v5.13-10-netfilter-nftables-update-table-flags-from-the-commi.patch deleted file mode 100644 index b3f6066a32d5d4..00000000000000 --- a/target/linux/generic/backport-5.10/610-v5.13-10-netfilter-nftables-update-table-flags-from-the-commi.patch +++ /dev/null @@ -1,103 +0,0 @@ -From: Pablo Neira Ayuso -Date: Tue, 23 Mar 2021 00:56:28 +0100 -Subject: [PATCH] netfilter: nftables: update table flags from the commit - phase - -Do not update table flags from the preparation phase. Store the flags -update into the transaction, then update the flags from the commit -phase. - -Signed-off-by: Pablo Neira Ayuso ---- - ---- a/include/net/netfilter/nf_tables.h -+++ b/include/net/netfilter/nf_tables.h -@@ -1500,13 +1500,16 @@ struct nft_trans_chain { - - struct nft_trans_table { - bool update; -- bool enable; -+ u8 state; -+ u32 flags; - }; - - #define nft_trans_table_update(trans) \ - (((struct nft_trans_table *)trans->data)->update) --#define nft_trans_table_enable(trans) \ -- (((struct nft_trans_table *)trans->data)->enable) -+#define nft_trans_table_state(trans) \ -+ (((struct nft_trans_table *)trans->data)->state) -+#define nft_trans_table_flags(trans) \ -+ (((struct nft_trans_table *)trans->data)->flags) - - struct nft_trans_elem { - struct nft_set *set; ---- a/net/netfilter/nf_tables_api.c -+++ b/net/netfilter/nf_tables_api.c -@@ -1056,6 +1056,12 @@ static void nf_tables_table_disable(stru - nft_table_disable(net, table, 0); - } - -+enum { -+ NFT_TABLE_STATE_UNCHANGED = 0, -+ NFT_TABLE_STATE_DORMANT, -+ NFT_TABLE_STATE_WAKEUP -+}; -+ - static int nf_tables_updtable(struct nft_ctx *ctx) - { - struct nft_trans *trans; -@@ -1079,19 +1085,17 @@ static int nf_tables_updtable(struct nft - - if ((flags & NFT_TABLE_F_DORMANT) && - !(ctx->table->flags & NFT_TABLE_F_DORMANT)) { -- nft_trans_table_enable(trans) = false; -+ nft_trans_table_state(trans) = NFT_TABLE_STATE_DORMANT; - } else if (!(flags & NFT_TABLE_F_DORMANT) && - ctx->table->flags & NFT_TABLE_F_DORMANT) { -- ctx->table->flags &= ~NFT_TABLE_F_DORMANT; - ret = nf_tables_table_enable(ctx->net, ctx->table); - if (ret >= 0) -- nft_trans_table_enable(trans) = true; -- else -- ctx->table->flags |= NFT_TABLE_F_DORMANT; -+ nft_trans_table_state(trans) = NFT_TABLE_STATE_WAKEUP; - } - if (ret < 0) - goto err; - -+ nft_trans_table_flags(trans) = flags; - nft_trans_table_update(trans) = true; - nft_trans_commit_list_add_tail(ctx->net, trans); - return 0; -@@ -8191,11 +8195,10 @@ static int nf_tables_commit(struct net * - switch (trans->msg_type) { - case NFT_MSG_NEWTABLE: - if (nft_trans_table_update(trans)) { -- if (!nft_trans_table_enable(trans)) { -- nf_tables_table_disable(net, -- trans->ctx.table); -- trans->ctx.table->flags |= NFT_TABLE_F_DORMANT; -- } -+ if (nft_trans_table_state(trans) == NFT_TABLE_STATE_DORMANT) -+ nf_tables_table_disable(net, trans->ctx.table); -+ -+ trans->ctx.table->flags = nft_trans_table_flags(trans); - } else { - nft_clear(net, trans->ctx.table); - } -@@ -8414,11 +8417,9 @@ static int __nf_tables_abort(struct net - switch (trans->msg_type) { - case NFT_MSG_NEWTABLE: - if (nft_trans_table_update(trans)) { -- if (nft_trans_table_enable(trans)) { -- nf_tables_table_disable(net, -- trans->ctx.table); -- trans->ctx.table->flags |= NFT_TABLE_F_DORMANT; -- } -+ if (nft_trans_table_state(trans) == NFT_TABLE_STATE_WAKEUP) -+ nf_tables_table_disable(net, trans->ctx.table); -+ - nft_trans_destroy(trans); - } else { - list_del_rcu(&trans->ctx.table->list); diff --git a/target/linux/generic/backport-5.10/610-v5.13-31-net-ethernet-mtk_eth_soc-fix-parsing-packets-in-GDM.patch b/target/linux/generic/backport-5.10/610-v5.13-31-net-ethernet-mtk_eth_soc-fix-parsing-packets-in-GDM.patch index 3be60aee1d2a3d..9e97764529718f 100644 --- a/target/linux/generic/backport-5.10/610-v5.13-31-net-ethernet-mtk_eth_soc-fix-parsing-packets-in-GDM.patch +++ b/target/linux/generic/backport-5.10/610-v5.13-31-net-ethernet-mtk_eth_soc-fix-parsing-packets-in-GDM.patch @@ -38,7 +38,7 @@ Signed-off-by: Pablo Neira Ayuso if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || !eth->netdev[mac])) -@@ -2275,6 +2275,9 @@ static void mtk_gdm_config(struct mtk_et +@@ -2278,6 +2278,9 @@ static void mtk_gdm_config(struct mtk_et val |= config; diff --git a/target/linux/generic/backport-5.10/610-v5.13-32-net-ethernet-mtk_eth_soc-add-support-for-initializin.patch b/target/linux/generic/backport-5.10/610-v5.13-32-net-ethernet-mtk_eth_soc-add-support-for-initializin.patch index 3648a354b97b61..063c52785536e4 100644 --- a/target/linux/generic/backport-5.10/610-v5.13-32-net-ethernet-mtk_eth_soc-add-support-for-initializin.patch +++ b/target/linux/generic/backport-5.10/610-v5.13-32-net-ethernet-mtk_eth_soc-add-support-for-initializin.patch @@ -27,7 +27,7 @@ Signed-off-by: Pablo Neira Ayuso obj-$(CONFIG_NET_MEDIATEK_STAR_EMAC) += mtk_star_emac.o --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -2300,15 +2300,20 @@ static int mtk_open(struct net_device *d +@@ -2303,15 +2303,20 @@ static int mtk_open(struct net_device *d /* we run 2 netdevs on the same dma ring so we only bring it up once */ if (!refcount_read(ð->dma_refcnt)) { @@ -50,7 +50,7 @@ Signed-off-by: Pablo Neira Ayuso napi_enable(ð->tx_napi); napi_enable(ð->rx_napi); -@@ -2375,6 +2380,9 @@ static int mtk_stop(struct net_device *d +@@ -2378,6 +2383,9 @@ static int mtk_stop(struct net_device *d mtk_dma_free(eth); @@ -60,7 +60,7 @@ Signed-off-by: Pablo Neira Ayuso return 0; } -@@ -3103,6 +3111,13 @@ static int mtk_probe(struct platform_dev +@@ -3106,6 +3114,13 @@ static int mtk_probe(struct platform_dev goto err_free_dev; } @@ -74,7 +74,7 @@ Signed-off-by: Pablo Neira Ayuso for (i = 0; i < MTK_MAX_DEVS; i++) { if (!eth->netdev[i]) continue; -@@ -3177,6 +3192,7 @@ static const struct mtk_soc_data mt7621_ +@@ -3180,6 +3195,7 @@ static const struct mtk_soc_data mt7621_ .hw_features = MTK_HW_FEATURES, .required_clks = MT7621_CLKS_BITMAP, .required_pctl = false, @@ -82,7 +82,7 @@ Signed-off-by: Pablo Neira Ayuso }; static const struct mtk_soc_data mt7622_data = { -@@ -3185,6 +3201,7 @@ static const struct mtk_soc_data mt7622_ +@@ -3188,6 +3204,7 @@ static const struct mtk_soc_data mt7622_ .hw_features = MTK_HW_FEATURES, .required_clks = MT7622_CLKS_BITMAP, .required_pctl = false, diff --git a/target/linux/generic/backport-5.10/610-v5.13-33-net-ethernet-mtk_eth_soc-add-flow-offloading-support.patch b/target/linux/generic/backport-5.10/610-v5.13-33-net-ethernet-mtk_eth_soc-add-flow-offloading-support.patch index cac84285c09a47..1ce24241f22c5d 100644 --- a/target/linux/generic/backport-5.10/610-v5.13-33-net-ethernet-mtk_eth_soc-add-flow-offloading-support.patch +++ b/target/linux/generic/backport-5.10/610-v5.13-33-net-ethernet-mtk_eth_soc-add-flow-offloading-support.patch @@ -21,7 +21,7 @@ Signed-off-by: Pablo Neira Ayuso obj-$(CONFIG_NET_MEDIATEK_STAR_EMAC) += mtk_star_emac.o --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -2858,6 +2858,7 @@ static const struct net_device_ops mtk_n +@@ -2861,6 +2861,7 @@ static const struct net_device_ops mtk_n #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = mtk_poll_controller, #endif @@ -29,7 +29,7 @@ Signed-off-by: Pablo Neira Ayuso }; static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) -@@ -3116,6 +3117,10 @@ static int mtk_probe(struct platform_dev +@@ -3119,6 +3120,10 @@ static int mtk_probe(struct platform_dev eth->base + MTK_ETH_PPE_BASE, 2); if (err) goto err_free_dev; diff --git a/target/linux/generic/backport-5.10/610-v5.13-43-net-ethernet-mtk_eth_soc-use-larger-burst-size-for-Q.patch b/target/linux/generic/backport-5.10/610-v5.13-43-net-ethernet-mtk_eth_soc-use-larger-burst-size-for-Q.patch index a8be3f466793ad..f8da860bf130be 100644 --- a/target/linux/generic/backport-5.10/610-v5.13-43-net-ethernet-mtk_eth_soc-use-larger-burst-size-for-Q.patch +++ b/target/linux/generic/backport-5.10/610-v5.13-43-net-ethernet-mtk_eth_soc-use-larger-burst-size-for-Q.patch @@ -15,7 +15,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -2235,7 +2235,7 @@ static int mtk_start_dma(struct mtk_eth +@@ -2238,7 +2238,7 @@ static int mtk_start_dma(struct mtk_eth if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | diff --git a/target/linux/generic/backport-5.10/610-v5.13-45-net-ethernet-mtk_eth_soc-implement-dynamic-interrupt.patch b/target/linux/generic/backport-5.10/610-v5.13-45-net-ethernet-mtk_eth_soc-implement-dynamic-interrupt.patch index 8382e61313c610..71803e7f4ee206 100644 --- a/target/linux/generic/backport-5.10/610-v5.13-45-net-ethernet-mtk_eth_soc-implement-dynamic-interrupt.patch +++ b/target/linux/generic/backport-5.10/610-v5.13-45-net-ethernet-mtk_eth_soc-implement-dynamic-interrupt.patch @@ -87,7 +87,7 @@ Signed-off-by: David S. Miller if (mtk_queue_stopped(eth) && (atomic_read(&ring->free_count) > ring->thresh)) mtk_wake_queue(eth); -@@ -2171,6 +2186,7 @@ static irqreturn_t mtk_handle_irq_rx(int +@@ -2174,6 +2189,7 @@ static irqreturn_t mtk_handle_irq_rx(int { struct mtk_eth *eth = _eth; @@ -95,7 +95,7 @@ Signed-off-by: David S. Miller if (likely(napi_schedule_prep(ð->rx_napi))) { __napi_schedule(ð->rx_napi); mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); -@@ -2183,6 +2199,7 @@ static irqreturn_t mtk_handle_irq_tx(int +@@ -2186,6 +2202,7 @@ static irqreturn_t mtk_handle_irq_tx(int { struct mtk_eth *eth = _eth; @@ -103,7 +103,7 @@ Signed-off-by: David S. Miller if (likely(napi_schedule_prep(ð->tx_napi))) { __napi_schedule(ð->tx_napi); mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); -@@ -2370,6 +2387,9 @@ static int mtk_stop(struct net_device *d +@@ -2373,6 +2390,9 @@ static int mtk_stop(struct net_device *d napi_disable(ð->tx_napi); napi_disable(ð->rx_napi); @@ -113,7 +113,7 @@ Signed-off-by: David S. Miller if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); mtk_stop_dma(eth, MTK_PDMA_GLO_CFG); -@@ -2422,6 +2442,64 @@ err_disable_clks: +@@ -2425,6 +2445,64 @@ err_disable_clks: return ret; } @@ -178,7 +178,7 @@ Signed-off-by: David S. Miller static int mtk_hw_init(struct mtk_eth *eth) { int i, val, ret; -@@ -2443,9 +2521,6 @@ static int mtk_hw_init(struct mtk_eth *e +@@ -2446,9 +2524,6 @@ static int mtk_hw_init(struct mtk_eth *e goto err_disable_pm; } @@ -188,7 +188,7 @@ Signed-off-by: David S. Miller /* disable delay and normal interrupt */ mtk_tx_irq_disable(eth, ~0); mtk_rx_irq_disable(eth, ~0); -@@ -2484,11 +2559,11 @@ static int mtk_hw_init(struct mtk_eth *e +@@ -2487,11 +2562,11 @@ static int mtk_hw_init(struct mtk_eth *e /* Enable RX VLan Offloading */ mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); @@ -203,7 +203,7 @@ Signed-off-by: David S. Miller mtk_tx_irq_disable(eth, ~0); mtk_rx_irq_disable(eth, ~0); -@@ -2993,6 +3068,13 @@ static int mtk_probe(struct platform_dev +@@ -2996,6 +3071,13 @@ static int mtk_probe(struct platform_dev spin_lock_init(ð->page_lock); spin_lock_init(ð->tx_irq_lock); spin_lock_init(ð->rx_irq_lock); diff --git a/target/linux/generic/backport-5.10/610-v5.13-51-net-ethernet-mtk_eth_soc-use-iopoll.h-macro-for-DMA-.patch b/target/linux/generic/backport-5.10/610-v5.13-51-net-ethernet-mtk_eth_soc-use-iopoll.h-macro-for-DMA-.patch index 493883f4f1c2b6..a5b1b7d86ee0c6 100644 --- a/target/linux/generic/backport-5.10/610-v5.13-51-net-ethernet-mtk_eth_soc-use-iopoll.h-macro-for-DMA-.patch +++ b/target/linux/generic/backport-5.10/610-v5.13-51-net-ethernet-mtk_eth_soc-use-iopoll.h-macro-for-DMA-.patch @@ -19,7 +19,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -2075,25 +2075,22 @@ static int mtk_set_features(struct net_d +@@ -2078,25 +2078,22 @@ static int mtk_set_features(struct net_d /* wait for DMA to finish whatever it is doing before we start using it again */ static int mtk_dma_busy_wait(struct mtk_eth *eth) { diff --git a/target/linux/generic/backport-5.10/611-v5.12-net-ethernet-mediatek-support-setting-MTU.patch b/target/linux/generic/backport-5.10/611-v5.12-net-ethernet-mediatek-support-setting-MTU.patch index 91906618fd57e8..7e373e2d11471e 100644 --- a/target/linux/generic/backport-5.10/611-v5.12-net-ethernet-mediatek-support-setting-MTU.patch +++ b/target/linux/generic/backport-5.10/611-v5.12-net-ethernet-mediatek-support-setting-MTU.patch @@ -48,7 +48,7 @@ Signed-off-by: Jakub Kicinski return buf_size; } -@@ -2630,6 +2630,35 @@ static void mtk_uninit(struct net_device +@@ -2633,6 +2633,35 @@ static void mtk_uninit(struct net_device mtk_rx_irq_disable(eth, ~0); } @@ -84,7 +84,7 @@ Signed-off-by: Jakub Kicinski static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) { struct mtk_mac *mac = netdev_priv(dev); -@@ -2926,6 +2955,7 @@ static const struct net_device_ops mtk_n +@@ -2929,6 +2958,7 @@ static const struct net_device_ops mtk_n .ndo_set_mac_address = mtk_set_mac_address, .ndo_validate_addr = eth_validate_addr, .ndo_do_ioctl = mtk_do_ioctl, @@ -92,7 +92,7 @@ Signed-off-by: Jakub Kicinski .ndo_tx_timeout = mtk_tx_timeout, .ndo_get_stats64 = mtk_get_stats64, .ndo_fix_features = mtk_fix_features, -@@ -3028,7 +3058,10 @@ static int mtk_add_mac(struct mtk_eth *e +@@ -3031,7 +3061,10 @@ static int mtk_add_mac(struct mtk_eth *e eth->netdev[id]->irq = eth->irq[0]; eth->netdev[id]->dev.of_node = np; diff --git a/target/linux/generic/backport-5.10/630-v5.15-page_pool_frag_support.patch b/target/linux/generic/backport-5.10/630-v5.15-page_pool_frag_support.patch index 22ab8889f0d71e..f7ddcfdbf17772 100644 --- a/target/linux/generic/backport-5.10/630-v5.15-page_pool_frag_support.patch +++ b/target/linux/generic/backport-5.10/630-v5.15-page_pool_frag_support.patch @@ -646,7 +646,7 @@ } /* Reposition in the original skb */ -@@ -5197,6 +5218,20 @@ bool skb_try_coalesce(struct sk_buff *to +@@ -5203,6 +5224,20 @@ bool skb_try_coalesce(struct sk_buff *to if (skb_cloned(to)) return false; diff --git a/target/linux/generic/backport-5.10/633-v6.3-skbuff-Fix-a-race-between-coalescing-and-releasing-S.patch b/target/linux/generic/backport-5.10/633-v6.3-skbuff-Fix-a-race-between-coalescing-and-releasing-S.patch index 8021c08829ab0e..3acbb6ab192256 100644 --- a/target/linux/generic/backport-5.10/633-v6.3-skbuff-Fix-a-race-between-coalescing-and-releasing-S.patch +++ b/target/linux/generic/backport-5.10/633-v6.3-skbuff-Fix-a-race-between-coalescing-and-releasing-S.patch @@ -56,7 +56,7 @@ Signed-off-by: Jakub Kicinski --- a/net/core/skbuff.c +++ b/net/core/skbuff.c -@@ -5218,18 +5218,18 @@ bool skb_try_coalesce(struct sk_buff *to +@@ -5224,18 +5224,18 @@ bool skb_try_coalesce(struct sk_buff *to if (skb_cloned(to)) return false; diff --git a/target/linux/generic/backport-5.10/732-net-next-1-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch b/target/linux/generic/backport-5.10/732-net-next-1-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch index 5904db6dc4cc4e..13eb82afc241ce 100644 --- a/target/linux/generic/backport-5.10/732-net-next-1-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch +++ b/target/linux/generic/backport-5.10/732-net-next-1-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch @@ -895,7 +895,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -2604,14 +2604,11 @@ static int __init mtk_init(struct net_de +@@ -2607,14 +2607,11 @@ static int __init mtk_init(struct net_de { struct mtk_mac *mac = netdev_priv(dev); struct mtk_eth *eth = mac->hw; @@ -967,7 +967,7 @@ Signed-off-by: David S. Miller eth_hw_addr_random(ndev); --- a/drivers/net/ethernet/qualcomm/qca_spi.c +++ b/drivers/net/ethernet/qualcomm/qca_spi.c -@@ -884,7 +884,7 @@ qca_spi_probe(struct spi_device *spi) +@@ -902,7 +902,7 @@ qca_spi_probe(struct spi_device *spi) struct net_device *qcaspi_devs = NULL; u8 legacy_mode = 0; u16 signature; @@ -976,7 +976,7 @@ Signed-off-by: David S. Miller if (!spi->dev.of_node) { dev_err(&spi->dev, "Missing device tree\n"); -@@ -961,12 +961,8 @@ qca_spi_probe(struct spi_device *spi) +@@ -979,12 +979,8 @@ qca_spi_probe(struct spi_device *spi) spi_set_drvdata(spi, qcaspi_devs); @@ -1036,7 +1036,7 @@ Signed-off-by: David S. Miller u32 mahr = ravb_read(ndev, MAHR); u32 malr = ravb_read(ndev, MALR); -@@ -2191,7 +2193,7 @@ static int ravb_probe(struct platform_de +@@ -2202,7 +2204,7 @@ static int ravb_probe(struct platform_de priv->msg_enable = RAVB_DEF_MSG_ENABLE; /* Read and set MAC address */ @@ -1360,7 +1360,7 @@ Signed-off-by: David S. Miller int irq; --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -5019,7 +5019,7 @@ int stmmac_dvr_probe(struct device *devi +@@ -5016,7 +5016,7 @@ int stmmac_dvr_probe(struct device *devi priv->wol_irq = res->wol_irq; priv->lpi_irq = res->lpi_irq; diff --git a/target/linux/generic/backport-5.10/735-v5.14-25-net-phy-add-support-for-qca8k-switch-internal-PHY-in.patch b/target/linux/generic/backport-5.10/735-v5.14-25-net-phy-add-support-for-qca8k-switch-internal-PHY-in.patch index 20325f564d4f51..7e6d8efe332462 100644 --- a/target/linux/generic/backport-5.10/735-v5.14-25-net-phy-add-support-for-qca8k-switch-internal-PHY-in.patch +++ b/target/linux/generic/backport-5.10/735-v5.14-25-net-phy-add-support-for-qca8k-switch-internal-PHY-in.patch @@ -205,7 +205,7 @@ Signed-off-by: David S. Miller static struct phy_driver at803x_driver[] = { { /* Qualcomm Atheros AR8035 */ -@@ -1198,7 +1315,20 @@ static struct phy_driver at803x_driver[] +@@ -1196,7 +1313,20 @@ static struct phy_driver at803x_driver[] .read_status = at803x_read_status, .soft_reset = genphy_soft_reset, .config_aneg = at803x_config_aneg, diff --git a/target/linux/generic/backport-5.10/742-v5.16-net-phy-at803x-add-support-for-qca-8327-internal-phy.patch b/target/linux/generic/backport-5.10/742-v5.16-net-phy-at803x-add-support-for-qca-8327-internal-phy.patch index 16aa0711ad7610..8428220f8cfa18 100644 --- a/target/linux/generic/backport-5.10/742-v5.16-net-phy-at803x-add-support-for-qca-8327-internal-phy.patch +++ b/target/linux/generic/backport-5.10/742-v5.16-net-phy-at803x-add-support-for-qca-8327-internal-phy.patch @@ -17,7 +17,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c -@@ -1328,6 +1328,19 @@ static struct phy_driver at803x_driver[] +@@ -1326,6 +1326,19 @@ static struct phy_driver at803x_driver[] .get_sset_count = at803x_get_sset_count, .get_strings = at803x_get_strings, .get_stats = at803x_get_stats, @@ -37,7 +37,7 @@ Signed-off-by: David S. Miller }, }; module_phy_driver(at803x_driver); -@@ -1338,6 +1351,8 @@ static struct mdio_device_id __maybe_unu +@@ -1336,6 +1349,8 @@ static struct mdio_device_id __maybe_unu { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, diff --git a/target/linux/generic/backport-5.10/745-v5.16-01-net-phy-at803x-add-support-for-qca-8327-A-variant.patch b/target/linux/generic/backport-5.10/745-v5.16-01-net-phy-at803x-add-support-for-qca-8327-A-variant.patch index c82bf913a09ce0..e4624102141f13 100644 --- a/target/linux/generic/backport-5.10/745-v5.16-01-net-phy-at803x-add-support-for-qca-8327-A-variant.patch +++ b/target/linux/generic/backport-5.10/745-v5.16-01-net-phy-at803x-add-support-for-qca-8327-A-variant.patch @@ -26,7 +26,7 @@ Signed-off-by: David S. Miller #define QCA8337_PHY_ID 0x004dd036 #define QCA8K_PHY_ID_MASK 0xffffffff -@@ -1329,10 +1330,23 @@ static struct phy_driver at803x_driver[] +@@ -1327,10 +1328,23 @@ static struct phy_driver at803x_driver[] .get_strings = at803x_get_strings, .get_stats = at803x_get_stats, }, { @@ -53,7 +53,7 @@ Signed-off-by: David S. Miller /* PHY_GBIT_FEATURES */ .probe = at803x_probe, .flags = PHY_IS_INTERNAL, -@@ -1352,7 +1366,8 @@ static struct mdio_device_id __maybe_unu +@@ -1350,7 +1364,8 @@ static struct mdio_device_id __maybe_unu { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) }, diff --git a/target/linux/generic/backport-5.10/745-v5.16-02-net-phy-at803x-add-resume-suspend-function-to-qca83x.patch b/target/linux/generic/backport-5.10/745-v5.16-02-net-phy-at803x-add-resume-suspend-function-to-qca83x.patch index be24fd5cf7bb04..3cd35d934b79f3 100644 --- a/target/linux/generic/backport-5.10/745-v5.16-02-net-phy-at803x-add-resume-suspend-function-to-qca83x.patch +++ b/target/linux/generic/backport-5.10/745-v5.16-02-net-phy-at803x-add-resume-suspend-function-to-qca83x.patch @@ -16,7 +16,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c -@@ -1329,6 +1329,8 @@ static struct phy_driver at803x_driver[] +@@ -1327,6 +1327,8 @@ static struct phy_driver at803x_driver[] .get_sset_count = at803x_get_sset_count, .get_strings = at803x_get_strings, .get_stats = at803x_get_stats, @@ -25,7 +25,7 @@ Signed-off-by: David S. Miller }, { /* QCA8327-A from switch QCA8327-AL1A */ .phy_id = QCA8327_A_PHY_ID, -@@ -1342,6 +1344,8 @@ static struct phy_driver at803x_driver[] +@@ -1340,6 +1342,8 @@ static struct phy_driver at803x_driver[] .get_sset_count = at803x_get_sset_count, .get_strings = at803x_get_strings, .get_stats = at803x_get_stats, @@ -34,7 +34,7 @@ Signed-off-by: David S. Miller }, { /* QCA8327-B from switch QCA8327-BL1A */ .phy_id = QCA8327_B_PHY_ID, -@@ -1355,6 +1359,8 @@ static struct phy_driver at803x_driver[] +@@ -1353,6 +1357,8 @@ static struct phy_driver at803x_driver[] .get_sset_count = at803x_get_sset_count, .get_strings = at803x_get_strings, .get_stats = at803x_get_stats, diff --git a/target/linux/generic/backport-5.10/745-v5.16-03-net-phy-at803x-fix-spacing-and-improve-name-for-83xx.patch b/target/linux/generic/backport-5.10/745-v5.16-03-net-phy-at803x-fix-spacing-and-improve-name-for-83xx.patch index 23f574c76fe55f..098b231be3f2f9 100644 --- a/target/linux/generic/backport-5.10/745-v5.16-03-net-phy-at803x-fix-spacing-and-improve-name-for-83xx.patch +++ b/target/linux/generic/backport-5.10/745-v5.16-03-net-phy-at803x-fix-spacing-and-improve-name-for-83xx.patch @@ -15,7 +15,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c -@@ -1318,47 +1318,47 @@ static struct phy_driver at803x_driver[] +@@ -1316,47 +1316,47 @@ static struct phy_driver at803x_driver[] .config_aneg = at803x_config_aneg, }, { /* QCA8337 */ diff --git a/target/linux/generic/backport-5.10/746-v5.16-01-net-phy-at803x-fix-resume-for-QCA8327-phy.patch b/target/linux/generic/backport-5.10/746-v5.16-01-net-phy-at803x-fix-resume-for-QCA8327-phy.patch index 5dfe27dd24dbd8..69c459db72cadf 100644 --- a/target/linux/generic/backport-5.10/746-v5.16-01-net-phy-at803x-fix-resume-for-QCA8327-phy.patch +++ b/target/linux/generic/backport-5.10/746-v5.16-01-net-phy-at803x-fix-resume-for-QCA8327-phy.patch @@ -96,7 +96,7 @@ Signed-off-by: David S. Miller static struct phy_driver at803x_driver[] = { { /* Qualcomm Atheros AR8035 */ -@@ -1329,8 +1386,8 @@ static struct phy_driver at803x_driver[] +@@ -1327,8 +1384,8 @@ static struct phy_driver at803x_driver[] .get_sset_count = at803x_get_sset_count, .get_strings = at803x_get_strings, .get_stats = at803x_get_stats, @@ -107,7 +107,7 @@ Signed-off-by: David S. Miller }, { /* QCA8327-A from switch QCA8327-AL1A */ .phy_id = QCA8327_A_PHY_ID, -@@ -1344,8 +1401,8 @@ static struct phy_driver at803x_driver[] +@@ -1342,8 +1399,8 @@ static struct phy_driver at803x_driver[] .get_sset_count = at803x_get_sset_count, .get_strings = at803x_get_strings, .get_stats = at803x_get_stats, @@ -118,7 +118,7 @@ Signed-off-by: David S. Miller }, { /* QCA8327-B from switch QCA8327-BL1A */ .phy_id = QCA8327_B_PHY_ID, -@@ -1359,8 +1416,8 @@ static struct phy_driver at803x_driver[] +@@ -1357,8 +1414,8 @@ static struct phy_driver at803x_driver[] .get_sset_count = at803x_get_sset_count, .get_strings = at803x_get_strings, .get_stats = at803x_get_stats, diff --git a/target/linux/generic/backport-5.10/746-v5.16-02-net-phy-at803x-add-DAC-amplitude-fix-for-8327-phy.patch b/target/linux/generic/backport-5.10/746-v5.16-02-net-phy-at803x-add-DAC-amplitude-fix-for-8327-phy.patch index aeb43e2f67dbf3..be528522d19b43 100644 --- a/target/linux/generic/backport-5.10/746-v5.16-02-net-phy-at803x-add-DAC-amplitude-fix-for-8327-phy.patch +++ b/target/linux/generic/backport-5.10/746-v5.16-02-net-phy-at803x-add-DAC-amplitude-fix-for-8327-phy.patch @@ -65,7 +65,7 @@ Signed-off-by: David S. Miller static int qca83xx_resume(struct phy_device *phydev) { int ret, val; -@@ -1379,6 +1409,7 @@ static struct phy_driver at803x_driver[] +@@ -1377,6 +1407,7 @@ static struct phy_driver at803x_driver[] .phy_id_mask = QCA8K_PHY_ID_MASK, .name = "Qualcomm Atheros 8337 internal PHY", /* PHY_GBIT_FEATURES */ @@ -73,7 +73,7 @@ Signed-off-by: David S. Miller .probe = at803x_probe, .flags = PHY_IS_INTERNAL, .config_init = qca83xx_config_init, -@@ -1394,6 +1425,7 @@ static struct phy_driver at803x_driver[] +@@ -1392,6 +1423,7 @@ static struct phy_driver at803x_driver[] .phy_id_mask = QCA8K_PHY_ID_MASK, .name = "Qualcomm Atheros 8327-A internal PHY", /* PHY_GBIT_FEATURES */ @@ -81,7 +81,7 @@ Signed-off-by: David S. Miller .probe = at803x_probe, .flags = PHY_IS_INTERNAL, .config_init = qca83xx_config_init, -@@ -1409,6 +1441,7 @@ static struct phy_driver at803x_driver[] +@@ -1407,6 +1439,7 @@ static struct phy_driver at803x_driver[] .phy_id_mask = QCA8K_PHY_ID_MASK, .name = "Qualcomm Atheros 8327-B internal PHY", /* PHY_GBIT_FEATURES */ diff --git a/target/linux/generic/backport-5.10/782-v5.11-net-usb-r8153_ecm-support-ECM-mode-for-RTL8153.patch b/target/linux/generic/backport-5.10/782-v5.11-net-usb-r8153_ecm-support-ECM-mode-for-RTL8153.patch index 67c762d28cb41f..ffad91a8fa5113 100644 --- a/target/linux/generic/backport-5.10/782-v5.11-net-usb-r8153_ecm-support-ECM-mode-for-RTL8153.patch +++ b/target/linux/generic/backport-5.10/782-v5.11-net-usb-r8153_ecm-support-ECM-mode-for-RTL8153.patch @@ -89,7 +89,7 @@ Signed-off-by: Jakub Kicinski struct tally_counter { __le64 tx_packets; __le64 rx_packets; -@@ -6604,7 +6581,7 @@ static int rtl_fw_init(struct r8152 *tp) +@@ -6607,7 +6584,7 @@ static int rtl_fw_init(struct r8152 *tp) return 0; } @@ -98,7 +98,7 @@ Signed-off-by: Jakub Kicinski { struct usb_device *udev = interface_to_usbdev(intf); u32 ocp_data = 0; -@@ -6662,12 +6639,13 @@ static u8 rtl_get_version(struct usb_int +@@ -6666,12 +6643,13 @@ static u8 rtl_get_version(struct usb_int return version; } diff --git a/target/linux/generic/backport-5.10/783-v5.12-net-usb-r8152-use-new-tasklet-API.patch b/target/linux/generic/backport-5.10/783-v5.12-net-usb-r8152-use-new-tasklet-API.patch index 1f43340c68da39..d1cf7d5313d108 100644 --- a/target/linux/generic/backport-5.10/783-v5.12-net-usb-r8152-use-new-tasklet-API.patch +++ b/target/linux/generic/backport-5.10/783-v5.12-net-usb-r8152-use-new-tasklet-API.patch @@ -30,7 +30,7 @@ Signed-off-by: Jakub Kicinski if (test_bit(RTL8152_UNPLUG, &tp->flags)) return; -@@ -6697,7 +6695,7 @@ static int rtl8152_probe(struct usb_inte +@@ -6701,7 +6699,7 @@ static int rtl8152_probe(struct usb_inte mutex_init(&tp->control); INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t); diff --git a/target/linux/generic/backport-5.10/784-v5.12-r8152-replace-several-functions-about-phy-patch-requ.patch b/target/linux/generic/backport-5.10/784-v5.12-r8152-replace-several-functions-about-phy-patch-requ.patch index 759a09ae091749..267cb26d4a7231 100644 --- a/target/linux/generic/backport-5.10/784-v5.12-r8152-replace-several-functions-about-phy-patch-requ.patch +++ b/target/linux/generic/backport-5.10/784-v5.12-r8152-replace-several-functions-about-phy-patch-requ.patch @@ -25,7 +25,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c -@@ -3445,59 +3445,76 @@ static void rtl_clear_bp(struct r8152 *t +@@ -3448,59 +3448,76 @@ static void rtl_clear_bp(struct r8152 *t ocp_write_word(tp, type, PLA_BP_BA, 0); } @@ -127,7 +127,7 @@ Signed-off-by: Jakub Kicinski ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, tp->ocp_base); -@@ -3982,7 +3999,7 @@ static void rtl8152_fw_mac_apply(struct +@@ -3985,7 +4002,7 @@ static void rtl8152_fw_mac_apply(struct dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info); } @@ -136,7 +136,7 @@ Signed-off-by: Jakub Kicinski { struct rtl_fw *rtl_fw = &tp->rtl_fw; const struct firmware *fw; -@@ -4013,12 +4030,11 @@ static void rtl8152_apply_firmware(struc +@@ -4016,12 +4033,11 @@ static void rtl8152_apply_firmware(struc case RTL_FW_PHY_START: key = (struct fw_phy_patch_key *)block; key_addr = __le16_to_cpu(key->key_reg); @@ -151,7 +151,7 @@ Signed-off-by: Jakub Kicinski break; case RTL_FW_PHY_NC: rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block); -@@ -4223,7 +4239,7 @@ static void rtl8152_disable(struct r8152 +@@ -4226,7 +4242,7 @@ static void rtl8152_disable(struct r8152 static void r8152b_hw_phy_cfg(struct r8152 *tp) { @@ -160,7 +160,7 @@ Signed-off-by: Jakub Kicinski rtl_eee_enable(tp, tp->eee_en); r8152_aldps_en(tp, true); r8152b_enable_fc(tp); -@@ -4505,7 +4521,7 @@ static void r8153_hw_phy_cfg(struct r815 +@@ -4508,7 +4524,7 @@ static void r8153_hw_phy_cfg(struct r815 /* disable EEE before updating the PHY parameters */ rtl_eee_enable(tp, false); @@ -169,7 +169,7 @@ Signed-off-by: Jakub Kicinski if (tp->version == RTL_VER_03) { data = ocp_reg_read(tp, OCP_EEE_CFG); -@@ -4579,7 +4595,7 @@ static void r8153b_hw_phy_cfg(struct r81 +@@ -4582,7 +4598,7 @@ static void r8153b_hw_phy_cfg(struct r81 /* disable EEE before updating the PHY parameters */ rtl_eee_enable(tp, false); @@ -178,7 +178,7 @@ Signed-off-by: Jakub Kicinski r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); -@@ -4620,7 +4636,7 @@ static void r8153b_hw_phy_cfg(struct r81 +@@ -4623,7 +4639,7 @@ static void r8153b_hw_phy_cfg(struct r81 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); /* Advnace EEE */ @@ -187,7 +187,7 @@ Signed-off-by: Jakub Kicinski data = ocp_reg_read(tp, OCP_POWER_CFG); data |= EEE_CLKDIV_EN; ocp_reg_write(tp, OCP_POWER_CFG, data); -@@ -4637,7 +4653,7 @@ static void r8153b_hw_phy_cfg(struct r81 +@@ -4640,7 +4656,7 @@ static void r8153b_hw_phy_cfg(struct r81 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5)); tp->ups_info._250m_ckdiv = true; diff --git a/target/linux/generic/backport-5.10/785-v5.12-r8152-adjust-the-flow-of-power-cut-for-RTL8153B.patch b/target/linux/generic/backport-5.10/785-v5.12-r8152-adjust-the-flow-of-power-cut-for-RTL8153B.patch index 33969c7a546f23..313902d7ebf461 100644 --- a/target/linux/generic/backport-5.10/785-v5.12-r8152-adjust-the-flow-of-power-cut-for-RTL8153B.patch +++ b/target/linux/generic/backport-5.10/785-v5.12-r8152-adjust-the-flow-of-power-cut-for-RTL8153B.patch @@ -31,7 +31,7 @@ Signed-off-by: Jakub Kicinski static int rtl8152_set_mac_address(struct net_device *netdev, void *p) { struct r8152 *tp = netdev_priv(netdev); -@@ -3184,8 +3188,6 @@ static void r8153b_ups_en(struct r8152 * +@@ -3187,8 +3191,6 @@ static void r8153b_ups_en(struct r8152 * ocp_data |= BIT(0); ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); } else { @@ -40,7 +40,7 @@ Signed-off-by: Jakub Kicinski ocp_data &= ~(UPS_EN | USP_PREWAKE); ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); -@@ -3193,31 +3195,20 @@ static void r8153b_ups_en(struct r8152 * +@@ -3196,31 +3198,20 @@ static void r8153b_ups_en(struct r8152 * ocp_data &= ~BIT(0); ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); @@ -83,7 +83,7 @@ Signed-off-by: Jakub Kicinski } } } -@@ -4589,13 +4580,37 @@ static void r8153b_hw_phy_cfg(struct r81 +@@ -4592,13 +4583,37 @@ static void r8153b_hw_phy_cfg(struct r81 u32 ocp_data; u16 data; @@ -122,7 +122,7 @@ Signed-off-by: Jakub Kicinski r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); -@@ -5524,9 +5539,6 @@ static void r8153b_init(struct r8152 *tp +@@ -5527,9 +5542,6 @@ static void r8153b_init(struct r8152 *tp /* MSC timer = 0xfff * 8ms = 32760 ms */ ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); diff --git a/target/linux/generic/backport-5.10/786-v5.12-r8152-enable-U1-U2-for-USB_SPEED_SUPER.patch b/target/linux/generic/backport-5.10/786-v5.12-r8152-enable-U1-U2-for-USB_SPEED_SUPER.patch index 6815fabe102128..1159aa6c7577b6 100644 --- a/target/linux/generic/backport-5.10/786-v5.12-r8152-enable-U1-U2-for-USB_SPEED_SUPER.patch +++ b/target/linux/generic/backport-5.10/786-v5.12-r8152-enable-U1-U2-for-USB_SPEED_SUPER.patch @@ -16,7 +16,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c -@@ -3337,7 +3337,7 @@ static void rtl8153b_runtime_enable(stru +@@ -3340,7 +3340,7 @@ static void rtl8153b_runtime_enable(stru r8153b_ups_en(tp, false); r8153_queue_wake(tp, false); rtl_runtime_suspend_enable(tp, false); @@ -25,7 +25,7 @@ Signed-off-by: Jakub Kicinski r8153b_u1u2en(tp, true); } } -@@ -5030,7 +5030,7 @@ static void rtl8153b_up(struct r8152 *tp +@@ -5033,7 +5033,7 @@ static void rtl8153b_up(struct r8152 *tp r8153_aldps_en(tp, true); @@ -34,7 +34,7 @@ Signed-off-by: Jakub Kicinski r8153b_u1u2en(tp, true); } -@@ -5552,8 +5552,9 @@ static void r8153b_init(struct r8152 *tp +@@ -5555,8 +5555,9 @@ static void r8153b_init(struct r8152 *tp ocp_data |= POLL_LINK_CHG; ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); diff --git a/target/linux/generic/backport-5.10/787-v5.12-r8152-check-if-the-pointer-of-the-function-exists.patch b/target/linux/generic/backport-5.10/787-v5.12-r8152-check-if-the-pointer-of-the-function-exists.patch index f13626faf0c988..b0827ea43215b4 100644 --- a/target/linux/generic/backport-5.10/787-v5.12-r8152-check-if-the-pointer-of-the-function-exists.patch +++ b/target/linux/generic/backport-5.10/787-v5.12-r8152-check-if-the-pointer-of-the-function-exists.patch @@ -15,7 +15,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c -@@ -5737,6 +5737,9 @@ static int rtl8152_runtime_suspend(struc +@@ -5740,6 +5740,9 @@ static int rtl8152_runtime_suspend(struc struct net_device *netdev = tp->netdev; int ret = 0; @@ -25,7 +25,7 @@ Signed-off-by: Jakub Kicinski set_bit(SELECTIVE_SUSPEND, &tp->flags); smp_mb__after_atomic(); -@@ -6136,6 +6139,11 @@ rtl_ethtool_get_eee(struct net_device *n +@@ -6139,6 +6142,11 @@ rtl_ethtool_get_eee(struct net_device *n struct r8152 *tp = netdev_priv(net); int ret; @@ -37,7 +37,7 @@ Signed-off-by: Jakub Kicinski ret = usb_autopm_get_interface(tp->intf); if (ret < 0) goto out; -@@ -6158,6 +6166,11 @@ rtl_ethtool_set_eee(struct net_device *n +@@ -6161,6 +6169,11 @@ rtl_ethtool_set_eee(struct net_device *n struct r8152 *tp = netdev_priv(net); int ret; diff --git a/target/linux/generic/backport-5.10/788-v5.12-r8152-replace-netif_err-with-dev_err.patch b/target/linux/generic/backport-5.10/788-v5.12-r8152-replace-netif_err-with-dev_err.patch index 24c606b5f527ab..efddfc6ae3cc6d 100644 --- a/target/linux/generic/backport-5.10/788-v5.12-r8152-replace-netif_err-with-dev_err.patch +++ b/target/linux/generic/backport-5.10/788-v5.12-r8152-replace-netif_err-with-dev_err.patch @@ -16,7 +16,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c -@@ -6573,7 +6573,7 @@ static int rtl_ops_init(struct r8152 *tp +@@ -6576,7 +6576,7 @@ static int rtl_ops_init(struct r8152 *tp default: ret = -ENODEV; @@ -25,7 +25,7 @@ Signed-off-by: Jakub Kicinski break; } -@@ -6830,7 +6830,7 @@ static int rtl8152_probe(struct usb_inte +@@ -6834,7 +6834,7 @@ static int rtl8152_probe(struct usb_inte ret = register_netdev(netdev); if (ret != 0) { diff --git a/target/linux/generic/backport-5.10/789-v5.12-r8152-spilt-rtl_set_eee_plus-and-r8153b_green_en.patch b/target/linux/generic/backport-5.10/789-v5.12-r8152-spilt-rtl_set_eee_plus-and-r8153b_green_en.patch index c5e7ff96242932..d0418602bdb83a 100644 --- a/target/linux/generic/backport-5.10/789-v5.12-r8152-spilt-rtl_set_eee_plus-and-r8153b_green_en.patch +++ b/target/linux/generic/backport-5.10/789-v5.12-r8152-spilt-rtl_set_eee_plus-and-r8153b_green_en.patch @@ -15,7 +15,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c -@@ -2634,21 +2634,24 @@ static inline u8 rtl8152_get_speed(struc +@@ -2637,21 +2637,24 @@ static inline u8 rtl8152_get_speed(struc return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); } @@ -50,7 +50,7 @@ Signed-off-by: Jakub Kicinski } static void rxdy_gated_en(struct r8152 *tp, bool enable) -@@ -3129,10 +3132,22 @@ static void r8153b_ups_flags(struct r815 +@@ -3132,10 +3135,22 @@ static void r8153b_ups_flags(struct r815 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags); } @@ -74,7 +74,7 @@ Signed-off-by: Jakub Kicinski if (enable) { sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */ sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */ -@@ -3143,11 +3158,7 @@ static void r8153b_green_en(struct r8152 +@@ -3146,11 +3161,7 @@ static void r8153b_green_en(struct r8152 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */ } diff --git a/target/linux/generic/backport-5.10/790-v5.13-r8152-set-inter-fram-gap-time-depending-on-speed.patch b/target/linux/generic/backport-5.10/790-v5.13-r8152-set-inter-fram-gap-time-depending-on-speed.patch index 9ed92328c397f4..db337fdb852a06 100644 --- a/target/linux/generic/backport-5.10/790-v5.13-r8152-set-inter-fram-gap-time-depending-on-speed.patch +++ b/target/linux/generic/backport-5.10/790-v5.13-r8152-set-inter-fram-gap-time-depending-on-speed.patch @@ -34,7 +34,7 @@ Signed-off-by: David S. Miller /* PLA_MTPS */ #define MTPS_JUMBO (12 * 1024 / 64) -@@ -2749,6 +2752,29 @@ static int rtl_stop_rx(struct r8152 *tp) +@@ -2752,6 +2755,29 @@ static int rtl_stop_rx(struct r8152 *tp) return 0; } @@ -64,7 +64,7 @@ Signed-off-by: David S. Miller static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp) { ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN, -@@ -2852,6 +2878,8 @@ static int rtl8153_enable(struct r8152 * +@@ -2855,6 +2881,8 @@ static int rtl8153_enable(struct r8152 * r8153_set_rx_early_timeout(tp); r8153_set_rx_early_size(tp); diff --git a/target/linux/generic/backport-5.10/791-v5.13-r8152-adjust-rtl8152_check_firmware-function.patch b/target/linux/generic/backport-5.10/791-v5.13-r8152-adjust-rtl8152_check_firmware-function.patch index c61c4bb98a97e5..2774bc79a82a1f 100644 --- a/target/linux/generic/backport-5.10/791-v5.13-r8152-adjust-rtl8152_check_firmware-function.patch +++ b/target/linux/generic/backport-5.10/791-v5.13-r8152-adjust-rtl8152_check_firmware-function.patch @@ -30,7 +30,7 @@ Signed-off-by: David S. Miller /** * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB. * The layout of the firmware block is: -@@ -3802,10 +3810,7 @@ static long rtl8152_check_firmware(struc +@@ -3805,10 +3813,7 @@ static long rtl8152_check_firmware(struc { const struct firmware *fw = rtl_fw->fw; struct fw_header *fw_hdr = (struct fw_header *)fw->data; @@ -42,7 +42,7 @@ Signed-off-by: David S. Miller long ret = -EFAULT; int i; -@@ -3834,50 +3839,52 @@ static long rtl8152_check_firmware(struc +@@ -3837,50 +3842,52 @@ static long rtl8152_check_firmware(struc goto fail; goto fw_end; case RTL_FW_PLA: @@ -106,7 +106,7 @@ Signed-off-by: David S. Miller dev_err(&tp->intf->dev, "Check PHY_STOP fail\n"); goto fail; -@@ -3888,28 +3895,28 @@ static long rtl8152_check_firmware(struc +@@ -3891,28 +3898,28 @@ static long rtl8152_check_firmware(struc "Invalid length for PHY_STOP\n"); goto fail; } @@ -141,7 +141,7 @@ Signed-off-by: David S. Miller break; default: -@@ -3923,7 +3930,7 @@ static long rtl8152_check_firmware(struc +@@ -3926,7 +3933,7 @@ static long rtl8152_check_firmware(struc } fw_end: diff --git a/target/linux/generic/backport-5.10/792-v5.13-r8152-add-help-function-to-change-mtu.patch b/target/linux/generic/backport-5.10/792-v5.13-r8152-add-help-function-to-change-mtu.patch index cd7a514b71ff0f..3d067708661c33 100644 --- a/target/linux/generic/backport-5.10/792-v5.13-r8152-add-help-function-to-change-mtu.patch +++ b/target/linux/generic/backport-5.10/792-v5.13-r8152-add-help-function-to-change-mtu.patch @@ -57,7 +57,7 @@ Signed-off-by: David S. Miller static int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) -@@ -2634,10 +2632,7 @@ static void rtl8152_nic_reset(struct r81 +@@ -2637,10 +2635,7 @@ static void rtl8152_nic_reset(struct r81 static void set_tx_qlen(struct r8152 *tp) { @@ -69,7 +69,7 @@ Signed-off-by: David S. Miller } static inline u8 rtl8152_get_speed(struct r8152 *tp) -@@ -4726,6 +4721,12 @@ static void r8153b_hw_phy_cfg(struct r81 +@@ -4729,6 +4724,12 @@ static void r8153b_hw_phy_cfg(struct r81 set_bit(PHY_RESET, &tp->flags); } @@ -82,7 +82,7 @@ Signed-off-by: David S. Miller static void r8153_first_init(struct r8152 *tp) { u32 ocp_data; -@@ -4758,9 +4759,7 @@ static void r8153_first_init(struct r815 +@@ -4761,9 +4762,7 @@ static void r8153_first_init(struct r815 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); @@ -93,7 +93,7 @@ Signed-off-by: David S. Miller ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); ocp_data |= TCR0_AUTO_FIFO; -@@ -4795,8 +4794,7 @@ static void r8153_enter_oob(struct r8152 +@@ -4798,8 +4797,7 @@ static void r8153_enter_oob(struct r8152 wait_oob_link_list_ready(tp); @@ -103,7 +103,7 @@ Signed-off-by: David S. Miller switch (tp->version) { case RTL_VER_03: -@@ -6497,12 +6495,21 @@ static int rtl8152_change_mtu(struct net +@@ -6500,12 +6498,21 @@ static int rtl8152_change_mtu(struct net dev->mtu = new_mtu; if (netif_running(dev)) { @@ -130,7 +130,7 @@ Signed-off-by: David S. Miller } mutex_unlock(&tp->control); -@@ -6591,6 +6598,7 @@ static int rtl_ops_init(struct r8152 *tp +@@ -6594,6 +6601,7 @@ static int rtl_ops_init(struct r8152 *tp ops->in_nway = rtl8153_in_nway; ops->hw_phy_cfg = r8153_hw_phy_cfg; ops->autosuspend_en = rtl8153_runtime_enable; @@ -138,7 +138,7 @@ Signed-off-by: David S. Miller if (tp->udev->speed < USB_SPEED_SUPER) tp->rx_buf_sz = 16 * 1024; else -@@ -6612,6 +6620,7 @@ static int rtl_ops_init(struct r8152 *tp +@@ -6615,6 +6623,7 @@ static int rtl_ops_init(struct r8152 *tp ops->in_nway = rtl8153_in_nway; ops->hw_phy_cfg = r8153b_hw_phy_cfg; ops->autosuspend_en = rtl8153b_runtime_enable; @@ -146,7 +146,7 @@ Signed-off-by: David S. Miller tp->rx_buf_sz = 32 * 1024; tp->eee_en = true; tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; -@@ -6832,7 +6841,7 @@ static int rtl8152_probe(struct usb_inte +@@ -6836,7 +6845,7 @@ static int rtl8152_probe(struct usb_inte netdev->max_mtu = ETH_DATA_LEN; break; default: diff --git a/target/linux/generic/backport-5.10/793-v5.13-r8152-support-new-chips.patch b/target/linux/generic/backport-5.10/793-v5.13-r8152-support-new-chips.patch index 15332295643722..2e7130fd779611 100644 --- a/target/linux/generic/backport-5.10/793-v5.13-r8152-support-new-chips.patch +++ b/target/linux/generic/backport-5.10/793-v5.13-r8152-support-new-chips.patch @@ -379,7 +379,7 @@ Signed-off-by: David S. Miller /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). * The RTL chips use a 64 element hash table based on the Ethernet CRC. -@@ -2608,7 +2713,7 @@ static netdev_tx_t rtl8152_start_xmit(st +@@ -2611,7 +2716,7 @@ static netdev_tx_t rtl8152_start_xmit(st static void r8152b_reset_packet_filter(struct r8152 *tp) { @@ -388,7 +388,7 @@ Signed-off-by: David S. Miller ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); ocp_data &= ~FMC_FCR_MCU_EN; -@@ -2619,14 +2724,47 @@ static void r8152b_reset_packet_filter(s +@@ -2622,14 +2727,47 @@ static void r8152b_reset_packet_filter(s static void rtl8152_nic_reset(struct r8152 *tp) { @@ -442,7 +442,7 @@ Signed-off-by: David S. Miller } } -@@ -2635,9 +2773,9 @@ static void set_tx_qlen(struct r8152 *tp +@@ -2638,9 +2776,9 @@ static void set_tx_qlen(struct r8152 *tp tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc)); } @@ -454,7 +454,7 @@ Signed-off-by: David S. Miller } static void rtl_eee_plus_en(struct r8152 *tp, bool enable) -@@ -2797,6 +2935,7 @@ static int rtl_enable(struct r8152 *tp) +@@ -2800,6 +2938,7 @@ static int rtl_enable(struct r8152 *tp) switch (tp->version) { case RTL_VER_08: case RTL_VER_09: @@ -462,7 +462,7 @@ Signed-off-by: David S. Miller r8153b_rx_agg_chg_indicate(tp); break; default: -@@ -2834,6 +2973,7 @@ static void r8153_set_rx_early_timeout(s +@@ -2837,6 +2976,7 @@ static void r8153_set_rx_early_timeout(s case RTL_VER_08: case RTL_VER_09: @@ -470,7 +470,7 @@ Signed-off-by: David S. Miller /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns. */ -@@ -2843,6 +2983,18 @@ static void r8153_set_rx_early_timeout(s +@@ -2846,6 +2986,18 @@ static void r8153_set_rx_early_timeout(s ocp_data); break; @@ -489,7 +489,7 @@ Signed-off-by: David S. Miller default: break; } -@@ -2862,8 +3014,19 @@ static void r8153_set_rx_early_size(stru +@@ -2865,8 +3017,19 @@ static void r8153_set_rx_early_size(stru break; case RTL_VER_08: case RTL_VER_09: @@ -509,7 +509,7 @@ Signed-off-by: David S. Miller break; default: WARN_ON_ONCE(1); -@@ -2873,6 +3036,8 @@ static void r8153_set_rx_early_size(stru +@@ -2876,6 +3039,8 @@ static void r8153_set_rx_early_size(stru static int rtl8153_enable(struct r8152 *tp) { @@ -518,7 +518,7 @@ Signed-off-by: David S. Miller if (test_bit(RTL8152_UNPLUG, &tp->flags)) return -ENODEV; -@@ -2883,15 +3048,18 @@ static int rtl8153_enable(struct r8152 * +@@ -2886,15 +3051,18 @@ static int rtl8153_enable(struct r8152 * rtl_set_ifg(tp, rtl8152_get_speed(tp)); @@ -540,7 +540,7 @@ Signed-off-by: David S. Miller } return rtl_enable(tp); -@@ -2956,12 +3124,40 @@ static void rtl_rx_vlan_en(struct r8152 +@@ -2959,12 +3127,40 @@ static void rtl_rx_vlan_en(struct r8152 { u32 ocp_data; @@ -587,7 +587,7 @@ Signed-off-by: David S. Miller } static int rtl8152_set_features(struct net_device *dev, -@@ -3054,6 +3250,40 @@ static void __rtl_set_wol(struct r8152 * +@@ -3057,6 +3253,40 @@ static void __rtl_set_wol(struct r8152 * device_set_wakeup_enable(&tp->udev->dev, false); } @@ -628,7 +628,7 @@ Signed-off-by: David S. Miller static void r8153_u1u2en(struct r8152 *tp, bool enable) { u8 u1u2[8]; -@@ -3113,6 +3343,9 @@ static void r8153b_ups_flags(struct r815 +@@ -3116,6 +3346,9 @@ static void r8153b_ups_flags(struct r815 if (tp->ups_info.eee_cmod_lv) ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN; @@ -638,7 +638,7 @@ Signed-off-by: David S. Miller if (tp->ups_info._10m_ckdiv) ups_flags |= UPS_FLAGS_EN_10M_CKDIV; -@@ -3163,6 +3396,88 @@ static void r8153b_ups_flags(struct r815 +@@ -3166,6 +3399,88 @@ static void r8153b_ups_flags(struct r815 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags); } @@ -727,7 +727,7 @@ Signed-off-by: David S. Miller static void rtl_green_en(struct r8152 *tp, bool enable) { u16 data; -@@ -3226,16 +3541,16 @@ static void r8153b_ups_en(struct r8152 * +@@ -3229,16 +3544,16 @@ static void r8153b_ups_en(struct r8152 * ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); @@ -750,7 +750,7 @@ Signed-off-by: David S. Miller if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { int i; -@@ -3255,6 +3570,95 @@ static void r8153b_ups_en(struct r8152 * +@@ -3258,6 +3573,95 @@ static void r8153b_ups_en(struct r8152 * } } @@ -846,7 +846,7 @@ Signed-off-by: David S. Miller static void r8153_power_cut_en(struct r8152 *tp, bool enable) { u32 ocp_data; -@@ -3384,6 +3788,38 @@ static void rtl8153b_runtime_enable(stru +@@ -3387,6 +3791,38 @@ static void rtl8153b_runtime_enable(stru } } @@ -885,7 +885,7 @@ Signed-off-by: David S. Miller static void r8153_teredo_off(struct r8152 *tp) { u32 ocp_data; -@@ -3404,14 +3840,19 @@ static void r8153_teredo_off(struct r815 +@@ -3407,14 +3843,19 @@ static void r8153_teredo_off(struct r815 case RTL_VER_08: case RTL_VER_09: @@ -908,7 +908,7 @@ Signed-off-by: David S. Miller } ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); -@@ -3446,6 +3887,12 @@ static void rtl_clear_bp(struct r8152 *t +@@ -3449,6 +3890,12 @@ static void rtl_clear_bp(struct r8152 *t break; case RTL_VER_08: case RTL_VER_09: @@ -921,7 +921,7 @@ Signed-off-by: David S. Miller default: if (type == MCU_TYPE_USB) { ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0); -@@ -3655,6 +4102,11 @@ static bool rtl8152_is_fw_mac_ok(struct +@@ -3658,6 +4105,11 @@ static bool rtl8152_is_fw_mac_ok(struct case RTL_VER_06: case RTL_VER_08: case RTL_VER_09: @@ -933,7 +933,7 @@ Signed-off-by: David S. Miller fw_reg = 0xf800; bp_ba_addr = PLA_BP_BA; bp_en_addr = PLA_BP_EN; -@@ -3678,6 +4130,11 @@ static bool rtl8152_is_fw_mac_ok(struct +@@ -3681,6 +4133,11 @@ static bool rtl8152_is_fw_mac_ok(struct break; case RTL_VER_08: case RTL_VER_09: @@ -945,7 +945,7 @@ Signed-off-by: David S. Miller fw_reg = 0xe600; bp_ba_addr = USB_BP_BA; bp_en_addr = USB_BP2_EN; -@@ -4217,6 +4674,22 @@ static void r8153_eee_en(struct r8152 *t +@@ -4220,6 +4677,22 @@ static void r8153_eee_en(struct r8152 *t tp->ups_info.eee = enable; } @@ -968,7 +968,7 @@ Signed-off-by: David S. Miller static void rtl_eee_enable(struct r8152 *tp, bool enable) { switch (tp->version) { -@@ -4238,6 +4711,7 @@ static void rtl_eee_enable(struct r8152 +@@ -4241,6 +4714,7 @@ static void rtl_eee_enable(struct r8152 case RTL_VER_06: case RTL_VER_08: case RTL_VER_09: @@ -976,7 +976,7 @@ Signed-off-by: David S. Miller if (enable) { r8153_eee_en(tp, true); ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv); -@@ -4246,6 +4720,19 @@ static void rtl_eee_enable(struct r8152 +@@ -4249,6 +4723,19 @@ static void rtl_eee_enable(struct r8152 ocp_reg_write(tp, OCP_EEE_ADV, 0); } break; @@ -996,7 +996,7 @@ Signed-off-by: David S. Miller default: break; } -@@ -4292,6 +4779,20 @@ static void wait_oob_link_list_ready(str +@@ -4295,6 +4782,20 @@ static void wait_oob_link_list_ready(str } } @@ -1017,7 +1017,7 @@ Signed-off-by: David S. Miller static void r8152b_exit_oob(struct r8152 *tp) { u32 ocp_data; -@@ -4342,7 +4843,7 @@ static void r8152b_exit_oob(struct r8152 +@@ -4345,7 +4846,7 @@ static void r8152b_exit_oob(struct r8152 } /* TX share fifo free credit full threshold */ @@ -1026,7 +1026,7 @@ Signed-off-by: David S. Miller ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); -@@ -4519,6 +5020,21 @@ static int r8153b_post_firmware_1(struct +@@ -4522,6 +5023,21 @@ static int r8153b_post_firmware_1(struct return 0; } @@ -1048,7 +1048,7 @@ Signed-off-by: David S. Miller static void r8153_aldps_en(struct r8152 *tp, bool enable) { u16 data; -@@ -4721,6 +5237,13 @@ static void r8153b_hw_phy_cfg(struct r81 +@@ -4724,6 +5240,13 @@ static void r8153b_hw_phy_cfg(struct r81 set_bit(PHY_RESET, &tp->flags); } @@ -1062,7 +1062,7 @@ Signed-off-by: David S. Miller static void rtl8153_change_mtu(struct r8152 *tp) { ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu)); -@@ -4808,6 +5331,7 @@ static void r8153_enter_oob(struct r8152 +@@ -4811,6 +5334,7 @@ static void r8153_enter_oob(struct r8152 case RTL_VER_08: case RTL_VER_09: @@ -1070,7 +1070,7 @@ Signed-off-by: David S. Miller /* Clear teredo wake event. bit[15:8] is the teredo wakeup * type. Set it to zero. bits[7:0] are the W1C bits about * the events. Set them to all 1 to clear them. -@@ -4844,6 +5368,96 @@ static void rtl8153_disable(struct r8152 +@@ -4847,6 +5371,96 @@ static void rtl8153_disable(struct r8152 r8153_aldps_en(tp, true); } @@ -1167,7 +1167,7 @@ Signed-off-by: David S. Miller static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex, u32 advertising) { -@@ -4892,58 +5506,73 @@ static int rtl8152_set_speed(struct r815 +@@ -4895,58 +5509,73 @@ static int rtl8152_set_speed(struct r815 tp->mii.force_media = 1; } else { @@ -1259,7 +1259,7 @@ Signed-off-by: David S. Miller } bmcr = BMCR_ANENABLE | BMCR_ANRESTART; -@@ -5099,6 +5728,253 @@ static void rtl8153b_down(struct r8152 * +@@ -5102,6 +5731,253 @@ static void rtl8153b_down(struct r8152 * r8153_aldps_en(tp, true); } @@ -1513,7 +1513,7 @@ Signed-off-by: David S. Miller static bool rtl8152_in_nway(struct r8152 *tp) { u16 nway_state; -@@ -5129,7 +6005,7 @@ static void set_carrier(struct r8152 *tp +@@ -5132,7 +6008,7 @@ static void set_carrier(struct r8152 *tp { struct net_device *netdev = tp->netdev; struct napi_struct *napi = &tp->napi; @@ -1522,7 +1522,7 @@ Signed-off-by: David S. Miller speed = rtl8152_get_speed(tp); -@@ -5142,7 +6018,7 @@ static void set_carrier(struct r8152 *tp +@@ -5145,7 +6021,7 @@ static void set_carrier(struct r8152 *tp rtl_start_rx(tp); clear_bit(RTL8152_SET_RX_MODE, &tp->flags); _rtl8152_set_rx_mode(netdev); @@ -1531,7 +1531,7 @@ Signed-off-by: David S. Miller netif_wake_queue(netdev); netif_info(tp, link, netdev, "carrier on\n"); } else if (netif_queue_stopped(netdev) && -@@ -5504,14 +6380,9 @@ static void r8153_init(struct r8152 *tp) +@@ -5507,14 +6383,9 @@ static void r8153_init(struct r8152 *tp) ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); @@ -1547,7 +1547,7 @@ Signed-off-by: David S. Miller r8153_u1u2en(tp, true); usb_enable_lpm(tp->udev); -@@ -5602,9 +6473,7 @@ static void r8153b_init(struct r8152 *tp +@@ -5605,9 +6476,7 @@ static void r8153b_init(struct r8152 *tp usb_enable_lpm(tp->udev); /* MAC clock speed down */ @@ -1558,7 +1558,7 @@ Signed-off-by: David S. Miller ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); ocp_data &= ~PLA_MCU_SPDWN_EN; -@@ -5631,6 +6500,1069 @@ static void r8153b_init(struct r8152 *tp +@@ -5634,6 +6503,1069 @@ static void r8153b_init(struct r8152 *tp tp->coalesce = 15000; /* 15 us */ } @@ -2628,7 +2628,7 @@ Signed-off-by: David S. Miller static int rtl8152_pre_reset(struct usb_interface *intf) { struct r8152 *tp = usb_get_intfdata(intf); -@@ -5994,6 +7926,22 @@ int rtl8152_get_link_ksettings(struct ne +@@ -5997,6 +7929,22 @@ int rtl8152_get_link_ksettings(struct ne mii_ethtool_get_link_ksettings(&tp->mii, cmd); @@ -2651,7 +2651,7 @@ Signed-off-by: David S. Miller mutex_unlock(&tp->control); usb_autopm_put_interface(tp->intf); -@@ -6037,6 +7985,10 @@ static int rtl8152_set_link_ksettings(st +@@ -6040,6 +7988,10 @@ static int rtl8152_set_link_ksettings(st cmd->link_modes.advertising)) advertising |= RTL_ADVERTISED_1000_FULL; @@ -2662,7 +2662,7 @@ Signed-off-by: David S. Miller mutex_lock(&tp->control); ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed, -@@ -6626,6 +8578,67 @@ static int rtl_ops_init(struct r8152 *tp +@@ -6629,6 +8581,67 @@ static int rtl_ops_init(struct r8152 *tp tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; break; @@ -2730,7 +2730,7 @@ Signed-off-by: David S. Miller default: ret = -ENODEV; dev_err(&tp->intf->dev, "Unknown Device\n"); -@@ -6639,11 +8652,13 @@ static int rtl_ops_init(struct r8152 *tp +@@ -6642,11 +8655,13 @@ static int rtl_ops_init(struct r8152 *tp #define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw" #define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw" #define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw" @@ -2744,7 +2744,7 @@ Signed-off-by: David S. Miller static int rtl_fw_init(struct r8152 *tp) { -@@ -6669,6 +8684,11 @@ static int rtl_fw_init(struct r8152 *tp) +@@ -6672,6 +8687,11 @@ static int rtl_fw_init(struct r8152 *tp) rtl_fw->pre_fw = r8153b_pre_firmware_1; rtl_fw->post_fw = r8153b_post_firmware_1; break; @@ -2756,7 +2756,7 @@ Signed-off-by: David S. Miller default: break; } -@@ -6724,6 +8744,27 @@ u8 rtl8152_get_version(struct usb_interf +@@ -6728,6 +8748,27 @@ u8 rtl8152_get_version(struct usb_interf case 0x6010: version = RTL_VER_09; break; @@ -2784,7 +2784,7 @@ Signed-off-by: David S. Miller default: version = RTL_VER_UNKNOWN; dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data); -@@ -6836,12 +8877,29 @@ static int rtl8152_probe(struct usb_inte +@@ -6840,12 +8881,29 @@ static int rtl8152_probe(struct usb_inte /* MTU range: 68 - 1500 or 9194 */ netdev->min_mtu = ETH_MIN_MTU; switch (tp->version) { @@ -2817,7 +2817,7 @@ Signed-off-by: David S. Miller break; } -@@ -6857,7 +8915,13 @@ static int rtl8152_probe(struct usb_inte +@@ -6861,7 +8919,13 @@ static int rtl8152_probe(struct usb_inte tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL | RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL; if (tp->mii.supports_gmii) { @@ -2832,7 +2832,7 @@ Signed-off-by: David S. Miller tp->advertising |= RTL_ADVERTISED_1000_FULL; } tp->duplex = DUPLEX_FULL; -@@ -6881,7 +8945,11 @@ static int rtl8152_probe(struct usb_inte +@@ -6885,7 +8949,11 @@ static int rtl8152_probe(struct usb_inte set_ethernet_addr(tp); usb_set_intfdata(intf, tp); @@ -2845,7 +2845,7 @@ Signed-off-by: David S. Miller ret = register_netdev(netdev); if (ret != 0) { -@@ -6917,7 +8985,8 @@ static void rtl8152_disconnect(struct us +@@ -6925,7 +8993,8 @@ static void rtl8152_disconnect(struct us unregister_netdev(tp->netdev); tasklet_kill(&tp->tx_tl); cancel_delayed_work_sync(&tp->hw_phy_work); @@ -2855,7 +2855,7 @@ Signed-off-by: David S. Miller rtl8152_release_firmware(tp); free_netdev(tp->netdev); } -@@ -6937,13 +9006,28 @@ static void rtl8152_disconnect(struct us +@@ -6945,13 +9014,28 @@ static void rtl8152_disconnect(struct us .idProduct = (prod), \ .bInterfaceClass = USB_CLASS_COMM, \ .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ diff --git a/target/linux/generic/backport-5.10/794-v5.13-r8152-support-PHY-firmware-for-RTL8156-series.patch b/target/linux/generic/backport-5.10/794-v5.13-r8152-support-PHY-firmware-for-RTL8156-series.patch index 40dae54f8c71b0..25acbd542f9914 100644 --- a/target/linux/generic/backport-5.10/794-v5.13-r8152-support-PHY-firmware-for-RTL8156-series.patch +++ b/target/linux/generic/backport-5.10/794-v5.13-r8152-support-PHY-firmware-for-RTL8156-series.patch @@ -92,7 +92,7 @@ Signed-off-by: David S. Miller }; enum rtl_version { -@@ -4001,6 +4062,162 @@ static int rtl_post_ram_code(struct r815 +@@ -4004,6 +4065,162 @@ static int rtl_post_ram_code(struct r815 return 0; } @@ -255,7 +255,7 @@ Signed-off-by: David S. Miller static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy) { u32 length; -@@ -4321,6 +4538,10 @@ static long rtl8152_check_firmware(struc +@@ -4324,6 +4541,10 @@ static long rtl8152_check_firmware(struc case RTL_FW_PHY_START: if (test_bit(FW_FLAGS_START, &fw_flags) || test_bit(FW_FLAGS_NC, &fw_flags) || @@ -266,7 +266,7 @@ Signed-off-by: David S. Miller test_bit(FW_FLAGS_STOP, &fw_flags)) { dev_err(&tp->intf->dev, "check PHY_START fail\n"); -@@ -4369,7 +4590,153 @@ static long rtl8152_check_firmware(struc +@@ -4372,7 +4593,153 @@ static long rtl8152_check_firmware(struc goto fail; } __set_bit(FW_FLAGS_NC, &fw_flags); @@ -420,7 +420,7 @@ Signed-off-by: David S. Miller break; default: dev_warn(&tp->intf->dev, "Unknown type %u is found\n", -@@ -4392,6 +4759,143 @@ fail: +@@ -4395,6 +4762,143 @@ fail: return ret; } @@ -564,7 +564,7 @@ Signed-off-by: David S. Miller static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy) { u16 mode_reg, bp_index; -@@ -4445,6 +4949,12 @@ static void rtl8152_fw_mac_apply(struct +@@ -4448,6 +4952,12 @@ static void rtl8152_fw_mac_apply(struct return; } @@ -577,7 +577,7 @@ Signed-off-by: David S. Miller rtl_clear_bp(tp, type); /* Enable backup/restore of MACDBG. This is required after clearing PLA -@@ -4480,7 +4990,6 @@ static void rtl8152_fw_mac_apply(struct +@@ -4483,7 +4993,6 @@ static void rtl8152_fw_mac_apply(struct ocp_write_word(tp, type, bp_en_addr, __le16_to_cpu(mac->bp_en_value)); @@ -585,7 +585,7 @@ Signed-off-by: David S. Miller if (fw_ver_reg) ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg, mac->fw_ver_data); -@@ -4495,7 +5004,7 @@ static void rtl8152_apply_firmware(struc +@@ -4498,7 +5007,7 @@ static void rtl8152_apply_firmware(struc struct fw_header *fw_hdr; struct fw_phy_patch_key *key; u16 key_addr = 0; @@ -594,7 +594,7 @@ Signed-off-by: David S. Miller if (IS_ERR_OR_NULL(rtl_fw->fw)) return; -@@ -4517,17 +5026,40 @@ static void rtl8152_apply_firmware(struc +@@ -4520,17 +5029,40 @@ static void rtl8152_apply_firmware(struc rtl8152_fw_mac_apply(tp, (struct fw_mac *)block); break; case RTL_FW_PHY_START: @@ -635,7 +635,7 @@ Signed-off-by: David S. Miller default: break; } -@@ -5035,6 +5567,21 @@ static int r8153c_post_firmware_1(struct +@@ -5038,6 +5570,21 @@ static int r8153c_post_firmware_1(struct return 0; } @@ -657,7 +657,7 @@ Signed-off-by: David S. Miller static void r8153_aldps_en(struct r8152 *tp, bool enable) { u16 data; -@@ -8653,12 +9200,16 @@ static int rtl_ops_init(struct r8152 *tp +@@ -8656,12 +9203,16 @@ static int rtl_ops_init(struct r8152 *tp #define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw" #define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw" #define FIRMWARE_8153C_1 "rtl_nic/rtl8153c-1.fw" @@ -674,7 +674,7 @@ Signed-off-by: David S. Miller static int rtl_fw_init(struct r8152 *tp) { -@@ -8684,6 +9235,14 @@ static int rtl_fw_init(struct r8152 *tp) +@@ -8687,6 +9238,14 @@ static int rtl_fw_init(struct r8152 *tp) rtl_fw->pre_fw = r8153b_pre_firmware_1; rtl_fw->post_fw = r8153b_post_firmware_1; break; diff --git a/target/linux/generic/backport-5.10/795-v5.13-r8152-search-the-configuration-of-vendor-mode.patch b/target/linux/generic/backport-5.10/795-v5.13-r8152-search-the-configuration-of-vendor-mode.patch index 751ff3d30ca69d..045c3549819829 100644 --- a/target/linux/generic/backport-5.10/795-v5.13-r8152-search-the-configuration-of-vendor-mode.patch +++ b/target/linux/generic/backport-5.10/795-v5.13-r8152-search-the-configuration-of-vendor-mode.patch @@ -25,7 +25,7 @@ Signed-off-by: David S. Miller /* Information for net */ #define NET_VERSION "11" -@@ -8110,6 +8110,39 @@ static void r8156b_init(struct r8152 *tp +@@ -8113,6 +8113,39 @@ static void r8156b_init(struct r8152 *tp tp->coalesce = 15000; /* 15 us */ } @@ -65,7 +65,7 @@ Signed-off-by: David S. Miller static int rtl8152_pre_reset(struct usb_interface *intf) { struct r8152 *tp = usb_get_intfdata(intf); -@@ -9348,10 +9381,8 @@ static int rtl8152_probe(struct usb_inte +@@ -9352,10 +9385,8 @@ static int rtl8152_probe(struct usb_inte if (version == RTL_VER_UNKNOWN) return -ENODEV; diff --git a/target/linux/generic/backport-5.15/020-v6.1-01-mm-x86-arm64-add-arch_has_hw_pte_young.patch b/target/linux/generic/backport-5.15/020-v6.1-01-mm-x86-arm64-add-arch_has_hw_pte_young.patch index 73acadd804c0bf..865da6b18284dd 100644 --- a/target/linux/generic/backport-5.15/020-v6.1-01-mm-x86-arm64-add-arch_has_hw_pte_young.patch +++ b/target/linux/generic/backport-5.15/020-v6.1-01-mm-x86-arm64-add-arch_has_hw_pte_young.patch @@ -329,7 +329,7 @@ Signed-off-by: Andrew Morton --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h -@@ -999,23 +999,13 @@ static inline void update_mmu_cache(stru +@@ -1005,23 +1005,13 @@ static inline void update_mmu_cache(stru * page after fork() + CoW for pfn mappings. We don't always have a * hardware-managed access flag on arm64. */ diff --git a/target/linux/generic/backport-5.15/020-v6.1-05-mm-multi-gen-LRU-groundwork.patch b/target/linux/generic/backport-5.15/020-v6.1-05-mm-multi-gen-LRU-groundwork.patch index 25457926a48973..769384f500f301 100644 --- a/target/linux/generic/backport-5.15/020-v6.1-05-mm-multi-gen-LRU-groundwork.patch +++ b/target/linux/generic/backport-5.15/020-v6.1-05-mm-multi-gen-LRU-groundwork.patch @@ -594,7 +594,7 @@ Signed-off-by: Andrew Morton VM_BUG_ON_PAGE(tail > 2 && page_tail->mapping != TAIL_MAPPING, --- a/mm/memcontrol.c +++ b/mm/memcontrol.c -@@ -5178,6 +5178,7 @@ static void __mem_cgroup_free(struct mem +@@ -5179,6 +5179,7 @@ static void __mem_cgroup_free(struct mem static void mem_cgroup_free(struct mem_cgroup *memcg) { @@ -602,7 +602,7 @@ Signed-off-by: Andrew Morton memcg_wb_domain_exit(memcg); __mem_cgroup_free(memcg); } -@@ -5241,6 +5242,7 @@ static struct mem_cgroup *mem_cgroup_all +@@ -5242,6 +5243,7 @@ static struct mem_cgroup *mem_cgroup_all memcg->deferred_split_queue.split_queue_len = 0; #endif idr_replace(&mem_cgroup_idr, memcg, memcg->id.id); diff --git a/target/linux/generic/backport-5.15/020-v6.1-08-mm-multi-gen-LRU-support-page-table-walks.patch b/target/linux/generic/backport-5.15/020-v6.1-08-mm-multi-gen-LRU-support-page-table-walks.patch index 754d97d84b42dd..234dfd916f0887 100644 --- a/target/linux/generic/backport-5.15/020-v6.1-08-mm-multi-gen-LRU-support-page-table-walks.patch +++ b/target/linux/generic/backport-5.15/020-v6.1-08-mm-multi-gen-LRU-support-page-table-walks.patch @@ -414,7 +414,7 @@ Signed-off-by: Andrew Morton /* forking complete and child started to run, tell ptracer */ --- a/kernel/sched/core.c +++ b/kernel/sched/core.c -@@ -5010,6 +5010,7 @@ context_switch(struct rq *rq, struct tas +@@ -5014,6 +5014,7 @@ context_switch(struct rq *rq, struct tas * finish_task_switch()'s mmdrop(). */ switch_mm_irqs_off(prev->active_mm, next->mm, next); @@ -424,7 +424,7 @@ Signed-off-by: Andrew Morton /* will mmdrop() in finish_task_switch(). */ --- a/mm/memcontrol.c +++ b/mm/memcontrol.c -@@ -6212,6 +6212,30 @@ static void mem_cgroup_move_task(void) +@@ -6213,6 +6213,30 @@ static void mem_cgroup_move_task(void) } #endif @@ -455,7 +455,7 @@ Signed-off-by: Andrew Morton static int seq_puts_memcg_tunable(struct seq_file *m, unsigned long value) { if (value == PAGE_COUNTER_MAX) -@@ -6555,6 +6579,7 @@ struct cgroup_subsys memory_cgrp_subsys +@@ -6556,6 +6580,7 @@ struct cgroup_subsys memory_cgrp_subsys .css_reset = mem_cgroup_css_reset, .css_rstat_flush = mem_cgroup_css_rstat_flush, .can_attach = mem_cgroup_can_attach, diff --git a/target/linux/generic/backport-5.15/020-v6.3-26-mm-multi-gen-LRU-per-node-lru_gen_page-lists.patch b/target/linux/generic/backport-5.15/020-v6.3-26-mm-multi-gen-LRU-per-node-lru_gen_page-lists.patch index 6010e617b863e4..8cc9abd84f09e2 100644 --- a/target/linux/generic/backport-5.15/020-v6.3-26-mm-multi-gen-LRU-per-node-lru_gen_page-lists.patch +++ b/target/linux/generic/backport-5.15/020-v6.3-26-mm-multi-gen-LRU-per-node-lru_gen_page-lists.patch @@ -318,7 +318,7 @@ Signed-off-by: Andrew Morton mctz = soft_limit_tree_from_page(page); if (!mctz) return; -@@ -3433,6 +3443,9 @@ unsigned long mem_cgroup_soft_limit_recl +@@ -3434,6 +3444,9 @@ unsigned long mem_cgroup_soft_limit_recl unsigned long excess; unsigned long nr_scanned; @@ -328,7 +328,7 @@ Signed-off-by: Andrew Morton if (order > 0) return 0; -@@ -5321,6 +5334,7 @@ static int mem_cgroup_css_online(struct +@@ -5322,6 +5335,7 @@ static int mem_cgroup_css_online(struct if (unlikely(mem_cgroup_is_root(memcg))) queue_delayed_work(system_unbound_wq, &stats_flush_dwork, 2UL*HZ); @@ -336,7 +336,7 @@ Signed-off-by: Andrew Morton return 0; } -@@ -5347,6 +5361,7 @@ static void mem_cgroup_css_offline(struc +@@ -5348,6 +5362,7 @@ static void mem_cgroup_css_offline(struc memcg_offline_kmem(memcg); reparent_shrinker_deferred(memcg); wb_memcg_offline(memcg); @@ -344,7 +344,7 @@ Signed-off-by: Andrew Morton drain_all_stock(memcg); -@@ -5358,6 +5373,7 @@ static void mem_cgroup_css_released(stru +@@ -5359,6 +5374,7 @@ static void mem_cgroup_css_released(stru struct mem_cgroup *memcg = mem_cgroup_from_css(css); invalidate_reclaim_iterators(memcg); diff --git a/target/linux/generic/backport-5.15/350-v5.18-regmap-add-configurable-downshift-for-addresses.patch b/target/linux/generic/backport-5.15/350-v5.18-regmap-add-configurable-downshift-for-addresses.patch index 99cd89ea002f43..7bb328f3a6de9a 100644 --- a/target/linux/generic/backport-5.15/350-v5.18-regmap-add-configurable-downshift-for-addresses.patch +++ b/target/linux/generic/backport-5.15/350-v5.18-regmap-add-configurable-downshift-for-addresses.patch @@ -37,7 +37,7 @@ Signed-off-by: Mark Brown map->format.val_bytes = DIV_ROUND_UP(config->val_bits, 8); map->format.buf_size = DIV_ROUND_UP(config->reg_bits + config->val_bits + config->pad_bits, 8); -@@ -1735,6 +1736,7 @@ static int _regmap_raw_write_impl(struct +@@ -1737,6 +1738,7 @@ static int _regmap_raw_write_impl(struct return ret; } @@ -45,7 +45,7 @@ Signed-off-by: Mark Brown map->format.format_reg(map->work_buf, reg, map->reg_shift); regmap_set_work_buf_flag_mask(map, map->format.reg_bytes, map->write_flag_mask); -@@ -1905,6 +1907,7 @@ static int _regmap_bus_formatted_write(v +@@ -1907,6 +1909,7 @@ static int _regmap_bus_formatted_write(v return ret; } @@ -53,7 +53,7 @@ Signed-off-by: Mark Brown map->format.format_write(map, reg, val); trace_regmap_hw_write_start(map, reg, 1); -@@ -2346,6 +2349,7 @@ static int _regmap_raw_multi_reg_write(s +@@ -2348,6 +2351,7 @@ static int _regmap_raw_multi_reg_write(s unsigned int reg = regs[i].reg; unsigned int val = regs[i].def; trace_regmap_hw_write_start(map, reg, 1); @@ -61,7 +61,7 @@ Signed-off-by: Mark Brown map->format.format_reg(u8, reg, map->reg_shift); u8 += reg_bytes + pad_bytes; map->format.format_val(u8, val, 0); -@@ -2673,6 +2677,7 @@ static int _regmap_raw_read(struct regma +@@ -2675,6 +2679,7 @@ static int _regmap_raw_read(struct regma return ret; } diff --git a/target/linux/generic/backport-5.15/351-v5.18-regmap-allow-a-defined-reg_base-to-be-added-to-every.patch b/target/linux/generic/backport-5.15/351-v5.18-regmap-allow-a-defined-reg_base-to-be-added-to-every.patch index 0f32288fcab5b3..841f8d45286fe0 100644 --- a/target/linux/generic/backport-5.15/351-v5.18-regmap-allow-a-defined-reg_base-to-be-added-to-every.patch +++ b/target/linux/generic/backport-5.15/351-v5.18-regmap-allow-a-defined-reg_base-to-be-added-to-every.patch @@ -42,7 +42,7 @@ Signed-off-by: Mark Brown map->format.reg_bytes = DIV_ROUND_UP(config->reg_bits, 8); map->format.pad_bytes = config->pad_bits / 8; map->format.reg_downshift = config->reg_downshift; -@@ -1736,6 +1738,7 @@ static int _regmap_raw_write_impl(struct +@@ -1738,6 +1740,7 @@ static int _regmap_raw_write_impl(struct return ret; } @@ -50,7 +50,7 @@ Signed-off-by: Mark Brown reg >>= map->format.reg_downshift; map->format.format_reg(map->work_buf, reg, map->reg_shift); regmap_set_work_buf_flag_mask(map, map->format.reg_bytes, -@@ -1907,6 +1910,7 @@ static int _regmap_bus_formatted_write(v +@@ -1909,6 +1912,7 @@ static int _regmap_bus_formatted_write(v return ret; } @@ -58,7 +58,7 @@ Signed-off-by: Mark Brown reg >>= map->format.reg_downshift; map->format.format_write(map, reg, val); -@@ -2349,6 +2353,7 @@ static int _regmap_raw_multi_reg_write(s +@@ -2351,6 +2355,7 @@ static int _regmap_raw_multi_reg_write(s unsigned int reg = regs[i].reg; unsigned int val = regs[i].def; trace_regmap_hw_write_start(map, reg, 1); @@ -66,7 +66,7 @@ Signed-off-by: Mark Brown reg >>= map->format.reg_downshift; map->format.format_reg(u8, reg, map->reg_shift); u8 += reg_bytes + pad_bytes; -@@ -2677,6 +2682,7 @@ static int _regmap_raw_read(struct regma +@@ -2679,6 +2684,7 @@ static int _regmap_raw_read(struct regma return ret; } diff --git a/target/linux/generic/backport-5.15/352-v6.3-regmap-apply-reg_base-and-reg_downshift-for-single-r.patch b/target/linux/generic/backport-5.15/352-v6.3-regmap-apply-reg_base-and-reg_downshift-for-single-r.patch index 804f68d23c50a5..bc3865c75b92af 100644 --- a/target/linux/generic/backport-5.15/352-v6.3-regmap-apply-reg_base-and-reg_downshift-for-single-r.patch +++ b/target/linux/generic/backport-5.15/352-v6.3-regmap-apply-reg_base-and-reg_downshift-for-single-r.patch @@ -28,7 +28,7 @@ Signed-off-by: Mark Brown --- a/drivers/base/regmap/regmap.c +++ b/drivers/base/regmap/regmap.c -@@ -1929,6 +1929,8 @@ static int _regmap_bus_reg_write(void *c +@@ -1931,6 +1931,8 @@ static int _regmap_bus_reg_write(void *c { struct regmap *map = context; @@ -37,7 +37,7 @@ Signed-off-by: Mark Brown return map->bus->reg_write(map->bus_context, reg, val); } -@@ -2703,6 +2705,8 @@ static int _regmap_bus_reg_read(void *co +@@ -2705,6 +2707,8 @@ static int _regmap_bus_reg_read(void *co { struct regmap *map = context; @@ -46,7 +46,7 @@ Signed-off-by: Mark Brown return map->bus->reg_read(map->bus_context, reg, val); } -@@ -3078,6 +3082,8 @@ static int _regmap_update_bits(struct re +@@ -3080,6 +3084,8 @@ static int _regmap_update_bits(struct re *change = false; if (regmap_volatile(map, reg) && map->reg_update_bits) { diff --git a/target/linux/generic/backport-5.15/703-00-v5.16-net-convert-users-of-bitmap_foo-to-linkmode_foo.patch b/target/linux/generic/backport-5.15/703-00-v5.16-net-convert-users-of-bitmap_foo-to-linkmode_foo.patch index 284a6d072255eb..eca3c7ff9fd187 100644 --- a/target/linux/generic/backport-5.15/703-00-v5.16-net-convert-users-of-bitmap_foo-to-linkmode_foo.patch +++ b/target/linux/generic/backport-5.15/703-00-v5.16-net-convert-users-of-bitmap_foo-to-linkmode_foo.patch @@ -554,7 +554,7 @@ Signed-off-by: David S. Miller static void xrs700x_mac_link_up(struct dsa_switch *ds, int port, --- a/drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c +++ b/drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c -@@ -369,9 +369,8 @@ static int xgbe_set_link_ksettings(struc +@@ -374,9 +374,8 @@ static int xgbe_set_link_ksettings(struc __ETHTOOL_LINK_MODE_MASK_NBITS, cmd->link_modes.advertising, __ETHTOOL_LINK_MODE_MASK_NBITS, lks->link_modes.supported); @@ -566,7 +566,7 @@ Signed-off-by: David S. Miller if ((cmd->base.autoneg == AUTONEG_ENABLE) && bitmap_empty(advertising, __ETHTOOL_LINK_MODE_MASK_NBITS)) { -@@ -384,8 +383,7 @@ static int xgbe_set_link_ksettings(struc +@@ -389,8 +388,7 @@ static int xgbe_set_link_ksettings(struc pdata->phy.autoneg = cmd->base.autoneg; pdata->phy.speed = speed; pdata->phy.duplex = cmd->base.duplex; @@ -747,7 +747,7 @@ Signed-off-by: David S. Miller static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode, --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c -@@ -1168,9 +1168,8 @@ static int otx2_set_link_ksettings(struc +@@ -1172,9 +1172,8 @@ static int otx2_set_link_ksettings(struc otx2_get_link_ksettings(netdev, &cur_ks); /* Check requested modes against supported modes by hardware */ diff --git a/target/linux/generic/backport-5.15/703-08-v5.17-net-phylink-add-mac_select_pcs-method-to-phylink_mac.patch b/target/linux/generic/backport-5.15/703-08-v5.17-net-phylink-add-mac_select_pcs-method-to-phylink_mac.patch index d826877e7dc693..5d5ac4b0094887 100644 --- a/target/linux/generic/backport-5.15/703-08-v5.17-net-phylink-add-mac_select_pcs-method-to-phylink_mac.patch +++ b/target/linux/generic/backport-5.15/703-08-v5.17-net-phylink-add-mac_select_pcs-method-to-phylink_mac.patch @@ -125,7 +125,7 @@ Signed-off-by: David S. Miller pl = kzalloc(sizeof(*pl), GFP_KERNEL); if (!pl) return ERR_PTR(-ENOMEM); -@@ -946,9 +987,10 @@ EXPORT_SYMBOL_GPL(phylink_create); +@@ -947,9 +988,10 @@ EXPORT_SYMBOL_GPL(phylink_create); * @pl: a pointer to a &struct phylink returned from phylink_create() * @pcs: a pointer to the &struct phylink_pcs * @@ -139,7 +139,7 @@ Signed-off-by: David S. Miller * * Please note that there are behavioural changes with the mac_config() * callback if a PCS is present (denoting a newer setup) so removing a PCS -@@ -959,6 +1001,14 @@ void phylink_set_pcs(struct phylink *pl, +@@ -960,6 +1002,14 @@ void phylink_set_pcs(struct phylink *pl, { pl->pcs = pcs; pl->pcs_ops = pcs->ops; diff --git a/target/linux/generic/backport-5.15/703-15-v5.18-net-phy-phylink-fix-DSA-mac_select_pcs-introduction.patch b/target/linux/generic/backport-5.15/703-15-v5.18-net-phy-phylink-fix-DSA-mac_select_pcs-introduction.patch index 9e5061aaed832b..924d0e954a9079 100644 --- a/target/linux/generic/backport-5.15/703-15-v5.18-net-phy-phylink-fix-DSA-mac_select_pcs-introduction.patch +++ b/target/linux/generic/backport-5.15/703-15-v5.18-net-phy-phylink-fix-DSA-mac_select_pcs-introduction.patch @@ -66,7 +66,7 @@ Signed-off-by: Jakub Kicinski phy_interface_empty(config->supported_interfaces)) { dev_err(config->dev, "phylink: error: empty supported_interfaces but mac_select_pcs() method present\n"); -@@ -1220,6 +1227,7 @@ struct phylink *phylink_create(struct ph +@@ -1221,6 +1228,7 @@ struct phylink *phylink_create(struct ph return ERR_PTR(-EINVAL); } diff --git a/target/linux/generic/backport-5.15/775-v6.0-01-net-ethernet-stmicro-stmmac-move-queue-reset-to-dedi.patch b/target/linux/generic/backport-5.15/775-v6.0-01-net-ethernet-stmicro-stmmac-move-queue-reset-to-dedi.patch index 3c9d4e72e85271..3c10819b681375 100644 --- a/target/linux/generic/backport-5.15/775-v6.0-01-net-ethernet-stmicro-stmmac-move-queue-reset-to-dedi.patch +++ b/target/linux/generic/backport-5.15/775-v6.0-01-net-ethernet-stmicro-stmmac-move-queue-reset-to-dedi.patch @@ -27,7 +27,7 @@ Signed-off-by: Jakub Kicinski static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue); static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue); -@@ -1712,9 +1715,6 @@ static int __init_dma_rx_desc_rings(stru +@@ -1713,9 +1716,6 @@ static int __init_dma_rx_desc_rings(stru return -ENOMEM; } @@ -37,7 +37,7 @@ Signed-off-by: Jakub Kicinski /* Setup the chained descriptor addresses */ if (priv->mode == STMMAC_CHAIN_MODE) { if (priv->extend_desc) -@@ -1820,12 +1820,6 @@ static int __init_dma_tx_desc_rings(stru +@@ -1821,12 +1821,6 @@ static int __init_dma_tx_desc_rings(stru tx_q->tx_skbuff[i] = NULL; } @@ -50,7 +50,7 @@ Signed-off-by: Jakub Kicinski return 0; } -@@ -2694,10 +2688,7 @@ static void stmmac_tx_err(struct stmmac_ +@@ -2695,10 +2689,7 @@ static void stmmac_tx_err(struct stmmac_ stmmac_stop_tx_dma(priv, chan); dma_free_tx_skbufs(priv, chan); stmmac_clear_tx_descriptors(priv, chan); @@ -62,7 +62,7 @@ Signed-off-by: Jakub Kicinski stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, tx_q->dma_tx_phy, chan); stmmac_start_tx_dma(priv, chan); -@@ -3781,6 +3772,8 @@ static int stmmac_open(struct net_device +@@ -3782,6 +3773,8 @@ static int stmmac_open(struct net_device } } @@ -71,7 +71,7 @@ Signed-off-by: Jakub Kicinski ret = stmmac_hw_setup(dev, true); if (ret < 0) { netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); -@@ -6430,6 +6423,7 @@ void stmmac_enable_rx_queue(struct stmma +@@ -6429,6 +6422,7 @@ void stmmac_enable_rx_queue(struct stmma return; } @@ -79,7 +79,7 @@ Signed-off-by: Jakub Kicinski stmmac_clear_rx_descriptors(priv, queue); stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, -@@ -6491,6 +6485,7 @@ void stmmac_enable_tx_queue(struct stmma +@@ -6490,6 +6484,7 @@ void stmmac_enable_tx_queue(struct stmma return; } @@ -87,7 +87,7 @@ Signed-off-by: Jakub Kicinski stmmac_clear_tx_descriptors(priv, queue); stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, -@@ -7411,6 +7406,25 @@ int stmmac_suspend(struct device *dev) +@@ -7414,6 +7409,25 @@ int stmmac_suspend(struct device *dev) } EXPORT_SYMBOL_GPL(stmmac_suspend); @@ -113,7 +113,7 @@ Signed-off-by: Jakub Kicinski /** * stmmac_reset_queues_param - reset queue parameters * @priv: device pointer -@@ -7421,22 +7435,11 @@ static void stmmac_reset_queues_param(st +@@ -7424,22 +7438,11 @@ static void stmmac_reset_queues_param(st u32 tx_cnt = priv->plat->tx_queues_to_use; u32 queue; diff --git a/target/linux/generic/backport-5.15/775-v6.0-02-net-ethernet-stmicro-stmmac-first-disable-all-queues.patch b/target/linux/generic/backport-5.15/775-v6.0-02-net-ethernet-stmicro-stmmac-first-disable-all-queues.patch index 8eca92a5c54dc2..6e115834eb8911 100644 --- a/target/linux/generic/backport-5.15/775-v6.0-02-net-ethernet-stmicro-stmmac-first-disable-all-queues.patch +++ b/target/linux/generic/backport-5.15/775-v6.0-02-net-ethernet-stmicro-stmmac-first-disable-all-queues.patch @@ -17,7 +17,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -3833,8 +3833,6 @@ static int stmmac_release(struct net_dev +@@ -3834,8 +3834,6 @@ static int stmmac_release(struct net_dev struct stmmac_priv *priv = netdev_priv(dev); u32 chan; @@ -26,7 +26,7 @@ Signed-off-by: Jakub Kicinski if (device_may_wakeup(priv->device)) phylink_speed_down(priv->phylink, false); /* Stop and disconnect the PHY */ -@@ -3846,6 +3844,8 @@ static int stmmac_release(struct net_dev +@@ -3847,6 +3845,8 @@ static int stmmac_release(struct net_dev for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) hrtimer_cancel(&priv->tx_queue[chan].txtimer); diff --git a/target/linux/generic/backport-5.15/775-v6.0-03-net-ethernet-stmicro-stmmac-move-dma-conf-to-dedicat.patch b/target/linux/generic/backport-5.15/775-v6.0-03-net-ethernet-stmicro-stmmac-move-dma-conf-to-dedicat.patch index 34b7e1fd8d199e..99518b11a040ef 100644 --- a/target/linux/generic/backport-5.15/775-v6.0-03-net-ethernet-stmicro-stmmac-move-dma-conf-to-dedicat.patch +++ b/target/linux/generic/backport-5.15/775-v6.0-03-net-ethernet-stmicro-stmmac-move-dma-conf-to-dedicat.patch @@ -189,7 +189,7 @@ Signed-off-by: Jakub Kicinski if (tx_q->dirty_tx != tx_q->cur_tx) return -EBUSY; /* still unfinished work */ -@@ -1309,7 +1309,7 @@ static void stmmac_display_rx_rings(stru +@@ -1310,7 +1310,7 @@ static void stmmac_display_rx_rings(stru /* Display RX rings */ for (queue = 0; queue < rx_cnt; queue++) { @@ -198,7 +198,7 @@ Signed-off-by: Jakub Kicinski pr_info("\tRX Queue %u rings\n", queue); -@@ -1322,7 +1322,7 @@ static void stmmac_display_rx_rings(stru +@@ -1323,7 +1323,7 @@ static void stmmac_display_rx_rings(stru } /* Display RX ring */ @@ -207,7 +207,7 @@ Signed-off-by: Jakub Kicinski rx_q->dma_rx_phy, desc_size); } } -@@ -1336,7 +1336,7 @@ static void stmmac_display_tx_rings(stru +@@ -1337,7 +1337,7 @@ static void stmmac_display_tx_rings(stru /* Display TX rings */ for (queue = 0; queue < tx_cnt; queue++) { @@ -216,7 +216,7 @@ Signed-off-by: Jakub Kicinski pr_info("\tTX Queue %d rings\n", queue); -@@ -1351,7 +1351,7 @@ static void stmmac_display_tx_rings(stru +@@ -1352,7 +1352,7 @@ static void stmmac_display_tx_rings(stru desc_size = sizeof(struct dma_desc); } @@ -225,7 +225,7 @@ Signed-off-by: Jakub Kicinski tx_q->dma_tx_phy, desc_size); } } -@@ -1392,21 +1392,21 @@ static int stmmac_set_bfsize(int mtu, in +@@ -1393,21 +1393,21 @@ static int stmmac_set_bfsize(int mtu, in */ static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue) { @@ -253,7 +253,7 @@ Signed-off-by: Jakub Kicinski } /** -@@ -1418,12 +1418,12 @@ static void stmmac_clear_rx_descriptors( +@@ -1419,12 +1419,12 @@ static void stmmac_clear_rx_descriptors( */ static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue) { @@ -269,7 +269,7 @@ Signed-off-by: Jakub Kicinski struct dma_desc *p; if (priv->extend_desc) -@@ -1471,7 +1471,7 @@ static void stmmac_clear_descriptors(str +@@ -1472,7 +1472,7 @@ static void stmmac_clear_descriptors(str static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, int i, gfp_t flags, u32 queue) { @@ -278,7 +278,7 @@ Signed-off-by: Jakub Kicinski struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; if (!buf->page) { -@@ -1496,7 +1496,7 @@ static int stmmac_init_rx_buffers(struct +@@ -1497,7 +1497,7 @@ static int stmmac_init_rx_buffers(struct buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; stmmac_set_desc_addr(priv, p, buf->addr); @@ -287,7 +287,7 @@ Signed-off-by: Jakub Kicinski stmmac_init_desc3(priv, p); return 0; -@@ -1510,7 +1510,7 @@ static int stmmac_init_rx_buffers(struct +@@ -1511,7 +1511,7 @@ static int stmmac_init_rx_buffers(struct */ static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i) { @@ -296,7 +296,7 @@ Signed-off-by: Jakub Kicinski struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; if (buf->page) -@@ -1530,7 +1530,7 @@ static void stmmac_free_rx_buffer(struct +@@ -1531,7 +1531,7 @@ static void stmmac_free_rx_buffer(struct */ static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i) { @@ -305,7 +305,7 @@ Signed-off-by: Jakub Kicinski if (tx_q->tx_skbuff_dma[i].buf && tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) { -@@ -1575,17 +1575,17 @@ static void dma_free_rx_skbufs(struct st +@@ -1576,17 +1576,17 @@ static void dma_free_rx_skbufs(struct st { int i; @@ -326,7 +326,7 @@ Signed-off-by: Jakub Kicinski struct dma_desc *p; int ret; -@@ -1612,10 +1612,10 @@ static int stmmac_alloc_rx_buffers(struc +@@ -1613,10 +1613,10 @@ static int stmmac_alloc_rx_buffers(struc */ static void dma_free_rx_xskbufs(struct stmmac_priv *priv, u32 queue) { @@ -339,7 +339,7 @@ Signed-off-by: Jakub Kicinski struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; if (!buf->xdp) -@@ -1628,10 +1628,10 @@ static void dma_free_rx_xskbufs(struct s +@@ -1629,10 +1629,10 @@ static void dma_free_rx_xskbufs(struct s static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, u32 queue) { @@ -352,7 +352,7 @@ Signed-off-by: Jakub Kicinski struct stmmac_rx_buffer *buf; dma_addr_t dma_addr; struct dma_desc *p; -@@ -1674,7 +1674,7 @@ static struct xsk_buff_pool *stmmac_get_ +@@ -1675,7 +1675,7 @@ static struct xsk_buff_pool *stmmac_get_ */ static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, u32 queue, gfp_t flags) { @@ -361,7 +361,7 @@ Signed-off-by: Jakub Kicinski int ret; netif_dbg(priv, probe, priv->dev, -@@ -1720,11 +1720,11 @@ static int __init_dma_rx_desc_rings(stru +@@ -1721,11 +1721,11 @@ static int __init_dma_rx_desc_rings(stru if (priv->extend_desc) stmmac_mode_init(priv, rx_q->dma_erx, rx_q->dma_rx_phy, @@ -375,7 +375,7 @@ Signed-off-by: Jakub Kicinski } return 0; -@@ -1751,7 +1751,7 @@ static int init_dma_rx_desc_rings(struct +@@ -1752,7 +1752,7 @@ static int init_dma_rx_desc_rings(struct err_init_rx_buffers: while (queue >= 0) { @@ -384,7 +384,7 @@ Signed-off-by: Jakub Kicinski if (rx_q->xsk_pool) dma_free_rx_xskbufs(priv, queue); -@@ -1780,7 +1780,7 @@ err_init_rx_buffers: +@@ -1781,7 +1781,7 @@ err_init_rx_buffers: */ static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, u32 queue) { @@ -393,7 +393,7 @@ Signed-off-by: Jakub Kicinski int i; netif_dbg(priv, probe, priv->dev, -@@ -1792,16 +1792,16 @@ static int __init_dma_tx_desc_rings(stru +@@ -1793,16 +1793,16 @@ static int __init_dma_tx_desc_rings(stru if (priv->extend_desc) stmmac_mode_init(priv, tx_q->dma_etx, tx_q->dma_tx_phy, @@ -413,7 +413,7 @@ Signed-off-by: Jakub Kicinski struct dma_desc *p; if (priv->extend_desc) -@@ -1871,12 +1871,12 @@ static int init_dma_desc_rings(struct ne +@@ -1872,12 +1872,12 @@ static int init_dma_desc_rings(struct ne */ static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue) { @@ -428,7 +428,7 @@ Signed-off-by: Jakub Kicinski stmmac_free_tx_buffer(priv, queue, i); if (tx_q->xsk_pool && tx_q->xsk_frames_done) { -@@ -1906,7 +1906,7 @@ static void stmmac_free_tx_skbufs(struct +@@ -1907,7 +1907,7 @@ static void stmmac_free_tx_skbufs(struct */ static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue) { @@ -437,7 +437,7 @@ Signed-off-by: Jakub Kicinski /* Release the DMA RX socket buffers */ if (rx_q->xsk_pool) -@@ -1919,11 +1919,11 @@ static void __free_dma_rx_desc_resources +@@ -1920,11 +1920,11 @@ static void __free_dma_rx_desc_resources /* Free DMA regions of consistent memory previously allocated */ if (!priv->extend_desc) @@ -451,7 +451,7 @@ Signed-off-by: Jakub Kicinski sizeof(struct dma_extended_desc), rx_q->dma_erx, rx_q->dma_rx_phy); -@@ -1952,7 +1952,7 @@ static void free_dma_rx_desc_resources(s +@@ -1953,7 +1953,7 @@ static void free_dma_rx_desc_resources(s */ static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue) { @@ -460,7 +460,7 @@ Signed-off-by: Jakub Kicinski size_t size; void *addr; -@@ -1970,7 +1970,7 @@ static void __free_dma_tx_desc_resources +@@ -1971,7 +1971,7 @@ static void __free_dma_tx_desc_resources addr = tx_q->dma_tx; } @@ -469,7 +469,7 @@ Signed-off-by: Jakub Kicinski dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); -@@ -1999,7 +1999,7 @@ static void free_dma_tx_desc_resources(s +@@ -2000,7 +2000,7 @@ static void free_dma_tx_desc_resources(s */ static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue) { @@ -478,7 +478,7 @@ Signed-off-by: Jakub Kicinski struct stmmac_channel *ch = &priv->channel[queue]; bool xdp_prog = stmmac_xdp_is_enabled(priv); struct page_pool_params pp_params = { 0 }; -@@ -2011,8 +2011,8 @@ static int __alloc_dma_rx_desc_resources +@@ -2012,8 +2012,8 @@ static int __alloc_dma_rx_desc_resources rx_q->priv_data = priv; pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV; @@ -489,7 +489,7 @@ Signed-off-by: Jakub Kicinski pp_params.order = ilog2(num_pages); pp_params.nid = dev_to_node(priv->device); pp_params.dev = priv->device; -@@ -2027,7 +2027,7 @@ static int __alloc_dma_rx_desc_resources +@@ -2028,7 +2028,7 @@ static int __alloc_dma_rx_desc_resources return ret; } @@ -498,7 +498,7 @@ Signed-off-by: Jakub Kicinski sizeof(*rx_q->buf_pool), GFP_KERNEL); if (!rx_q->buf_pool) -@@ -2035,7 +2035,7 @@ static int __alloc_dma_rx_desc_resources +@@ -2036,7 +2036,7 @@ static int __alloc_dma_rx_desc_resources if (priv->extend_desc) { rx_q->dma_erx = dma_alloc_coherent(priv->device, @@ -507,7 +507,7 @@ Signed-off-by: Jakub Kicinski sizeof(struct dma_extended_desc), &rx_q->dma_rx_phy, GFP_KERNEL); -@@ -2044,7 +2044,7 @@ static int __alloc_dma_rx_desc_resources +@@ -2045,7 +2045,7 @@ static int __alloc_dma_rx_desc_resources } else { rx_q->dma_rx = dma_alloc_coherent(priv->device, @@ -516,7 +516,7 @@ Signed-off-by: Jakub Kicinski sizeof(struct dma_desc), &rx_q->dma_rx_phy, GFP_KERNEL); -@@ -2101,20 +2101,20 @@ err_dma: +@@ -2102,20 +2102,20 @@ err_dma: */ static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue) { @@ -540,7 +540,7 @@ Signed-off-by: Jakub Kicinski sizeof(struct sk_buff *), GFP_KERNEL); if (!tx_q->tx_skbuff) -@@ -2127,7 +2127,7 @@ static int __alloc_dma_tx_desc_resources +@@ -2128,7 +2128,7 @@ static int __alloc_dma_tx_desc_resources else size = sizeof(struct dma_desc); @@ -549,7 +549,7 @@ Signed-off-by: Jakub Kicinski addr = dma_alloc_coherent(priv->device, size, &tx_q->dma_tx_phy, GFP_KERNEL); -@@ -2371,7 +2371,7 @@ static void stmmac_dma_operation_mode(st +@@ -2372,7 +2372,7 @@ static void stmmac_dma_operation_mode(st /* configure all channels */ for (chan = 0; chan < rx_channels_count; chan++) { @@ -558,7 +558,7 @@ Signed-off-by: Jakub Kicinski u32 buf_size; qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; -@@ -2386,7 +2386,7 @@ static void stmmac_dma_operation_mode(st +@@ -2387,7 +2387,7 @@ static void stmmac_dma_operation_mode(st chan); } else { stmmac_set_dma_bfsize(priv, priv->ioaddr, @@ -567,7 +567,7 @@ Signed-off-by: Jakub Kicinski chan); } } -@@ -2402,7 +2402,7 @@ static void stmmac_dma_operation_mode(st +@@ -2403,7 +2403,7 @@ static void stmmac_dma_operation_mode(st static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget) { struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue); @@ -576,7 +576,7 @@ Signed-off-by: Jakub Kicinski struct xsk_buff_pool *pool = tx_q->xsk_pool; unsigned int entry = tx_q->cur_tx; struct dma_desc *tx_desc = NULL; -@@ -2477,7 +2477,7 @@ static bool stmmac_xdp_xmit_zc(struct st +@@ -2478,7 +2478,7 @@ static bool stmmac_xdp_xmit_zc(struct st stmmac_enable_dma_transmission(priv, priv->ioaddr); @@ -585,7 +585,7 @@ Signed-off-by: Jakub Kicinski entry = tx_q->cur_tx; } -@@ -2503,7 +2503,7 @@ static bool stmmac_xdp_xmit_zc(struct st +@@ -2504,7 +2504,7 @@ static bool stmmac_xdp_xmit_zc(struct st */ static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) { @@ -594,7 +594,7 @@ Signed-off-by: Jakub Kicinski unsigned int bytes_compl = 0, pkts_compl = 0; unsigned int entry, xmits = 0, count = 0; -@@ -2516,7 +2516,7 @@ static int stmmac_tx_clean(struct stmmac +@@ -2517,7 +2517,7 @@ static int stmmac_tx_clean(struct stmmac entry = tx_q->dirty_tx; /* Try to clean all TX complete frame in 1 shot */ @@ -603,7 +603,7 @@ Signed-off-by: Jakub Kicinski struct xdp_frame *xdpf; struct sk_buff *skb; struct dma_desc *p; -@@ -2616,7 +2616,7 @@ static int stmmac_tx_clean(struct stmmac +@@ -2617,7 +2617,7 @@ static int stmmac_tx_clean(struct stmmac stmmac_release_tx_desc(priv, p, priv->mode); @@ -612,7 +612,7 @@ Signed-off-by: Jakub Kicinski } tx_q->dirty_tx = entry; -@@ -2681,7 +2681,7 @@ static int stmmac_tx_clean(struct stmmac +@@ -2682,7 +2682,7 @@ static int stmmac_tx_clean(struct stmmac */ static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) { @@ -621,7 +621,7 @@ Signed-off-by: Jakub Kicinski netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); -@@ -2748,8 +2748,8 @@ static int stmmac_napi_check(struct stmm +@@ -2749,8 +2749,8 @@ static int stmmac_napi_check(struct stmm { int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, &priv->xstats, chan, dir); @@ -632,7 +632,7 @@ Signed-off-by: Jakub Kicinski struct stmmac_channel *ch = &priv->channel[chan]; struct napi_struct *rx_napi; struct napi_struct *tx_napi; -@@ -2925,7 +2925,7 @@ static int stmmac_init_dma_engine(struct +@@ -2926,7 +2926,7 @@ static int stmmac_init_dma_engine(struct /* DMA RX Channel Configuration */ for (chan = 0; chan < rx_channels_count; chan++) { @@ -641,7 +641,7 @@ Signed-off-by: Jakub Kicinski stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, rx_q->dma_rx_phy, chan); -@@ -2939,7 +2939,7 @@ static int stmmac_init_dma_engine(struct +@@ -2940,7 +2940,7 @@ static int stmmac_init_dma_engine(struct /* DMA TX Channel Configuration */ for (chan = 0; chan < tx_channels_count; chan++) { @@ -650,7 +650,7 @@ Signed-off-by: Jakub Kicinski stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, tx_q->dma_tx_phy, chan); -@@ -2954,7 +2954,7 @@ static int stmmac_init_dma_engine(struct +@@ -2955,7 +2955,7 @@ static int stmmac_init_dma_engine(struct static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) { @@ -659,7 +659,7 @@ Signed-off-by: Jakub Kicinski hrtimer_start(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), -@@ -3004,7 +3004,7 @@ static void stmmac_init_coalesce(struct +@@ -3005,7 +3005,7 @@ static void stmmac_init_coalesce(struct u32 chan; for (chan = 0; chan < tx_channel_count; chan++) { @@ -668,7 +668,7 @@ Signed-off-by: Jakub Kicinski priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES; priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER; -@@ -3026,12 +3026,12 @@ static void stmmac_set_rings_length(stru +@@ -3027,12 +3027,12 @@ static void stmmac_set_rings_length(stru /* set TX ring length */ for (chan = 0; chan < tx_channels_count; chan++) stmmac_set_tx_ring_len(priv, priv->ioaddr, @@ -683,7 +683,7 @@ Signed-off-by: Jakub Kicinski } /** -@@ -3366,7 +3366,7 @@ static int stmmac_hw_setup(struct net_de +@@ -3367,7 +3367,7 @@ static int stmmac_hw_setup(struct net_de /* Enable TSO */ if (priv->tso) { for (chan = 0; chan < tx_cnt; chan++) { @@ -692,7 +692,7 @@ Signed-off-by: Jakub Kicinski /* TSO and TBS cannot co-exist */ if (tx_q->tbs & STMMAC_TBS_AVAIL) -@@ -3388,7 +3388,7 @@ static int stmmac_hw_setup(struct net_de +@@ -3389,7 +3389,7 @@ static int stmmac_hw_setup(struct net_de /* TBS */ for (chan = 0; chan < tx_cnt; chan++) { @@ -701,7 +701,7 @@ Signed-off-by: Jakub Kicinski int enable = tx_q->tbs & STMMAC_TBS_AVAIL; stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); -@@ -3432,7 +3432,7 @@ static void stmmac_free_irq(struct net_d +@@ -3433,7 +3433,7 @@ static void stmmac_free_irq(struct net_d for (j = irq_idx - 1; j >= 0; j--) { if (priv->tx_irq[j] > 0) { irq_set_affinity_hint(priv->tx_irq[j], NULL); @@ -710,7 +710,7 @@ Signed-off-by: Jakub Kicinski } } irq_idx = priv->plat->rx_queues_to_use; -@@ -3441,7 +3441,7 @@ static void stmmac_free_irq(struct net_d +@@ -3442,7 +3442,7 @@ static void stmmac_free_irq(struct net_d for (j = irq_idx - 1; j >= 0; j--) { if (priv->rx_irq[j] > 0) { irq_set_affinity_hint(priv->rx_irq[j], NULL); @@ -719,7 +719,7 @@ Signed-off-by: Jakub Kicinski } } -@@ -3574,7 +3574,7 @@ static int stmmac_request_irq_multi_msi( +@@ -3575,7 +3575,7 @@ static int stmmac_request_irq_multi_msi( sprintf(int_name, "%s:%s-%d", dev->name, "rx", i); ret = request_irq(priv->rx_irq[i], stmmac_msi_intr_rx, @@ -728,7 +728,7 @@ Signed-off-by: Jakub Kicinski if (unlikely(ret < 0)) { netdev_err(priv->dev, "%s: alloc rx-%d MSI %d (error: %d)\n", -@@ -3597,7 +3597,7 @@ static int stmmac_request_irq_multi_msi( +@@ -3598,7 +3598,7 @@ static int stmmac_request_irq_multi_msi( sprintf(int_name, "%s:%s-%d", dev->name, "tx", i); ret = request_irq(priv->tx_irq[i], stmmac_msi_intr_tx, @@ -737,7 +737,7 @@ Signed-off-by: Jakub Kicinski if (unlikely(ret < 0)) { netdev_err(priv->dev, "%s: alloc tx-%d MSI %d (error: %d)\n", -@@ -3728,21 +3728,21 @@ static int stmmac_open(struct net_device +@@ -3729,21 +3729,21 @@ static int stmmac_open(struct net_device bfsize = 0; if (bfsize < BUF_SIZE_16KiB) @@ -766,7 +766,7 @@ Signed-off-by: Jakub Kicinski int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; /* Setup per-TXQ tbs flag before TX descriptor alloc */ -@@ -3800,7 +3800,7 @@ irq_error: +@@ -3801,7 +3801,7 @@ irq_error: phylink_stop(priv->phylink); for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) @@ -775,7 +775,7 @@ Signed-off-by: Jakub Kicinski stmmac_hw_teardown(dev); init_error: -@@ -3842,7 +3842,7 @@ static int stmmac_release(struct net_dev +@@ -3843,7 +3843,7 @@ static int stmmac_release(struct net_dev stmmac_disable_all_queues(priv); for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) @@ -784,7 +784,7 @@ Signed-off-by: Jakub Kicinski netif_tx_disable(dev); -@@ -3906,7 +3906,7 @@ static bool stmmac_vlan_insert(struct st +@@ -3907,7 +3907,7 @@ static bool stmmac_vlan_insert(struct st return false; stmmac_set_tx_owner(priv, p); @@ -793,7 +793,7 @@ Signed-off-by: Jakub Kicinski return true; } -@@ -3924,7 +3924,7 @@ static bool stmmac_vlan_insert(struct st +@@ -3925,7 +3925,7 @@ static bool stmmac_vlan_insert(struct st static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, int total_len, bool last_segment, u32 queue) { @@ -802,7 +802,7 @@ Signed-off-by: Jakub Kicinski struct dma_desc *desc; u32 buff_size; int tmp_len; -@@ -3935,7 +3935,7 @@ static void stmmac_tso_allocator(struct +@@ -3936,7 +3936,7 @@ static void stmmac_tso_allocator(struct dma_addr_t curr_addr; tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, @@ -811,7 +811,7 @@ Signed-off-by: Jakub Kicinski WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); if (tx_q->tbs & STMMAC_TBS_AVAIL) -@@ -3963,7 +3963,7 @@ static void stmmac_tso_allocator(struct +@@ -3964,7 +3964,7 @@ static void stmmac_tso_allocator(struct static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue) { @@ -820,7 +820,7 @@ Signed-off-by: Jakub Kicinski int desc_size; if (likely(priv->extend_desc)) -@@ -4025,7 +4025,7 @@ static netdev_tx_t stmmac_tso_xmit(struc +@@ -4026,7 +4026,7 @@ static netdev_tx_t stmmac_tso_xmit(struc dma_addr_t des; int i; @@ -829,7 +829,7 @@ Signed-off-by: Jakub Kicinski first_tx = tx_q->cur_tx; /* Compute header lengths */ -@@ -4065,7 +4065,7 @@ static netdev_tx_t stmmac_tso_xmit(struc +@@ -4066,7 +4066,7 @@ static netdev_tx_t stmmac_tso_xmit(struc stmmac_set_mss(priv, mss_desc, mss); tx_q->mss = mss; tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, @@ -838,7 +838,7 @@ Signed-off-by: Jakub Kicinski WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); } -@@ -4177,7 +4177,7 @@ static netdev_tx_t stmmac_tso_xmit(struc +@@ -4178,7 +4178,7 @@ static netdev_tx_t stmmac_tso_xmit(struc * ndo_start_xmit will fill this descriptor the next time it's * called and stmmac_tx_clean may clean up to this descriptor. */ @@ -847,7 +847,7 @@ Signed-off-by: Jakub Kicinski if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", -@@ -4265,7 +4265,7 @@ static netdev_tx_t stmmac_xmit(struct sk +@@ -4266,7 +4266,7 @@ static netdev_tx_t stmmac_xmit(struct sk int entry, first_tx; dma_addr_t des; @@ -856,7 +856,7 @@ Signed-off-by: Jakub Kicinski first_tx = tx_q->cur_tx; if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en) -@@ -4328,7 +4328,7 @@ static netdev_tx_t stmmac_xmit(struct sk +@@ -4329,7 +4329,7 @@ static netdev_tx_t stmmac_xmit(struct sk int len = skb_frag_size(frag); bool last_segment = (i == (nfrags - 1)); @@ -865,7 +865,7 @@ Signed-off-by: Jakub Kicinski WARN_ON(tx_q->tx_skbuff[entry]); if (likely(priv->extend_desc)) -@@ -4399,7 +4399,7 @@ static netdev_tx_t stmmac_xmit(struct sk +@@ -4400,7 +4400,7 @@ static netdev_tx_t stmmac_xmit(struct sk * ndo_start_xmit will fill this descriptor the next time it's * called and stmmac_tx_clean may clean up to this descriptor. */ @@ -874,7 +874,7 @@ Signed-off-by: Jakub Kicinski tx_q->cur_tx = entry; if (netif_msg_pktdata(priv)) { -@@ -4514,7 +4514,7 @@ static void stmmac_rx_vlan(struct net_de +@@ -4512,7 +4512,7 @@ static void stmmac_rx_vlan(struct net_de */ static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) { @@ -883,7 +883,7 @@ Signed-off-by: Jakub Kicinski int dirty = stmmac_rx_dirty(priv, queue); unsigned int entry = rx_q->dirty_rx; -@@ -4564,7 +4564,7 @@ static inline void stmmac_rx_refill(stru +@@ -4562,7 +4562,7 @@ static inline void stmmac_rx_refill(stru dma_wmb(); stmmac_set_rx_owner(priv, p, use_rx_wd); @@ -892,7 +892,7 @@ Signed-off-by: Jakub Kicinski } rx_q->dirty_rx = entry; rx_q->rx_tail_addr = rx_q->dma_rx_phy + -@@ -4592,12 +4592,12 @@ static unsigned int stmmac_rx_buf1_len(s +@@ -4590,12 +4590,12 @@ static unsigned int stmmac_rx_buf1_len(s /* First descriptor, not last descriptor and not split header */ if (status & rx_not_ls) @@ -907,7 +907,7 @@ Signed-off-by: Jakub Kicinski } static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, -@@ -4613,7 +4613,7 @@ static unsigned int stmmac_rx_buf2_len(s +@@ -4611,7 +4611,7 @@ static unsigned int stmmac_rx_buf2_len(s /* Not last descriptor */ if (status & rx_not_ls) @@ -916,7 +916,7 @@ Signed-off-by: Jakub Kicinski plen = stmmac_get_rx_frame_len(priv, p, coe); -@@ -4624,7 +4624,7 @@ static unsigned int stmmac_rx_buf2_len(s +@@ -4622,7 +4622,7 @@ static unsigned int stmmac_rx_buf2_len(s static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue, struct xdp_frame *xdpf, bool dma_map) { @@ -925,7 +925,7 @@ Signed-off-by: Jakub Kicinski unsigned int entry = tx_q->cur_tx; struct dma_desc *tx_desc; dma_addr_t dma_addr; -@@ -4687,7 +4687,7 @@ static int stmmac_xdp_xmit_xdpf(struct s +@@ -4685,7 +4685,7 @@ static int stmmac_xdp_xmit_xdpf(struct s stmmac_enable_dma_transmission(priv, priv->ioaddr); @@ -934,7 +934,7 @@ Signed-off-by: Jakub Kicinski tx_q->cur_tx = entry; return STMMAC_XDP_TX; -@@ -4861,7 +4861,7 @@ static void stmmac_dispatch_skb_zc(struc +@@ -4859,7 +4859,7 @@ static void stmmac_dispatch_skb_zc(struc static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget) { @@ -943,7 +943,7 @@ Signed-off-by: Jakub Kicinski unsigned int entry = rx_q->dirty_rx; struct dma_desc *rx_desc = NULL; bool ret = true; -@@ -4904,7 +4904,7 @@ static bool stmmac_rx_refill_zc(struct s +@@ -4902,7 +4902,7 @@ static bool stmmac_rx_refill_zc(struct s dma_wmb(); stmmac_set_rx_owner(priv, rx_desc, use_rx_wd); @@ -952,7 +952,7 @@ Signed-off-by: Jakub Kicinski } if (rx_desc) { -@@ -4919,7 +4919,7 @@ static bool stmmac_rx_refill_zc(struct s +@@ -4917,7 +4917,7 @@ static bool stmmac_rx_refill_zc(struct s static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue) { @@ -961,7 +961,7 @@ Signed-off-by: Jakub Kicinski unsigned int count = 0, error = 0, len = 0; int dirty = stmmac_rx_dirty(priv, queue); unsigned int next_entry = rx_q->cur_rx; -@@ -4941,7 +4941,7 @@ static int stmmac_rx_zc(struct stmmac_pr +@@ -4939,7 +4939,7 @@ static int stmmac_rx_zc(struct stmmac_pr desc_size = sizeof(struct dma_desc); } @@ -970,7 +970,7 @@ Signed-off-by: Jakub Kicinski rx_q->dma_rx_phy, desc_size); } while (count < limit) { -@@ -4988,7 +4988,7 @@ read_again: +@@ -4986,7 +4986,7 @@ read_again: /* Prefetch the next RX descriptor */ rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, @@ -979,7 +979,7 @@ Signed-off-by: Jakub Kicinski next_entry = rx_q->cur_rx; if (priv->extend_desc) -@@ -5109,7 +5109,7 @@ read_again: +@@ -5107,7 +5107,7 @@ read_again: */ static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) { @@ -988,7 +988,7 @@ Signed-off-by: Jakub Kicinski struct stmmac_channel *ch = &priv->channel[queue]; unsigned int count = 0, error = 0, len = 0; int status = 0, coe = priv->hw->rx_csum; -@@ -5122,7 +5122,7 @@ static int stmmac_rx(struct stmmac_priv +@@ -5120,7 +5120,7 @@ static int stmmac_rx(struct stmmac_priv int buf_sz; dma_dir = page_pool_get_dma_dir(rx_q->page_pool); @@ -997,7 +997,7 @@ Signed-off-by: Jakub Kicinski if (netif_msg_rx_status(priv)) { void *rx_head; -@@ -5136,7 +5136,7 @@ static int stmmac_rx(struct stmmac_priv +@@ -5134,7 +5134,7 @@ static int stmmac_rx(struct stmmac_priv desc_size = sizeof(struct dma_desc); } @@ -1006,7 +1006,7 @@ Signed-off-by: Jakub Kicinski rx_q->dma_rx_phy, desc_size); } while (count < limit) { -@@ -5180,7 +5180,7 @@ read_again: +@@ -5178,7 +5178,7 @@ read_again: break; rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, @@ -1015,7 +1015,7 @@ Signed-off-by: Jakub Kicinski next_entry = rx_q->cur_rx; if (priv->extend_desc) -@@ -5314,7 +5314,7 @@ read_again: +@@ -5312,7 +5312,7 @@ read_again: buf1_len, dma_dir); skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, buf->page, buf->page_offset, buf1_len, @@ -1024,7 +1024,7 @@ Signed-off-by: Jakub Kicinski /* Data payload appended into SKB */ page_pool_release_page(rx_q->page_pool, buf->page); -@@ -5326,7 +5326,7 @@ read_again: +@@ -5324,7 +5324,7 @@ read_again: buf2_len, dma_dir); skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, buf->sec_page, 0, buf2_len, @@ -1033,7 +1033,7 @@ Signed-off-by: Jakub Kicinski /* Data payload appended into SKB */ page_pool_release_page(rx_q->page_pool, buf->sec_page); -@@ -5768,11 +5768,13 @@ static irqreturn_t stmmac_safety_interru +@@ -5767,11 +5767,13 @@ static irqreturn_t stmmac_safety_interru static irqreturn_t stmmac_msi_intr_tx(int irq, void *data) { struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data; @@ -1048,7 +1048,7 @@ Signed-off-by: Jakub Kicinski if (unlikely(!data)) { netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); -@@ -5812,10 +5814,12 @@ static irqreturn_t stmmac_msi_intr_tx(in +@@ -5811,10 +5813,12 @@ static irqreturn_t stmmac_msi_intr_tx(in static irqreturn_t stmmac_msi_intr_rx(int irq, void *data) { struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data; @@ -1062,7 +1062,7 @@ Signed-off-by: Jakub Kicinski if (unlikely(!data)) { netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); -@@ -5846,10 +5850,10 @@ static void stmmac_poll_controller(struc +@@ -5845,10 +5849,10 @@ static void stmmac_poll_controller(struc if (priv->plat->multi_msi_en) { for (i = 0; i < priv->plat->rx_queues_to_use; i++) @@ -1075,7 +1075,7 @@ Signed-off-by: Jakub Kicinski } else { disable_irq(dev->irq); stmmac_interrupt(dev->irq, dev); -@@ -6030,34 +6034,34 @@ static int stmmac_rings_status_show(stru +@@ -6029,34 +6033,34 @@ static int stmmac_rings_status_show(stru return 0; for (queue = 0; queue < rx_count; queue++) { @@ -1116,7 +1116,7 @@ Signed-off-by: Jakub Kicinski } } -@@ -6404,7 +6408,7 @@ void stmmac_disable_rx_queue(struct stmm +@@ -6403,7 +6407,7 @@ void stmmac_disable_rx_queue(struct stmm void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue) { @@ -1125,7 +1125,7 @@ Signed-off-by: Jakub Kicinski struct stmmac_channel *ch = &priv->channel[queue]; unsigned long flags; u32 buf_size; -@@ -6441,7 +6445,7 @@ void stmmac_enable_rx_queue(struct stmma +@@ -6440,7 +6444,7 @@ void stmmac_enable_rx_queue(struct stmma rx_q->queue_index); } else { stmmac_set_dma_bfsize(priv, priv->ioaddr, @@ -1134,7 +1134,7 @@ Signed-off-by: Jakub Kicinski rx_q->queue_index); } -@@ -6467,7 +6471,7 @@ void stmmac_disable_tx_queue(struct stmm +@@ -6466,7 +6470,7 @@ void stmmac_disable_tx_queue(struct stmm void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue) { @@ -1143,7 +1143,7 @@ Signed-off-by: Jakub Kicinski struct stmmac_channel *ch = &priv->channel[queue]; unsigned long flags; int ret; -@@ -6517,7 +6521,7 @@ void stmmac_xdp_release(struct net_devic +@@ -6516,7 +6520,7 @@ void stmmac_xdp_release(struct net_devic stmmac_disable_all_queues(priv); for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) @@ -1152,7 +1152,7 @@ Signed-off-by: Jakub Kicinski /* Free the IRQ lines */ stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); -@@ -6576,7 +6580,7 @@ int stmmac_xdp_open(struct net_device *d +@@ -6575,7 +6579,7 @@ int stmmac_xdp_open(struct net_device *d /* DMA RX Channel Configuration */ for (chan = 0; chan < rx_cnt; chan++) { @@ -1161,7 +1161,7 @@ Signed-off-by: Jakub Kicinski stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, rx_q->dma_rx_phy, chan); -@@ -6594,7 +6598,7 @@ int stmmac_xdp_open(struct net_device *d +@@ -6593,7 +6597,7 @@ int stmmac_xdp_open(struct net_device *d rx_q->queue_index); } else { stmmac_set_dma_bfsize(priv, priv->ioaddr, @@ -1170,7 +1170,7 @@ Signed-off-by: Jakub Kicinski rx_q->queue_index); } -@@ -6603,7 +6607,7 @@ int stmmac_xdp_open(struct net_device *d +@@ -6602,7 +6606,7 @@ int stmmac_xdp_open(struct net_device *d /* DMA TX Channel Configuration */ for (chan = 0; chan < tx_cnt; chan++) { @@ -1179,7 +1179,7 @@ Signed-off-by: Jakub Kicinski stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, tx_q->dma_tx_phy, chan); -@@ -6636,7 +6640,7 @@ int stmmac_xdp_open(struct net_device *d +@@ -6635,7 +6639,7 @@ int stmmac_xdp_open(struct net_device *d irq_error: for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) @@ -1188,7 +1188,7 @@ Signed-off-by: Jakub Kicinski stmmac_hw_teardown(dev); init_error: -@@ -6663,8 +6667,8 @@ int stmmac_xsk_wakeup(struct net_device +@@ -6662,8 +6666,8 @@ int stmmac_xsk_wakeup(struct net_device queue >= priv->plat->tx_queues_to_use) return -EINVAL; @@ -1199,7 +1199,7 @@ Signed-off-by: Jakub Kicinski ch = &priv->channel[queue]; if (!rx_q->xsk_pool && !tx_q->xsk_pool) -@@ -6924,8 +6928,8 @@ int stmmac_reinit_ringparam(struct net_d +@@ -6923,8 +6927,8 @@ int stmmac_reinit_ringparam(struct net_d if (netif_running(dev)) stmmac_release(dev); @@ -1210,7 +1210,7 @@ Signed-off-by: Jakub Kicinski if (netif_running(dev)) ret = stmmac_open(dev); -@@ -7357,7 +7361,7 @@ int stmmac_suspend(struct device *dev) +@@ -7359,7 +7363,7 @@ int stmmac_suspend(struct device *dev) stmmac_disable_all_queues(priv); for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) @@ -1219,7 +1219,7 @@ Signed-off-by: Jakub Kicinski if (priv->eee_enabled) { priv->tx_path_in_lpi_mode = false; -@@ -7408,7 +7412,7 @@ EXPORT_SYMBOL_GPL(stmmac_suspend); +@@ -7411,7 +7415,7 @@ EXPORT_SYMBOL_GPL(stmmac_suspend); static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue) { @@ -1228,7 +1228,7 @@ Signed-off-by: Jakub Kicinski rx_q->cur_rx = 0; rx_q->dirty_rx = 0; -@@ -7416,7 +7420,7 @@ static void stmmac_reset_rx_queue(struct +@@ -7419,7 +7423,7 @@ static void stmmac_reset_rx_queue(struct static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue) { @@ -1270,7 +1270,7 @@ Signed-off-by: Jakub Kicinski if (i >= priv->plat->tx_queues_to_use) --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c -@@ -970,13 +970,13 @@ static int tc_setup_etf(struct stmmac_pr +@@ -971,13 +971,13 @@ static int tc_setup_etf(struct stmmac_pr return -EOPNOTSUPP; if (qopt->queue >= priv->plat->tx_queues_to_use) return -EINVAL; diff --git a/target/linux/generic/backport-5.15/775-v6.0-04-net-ethernet-stmicro-stmmac-generate-stmmac-dma-conf.patch b/target/linux/generic/backport-5.15/775-v6.0-04-net-ethernet-stmicro-stmmac-generate-stmmac-dma-conf.patch index a7ee50ddd02b45..7336456c0c0e9b 100644 --- a/target/linux/generic/backport-5.15/775-v6.0-04-net-ethernet-stmicro-stmmac-generate-stmmac-dma-conf.patch +++ b/target/linux/generic/backport-5.15/775-v6.0-04-net-ethernet-stmicro-stmmac-generate-stmmac-dma-conf.patch @@ -17,7 +17,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -1300,7 +1300,8 @@ static int stmmac_phy_setup(struct stmma +@@ -1301,7 +1301,8 @@ static int stmmac_phy_setup(struct stmma return 0; } @@ -27,7 +27,7 @@ Signed-off-by: Jakub Kicinski { u32 rx_cnt = priv->plat->rx_queues_to_use; unsigned int desc_size; -@@ -1309,7 +1310,7 @@ static void stmmac_display_rx_rings(stru +@@ -1310,7 +1311,7 @@ static void stmmac_display_rx_rings(stru /* Display RX rings */ for (queue = 0; queue < rx_cnt; queue++) { @@ -36,7 +36,7 @@ Signed-off-by: Jakub Kicinski pr_info("\tRX Queue %u rings\n", queue); -@@ -1322,12 +1323,13 @@ static void stmmac_display_rx_rings(stru +@@ -1323,12 +1324,13 @@ static void stmmac_display_rx_rings(stru } /* Display RX ring */ @@ -52,7 +52,7 @@ Signed-off-by: Jakub Kicinski { u32 tx_cnt = priv->plat->tx_queues_to_use; unsigned int desc_size; -@@ -1336,7 +1338,7 @@ static void stmmac_display_tx_rings(stru +@@ -1337,7 +1339,7 @@ static void stmmac_display_tx_rings(stru /* Display TX rings */ for (queue = 0; queue < tx_cnt; queue++) { @@ -61,7 +61,7 @@ Signed-off-by: Jakub Kicinski pr_info("\tTX Queue %d rings\n", queue); -@@ -1351,18 +1353,19 @@ static void stmmac_display_tx_rings(stru +@@ -1352,18 +1354,19 @@ static void stmmac_display_tx_rings(stru desc_size = sizeof(struct dma_desc); } @@ -85,7 +85,7 @@ Signed-off-by: Jakub Kicinski } static int stmmac_set_bfsize(int mtu, int bufsize) -@@ -1386,44 +1389,50 @@ static int stmmac_set_bfsize(int mtu, in +@@ -1387,44 +1390,50 @@ static int stmmac_set_bfsize(int mtu, in /** * stmmac_clear_rx_descriptors - clear RX descriptors * @priv: driver private structure @@ -147,7 +147,7 @@ Signed-off-by: Jakub Kicinski struct dma_desc *p; if (priv->extend_desc) -@@ -1440,10 +1449,12 @@ static void stmmac_clear_tx_descriptors( +@@ -1441,10 +1450,12 @@ static void stmmac_clear_tx_descriptors( /** * stmmac_clear_descriptors - clear descriptors * @priv: driver private structure @@ -161,7 +161,7 @@ Signed-off-by: Jakub Kicinski { u32 rx_queue_cnt = priv->plat->rx_queues_to_use; u32 tx_queue_cnt = priv->plat->tx_queues_to_use; -@@ -1451,16 +1462,17 @@ static void stmmac_clear_descriptors(str +@@ -1452,16 +1463,17 @@ static void stmmac_clear_descriptors(str /* Clear the RX descriptors */ for (queue = 0; queue < rx_queue_cnt; queue++) @@ -181,7 +181,7 @@ Signed-off-by: Jakub Kicinski * @p: descriptor pointer * @i: descriptor index * @flags: gfp flag -@@ -1468,10 +1480,12 @@ static void stmmac_clear_descriptors(str +@@ -1469,10 +1481,12 @@ static void stmmac_clear_descriptors(str * Description: this function is called to allocate a receive buffer, perform * the DMA mapping and init the descriptor. */ @@ -196,7 +196,7 @@ Signed-off-by: Jakub Kicinski struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; if (!buf->page) { -@@ -1496,7 +1510,7 @@ static int stmmac_init_rx_buffers(struct +@@ -1497,7 +1511,7 @@ static int stmmac_init_rx_buffers(struct buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; stmmac_set_desc_addr(priv, p, buf->addr); @@ -205,7 +205,7 @@ Signed-off-by: Jakub Kicinski stmmac_init_desc3(priv, p); return 0; -@@ -1505,12 +1519,13 @@ static int stmmac_init_rx_buffers(struct +@@ -1506,12 +1520,13 @@ static int stmmac_init_rx_buffers(struct /** * stmmac_free_rx_buffer - free RX dma buffers * @priv: private structure @@ -222,7 +222,7 @@ Signed-off-by: Jakub Kicinski struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; if (buf->page) -@@ -1525,12 +1540,15 @@ static void stmmac_free_rx_buffer(struct +@@ -1526,12 +1541,15 @@ static void stmmac_free_rx_buffer(struct /** * stmmac_free_tx_buffer - free RX dma buffers * @priv: private structure @@ -240,7 +240,7 @@ Signed-off-by: Jakub Kicinski if (tx_q->tx_skbuff_dma[i].buf && tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) { -@@ -1569,23 +1587,28 @@ static void stmmac_free_tx_buffer(struct +@@ -1570,23 +1588,28 @@ static void stmmac_free_tx_buffer(struct /** * dma_free_rx_skbufs - free RX dma buffers * @priv: private structure @@ -276,7 +276,7 @@ Signed-off-by: Jakub Kicinski struct dma_desc *p; int ret; -@@ -1594,7 +1617,7 @@ static int stmmac_alloc_rx_buffers(struc +@@ -1595,7 +1618,7 @@ static int stmmac_alloc_rx_buffers(struc else p = rx_q->dma_rx + i; @@ -285,7 +285,7 @@ Signed-off-by: Jakub Kicinski queue); if (ret) return ret; -@@ -1608,14 +1631,17 @@ static int stmmac_alloc_rx_buffers(struc +@@ -1609,14 +1632,17 @@ static int stmmac_alloc_rx_buffers(struc /** * dma_free_rx_xskbufs - free RX dma buffers from XSK pool * @priv: private structure @@ -306,7 +306,7 @@ Signed-off-by: Jakub Kicinski struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; if (!buf->xdp) -@@ -1626,12 +1652,14 @@ static void dma_free_rx_xskbufs(struct s +@@ -1627,12 +1653,14 @@ static void dma_free_rx_xskbufs(struct s } } @@ -324,7 +324,7 @@ Signed-off-by: Jakub Kicinski struct stmmac_rx_buffer *buf; dma_addr_t dma_addr; struct dma_desc *p; -@@ -1666,22 +1694,25 @@ static struct xsk_buff_pool *stmmac_get_ +@@ -1667,22 +1695,25 @@ static struct xsk_buff_pool *stmmac_get_ /** * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue) * @priv: driver private structure @@ -353,7 +353,7 @@ Signed-off-by: Jakub Kicinski xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq); -@@ -1708,9 +1739,9 @@ static int __init_dma_rx_desc_rings(stru +@@ -1709,9 +1740,9 @@ static int __init_dma_rx_desc_rings(stru /* RX XDP ZC buffer pool may not be populated, e.g. * xdpsock TX-only. */ @@ -365,7 +365,7 @@ Signed-off-by: Jakub Kicinski if (ret < 0) return -ENOMEM; } -@@ -1720,17 +1751,19 @@ static int __init_dma_rx_desc_rings(stru +@@ -1721,17 +1752,19 @@ static int __init_dma_rx_desc_rings(stru if (priv->extend_desc) stmmac_mode_init(priv, rx_q->dma_erx, rx_q->dma_rx_phy, @@ -388,7 +388,7 @@ Signed-off-by: Jakub Kicinski { struct stmmac_priv *priv = netdev_priv(dev); u32 rx_count = priv->plat->rx_queues_to_use; -@@ -1742,7 +1775,7 @@ static int init_dma_rx_desc_rings(struct +@@ -1743,7 +1776,7 @@ static int init_dma_rx_desc_rings(struct "SKB addresses:\nskb\t\tskb data\tdma data\n"); for (queue = 0; queue < rx_count; queue++) { @@ -397,7 +397,7 @@ Signed-off-by: Jakub Kicinski if (ret) goto err_init_rx_buffers; } -@@ -1751,12 +1784,12 @@ static int init_dma_rx_desc_rings(struct +@@ -1752,12 +1785,12 @@ static int init_dma_rx_desc_rings(struct err_init_rx_buffers: while (queue >= 0) { @@ -413,7 +413,7 @@ Signed-off-by: Jakub Kicinski rx_q->buf_alloc_num = 0; rx_q->xsk_pool = NULL; -@@ -1773,14 +1806,17 @@ err_init_rx_buffers: +@@ -1774,14 +1807,17 @@ err_init_rx_buffers: /** * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue) * @priv: driver private structure @@ -434,7 +434,7 @@ Signed-off-by: Jakub Kicinski int i; netif_dbg(priv, probe, priv->dev, -@@ -1792,16 +1828,16 @@ static int __init_dma_tx_desc_rings(stru +@@ -1793,16 +1829,16 @@ static int __init_dma_tx_desc_rings(stru if (priv->extend_desc) stmmac_mode_init(priv, tx_q->dma_etx, tx_q->dma_tx_phy, @@ -454,7 +454,7 @@ Signed-off-by: Jakub Kicinski struct dma_desc *p; if (priv->extend_desc) -@@ -1823,7 +1859,8 @@ static int __init_dma_tx_desc_rings(stru +@@ -1824,7 +1860,8 @@ static int __init_dma_tx_desc_rings(stru return 0; } @@ -464,7 +464,7 @@ Signed-off-by: Jakub Kicinski { struct stmmac_priv *priv = netdev_priv(dev); u32 tx_queue_cnt; -@@ -1832,7 +1869,7 @@ static int init_dma_tx_desc_rings(struct +@@ -1833,7 +1870,7 @@ static int init_dma_tx_desc_rings(struct tx_queue_cnt = priv->plat->tx_queues_to_use; for (queue = 0; queue < tx_queue_cnt; queue++) @@ -473,7 +473,7 @@ Signed-off-by: Jakub Kicinski return 0; } -@@ -1840,26 +1877,29 @@ static int init_dma_tx_desc_rings(struct +@@ -1841,26 +1878,29 @@ static int init_dma_tx_desc_rings(struct /** * init_dma_desc_rings - init the RX/TX descriptor rings * @dev: net device structure @@ -508,7 +508,7 @@ Signed-off-by: Jakub Kicinski return ret; } -@@ -1867,17 +1907,20 @@ static int init_dma_desc_rings(struct ne +@@ -1868,17 +1908,20 @@ static int init_dma_desc_rings(struct ne /** * dma_free_tx_skbufs - free TX dma buffers * @priv: private structure @@ -533,7 +533,7 @@ Signed-off-by: Jakub Kicinski if (tx_q->xsk_pool && tx_q->xsk_frames_done) { xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); -@@ -1896,34 +1939,37 @@ static void stmmac_free_tx_skbufs(struct +@@ -1897,34 +1940,37 @@ static void stmmac_free_tx_skbufs(struct u32 queue; for (queue = 0; queue < tx_queue_cnt; queue++) @@ -578,7 +578,7 @@ Signed-off-by: Jakub Kicinski sizeof(struct dma_extended_desc), rx_q->dma_erx, rx_q->dma_rx_phy); -@@ -1935,29 +1981,33 @@ static void __free_dma_rx_desc_resources +@@ -1936,29 +1982,33 @@ static void __free_dma_rx_desc_resources page_pool_destroy(rx_q->page_pool); } @@ -617,7 +617,7 @@ Signed-off-by: Jakub Kicinski if (priv->extend_desc) { size = sizeof(struct dma_extended_desc); -@@ -1970,7 +2020,7 @@ static void __free_dma_tx_desc_resources +@@ -1971,7 +2021,7 @@ static void __free_dma_tx_desc_resources addr = tx_q->dma_tx; } @@ -626,7 +626,7 @@ Signed-off-by: Jakub Kicinski dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); -@@ -1978,28 +2028,32 @@ static void __free_dma_tx_desc_resources +@@ -1979,28 +2029,32 @@ static void __free_dma_tx_desc_resources kfree(tx_q->tx_skbuff); } @@ -663,7 +663,7 @@ Signed-off-by: Jakub Kicinski struct stmmac_channel *ch = &priv->channel[queue]; bool xdp_prog = stmmac_xdp_is_enabled(priv); struct page_pool_params pp_params = { 0 }; -@@ -2011,8 +2065,8 @@ static int __alloc_dma_rx_desc_resources +@@ -2012,8 +2066,8 @@ static int __alloc_dma_rx_desc_resources rx_q->priv_data = priv; pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV; @@ -674,7 +674,7 @@ Signed-off-by: Jakub Kicinski pp_params.order = ilog2(num_pages); pp_params.nid = dev_to_node(priv->device); pp_params.dev = priv->device; -@@ -2027,7 +2081,7 @@ static int __alloc_dma_rx_desc_resources +@@ -2028,7 +2082,7 @@ static int __alloc_dma_rx_desc_resources return ret; } @@ -683,7 +683,7 @@ Signed-off-by: Jakub Kicinski sizeof(*rx_q->buf_pool), GFP_KERNEL); if (!rx_q->buf_pool) -@@ -2035,7 +2089,7 @@ static int __alloc_dma_rx_desc_resources +@@ -2036,7 +2090,7 @@ static int __alloc_dma_rx_desc_resources if (priv->extend_desc) { rx_q->dma_erx = dma_alloc_coherent(priv->device, @@ -692,7 +692,7 @@ Signed-off-by: Jakub Kicinski sizeof(struct dma_extended_desc), &rx_q->dma_rx_phy, GFP_KERNEL); -@@ -2044,7 +2098,7 @@ static int __alloc_dma_rx_desc_resources +@@ -2045,7 +2099,7 @@ static int __alloc_dma_rx_desc_resources } else { rx_q->dma_rx = dma_alloc_coherent(priv->device, @@ -701,7 +701,7 @@ Signed-off-by: Jakub Kicinski sizeof(struct dma_desc), &rx_q->dma_rx_phy, GFP_KERNEL); -@@ -2069,7 +2123,8 @@ static int __alloc_dma_rx_desc_resources +@@ -2070,7 +2124,8 @@ static int __alloc_dma_rx_desc_resources return 0; } @@ -711,7 +711,7 @@ Signed-off-by: Jakub Kicinski { u32 rx_count = priv->plat->rx_queues_to_use; u32 queue; -@@ -2077,7 +2132,7 @@ static int alloc_dma_rx_desc_resources(s +@@ -2078,7 +2133,7 @@ static int alloc_dma_rx_desc_resources(s /* RX queues buffers and DMA */ for (queue = 0; queue < rx_count; queue++) { @@ -720,7 +720,7 @@ Signed-off-by: Jakub Kicinski if (ret) goto err_dma; } -@@ -2085,7 +2140,7 @@ static int alloc_dma_rx_desc_resources(s +@@ -2086,7 +2141,7 @@ static int alloc_dma_rx_desc_resources(s return 0; err_dma: @@ -729,7 +729,7 @@ Signed-off-by: Jakub Kicinski return ret; } -@@ -2093,28 +2148,31 @@ err_dma: +@@ -2094,28 +2149,31 @@ err_dma: /** * __alloc_dma_tx_desc_resources - alloc TX resources (per queue). * @priv: private structure @@ -765,7 +765,7 @@ Signed-off-by: Jakub Kicinski sizeof(struct sk_buff *), GFP_KERNEL); if (!tx_q->tx_skbuff) -@@ -2127,7 +2185,7 @@ static int __alloc_dma_tx_desc_resources +@@ -2128,7 +2186,7 @@ static int __alloc_dma_tx_desc_resources else size = sizeof(struct dma_desc); @@ -774,7 +774,7 @@ Signed-off-by: Jakub Kicinski addr = dma_alloc_coherent(priv->device, size, &tx_q->dma_tx_phy, GFP_KERNEL); -@@ -2144,7 +2202,8 @@ static int __alloc_dma_tx_desc_resources +@@ -2145,7 +2203,8 @@ static int __alloc_dma_tx_desc_resources return 0; } @@ -784,7 +784,7 @@ Signed-off-by: Jakub Kicinski { u32 tx_count = priv->plat->tx_queues_to_use; u32 queue; -@@ -2152,7 +2211,7 @@ static int alloc_dma_tx_desc_resources(s +@@ -2153,7 +2212,7 @@ static int alloc_dma_tx_desc_resources(s /* TX queues buffers and DMA */ for (queue = 0; queue < tx_count; queue++) { @@ -793,7 +793,7 @@ Signed-off-by: Jakub Kicinski if (ret) goto err_dma; } -@@ -2160,27 +2219,29 @@ static int alloc_dma_tx_desc_resources(s +@@ -2161,27 +2220,29 @@ static int alloc_dma_tx_desc_resources(s return 0; err_dma: @@ -827,7 +827,7 @@ Signed-off-by: Jakub Kicinski return ret; } -@@ -2188,16 +2249,18 @@ static int alloc_dma_desc_resources(stru +@@ -2189,16 +2250,18 @@ static int alloc_dma_desc_resources(stru /** * free_dma_desc_resources - free dma desc resources * @priv: private structure @@ -849,7 +849,7 @@ Signed-off-by: Jakub Kicinski } /** -@@ -2686,8 +2749,8 @@ static void stmmac_tx_err(struct stmmac_ +@@ -2687,8 +2750,8 @@ static void stmmac_tx_err(struct stmmac_ netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); stmmac_stop_tx_dma(priv, chan); @@ -860,7 +860,7 @@ Signed-off-by: Jakub Kicinski stmmac_reset_tx_queue(priv, chan); stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, tx_q->dma_tx_phy, chan); -@@ -3684,19 +3747,93 @@ static int stmmac_request_irq(struct net +@@ -3685,19 +3748,93 @@ static int stmmac_request_irq(struct net } /** @@ -957,7 +957,7 @@ Signed-off-by: Jakub Kicinski u32 chan; int ret; -@@ -3723,45 +3860,10 @@ static int stmmac_open(struct net_device +@@ -3724,45 +3861,10 @@ static int stmmac_open(struct net_device memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); priv->xstats.threshold = tc; @@ -1005,7 +1005,7 @@ Signed-off-by: Jakub Kicinski if (priv->plat->serdes_powerup) { ret = priv->plat->serdes_powerup(dev, priv->plat->bsp_priv); -@@ -3804,14 +3906,28 @@ irq_error: +@@ -3805,14 +3907,28 @@ irq_error: stmmac_hw_teardown(dev); init_error: @@ -1036,7 +1036,7 @@ Signed-off-by: Jakub Kicinski static void stmmac_fpe_stop_wq(struct stmmac_priv *priv) { set_bit(__FPE_REMOVING, &priv->fpe_task_state); -@@ -3858,7 +3974,7 @@ static int stmmac_release(struct net_dev +@@ -3859,7 +3975,7 @@ static int stmmac_release(struct net_dev stmmac_stop_all_dma(priv); /* Release and free the Rx/Tx resources */ @@ -1045,7 +1045,7 @@ Signed-off-by: Jakub Kicinski /* Disable the MAC Rx/Tx */ stmmac_mac_set(priv, priv->ioaddr, false); -@@ -6403,7 +6519,7 @@ void stmmac_disable_rx_queue(struct stmm +@@ -6402,7 +6518,7 @@ void stmmac_disable_rx_queue(struct stmm spin_unlock_irqrestore(&ch->lock, flags); stmmac_stop_rx_dma(priv, queue); @@ -1054,7 +1054,7 @@ Signed-off-by: Jakub Kicinski } void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue) -@@ -6414,21 +6530,21 @@ void stmmac_enable_rx_queue(struct stmma +@@ -6413,21 +6529,21 @@ void stmmac_enable_rx_queue(struct stmma u32 buf_size; int ret; @@ -1080,7 +1080,7 @@ Signed-off-by: Jakub Kicinski stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, rx_q->dma_rx_phy, rx_q->queue_index); -@@ -6466,7 +6582,7 @@ void stmmac_disable_tx_queue(struct stmm +@@ -6465,7 +6581,7 @@ void stmmac_disable_tx_queue(struct stmm spin_unlock_irqrestore(&ch->lock, flags); stmmac_stop_tx_dma(priv, queue); @@ -1089,7 +1089,7 @@ Signed-off-by: Jakub Kicinski } void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue) -@@ -6476,21 +6592,21 @@ void stmmac_enable_tx_queue(struct stmma +@@ -6475,21 +6591,21 @@ void stmmac_enable_tx_queue(struct stmma unsigned long flags; int ret; @@ -1115,7 +1115,7 @@ Signed-off-by: Jakub Kicinski stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, tx_q->dma_tx_phy, tx_q->queue_index); -@@ -6530,7 +6646,7 @@ void stmmac_xdp_release(struct net_devic +@@ -6529,7 +6645,7 @@ void stmmac_xdp_release(struct net_devic stmmac_stop_all_dma(priv); /* Release and free the Rx/Tx resources */ @@ -1124,7 +1124,7 @@ Signed-off-by: Jakub Kicinski /* Disable the MAC Rx/Tx */ stmmac_mac_set(priv, priv->ioaddr, false); -@@ -6555,14 +6671,14 @@ int stmmac_xdp_open(struct net_device *d +@@ -6554,14 +6670,14 @@ int stmmac_xdp_open(struct net_device *d u32 chan; int ret; @@ -1141,7 +1141,7 @@ Signed-off-by: Jakub Kicinski if (ret < 0) { netdev_err(dev, "%s: DMA descriptors initialization failed\n", __func__); -@@ -6644,7 +6760,7 @@ irq_error: +@@ -6643,7 +6759,7 @@ irq_error: stmmac_hw_teardown(dev); init_error: @@ -1150,7 +1150,7 @@ Signed-off-by: Jakub Kicinski dma_desc_error: return ret; } -@@ -7503,7 +7619,7 @@ int stmmac_resume(struct device *dev) +@@ -7506,7 +7622,7 @@ int stmmac_resume(struct device *dev) stmmac_reset_queues_param(priv); stmmac_free_tx_skbufs(priv); diff --git a/target/linux/generic/backport-5.15/775-v6.0-05-net-ethernet-stmicro-stmmac-permit-MTU-change-with-i.patch b/target/linux/generic/backport-5.15/775-v6.0-05-net-ethernet-stmicro-stmmac-permit-MTU-change-with-i.patch index 8fccc716597cf5..6ebb527726e440 100644 --- a/target/linux/generic/backport-5.15/775-v6.0-05-net-ethernet-stmicro-stmmac-permit-MTU-change-with-i.patch +++ b/target/linux/generic/backport-5.15/775-v6.0-05-net-ethernet-stmicro-stmmac-permit-MTU-change-with-i.patch @@ -19,7 +19,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -5626,18 +5626,15 @@ static int stmmac_change_mtu(struct net_ +@@ -5624,18 +5624,15 @@ static int stmmac_change_mtu(struct net_ { struct stmmac_priv *priv = netdev_priv(dev); int txfifosz = priv->plat->tx_fifo_size; @@ -40,7 +40,7 @@ Signed-off-by: Jakub Kicinski if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) { netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n"); return -EINVAL; -@@ -5649,8 +5646,29 @@ static int stmmac_change_mtu(struct net_ +@@ -5647,8 +5644,29 @@ static int stmmac_change_mtu(struct net_ if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) return -EINVAL; diff --git a/target/linux/generic/backport-5.15/790-v6.4-0002-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch b/target/linux/generic/backport-5.15/790-v6.4-0002-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch index 8963d93d107ac5..983423aaff6a11 100644 --- a/target/linux/generic/backport-5.15/790-v6.4-0002-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch +++ b/target/linux/generic/backport-5.15/790-v6.4-0002-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch @@ -18,7 +18,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2926,26 +2926,56 @@ static const struct regmap_bus mt7531_re +@@ -2951,26 +2951,56 @@ static const struct regmap_bus mt7531_re .reg_update_bits = mt7530_regmap_update_bits, }; @@ -88,7 +88,7 @@ Signed-off-by: David S. Miller int i, ret; /* Initialise the PCS devices */ -@@ -2967,15 +2997,11 @@ mt753x_setup(struct dsa_switch *ds) +@@ -2992,15 +3022,11 @@ mt753x_setup(struct dsa_switch *ds) if (ret && priv->irq) mt7530_free_irq_common(priv); diff --git a/target/linux/generic/backport-5.15/790-v6.4-0003-net-dsa-mt7530-use-unlocked-regmap-accessors.patch b/target/linux/generic/backport-5.15/790-v6.4-0003-net-dsa-mt7530-use-unlocked-regmap-accessors.patch index 1b4a9561992f36..9d8f67ba957f39 100644 --- a/target/linux/generic/backport-5.15/790-v6.4-0003-net-dsa-mt7530-use-unlocked-regmap-accessors.patch +++ b/target/linux/generic/backport-5.15/790-v6.4-0003-net-dsa-mt7530-use-unlocked-regmap-accessors.patch @@ -19,7 +19,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2899,7 +2899,7 @@ static int mt7530_regmap_read(void *cont +@@ -2924,7 +2924,7 @@ static int mt7530_regmap_read(void *cont { struct mt7530_priv *priv = context; @@ -28,7 +28,7 @@ Signed-off-by: David S. Miller return 0; }; -@@ -2907,23 +2907,25 @@ static int mt7530_regmap_write(void *con +@@ -2932,23 +2932,25 @@ static int mt7530_regmap_write(void *con { struct mt7530_priv *priv = context; @@ -62,7 +62,7 @@ Signed-off-by: David S. Miller }; static int -@@ -2949,6 +2951,9 @@ mt7531_create_sgmii(struct mt7530_priv * +@@ -2974,6 +2976,9 @@ mt7531_create_sgmii(struct mt7530_priv * mt7531_pcs_config[i]->reg_stride = 4; mt7531_pcs_config[i]->reg_base = MT7531_SGMII_REG_BASE(5 + i); mt7531_pcs_config[i]->max_register = 0x17c; diff --git a/target/linux/generic/backport-5.15/790-v6.4-0004-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch b/target/linux/generic/backport-5.15/790-v6.4-0004-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch index 2d8bab9da63e59..bd1d5c98a7ce3c 100644 --- a/target/linux/generic/backport-5.15/790-v6.4-0004-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch +++ b/target/linux/generic/backport-5.15/790-v6.4-0004-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch @@ -133,7 +133,7 @@ Signed-off-by: David S. Miller } static void -@@ -2895,22 +2916,6 @@ static const struct phylink_pcs_ops mt75 +@@ -2920,22 +2941,6 @@ static const struct phylink_pcs_ops mt75 .pcs_an_restart = mt7530_pcs_an_restart, }; @@ -156,7 +156,7 @@ Signed-off-by: David S. Miller static void mt7530_mdio_regmap_lock(void *mdio_lock) { -@@ -2923,7 +2928,7 @@ mt7530_mdio_regmap_unlock(void *mdio_loc +@@ -2948,7 +2953,7 @@ mt7530_mdio_regmap_unlock(void *mdio_loc mutex_unlock(mdio_lock); } @@ -165,7 +165,7 @@ Signed-off-by: David S. Miller .reg_write = mt7530_regmap_write, .reg_read = mt7530_regmap_read, }; -@@ -2956,7 +2961,7 @@ mt7531_create_sgmii(struct mt7530_priv * +@@ -2981,7 +2986,7 @@ mt7531_create_sgmii(struct mt7530_priv * mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock; regmap = devm_regmap_init(priv->dev, @@ -174,7 +174,7 @@ Signed-off-by: David S. Miller mt7531_pcs_config[i]); if (IS_ERR(regmap)) { ret = PTR_ERR(regmap); -@@ -3121,6 +3126,7 @@ MODULE_DEVICE_TABLE(of, mt7530_of_match) +@@ -3146,6 +3151,7 @@ MODULE_DEVICE_TABLE(of, mt7530_of_match) static int mt7530_probe(struct mdio_device *mdiodev) { @@ -182,7 +182,7 @@ Signed-off-by: David S. Miller struct mt7530_priv *priv; struct device_node *dn; -@@ -3200,6 +3206,21 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3225,6 +3231,21 @@ mt7530_probe(struct mdio_device *mdiodev mutex_init(&priv->reg_mutex); dev_set_drvdata(&mdiodev->dev, priv); diff --git a/target/linux/generic/backport-5.15/790-v6.4-0005-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch b/target/linux/generic/backport-5.15/790-v6.4-0005-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch index 0bb64c3c5e9924..8c11bc3733ec57 100644 --- a/target/linux/generic/backport-5.15/790-v6.4-0005-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch +++ b/target/linux/generic/backport-5.15/790-v6.4-0005-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch @@ -18,7 +18,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3007,12 +3007,6 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3032,12 +3032,6 @@ mt753x_setup(struct dsa_switch *ds) if (ret && priv->irq) mt7530_free_irq_common(priv); @@ -31,7 +31,7 @@ Signed-off-by: David S. Miller return ret; } -@@ -3129,6 +3123,7 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3154,6 +3148,7 @@ mt7530_probe(struct mdio_device *mdiodev static struct regmap_config *regmap_config; struct mt7530_priv *priv; struct device_node *dn; @@ -39,7 +39,7 @@ Signed-off-by: David S. Miller dn = mdiodev->dev.of_node; -@@ -3221,6 +3216,12 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3246,6 +3241,12 @@ mt7530_probe(struct mdio_device *mdiodev if (IS_ERR(priv->regmap)) return PTR_ERR(priv->regmap); diff --git a/target/linux/generic/backport-5.15/790-v6.4-0006-net-dsa-mt7530-introduce-mutex-helpers.patch b/target/linux/generic/backport-5.15/790-v6.4-0006-net-dsa-mt7530-introduce-mutex-helpers.patch index c23f96e7a6605a..4d75c55647c150 100644 --- a/target/linux/generic/backport-5.15/790-v6.4-0006-net-dsa-mt7530-introduce-mutex-helpers.patch +++ b/target/linux/generic/backport-5.15/790-v6.4-0006-net-dsa-mt7530-introduce-mutex-helpers.patch @@ -214,7 +214,7 @@ Signed-off-by: David S. Miller return ret; } -@@ -1109,7 +1109,6 @@ static int +@@ -1117,7 +1117,6 @@ static int mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) { struct mt7530_priv *priv = ds->priv; @@ -222,7 +222,7 @@ Signed-off-by: David S. Miller int length; u32 val; -@@ -1120,7 +1119,7 @@ mt7530_port_change_mtu(struct dsa_switch +@@ -1128,7 +1127,7 @@ mt7530_port_change_mtu(struct dsa_switch if (!dsa_is_cpu_port(ds, port)) return 0; @@ -231,7 +231,7 @@ Signed-off-by: David S. Miller val = mt7530_mii_read(priv, MT7530_GMACCR); val &= ~MAX_RX_PKT_LEN_MASK; -@@ -1141,7 +1140,7 @@ mt7530_port_change_mtu(struct dsa_switch +@@ -1149,7 +1148,7 @@ mt7530_port_change_mtu(struct dsa_switch mt7530_mii_write(priv, MT7530_GMACCR, val); @@ -240,7 +240,7 @@ Signed-off-by: David S. Miller return 0; } -@@ -1937,10 +1936,10 @@ mt7530_irq_thread_fn(int irq, void *dev_ +@@ -1945,10 +1944,10 @@ mt7530_irq_thread_fn(int irq, void *dev_ u32 val; int p; @@ -253,7 +253,7 @@ Signed-off-by: David S. Miller for (p = 0; p < MT7530_NUM_PHYS; p++) { if (BIT(p) & val) { -@@ -1976,7 +1975,7 @@ mt7530_irq_bus_lock(struct irq_data *d) +@@ -1984,7 +1983,7 @@ mt7530_irq_bus_lock(struct irq_data *d) { struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); @@ -262,7 +262,7 @@ Signed-off-by: David S. Miller } static void -@@ -1985,7 +1984,7 @@ mt7530_irq_bus_sync_unlock(struct irq_da +@@ -1993,7 +1992,7 @@ mt7530_irq_bus_sync_unlock(struct irq_da struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); diff --git a/target/linux/generic/backport-5.15/790-v6.4-0008-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch b/target/linux/generic/backport-5.15/790-v6.4-0008-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch index 34a1bd7372d536..00dd91bbc957fb 100644 --- a/target/linux/generic/backport-5.15/790-v6.4-0008-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch +++ b/target/linux/generic/backport-5.15/790-v6.4-0008-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch @@ -17,7 +17,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3135,44 +3135,21 @@ static const struct of_device_id mt7530_ +@@ -3160,44 +3160,21 @@ static const struct of_device_id mt7530_ MODULE_DEVICE_TABLE(of, mt7530_of_match); static int @@ -67,7 +67,7 @@ Signed-off-by: David S. Miller if (!priv->info) return -EINVAL; -@@ -3186,23 +3163,53 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3211,23 +3188,53 @@ mt7530_probe(struct mdio_device *mdiodev return -EINVAL; priv->id = priv->info->id; @@ -131,7 +131,7 @@ Signed-off-by: David S. Miller priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", GPIOD_OUT_LOW); if (IS_ERR(priv->reset)) { -@@ -3211,12 +3218,15 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3236,12 +3243,15 @@ mt7530_probe(struct mdio_device *mdiodev } } diff --git a/target/linux/generic/backport-5.15/790-v6.4-0009-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch b/target/linux/generic/backport-5.15/790-v6.4-0009-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch index 2881365ec77d7b..be73b67c948ce5 100644 --- a/target/linux/generic/backport-5.15/790-v6.4-0009-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch +++ b/target/linux/generic/backport-5.15/790-v6.4-0009-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch @@ -17,7 +17,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3253,6 +3253,17 @@ mt7530_probe(struct mdio_device *mdiodev +@@ -3278,6 +3278,17 @@ mt7530_probe(struct mdio_device *mdiodev } static void @@ -35,7 +35,7 @@ Signed-off-by: David S. Miller mt7530_remove(struct mdio_device *mdiodev) { struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); -@@ -3271,16 +3282,11 @@ mt7530_remove(struct mdio_device *mdiode +@@ -3296,16 +3307,11 @@ mt7530_remove(struct mdio_device *mdiode dev_err(priv->dev, "Failed to disable io pwr: %d\n", ret); diff --git a/target/linux/generic/backport-5.15/790-v6.4-0011-net-dsa-mt7530-introduce-separate-MDIO-driver.patch b/target/linux/generic/backport-5.15/790-v6.4-0011-net-dsa-mt7530-introduce-separate-MDIO-driver.patch index 96afa041aad180..dfc061e054b50b 100644 --- a/target/linux/generic/backport-5.15/790-v6.4-0011-net-dsa-mt7530-introduce-separate-MDIO-driver.patch +++ b/target/linux/generic/backport-5.15/790-v6.4-0011-net-dsa-mt7530-introduce-separate-MDIO-driver.patch @@ -25,7 +25,7 @@ Signed-off-by: David S. Miller --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -11901,6 +11901,7 @@ M: Landen Chao L: netdev@vger.kernel.org S: Maintained @@ -68,8 +68,8 @@ Signed-off-by: David S. Miller obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o +obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o + obj-$(CONFIG_NET_DSA_QCA8K) += qca8k.o obj-$(CONFIG_NET_DSA_REALTEK_SMI) += realtek-smi.o - realtek-smi-objs := realtek-smi-core.o rtl8366.o rtl8366rb.o --- /dev/null +++ b/drivers/net/dsa/mt7530-mdio.c @@ -0,0 +1,271 @@ @@ -416,7 +416,7 @@ Signed-off-by: David S. Miller static u32 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) { -@@ -2944,72 +2895,6 @@ static const struct phylink_pcs_ops mt75 +@@ -2958,72 +2909,6 @@ static const struct phylink_pcs_ops mt75 .pcs_an_restart = mt7530_pcs_an_restart, }; @@ -489,7 +489,7 @@ Signed-off-by: David S. Miller static int mt753x_setup(struct dsa_switch *ds) { -@@ -3068,7 +2953,7 @@ static int mt753x_set_mac_eee(struct dsa +@@ -3082,7 +2967,7 @@ static int mt753x_set_mac_eee(struct dsa return 0; } @@ -498,7 +498,7 @@ Signed-off-by: David S. Miller .get_tag_protocol = mtk_get_tag_protocol, .setup = mt753x_setup, .get_strings = mt7530_get_strings, -@@ -3102,8 +2987,9 @@ static const struct dsa_switch_ops mt753 +@@ -3116,8 +3001,9 @@ static const struct dsa_switch_ops mt753 .get_mac_eee = mt753x_get_mac_eee, .set_mac_eee = mt753x_set_mac_eee, }; @@ -509,7 +509,7 @@ Signed-off-by: David S. Miller [ID_MT7621] = { .id = ID_MT7621, .pcs_ops = &mt7530_pcs_ops, -@@ -3136,16 +3022,9 @@ static const struct mt753x_info mt753x_t +@@ -3150,16 +3036,9 @@ static const struct mt753x_info mt753x_t .mac_port_config = mt7531_mac_config, }, }; @@ -528,7 +528,7 @@ Signed-off-by: David S. Miller mt7530_probe_common(struct mt7530_priv *priv) { struct device *dev = priv->dev; -@@ -3182,88 +3061,9 @@ mt7530_probe_common(struct mt7530_priv * +@@ -3196,88 +3075,9 @@ mt7530_probe_common(struct mt7530_priv * return 0; } @@ -619,7 +619,7 @@ Signed-off-by: David S. Miller mt7530_remove_common(struct mt7530_priv *priv) { if (priv->irq) -@@ -3274,57 +3074,6 @@ mt7530_remove_common(struct mt7530_priv +@@ -3288,57 +3088,6 @@ mt7530_remove_common(struct mt7530_priv mutex_destroy(&priv->reg_mutex); } diff --git a/target/linux/generic/backport-5.15/790-v6.4-0013-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch b/target/linux/generic/backport-5.15/790-v6.4-0013-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch index 8210aae27ce0c7..042ecdf766dd9f 100644 --- a/target/linux/generic/backport-5.15/790-v6.4-0013-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch +++ b/target/linux/generic/backport-5.15/790-v6.4-0013-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch @@ -28,7 +28,7 @@ Signed-off-by: David S. Miller --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -11899,9 +11899,11 @@ MEDIATEK SWITCH DRIVER +@@ -11893,9 +11893,11 @@ MEDIATEK SWITCH DRIVER M: Sean Wang M: Landen Chao M: DENG Qingfang @@ -76,8 +76,8 @@ Signed-off-by: David S. Miller obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o +obj-$(CONFIG_NET_DSA_MT7530_MMIO) += mt7530-mmio.o obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o + obj-$(CONFIG_NET_DSA_QCA8K) += qca8k.o obj-$(CONFIG_NET_DSA_REALTEK_SMI) += realtek-smi.o - realtek-smi-objs := realtek-smi-core.o rtl8366.o rtl8366rb.o --- /dev/null +++ b/drivers/net/dsa/mt7530-mmio.c @@ -0,0 +1,101 @@ @@ -184,7 +184,7 @@ Signed-off-by: David S. Miller +MODULE_LICENSE("GPL"); --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -1984,6 +1984,47 @@ static const struct irq_domain_ops mt753 +@@ -1992,6 +1992,47 @@ static const struct irq_domain_ops mt753 }; static void @@ -232,7 +232,7 @@ Signed-off-by: David S. Miller mt7530_setup_mdio_irq(struct mt7530_priv *priv) { struct dsa_switch *ds = priv->ds; -@@ -2017,8 +2058,15 @@ mt7530_setup_irq(struct mt7530_priv *pri +@@ -2025,8 +2066,15 @@ mt7530_setup_irq(struct mt7530_priv *pri return priv->irq ? : -EINVAL; } @@ -250,7 +250,7 @@ Signed-off-by: David S. Miller if (!priv->irq_domain) { dev_err(dev, "failed to create IRQ domain\n"); return -ENOMEM; -@@ -2507,6 +2555,25 @@ static void mt7531_mac_port_get_caps(str +@@ -2521,6 +2569,25 @@ static void mt7531_mac_port_get_caps(str } } @@ -276,7 +276,7 @@ Signed-off-by: David S. Miller static int mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) { -@@ -2583,6 +2650,17 @@ static bool mt753x_is_mac_port(u32 port) +@@ -2597,6 +2664,17 @@ static bool mt753x_is_mac_port(u32 port) } static int @@ -294,7 +294,7 @@ Signed-off-by: David S. Miller mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) { -@@ -2652,7 +2730,8 @@ mt753x_phylink_mac_config(struct dsa_swi +@@ -2666,7 +2744,8 @@ mt753x_phylink_mac_config(struct dsa_swi switch (port) { case 0 ... 4: /* Internal phy */ @@ -304,7 +304,7 @@ Signed-off-by: David S. Miller goto unsupported; break; case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ -@@ -2730,7 +2809,8 @@ static void mt753x_phylink_mac_link_up(s +@@ -2744,7 +2823,8 @@ static void mt753x_phylink_mac_link_up(s /* MT753x MAC works in 1G full duplex mode for all up-clocked * variants. */ @@ -314,7 +314,7 @@ Signed-off-by: David S. Miller (phy_interface_mode_is_8023z(interface))) { speed = SPEED_1000; duplex = DUPLEX_FULL; -@@ -2810,6 +2890,21 @@ mt7531_cpu_port_config(struct dsa_switch +@@ -2824,6 +2904,21 @@ mt7531_cpu_port_config(struct dsa_switch return 0; } @@ -336,7 +336,7 @@ Signed-off-by: David S. Miller static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, struct phylink_config *config) { -@@ -2955,6 +3050,27 @@ static int mt753x_set_mac_eee(struct dsa +@@ -2969,6 +3064,27 @@ static int mt753x_set_mac_eee(struct dsa return 0; } @@ -364,7 +364,7 @@ Signed-off-by: David S. Miller const struct dsa_switch_ops mt7530_switch_ops = { .get_tag_protocol = mtk_get_tag_protocol, .setup = mt753x_setup, -@@ -3023,6 +3139,17 @@ const struct mt753x_info mt753x_table[] +@@ -3037,6 +3153,17 @@ const struct mt753x_info mt753x_table[] .mac_port_get_caps = mt7531_mac_port_get_caps, .mac_port_config = mt7531_mac_config, }, diff --git a/target/linux/generic/backport-5.15/790-v6.4-0014-net-dsa-mt7530-fix-support-for-MT7531BE.patch b/target/linux/generic/backport-5.15/790-v6.4-0014-net-dsa-mt7530-fix-support-for-MT7531BE.patch index 5259730996d1c5..40e18167267d2d 100644 --- a/target/linux/generic/backport-5.15/790-v6.4-0014-net-dsa-mt7530-fix-support-for-MT7531BE.patch +++ b/target/linux/generic/backport-5.15/790-v6.4-0014-net-dsa-mt7530-fix-support-for-MT7531BE.patch @@ -73,7 +73,7 @@ Signed-off-by: Jakub Kicinski } --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -3017,6 +3017,12 @@ mt753x_setup(struct dsa_switch *ds) +@@ -3031,6 +3031,12 @@ mt753x_setup(struct dsa_switch *ds) if (ret && priv->irq) mt7530_free_irq_common(priv); diff --git a/target/linux/generic/backport-5.15/795-v6.3-01-r8152-add-USB-device-driver-for-config-selection.patch b/target/linux/generic/backport-5.15/795-v6.3-01-r8152-add-USB-device-driver-for-config-selection.patch deleted file mode 100644 index 38ddcb5714cbe5..00000000000000 --- a/target/linux/generic/backport-5.15/795-v6.3-01-r8152-add-USB-device-driver-for-config-selection.patch +++ /dev/null @@ -1,229 +0,0 @@ -From ec51fbd1b8a2bca2948dede99c14ec63dc57ff6b Mon Sep 17 00:00:00 2001 -From: Bjørn Mork -Date: Fri, 6 Jan 2023 17:07:38 +0100 -Subject: [PATCH] r8152: add USB device driver for config selection -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Subclassing the generic USB device driver to override the -default configuration selection regardless of matching interface -drivers. - -The r815x family devices expose a vendor specific function which -the r8152 interface driver wants to handle. This is the preferred -device mode. Additionally one or more USB class functions are -usually supported for hosts lacking a vendor specific driver. The -choice is USB configuration based, with one alternate function per -configuration. - -Example device with both NCM and ECM alternate cfgs: - -T: Bus=02 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#= 4 Spd=5000 MxCh= 0 -D: Ver= 3.20 Cls=00(>ifc ) Sub=00 Prot=00 MxPS= 9 #Cfgs= 3 -P: Vendor=0bda ProdID=8156 Rev=31.00 -S: Manufacturer=Realtek -S: Product=USB 10/100/1G/2.5G LAN -S: SerialNumber=001000001 -C:* #Ifs= 1 Cfg#= 1 Atr=a0 MxPwr=256mA -I:* If#= 0 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=00 Driver=r8152 -E: Ad=81(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms -E: Ad=02(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms -E: Ad=83(I) Atr=03(Int.) MxPS= 2 Ivl=128ms -C: #Ifs= 2 Cfg#= 2 Atr=a0 MxPwr=256mA -I: If#= 0 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=0d Prot=00 Driver= -E: Ad=83(I) Atr=03(Int.) MxPS= 16 Ivl=128ms -I: If#= 1 Alt= 0 #EPs= 0 Cls=0a(data ) Sub=00 Prot=01 Driver= -I: If#= 1 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=01 Driver= -E: Ad=81(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms -E: Ad=02(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms -C: #Ifs= 2 Cfg#= 3 Atr=a0 MxPwr=256mA -I: If#= 0 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=06 Prot=00 Driver= -E: Ad=83(I) Atr=03(Int.) MxPS= 16 Ivl=128ms -I: If#= 1 Alt= 0 #EPs= 0 Cls=0a(data ) Sub=00 Prot=00 Driver= -I: If#= 1 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=00 Driver= -E: Ad=81(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms -E: Ad=02(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms - -A problem with this is that Linux will prefer class functions over -vendor specific functions. Using the above example, Linux defaults -to cfg #2, running the device in a sub-optimal NCM mode. - -Previously we've attempted to work around the problem by -blacklisting the devices in the ECM class driver "cdc_ether", and -matching on the ECM class function in the vendor specific interface -driver. The latter has been used to switch back to the vendor -specific configuration when the driver is probed for a class -function. - -This workaround has several issues; -- class driver blacklists is additional maintanence cruft in an - unrelated driver -- class driver blacklists prevents users from optionally running - the devices in class mode -- each device needs double match entries in the vendor driver -- the initial probing as a class function slows down device - discovery - -Now these issues have become even worse with the introduction of -firmware supporting both NCM and ECM, where NCM ends up as the -default mode in Linux. To use the same workaround, we now have -to blacklist the devices in to two different class drivers and -add yet another match entry to the vendor specific driver. - -This patch implements an alternative workaround strategy - -independent of the interface drivers. It avoids adding a -blacklist to the cdc_ncm driver and will let us remove the -existing blacklist from the cdc_ether driver. - -As an additional bonus, removing the blacklists allow users to -select one of the other device modes if wanted. - -Signed-off-by: Bjørn Mork -Signed-off-by: David S. Miller ---- - drivers/net/usb/r8152.c | 113 ++++++++++++++++++++++++++++------------ - 1 file changed, 81 insertions(+), 32 deletions(-) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -9625,6 +9625,9 @@ static int rtl8152_probe(struct usb_inte - if (version == RTL_VER_UNKNOWN) - return -ENODEV; - -+ if (intf->cur_altsetting->desc.bInterfaceClass != USB_CLASS_VENDOR_SPEC) -+ return -ENODEV; -+ - if (!rtl_vendor_mode(intf)) - return -ENODEV; - -@@ -9834,43 +9837,35 @@ static void rtl8152_disconnect(struct us - } - } - --#define REALTEK_USB_DEVICE(vend, prod) { \ -- USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC), \ --}, \ --{ \ -- USB_DEVICE_AND_INTERFACE_INFO(vend, prod, USB_CLASS_COMM, \ -- USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE), \ --} - - /* table of devices that work with this driver */ - static const struct usb_device_id rtl8152_table[] = { - /* Realtek */ -- REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050), -- REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8053), -- REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152), -- REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153), -- REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8155), -- REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8156), -+ { USB_DEVICE(VENDOR_ID_REALTEK, 0x8050) }, -+ { USB_DEVICE(VENDOR_ID_REALTEK, 0x8053) }, -+ { USB_DEVICE(VENDOR_ID_REALTEK, 0x8152) }, -+ { USB_DEVICE(VENDOR_ID_REALTEK, 0x8153) }, -+ { USB_DEVICE(VENDOR_ID_REALTEK, 0x8155) }, -+ { USB_DEVICE(VENDOR_ID_REALTEK, 0x8156) }, - - /* Microsoft */ -- REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab), -- REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6), -- REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927), -- REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0c5e), -- REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101), -- REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f), -- REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3054), -- REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062), -- REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069), -- REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3082), -- REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205), -- REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c), -- REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214), -- REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x721e), -- REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0xa387), -- REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041), -- REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff), -- REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601), -+ { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab) }, -+ { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6) }, -+ { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927) }, -+ { USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101) }, -+ { USB_DEVICE(VENDOR_ID_LENOVO, 0x304f) }, -+ { USB_DEVICE(VENDOR_ID_LENOVO, 0x3054) }, -+ { USB_DEVICE(VENDOR_ID_LENOVO, 0x3062) }, -+ { USB_DEVICE(VENDOR_ID_LENOVO, 0x3069) }, -+ { USB_DEVICE(VENDOR_ID_LENOVO, 0x3082) }, -+ { USB_DEVICE(VENDOR_ID_LENOVO, 0x7205) }, -+ { USB_DEVICE(VENDOR_ID_LENOVO, 0x720c) }, -+ { USB_DEVICE(VENDOR_ID_LENOVO, 0x7214) }, -+ { USB_DEVICE(VENDOR_ID_LENOVO, 0x721e) }, -+ { USB_DEVICE(VENDOR_ID_LENOVO, 0xa387) }, -+ { USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041) }, -+ { USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff) }, -+ { USB_DEVICE(VENDOR_ID_TPLINK, 0x0601) }, - {} - }; - -@@ -9890,7 +9885,61 @@ static struct usb_driver rtl8152_driver - .disable_hub_initiated_lpm = 1, - }; - --module_usb_driver(rtl8152_driver); -+static int rtl8152_cfgselector_probe(struct usb_device *udev) -+{ -+ struct usb_host_config *c; -+ int i, num_configs; -+ -+ /* The vendor mode is not always config #1, so to find it out. */ -+ c = udev->config; -+ num_configs = udev->descriptor.bNumConfigurations; -+ for (i = 0; i < num_configs; (i++, c++)) { -+ struct usb_interface_descriptor *desc = NULL; -+ -+ if (!c->desc.bNumInterfaces) -+ continue; -+ desc = &c->intf_cache[0]->altsetting->desc; -+ if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC) -+ break; -+ } -+ -+ if (i == num_configs) -+ return -ENODEV; -+ -+ if (usb_set_configuration(udev, c->desc.bConfigurationValue)) { -+ dev_err(&udev->dev, "Failed to set configuration %d\n", -+ c->desc.bConfigurationValue); -+ return -ENODEV; -+ } -+ -+ return 0; -+} -+ -+static struct usb_device_driver rtl8152_cfgselector_driver = { -+ .name = MODULENAME "-cfgselector", -+ .probe = rtl8152_cfgselector_probe, -+ .id_table = rtl8152_table, -+ .generic_subclass = 1, -+}; -+ -+static int __init rtl8152_driver_init(void) -+{ -+ int ret; -+ -+ ret = usb_register_device_driver(&rtl8152_cfgselector_driver, THIS_MODULE); -+ if (ret) -+ return ret; -+ return usb_register(&rtl8152_driver); -+} -+ -+static void __exit rtl8152_driver_exit(void) -+{ -+ usb_deregister(&rtl8152_driver); -+ usb_deregister_device_driver(&rtl8152_cfgselector_driver); -+} -+ -+module_init(rtl8152_driver_init); -+module_exit(rtl8152_driver_exit); - - MODULE_AUTHOR(DRIVER_AUTHOR); - MODULE_DESCRIPTION(DRIVER_DESC); diff --git a/target/linux/generic/backport-5.15/795-v6.3-03-r8152-avoid-to-change-cfg-for-all-devices.patch b/target/linux/generic/backport-5.15/795-v6.3-03-r8152-avoid-to-change-cfg-for-all-devices.patch deleted file mode 100644 index 8bbf0be802be18..00000000000000 --- a/target/linux/generic/backport-5.15/795-v6.3-03-r8152-avoid-to-change-cfg-for-all-devices.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 0d4cda805a183bbe523f2407edb5c14ade50b841 Mon Sep 17 00:00:00 2001 -From: Hayes Wang -Date: Tue, 17 Jan 2023 11:03:44 +0800 -Subject: [PATCH] r8152: avoid to change cfg for all devices - -The rtl8152_cfgselector_probe() should set the USB configuration to the -vendor mode only for the devices which the driver (r8152) supports. -Otherwise, no driver would be used for such devices. - -Fixes: ec51fbd1b8a2 ("r8152: add USB device driver for config selection") -Signed-off-by: Hayes Wang -Reviewed-by: Simon Horman -Signed-off-by: David S. Miller ---- - drivers/net/usb/r8152.c | 20 +++++++++++++++++--- - 1 file changed, 17 insertions(+), 3 deletions(-) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -9531,9 +9531,8 @@ static int rtl_fw_init(struct r8152 *tp) - return 0; - } - --u8 rtl8152_get_version(struct usb_interface *intf) -+static u8 __rtl_get_hw_ver(struct usb_device *udev) - { -- struct usb_device *udev = interface_to_usbdev(intf); - u32 ocp_data = 0; - __le32 *tmp; - u8 version; -@@ -9603,10 +9602,19 @@ u8 rtl8152_get_version(struct usb_interf - break; - default: - version = RTL_VER_UNKNOWN; -- dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data); -+ dev_info(&udev->dev, "Unknown version 0x%04x\n", ocp_data); - break; - } - -+ return version; -+} -+ -+u8 rtl8152_get_version(struct usb_interface *intf) -+{ -+ u8 version; -+ -+ version = __rtl_get_hw_ver(interface_to_usbdev(intf)); -+ - dev_dbg(&intf->dev, "Detected version 0x%04x\n", version); - - return version; -@@ -9890,6 +9898,12 @@ static int rtl8152_cfgselector_probe(str - struct usb_host_config *c; - int i, num_configs; - -+ /* Switch the device to vendor mode, if and only if the vendor mode -+ * driver supports it. -+ */ -+ if (__rtl_get_hw_ver(udev) == RTL_VER_UNKNOWN) -+ return 0; -+ - /* The vendor mode is not always config #1, so to find it out. */ - c = udev->config; - num_configs = udev->descriptor.bNumConfigurations; diff --git a/target/linux/generic/backport-5.15/795-v6.3-04-r8152-remove-rtl_vendor_mode-function.patch b/target/linux/generic/backport-5.15/795-v6.3-04-r8152-remove-rtl_vendor_mode-function.patch deleted file mode 100644 index c9bd0df202fbf8..00000000000000 --- a/target/linux/generic/backport-5.15/795-v6.3-04-r8152-remove-rtl_vendor_mode-function.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 95a4c1d617b92cdc4522297741b56e8f6cd01a1e Mon Sep 17 00:00:00 2001 -From: Hayes Wang -Date: Thu, 19 Jan 2023 15:40:42 +0800 -Subject: [PATCH] r8152: remove rtl_vendor_mode function - -After commit ec51fbd1b8a2 ("r8152: add USB device driver for -config selection"), the code about changing USB configuration -in rtl_vendor_mode() wouldn't be run anymore. Therefore, the -function could be removed. - -Signed-off-by: Hayes Wang -Signed-off-by: Jakub Kicinski ---- - drivers/net/usb/r8152.c | 39 +-------------------------------------- - 1 file changed, 1 insertion(+), 38 deletions(-) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -8267,43 +8267,6 @@ static bool rtl_check_vendor_ok(struct u - return true; - } - --static bool rtl_vendor_mode(struct usb_interface *intf) --{ -- struct usb_host_interface *alt = intf->cur_altsetting; -- struct usb_device *udev; -- struct usb_host_config *c; -- int i, num_configs; -- -- if (alt->desc.bInterfaceClass == USB_CLASS_VENDOR_SPEC) -- return rtl_check_vendor_ok(intf); -- -- /* The vendor mode is not always config #1, so to find it out. */ -- udev = interface_to_usbdev(intf); -- c = udev->config; -- num_configs = udev->descriptor.bNumConfigurations; -- if (num_configs < 2) -- return false; -- -- for (i = 0; i < num_configs; (i++, c++)) { -- struct usb_interface_descriptor *desc = NULL; -- -- if (c->desc.bNumInterfaces > 0) -- desc = &c->intf_cache[0]->altsetting->desc; -- else -- continue; -- -- if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC) { -- usb_driver_set_configuration(udev, c->desc.bConfigurationValue); -- break; -- } -- } -- -- if (i == num_configs) -- dev_err(&intf->dev, "Unexpected Device\n"); -- -- return false; --} -- - static int rtl8152_pre_reset(struct usb_interface *intf) - { - struct r8152 *tp = usb_get_intfdata(intf); -@@ -9636,7 +9599,7 @@ static int rtl8152_probe(struct usb_inte - if (intf->cur_altsetting->desc.bInterfaceClass != USB_CLASS_VENDOR_SPEC) - return -ENODEV; - -- if (!rtl_vendor_mode(intf)) -+ if (!rtl_check_vendor_ok(intf)) - return -ENODEV; - - usb_reset_device(udev); diff --git a/target/linux/generic/backport-5.15/795-v6.3-05-r8152-reduce-the-control-transfer-of-rtl8152_get_ver.patch b/target/linux/generic/backport-5.15/795-v6.3-05-r8152-reduce-the-control-transfer-of-rtl8152_get_ver.patch index 7d1053aea5a960..482c6c6f133b40 100644 --- a/target/linux/generic/backport-5.15/795-v6.3-05-r8152-reduce-the-control-transfer-of-rtl8152_get_ver.patch +++ b/target/linux/generic/backport-5.15/795-v6.3-05-r8152-reduce-the-control-transfer-of-rtl8152_get_ver.patch @@ -18,7 +18,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c -@@ -9588,20 +9588,21 @@ static int rtl8152_probe(struct usb_inte +@@ -9602,20 +9602,21 @@ static int rtl8152_probe(struct usb_inte const struct usb_device_id *id) { struct usb_device *udev = interface_to_usbdev(intf); diff --git a/target/linux/generic/backport-5.15/795-v6.4-07-r8152-fix-the-autosuspend-doesn-t-work.patch b/target/linux/generic/backport-5.15/795-v6.4-07-r8152-fix-the-autosuspend-doesn-t-work.patch deleted file mode 100644 index df881e26083933..00000000000000 --- a/target/linux/generic/backport-5.15/795-v6.4-07-r8152-fix-the-autosuspend-doesn-t-work.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 0fbd79c01a9a657348f7032df70c57a406468c86 Mon Sep 17 00:00:00 2001 -From: Hayes Wang -Date: Tue, 2 May 2023 11:36:27 +0800 -Subject: [PATCH] r8152: fix the autosuspend doesn't work - -Set supports_autosuspend = 1 for the rtl8152_cfgselector_driver. - -Fixes: ec51fbd1b8a2 ("r8152: add USB device driver for config selection") -Signed-off-by: Hayes Wang -Signed-off-by: David S. Miller ---- - drivers/net/usb/r8152.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -9898,6 +9898,7 @@ static struct usb_device_driver rtl8152_ - .probe = rtl8152_cfgselector_probe, - .id_table = rtl8152_table, - .generic_subclass = 1, -+ .supports_autosuspend = 1, - }; - - static int __init rtl8152_driver_init(void) diff --git a/target/linux/generic/backport-5.15/795-v6.6-09-r8152-set-bp-in-bulk.patch b/target/linux/generic/backport-5.15/795-v6.6-09-r8152-set-bp-in-bulk.patch index cfc31daf12628c..6c7efd7f2bcdb0 100644 --- a/target/linux/generic/backport-5.15/795-v6.6-09-r8152-set-bp-in-bulk.patch +++ b/target/linux/generic/backport-5.15/795-v6.6-09-r8152-set-bp-in-bulk.patch @@ -15,7 +15,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c -@@ -3977,29 +3977,10 @@ static void rtl_reset_bmu(struct r8152 * +@@ -3983,29 +3983,10 @@ static void rtl_reset_bmu(struct r8152 * /* Clear the bp to stop the firmware before loading a new one */ static void rtl_clear_bp(struct r8152 *tp, u16 type) { @@ -48,7 +48,7 @@ Signed-off-by: Jakub Kicinski case RTL_VER_08: case RTL_VER_09: case RTL_VER_10: -@@ -4007,32 +3988,31 @@ static void rtl_clear_bp(struct r8152 *t +@@ -4013,32 +3994,31 @@ static void rtl_clear_bp(struct r8152 *t case RTL_VER_12: case RTL_VER_13: case RTL_VER_15: @@ -100,7 +100,7 @@ Signed-off-by: Jakub Kicinski /* wait 3 ms to make sure the firmware is stopped */ usleep_range(3000, 6000); -@@ -5009,10 +4989,9 @@ static void rtl8152_fw_phy_nc_apply(stru +@@ -5015,10 +4995,9 @@ static void rtl8152_fw_phy_nc_apply(stru static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac) { @@ -112,7 +112,7 @@ Signed-off-by: Jakub Kicinski switch (__le32_to_cpu(mac->blk_hdr.type)) { case RTL_FW_PLA: -@@ -5054,12 +5033,8 @@ static void rtl8152_fw_mac_apply(struct +@@ -5060,12 +5039,8 @@ static void rtl8152_fw_mac_apply(struct ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr), __le16_to_cpu(mac->bp_ba_value)); diff --git a/target/linux/generic/backport-5.15/795-v6.6-11-r8152-add-vendor-device-ID-pair-for-D-Link-DUB-E250.patch b/target/linux/generic/backport-5.15/795-v6.6-11-r8152-add-vendor-device-ID-pair-for-D-Link-DUB-E250.patch deleted file mode 100644 index 4d1b177ff204c4..00000000000000 --- a/target/linux/generic/backport-5.15/795-v6.6-11-r8152-add-vendor-device-ID-pair-for-D-Link-DUB-E250.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 72f93a3136ee18fd59fa6579f84c07e93424681e Mon Sep 17 00:00:00 2001 -From: Antonio Napolitano -Date: Sat, 26 Aug 2023 01:05:50 +0200 -Subject: [PATCH] r8152: add vendor/device ID pair for D-Link DUB-E250 - -The D-Link DUB-E250 is an RTL8156 based 2.5G Ethernet controller. - -Add the vendor and product ID values to the driver. This makes Ethernet -work with the adapter. - -Signed-off-by: Antonio Napolitano -Link: https://lore.kernel.org/r/CV200KJEEUPC.WPKAHXCQJ05I@mercurius -Signed-off-by: Jakub Kicinski ---- - drivers/net/usb/r8152.c | 1 + - include/linux/usb/r8152.h | 1 + - 2 files changed, 2 insertions(+) - - ---- a/include/linux/usb/r8152.h -+++ b/include/linux/usb/r8152.h -@@ -29,6 +29,7 @@ - #define VENDOR_ID_LINKSYS 0x13b1 - #define VENDOR_ID_NVIDIA 0x0955 - #define VENDOR_ID_TPLINK 0x2357 -+#define VENDOR_ID_DLINK 0x2001 - - #if IS_REACHABLE(CONFIG_USB_RTL8152) - extern u8 rtl8152_get_version(struct usb_interface *intf); ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -9820,6 +9820,7 @@ static const struct usb_device_id rtl815 - { USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041) }, - { USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff) }, - { USB_DEVICE(VENDOR_ID_TPLINK, 0x0601) }, -+ { USB_DEVICE(VENDOR_ID_DLINK, 0xb301) }, - {} - }; - diff --git a/target/linux/generic/backport-5.15/795-v6.6-12-r8152-Rename-RTL8152_UNPLUG-to-RTL8152_INACCESSIBLE.patch b/target/linux/generic/backport-5.15/795-v6.6-12-r8152-Rename-RTL8152_UNPLUG-to-RTL8152_INACCESSIBLE.patch deleted file mode 100644 index 4f0e0e1c658130..00000000000000 --- a/target/linux/generic/backport-5.15/795-v6.6-12-r8152-Rename-RTL8152_UNPLUG-to-RTL8152_INACCESSIBLE.patch +++ /dev/null @@ -1,447 +0,0 @@ -From 715f67f33af45ce2cc3a5b1ef133cc8c8e7787b0 Mon Sep 17 00:00:00 2001 -From: Douglas Anderson -Date: Fri, 20 Oct 2023 14:06:58 -0700 -Subject: [PATCH] r8152: Rename RTL8152_UNPLUG to RTL8152_INACCESSIBLE - -Whenever the RTL8152_UNPLUG is set that just tells the driver that all -accesses will fail and we should just immediately bail. A future patch -will use this same concept at a time when the driver hasn't actually -been unplugged but is about to be reset. Rename the flag in -preparation for the future patch. - -This is a no-op change and just a search and replace. - -Signed-off-by: Douglas Anderson -Reviewed-by: Grant Grundler -Signed-off-by: David S. Miller ---- - drivers/net/usb/r8152.c | 96 ++++++++++++++++++++--------------------- - 1 file changed, 48 insertions(+), 48 deletions(-) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -763,7 +763,7 @@ enum rtl_register_content { - - /* rtl8152 flags */ - enum rtl8152_flags { -- RTL8152_UNPLUG = 0, -+ RTL8152_INACCESSIBLE = 0, - RTL8152_SET_RX_MODE, - WORK_ENABLE, - RTL8152_LINK_CHG, -@@ -1241,7 +1241,7 @@ int set_registers(struct r8152 *tp, u16 - static void rtl_set_unplug(struct r8152 *tp) - { - if (tp->udev->state == USB_STATE_NOTATTACHED) { -- set_bit(RTL8152_UNPLUG, &tp->flags); -+ set_bit(RTL8152_INACCESSIBLE, &tp->flags); - smp_mb__after_atomic(); - } - } -@@ -1252,7 +1252,7 @@ static int generic_ocp_read(struct r8152 - u16 limit = 64; - int ret = 0; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return -ENODEV; - - /* both size and indix must be 4 bytes align */ -@@ -1296,7 +1296,7 @@ static int generic_ocp_write(struct r815 - u16 byteen_start, byteen_end, byen; - u16 limit = 512; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return -ENODEV; - - /* both size and indix must be 4 bytes align */ -@@ -1533,7 +1533,7 @@ static int read_mii_word(struct net_devi - struct r8152 *tp = netdev_priv(netdev); - int ret; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return -ENODEV; - - if (phy_id != R8152_PHY_ID) -@@ -1549,7 +1549,7 @@ void write_mii_word(struct net_device *n - { - struct r8152 *tp = netdev_priv(netdev); - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - if (phy_id != R8152_PHY_ID) -@@ -1754,7 +1754,7 @@ static void read_bulk_callback(struct ur - if (!tp) - return; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - if (!test_bit(WORK_ENABLE, &tp->flags)) -@@ -1846,7 +1846,7 @@ static void write_bulk_callback(struct u - if (!test_bit(WORK_ENABLE, &tp->flags)) - return; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - if (!skb_queue_empty(&tp->tx_queue)) -@@ -1867,7 +1867,7 @@ static void intr_callback(struct urb *ur - if (!test_bit(WORK_ENABLE, &tp->flags)) - return; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - switch (status) { -@@ -2611,7 +2611,7 @@ static void bottom_half(struct tasklet_s - { - struct r8152 *tp = from_tasklet(tp, t, tx_tl); - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - if (!test_bit(WORK_ENABLE, &tp->flags)) -@@ -2654,7 +2654,7 @@ int r8152_submit_rx(struct r8152 *tp, st - int ret; - - /* The rx would be stopped, so skip submitting */ -- if (test_bit(RTL8152_UNPLUG, &tp->flags) || -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) || - !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) - return 0; - -@@ -3050,7 +3050,7 @@ static int rtl_enable(struct r8152 *tp) - - static int rtl8152_enable(struct r8152 *tp) - { -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return -ENODEV; - - set_tx_qlen(tp); -@@ -3137,7 +3137,7 @@ static int rtl8153_enable(struct r8152 * - { - u32 ocp_data; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return -ENODEV; - - set_tx_qlen(tp); -@@ -3169,7 +3169,7 @@ static void rtl_disable(struct r8152 *tp - u32 ocp_data; - int i; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) { -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { - rtl_drop_queued_tx(tp); - return; - } -@@ -3623,7 +3623,7 @@ static u16 r8153_phy_status(struct r8152 - } - - msleep(20); -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - break; - } - -@@ -3655,7 +3655,7 @@ static void r8153b_ups_en(struct r8152 * - int i; - - for (i = 0; i < 500; i++) { -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & - AUTOLOAD_DONE) -@@ -3697,7 +3697,7 @@ static void r8153c_ups_en(struct r8152 * - int i; - - for (i = 0; i < 500; i++) { -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & - AUTOLOAD_DONE) -@@ -4042,8 +4042,8 @@ static int rtl_phy_patch_request(struct - for (i = 0; wait && i < 5000; i++) { - u32 ocp_data; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -- break; -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) -+ return -ENODEV; - - usleep_range(1000, 2000); - ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT); -@@ -6001,7 +6001,7 @@ static int rtl8156_enable(struct r8152 * - u32 ocp_data; - u16 speed; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return -ENODEV; - - r8156_fc_parameter(tp); -@@ -6059,7 +6059,7 @@ static int rtl8156b_enable(struct r8152 - u32 ocp_data; - u16 speed; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return -ENODEV; - - set_tx_qlen(tp); -@@ -6245,7 +6245,7 @@ out: - - static void rtl8152_up(struct r8152 *tp) - { -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - r8152_aldps_en(tp, false); -@@ -6255,7 +6255,7 @@ static void rtl8152_up(struct r8152 *tp) - - static void rtl8152_down(struct r8152 *tp) - { -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) { -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { - rtl_drop_queued_tx(tp); - return; - } -@@ -6270,7 +6270,7 @@ static void rtl8153_up(struct r8152 *tp) - { - u32 ocp_data; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - r8153_u1u2en(tp, false); -@@ -6310,7 +6310,7 @@ static void rtl8153_down(struct r8152 *t - { - u32 ocp_data; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) { -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { - rtl_drop_queued_tx(tp); - return; - } -@@ -6331,7 +6331,7 @@ static void rtl8153b_up(struct r8152 *tp - { - u32 ocp_data; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - r8153b_u1u2en(tp, false); -@@ -6355,7 +6355,7 @@ static void rtl8153b_down(struct r8152 * - { - u32 ocp_data; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) { -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { - rtl_drop_queued_tx(tp); - return; - } -@@ -6392,7 +6392,7 @@ static void rtl8153c_up(struct r8152 *tp - { - u32 ocp_data; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - r8153b_u1u2en(tp, false); -@@ -6473,7 +6473,7 @@ static void rtl8156_up(struct r8152 *tp) - { - u32 ocp_data; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - r8153b_u1u2en(tp, false); -@@ -6546,7 +6546,7 @@ static void rtl8156_down(struct r8152 *t - { - u32 ocp_data; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) { -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { - rtl_drop_queued_tx(tp); - return; - } -@@ -6684,7 +6684,7 @@ static void rtl_work_func_t(struct work_ - /* If the device is unplugged or !netif_running(), the workqueue - * doesn't need to wake the device, and could return directly. - */ -- if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) || !netif_running(tp->netdev)) - return; - - if (usb_autopm_get_interface(tp->intf) < 0) -@@ -6723,7 +6723,7 @@ static void rtl_hw_phy_work_func_t(struc - { - struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work); - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - if (usb_autopm_get_interface(tp->intf) < 0) -@@ -6850,7 +6850,7 @@ static int rtl8152_close(struct net_devi - netif_stop_queue(netdev); - - res = usb_autopm_get_interface(tp->intf); -- if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { -+ if (res < 0 || test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { - rtl_drop_queued_tx(tp); - rtl_stop_rx(tp); - } else { -@@ -6883,7 +6883,7 @@ static void r8152b_init(struct r8152 *tp - u32 ocp_data; - u16 data; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - data = r8152_mdio_read(tp, MII_BMCR); -@@ -6927,7 +6927,7 @@ static void r8153_init(struct r8152 *tp) - u16 data; - int i; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - r8153_u1u2en(tp, false); -@@ -6938,7 +6938,7 @@ static void r8153_init(struct r8152 *tp) - break; - - msleep(20); -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - break; - } - -@@ -7067,7 +7067,7 @@ static void r8153b_init(struct r8152 *tp - u16 data; - int i; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - r8153b_u1u2en(tp, false); -@@ -7078,7 +7078,7 @@ static void r8153b_init(struct r8152 *tp - break; - - msleep(20); -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - break; - } - -@@ -7149,7 +7149,7 @@ static void r8153c_init(struct r8152 *tp - u16 data; - int i; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - r8153b_u1u2en(tp, false); -@@ -7169,7 +7169,7 @@ static void r8153c_init(struct r8152 *tp - break; - - msleep(20); -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - } - -@@ -7998,7 +7998,7 @@ static void r8156_init(struct r8152 *tp) - u16 data; - int i; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP); -@@ -8019,7 +8019,7 @@ static void r8156_init(struct r8152 *tp) - break; - - msleep(20); -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - } - -@@ -8094,7 +8094,7 @@ static void r8156b_init(struct r8152 *tp - u16 data; - int i; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP); -@@ -8128,7 +8128,7 @@ static void r8156b_init(struct r8152 *tp - break; - - msleep(20); -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - } - -@@ -9153,7 +9153,7 @@ static int rtl8152_ioctl(struct net_devi - struct mii_ioctl_data *data = if_mii(rq); - int res; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return -ENODEV; - - res = usb_autopm_get_interface(tp->intf); -@@ -9255,7 +9255,7 @@ static const struct net_device_ops rtl81 - - static void rtl8152_unload(struct r8152 *tp) - { -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - if (tp->version != RTL_VER_01) -@@ -9264,7 +9264,7 @@ static void rtl8152_unload(struct r8152 - - static void rtl8153_unload(struct r8152 *tp) - { -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - r8153_power_cut_en(tp, false); -@@ -9272,7 +9272,7 @@ static void rtl8153_unload(struct r8152 - - static void rtl8153b_unload(struct r8152 *tp) - { -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - r8153b_power_cut_en(tp, false); diff --git a/target/linux/generic/backport-5.15/795-v6.6-13-r8152-Block-future-register-access-if-register-acces.patch b/target/linux/generic/backport-5.15/795-v6.6-13-r8152-Block-future-register-access-if-register-acces.patch index 0ce8206657a8e2..3ef8f379119639 100644 --- a/target/linux/generic/backport-5.15/795-v6.6-13-r8152-Block-future-register-access-if-register-acces.patch +++ b/target/linux/generic/backport-5.15/795-v6.6-13-r8152-Block-future-register-access-if-register-acces.patch @@ -232,7 +232,7 @@ Signed-off-by: David S. Miller } static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, -@@ -8254,7 +8348,7 @@ static int rtl8152_pre_reset(struct usb_ +@@ -8268,7 +8362,7 @@ static int rtl8152_pre_reset(struct usb_ struct r8152 *tp = usb_get_intfdata(intf); struct net_device *netdev; @@ -241,7 +241,7 @@ Signed-off-by: David S. Miller return 0; netdev = tp->netdev; -@@ -8269,7 +8363,9 @@ static int rtl8152_pre_reset(struct usb_ +@@ -8283,7 +8377,9 @@ static int rtl8152_pre_reset(struct usb_ napi_disable(&tp->napi); if (netif_carrier_ok(netdev)) { mutex_lock(&tp->control); @@ -251,7 +251,7 @@ Signed-off-by: David S. Miller mutex_unlock(&tp->control); } -@@ -8282,9 +8378,11 @@ static int rtl8152_post_reset(struct usb +@@ -8296,9 +8392,11 @@ static int rtl8152_post_reset(struct usb struct net_device *netdev; struct sockaddr sa; @@ -264,7 +264,7 @@ Signed-off-by: David S. Miller /* reset the MAC address in case of policy change */ if (determine_ethernet_addr(tp, &sa) >= 0) { rtnl_lock(); -@@ -9482,17 +9580,29 @@ static u8 __rtl_get_hw_ver(struct usb_de +@@ -9496,17 +9594,29 @@ static u8 __rtl_get_hw_ver(struct usb_de __le32 *tmp; u8 version; int ret; @@ -300,7 +300,7 @@ Signed-off-by: David S. Miller kfree(tmp); -@@ -9566,25 +9676,14 @@ u8 rtl8152_get_version(struct usb_interf +@@ -9580,25 +9690,14 @@ u8 rtl8152_get_version(struct usb_interf } EXPORT_SYMBOL_GPL(rtl8152_get_version); @@ -328,7 +328,7 @@ Signed-off-by: David S. Miller usb_reset_device(udev); netdev = alloc_etherdev(sizeof(struct r8152)); if (!netdev) { -@@ -9757,10 +9856,20 @@ static int rtl8152_probe(struct usb_inte +@@ -9771,10 +9870,20 @@ static int rtl8152_probe(struct usb_inte else device_set_wakeup_enable(&udev->dev, false); @@ -349,7 +349,7 @@ Signed-off-by: David S. Miller out1: tasklet_kill(&tp->tx_tl); cancel_delayed_work_sync(&tp->hw_phy_work); -@@ -9769,10 +9878,46 @@ out1: +@@ -9783,10 +9892,46 @@ out1: rtl8152_release_firmware(tp); usb_set_intfdata(intf, NULL); out: diff --git a/target/linux/generic/backport-5.15/810-v5.17-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch b/target/linux/generic/backport-5.15/810-v5.17-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch index 41d3e121de195f..dbd734e9cf43d5 100644 --- a/target/linux/generic/backport-5.15/810-v5.17-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch +++ b/target/linux/generic/backport-5.15/810-v5.17-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch @@ -49,7 +49,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/usb/qmi_wwan.c +++ b/drivers/net/usb/qmi_wwan.c -@@ -1316,6 +1316,7 @@ static const struct usb_device_id produc +@@ -1317,6 +1317,7 @@ static const struct usb_device_id produc {QMI_FIXED_INTF(0x19d2, 0x1426, 2)}, /* ZTE MF91 */ {QMI_FIXED_INTF(0x19d2, 0x1428, 2)}, /* Telewell TW-LTE 4G v2 */ {QMI_FIXED_INTF(0x19d2, 0x1432, 3)}, /* ZTE ME3620 */ diff --git a/target/linux/generic/backport-5.15/821-v5.16-Bluetooth-btusb-Support-public-address-configuration.patch b/target/linux/generic/backport-5.15/821-v5.16-Bluetooth-btusb-Support-public-address-configuration.patch index b23f9a4b9e2205..725af4b52cf179 100644 --- a/target/linux/generic/backport-5.15/821-v5.16-Bluetooth-btusb-Support-public-address-configuration.patch +++ b/target/linux/generic/backport-5.15/821-v5.16-Bluetooth-btusb-Support-public-address-configuration.patch @@ -17,7 +17,7 @@ Signed-off-by: Marcel Holtmann --- a/drivers/bluetooth/btusb.c +++ b/drivers/bluetooth/btusb.c -@@ -2275,6 +2275,23 @@ struct btmtk_section_map { +@@ -2287,6 +2287,23 @@ struct btmtk_section_map { }; } __packed; @@ -41,7 +41,7 @@ Signed-off-by: Marcel Holtmann static void btusb_mtk_wmt_recv(struct urb *urb) { struct hci_dev *hdev = urb->context; -@@ -3926,6 +3943,7 @@ static int btusb_probe(struct usb_interf +@@ -3941,6 +3958,7 @@ static int btusb_probe(struct usb_interf hdev->shutdown = btusb_mtk_shutdown; hdev->manufacturer = 70; hdev->cmd_timeout = btusb_mtk_cmd_timeout; diff --git a/target/linux/generic/backport-5.15/822-v5.17-Bluetooth-btusb-Fix-application-of-sizeof-to-pointer.patch b/target/linux/generic/backport-5.15/822-v5.17-Bluetooth-btusb-Fix-application-of-sizeof-to-pointer.patch index 6fe61a9defecd6..d72866eabf1490 100644 --- a/target/linux/generic/backport-5.15/822-v5.17-Bluetooth-btusb-Fix-application-of-sizeof-to-pointer.patch +++ b/target/linux/generic/backport-5.15/822-v5.17-Bluetooth-btusb-Fix-application-of-sizeof-to-pointer.patch @@ -18,7 +18,7 @@ Signed-off-by: Marcel Holtmann --- a/drivers/bluetooth/btusb.c +++ b/drivers/bluetooth/btusb.c -@@ -2280,7 +2280,7 @@ static int btusb_set_bdaddr_mtk(struct h +@@ -2292,7 +2292,7 @@ static int btusb_set_bdaddr_mtk(struct h struct sk_buff *skb; long ret; diff --git a/target/linux/generic/backport-5.15/823-v5.18-Bluetooth-btusb-Add-a-new-PID-VID-13d3-3567-for-MT79.patch b/target/linux/generic/backport-5.15/823-v5.18-Bluetooth-btusb-Add-a-new-PID-VID-13d3-3567-for-MT79.patch index d670195da1f2fa..ebb6cc471768e5 100644 --- a/target/linux/generic/backport-5.15/823-v5.18-Bluetooth-btusb-Add-a-new-PID-VID-13d3-3567-for-MT79.patch +++ b/target/linux/generic/backport-5.15/823-v5.18-Bluetooth-btusb-Add-a-new-PID-VID-13d3-3567-for-MT79.patch @@ -58,7 +58,7 @@ Signed-off-by: Marcel Holtmann --- a/drivers/bluetooth/btusb.c +++ b/drivers/bluetooth/btusb.c -@@ -464,6 +464,9 @@ static const struct usb_device_id blackl +@@ -476,6 +476,9 @@ static const struct usb_device_id blackl { USB_DEVICE(0x13d3, 0x3564), .driver_info = BTUSB_MEDIATEK | BTUSB_WIDEBAND_SPEECH | BTUSB_VALID_LE_STATES }, diff --git a/target/linux/generic/backport-5.15/824-v5.19-Bluetooth-btusb-Add-a-new-PID-VID-0489-e0c8-for-MT79.patch b/target/linux/generic/backport-5.15/824-v5.19-Bluetooth-btusb-Add-a-new-PID-VID-0489-e0c8-for-MT79.patch index be9dc734215194..a8c7ca003a9cd8 100644 --- a/target/linux/generic/backport-5.15/824-v5.19-Bluetooth-btusb-Add-a-new-PID-VID-0489-e0c8-for-MT79.patch +++ b/target/linux/generic/backport-5.15/824-v5.19-Bluetooth-btusb-Add-a-new-PID-VID-0489-e0c8-for-MT79.patch @@ -56,7 +56,7 @@ Signed-off-by: Marcel Holtmann --- a/drivers/bluetooth/btusb.c +++ b/drivers/bluetooth/btusb.c -@@ -455,6 +455,9 @@ static const struct usb_device_id blackl +@@ -467,6 +467,9 @@ static const struct usb_device_id blackl BTUSB_VALID_LE_STATES }, /* Additional MediaTek MT7921 Bluetooth devices */ diff --git a/target/linux/generic/backport-5.15/825-v6.1-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch b/target/linux/generic/backport-5.15/825-v6.1-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch index 24ec68a2ca50b8..b46e6926d1452e 100644 --- a/target/linux/generic/backport-5.15/825-v6.1-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch +++ b/target/linux/generic/backport-5.15/825-v6.1-Bluetooth-btusb-Add-a-new-VID-PID-0e8d-0608-for-MT79.patch @@ -54,7 +54,7 @@ Signed-off-by: Luiz Augusto von Dentz --- a/drivers/bluetooth/btusb.c +++ b/drivers/bluetooth/btusb.c -@@ -473,6 +473,9 @@ static const struct usb_device_id blackl +@@ -485,6 +485,9 @@ static const struct usb_device_id blackl { USB_DEVICE(0x0489, 0xe0cd), .driver_info = BTUSB_MEDIATEK | BTUSB_WIDEBAND_SPEECH | BTUSB_VALID_LE_STATES }, diff --git a/target/linux/generic/backport-5.4/782-net-next-1-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch b/target/linux/generic/backport-5.4/782-net-next-1-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch index 4632b4672e12db..a9ecc290321e0d 100644 --- a/target/linux/generic/backport-5.4/782-net-next-1-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch +++ b/target/linux/generic/backport-5.4/782-net-next-1-of-net-pass-the-dst-buffer-to-of_get_mac_address.patch @@ -931,7 +931,7 @@ Signed-off-by: David S. Miller eth_hw_addr_random(ndev); --- a/drivers/net/ethernet/qualcomm/qca_spi.c +++ b/drivers/net/ethernet/qualcomm/qca_spi.c -@@ -884,7 +884,7 @@ qca_spi_probe(struct spi_device *spi) +@@ -902,7 +902,7 @@ qca_spi_probe(struct spi_device *spi) struct net_device *qcaspi_devs = NULL; u8 legacy_mode = 0; u16 signature; @@ -940,7 +940,7 @@ Signed-off-by: David S. Miller if (!spi->dev.of_node) { dev_err(&spi->dev, "Missing device tree\n"); -@@ -961,12 +961,8 @@ qca_spi_probe(struct spi_device *spi) +@@ -979,12 +979,8 @@ qca_spi_probe(struct spi_device *spi) spi_set_drvdata(spi, qcaspi_devs); @@ -1000,7 +1000,7 @@ Signed-off-by: David S. Miller u32 mahr = ravb_read(ndev, MAHR); u32 malr = ravb_read(ndev, MALR); -@@ -2154,7 +2156,7 @@ static int ravb_probe(struct platform_de +@@ -2165,7 +2167,7 @@ static int ravb_probe(struct platform_de priv->msg_enable = RAVB_DEF_MSG_ENABLE; /* Read and set MAC address */ @@ -1302,7 +1302,7 @@ Signed-off-by: David S. Miller int irq; --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -4477,7 +4477,7 @@ int stmmac_dvr_probe(struct device *devi +@@ -4519,7 +4519,7 @@ int stmmac_dvr_probe(struct device *devi priv->wol_irq = res->wol_irq; priv->lpi_irq = res->lpi_irq; diff --git a/target/linux/generic/backport-5.4/903-v6.10-backport-genl-small-ops.patch b/target/linux/generic/backport-5.4/903-v6.10-backport-genl-small-ops.patch index f7288ae5a63572..729ef4881708e9 100644 --- a/target/linux/generic/backport-5.4/903-v6.10-backport-genl-small-ops.patch +++ b/target/linux/generic/backport-5.4/903-v6.10-backport-genl-small-ops.patch @@ -1,6 +1,6 @@ --- a/include/net/genetlink.h +++ b/include/net/genetlink.h -@@ -51,6 +51,7 @@ struct genl_family { +@@ -54,6 +54,7 @@ struct genl_family { unsigned int maxattr; bool netnsok; bool parallel_ops; @@ -8,7 +8,7 @@ const struct nla_policy *policy; int (*pre_doit)(const struct genl_ops *ops, struct sk_buff *skb, -@@ -60,6 +61,7 @@ struct genl_family { +@@ -63,6 +64,7 @@ struct genl_family { struct genl_info *info); struct nlattr ** attrbuf; /* private */ const struct genl_ops * ops; @@ -16,7 +16,7 @@ const struct genl_multicast_group *mcgrps; unsigned int n_ops; unsigned int n_mcgrps; -@@ -120,6 +122,27 @@ enum genl_validate_flags { +@@ -123,6 +125,27 @@ enum genl_validate_flags { }; /** diff --git a/target/linux/generic/backport-6.1/020-v6.3-06-BACKPORT-mm-multi-gen-LRU-per-node-lru_gen_folio-lis.patch b/target/linux/generic/backport-6.1/020-v6.3-06-BACKPORT-mm-multi-gen-LRU-per-node-lru_gen_folio-lis.patch index 612ed6f6bab8d1..99ec42fe488aec 100644 --- a/target/linux/generic/backport-6.1/020-v6.3-06-BACKPORT-mm-multi-gen-LRU-per-node-lru_gen_folio-lis.patch +++ b/target/linux/generic/backport-6.1/020-v6.3-06-BACKPORT-mm-multi-gen-LRU-per-node-lru_gen_folio-lis.patch @@ -121,7 +121,7 @@ Signed-off-by: T.J. Mercier static inline int lru_gen_from_seq(unsigned long seq) { return seq % MAX_NR_GENS; -@@ -297,6 +309,11 @@ static inline bool lru_gen_in_fault(void +@@ -302,6 +314,11 @@ static inline bool lru_gen_in_fault(void return false; } @@ -325,7 +325,7 @@ Signed-off-by: T.J. Mercier mctz = soft_limit_tree.rb_tree_per_node[nid]; if (!mctz) return; -@@ -3523,6 +3533,9 @@ unsigned long mem_cgroup_soft_limit_recl +@@ -3524,6 +3534,9 @@ unsigned long mem_cgroup_soft_limit_recl struct mem_cgroup_tree_per_node *mctz; unsigned long excess; @@ -335,7 +335,7 @@ Signed-off-by: T.J. Mercier if (order > 0) return 0; -@@ -5386,6 +5399,7 @@ static int mem_cgroup_css_online(struct +@@ -5387,6 +5400,7 @@ static int mem_cgroup_css_online(struct if (unlikely(mem_cgroup_is_root(memcg))) queue_delayed_work(system_unbound_wq, &stats_flush_dwork, 2UL*HZ); @@ -343,7 +343,7 @@ Signed-off-by: T.J. Mercier return 0; offline_kmem: memcg_offline_kmem(memcg); -@@ -5417,6 +5431,7 @@ static void mem_cgroup_css_offline(struc +@@ -5418,6 +5432,7 @@ static void mem_cgroup_css_offline(struc memcg_offline_kmem(memcg); reparent_shrinker_deferred(memcg); wb_memcg_offline(memcg); @@ -351,7 +351,7 @@ Signed-off-by: T.J. Mercier drain_all_stock(memcg); -@@ -5428,6 +5443,7 @@ static void mem_cgroup_css_released(stru +@@ -5429,6 +5444,7 @@ static void mem_cgroup_css_released(stru struct mem_cgroup *memcg = mem_cgroup_from_css(css); invalidate_reclaim_iterators(memcg); diff --git a/target/linux/generic/backport-6.1/020-v6.3-10-UPSTREAM-mm-add-vma_has_recency.patch b/target/linux/generic/backport-6.1/020-v6.3-10-UPSTREAM-mm-add-vma_has_recency.patch index aea6aa18e28fa9..faa7d1d9bf1f79 100644 --- a/target/linux/generic/backport-6.1/020-v6.3-10-UPSTREAM-mm-add-vma_has_recency.patch +++ b/target/linux/generic/backport-6.1/020-v6.3-10-UPSTREAM-mm-add-vma_has_recency.patch @@ -62,7 +62,7 @@ Signed-off-by: T.J. Mercier --- a/include/linux/mm_inline.h +++ b/include/linux/mm_inline.h -@@ -595,4 +595,12 @@ pte_install_uffd_wp_if_needed(struct vm_ +@@ -600,4 +600,12 @@ pte_install_uffd_wp_if_needed(struct vm_ #endif } diff --git a/target/linux/generic/backport-6.1/020-v6.3-11-UPSTREAM-mm-support-POSIX_FADV_NOREUSE.patch b/target/linux/generic/backport-6.1/020-v6.3-11-UPSTREAM-mm-support-POSIX_FADV_NOREUSE.patch index 00e5b6e8d513c8..f9c39be920cc85 100644 --- a/target/linux/generic/backport-6.1/020-v6.3-11-UPSTREAM-mm-support-POSIX_FADV_NOREUSE.patch +++ b/target/linux/generic/backport-6.1/020-v6.3-11-UPSTREAM-mm-support-POSIX_FADV_NOREUSE.patch @@ -96,7 +96,7 @@ Signed-off-by: T.J. Mercier --- a/include/linux/mm_inline.h +++ b/include/linux/mm_inline.h -@@ -600,6 +600,9 @@ static inline bool vma_has_recency(struc +@@ -605,6 +605,9 @@ static inline bool vma_has_recency(struc if (vma->vm_flags & (VM_SEQ_READ | VM_RAND_READ)) return false; diff --git a/target/linux/generic/backport-6.1/020-v6.3-15-UPSTREAM-mm-multi-gen-LRU-section-for-memcg-LRU.patch b/target/linux/generic/backport-6.1/020-v6.3-15-UPSTREAM-mm-multi-gen-LRU-section-for-memcg-LRU.patch index 39552b07c0e8f3..101a0a37572e28 100644 --- a/target/linux/generic/backport-6.1/020-v6.3-15-UPSTREAM-mm-multi-gen-LRU-section-for-memcg-LRU.patch +++ b/target/linux/generic/backport-6.1/020-v6.3-15-UPSTREAM-mm-multi-gen-LRU-section-for-memcg-LRU.patch @@ -87,7 +87,7 @@ Signed-off-by: T.J. Mercier static inline int lru_gen_from_seq(unsigned long seq) { return seq % MAX_NR_GENS; -@@ -309,11 +297,6 @@ static inline bool lru_gen_in_fault(void +@@ -314,11 +302,6 @@ static inline bool lru_gen_in_fault(void return false; } diff --git a/target/linux/generic/backport-6.1/790-v6.4-0001-net-dsa-mt7530-make-some-noise-if-register-read-fail.patch b/target/linux/generic/backport-6.1/790-v6.4-0001-net-dsa-mt7530-make-some-noise-if-register-read-fail.patch new file mode 100644 index 00000000000000..4d024b063ab544 --- /dev/null +++ b/target/linux/generic/backport-6.1/790-v6.4-0001-net-dsa-mt7530-make-some-noise-if-register-read-fail.patch @@ -0,0 +1,32 @@ +From c3552d3f85f06cf4b4818bd84c4fcc09d8d45165 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Mon, 3 Apr 2023 02:17:19 +0100 +Subject: [PATCH 01/13] net: dsa: mt7530: make some noise if register read + fails + +Simply returning the negative error value instead of the read value +doesn't seem like a good idea. Return 0 instead and add WARN_ON_ONCE(1) +so this kind of error will not go unnoticed. + +Suggested-by: Andrew Lunn +Signed-off-by: Daniel Golle +Reviewed-by: Andrew Lunn +Signed-off-by: David S. Miller +--- + drivers/net/dsa/mt7530.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -224,9 +224,10 @@ mt7530_mii_read(struct mt7530_priv *priv + /* MT7530 uses 31 as the pseudo port */ + ret = bus->write(bus, 0x1f, 0x1f, page); + if (ret < 0) { ++ WARN_ON_ONCE(1); + dev_err(&bus->dev, + "failed to read mt7530 register\n"); +- return ret; ++ return 0; + } + + lo = bus->read(bus, 0x1f, r); diff --git a/target/linux/generic/backport-6.1/790-v6.4-0002-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch b/target/linux/generic/backport-6.1/790-v6.4-0002-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch new file mode 100644 index 00000000000000..4f255abc5bc92f --- /dev/null +++ b/target/linux/generic/backport-6.1/790-v6.4-0002-net-dsa-mt7530-refactor-SGMII-PCS-creation.patch @@ -0,0 +1,111 @@ +From b896355fc4988216d4f38582d07add9252a795ae Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Mon, 3 Apr 2023 02:17:30 +0100 +Subject: [PATCH 02/13] net: dsa: mt7530: refactor SGMII PCS creation + +Instead of macro templates use a dedidated function and allocated +regmap_config when creating the regmaps for the pcs-mtk-lynxi +instances. +This is in preparation to switching to use unlocked regmap accessors +and have regmap's locking API handle locking for us. + +Signed-off-by: Daniel Golle +Reviewed-by: Andrew Lunn +Signed-off-by: David S. Miller +--- + drivers/net/dsa/mt7530.c | 74 +++++++++++++++++++++++++++------------- + 1 file changed, 50 insertions(+), 24 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2950,26 +2950,56 @@ static const struct regmap_bus mt7531_re + .reg_update_bits = mt7530_regmap_update_bits, + }; + +-#define MT7531_PCS_REGMAP_CONFIG(_name, _reg_base) \ +- { \ +- .name = _name, \ +- .reg_bits = 16, \ +- .val_bits = 32, \ +- .reg_stride = 4, \ +- .reg_base = _reg_base, \ +- .max_register = 0x17c, \ ++static int ++mt7531_create_sgmii(struct mt7530_priv *priv) ++{ ++ struct regmap_config *mt7531_pcs_config[2]; ++ struct phylink_pcs *pcs; ++ struct regmap *regmap; ++ int i, ret = 0; ++ ++ for (i = 0; i < 2; i++) { ++ mt7531_pcs_config[i] = devm_kzalloc(priv->dev, ++ sizeof(struct regmap_config), ++ GFP_KERNEL); ++ if (!mt7531_pcs_config[i]) { ++ ret = -ENOMEM; ++ break; ++ } ++ ++ mt7531_pcs_config[i]->name = i ? "port6" : "port5"; ++ mt7531_pcs_config[i]->reg_bits = 16; ++ mt7531_pcs_config[i]->val_bits = 32; ++ mt7531_pcs_config[i]->reg_stride = 4; ++ mt7531_pcs_config[i]->reg_base = MT7531_SGMII_REG_BASE(5 + i); ++ mt7531_pcs_config[i]->max_register = 0x17c; ++ ++ regmap = devm_regmap_init(priv->dev, ++ &mt7531_regmap_bus, priv, ++ mt7531_pcs_config[i]); ++ if (IS_ERR(regmap)) { ++ ret = PTR_ERR(regmap); ++ break; ++ } ++ pcs = mtk_pcs_lynxi_create(priv->dev, regmap, ++ MT7531_PHYA_CTRL_SIGNAL3, 0); ++ if (!pcs) { ++ ret = -ENXIO; ++ break; ++ } ++ priv->ports[5 + i].sgmii_pcs = pcs; + } + +-static const struct regmap_config mt7531_pcs_config[] = { +- MT7531_PCS_REGMAP_CONFIG("port5", MT7531_SGMII_REG_BASE(5)), +- MT7531_PCS_REGMAP_CONFIG("port6", MT7531_SGMII_REG_BASE(6)), +-}; ++ if (ret && i) ++ mtk_pcs_lynxi_destroy(priv->ports[5].sgmii_pcs); ++ ++ return ret; ++} + + static int + mt753x_setup(struct dsa_switch *ds) + { + struct mt7530_priv *priv = ds->priv; +- struct regmap *regmap; + int i, ret; + + /* Initialise the PCS devices */ +@@ -2991,15 +3021,11 @@ mt753x_setup(struct dsa_switch *ds) + if (ret && priv->irq) + mt7530_free_irq_common(priv); + +- if (priv->id == ID_MT7531) +- for (i = 0; i < 2; i++) { +- regmap = devm_regmap_init(ds->dev, +- &mt7531_regmap_bus, priv, +- &mt7531_pcs_config[i]); +- priv->ports[5 + i].sgmii_pcs = +- mtk_pcs_lynxi_create(ds->dev, regmap, +- MT7531_PHYA_CTRL_SIGNAL3, 0); +- } ++ if (priv->id == ID_MT7531) { ++ ret = mt7531_create_sgmii(priv); ++ if (ret && priv->irq) ++ mt7530_free_irq_common(priv); ++ } + + return ret; + } diff --git a/target/linux/generic/backport-6.1/790-v6.4-0003-net-dsa-mt7530-use-unlocked-regmap-accessors.patch b/target/linux/generic/backport-6.1/790-v6.4-0003-net-dsa-mt7530-use-unlocked-regmap-accessors.patch new file mode 100644 index 00000000000000..77ac3f3f26858f --- /dev/null +++ b/target/linux/generic/backport-6.1/790-v6.4-0003-net-dsa-mt7530-use-unlocked-regmap-accessors.patch @@ -0,0 +1,74 @@ +From 33396408776385f3d2f6069646169a6b5b28e3b3 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Mon, 3 Apr 2023 02:17:40 +0100 +Subject: [PATCH 03/13] net: dsa: mt7530: use unlocked regmap accessors + +Instead of wrapping the locked register accessor functions, use the +unlocked variants and add locking wrapper functions to let regmap +handle the locking. + +This is a preparation towards being able to always use regmap to +access switch registers instead of open-coded accessor functions. + +Signed-off-by: Daniel Golle +Reviewed-by: Andrew Lunn +Signed-off-by: David S. Miller +--- + drivers/net/dsa/mt7530.c | 23 ++++++++++++++--------- + 1 file changed, 14 insertions(+), 9 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -2923,7 +2923,7 @@ static int mt7530_regmap_read(void *cont + { + struct mt7530_priv *priv = context; + +- *val = mt7530_read(priv, reg); ++ *val = mt7530_mii_read(priv, reg); + return 0; + }; + +@@ -2931,23 +2931,25 @@ static int mt7530_regmap_write(void *con + { + struct mt7530_priv *priv = context; + +- mt7530_write(priv, reg, val); ++ mt7530_mii_write(priv, reg, val); + return 0; + }; + +-static int mt7530_regmap_update_bits(void *context, unsigned int reg, +- unsigned int mask, unsigned int val) ++static void ++mt7530_mdio_regmap_lock(void *mdio_lock) + { +- struct mt7530_priv *priv = context; ++ mutex_lock_nested(mdio_lock, MDIO_MUTEX_NESTED); ++} + +- mt7530_rmw(priv, reg, mask, val); +- return 0; +-}; ++static void ++mt7530_mdio_regmap_unlock(void *mdio_lock) ++{ ++ mutex_unlock(mdio_lock); ++} + + static const struct regmap_bus mt7531_regmap_bus = { + .reg_write = mt7530_regmap_write, + .reg_read = mt7530_regmap_read, +- .reg_update_bits = mt7530_regmap_update_bits, + }; + + static int +@@ -2973,6 +2975,9 @@ mt7531_create_sgmii(struct mt7530_priv * + mt7531_pcs_config[i]->reg_stride = 4; + mt7531_pcs_config[i]->reg_base = MT7531_SGMII_REG_BASE(5 + i); + mt7531_pcs_config[i]->max_register = 0x17c; ++ mt7531_pcs_config[i]->lock = mt7530_mdio_regmap_lock; ++ mt7531_pcs_config[i]->unlock = mt7530_mdio_regmap_unlock; ++ mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock; + + regmap = devm_regmap_init(priv->dev, + &mt7531_regmap_bus, priv, diff --git a/target/linux/generic/backport-6.1/790-v6.4-0004-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch b/target/linux/generic/backport-6.1/790-v6.4-0004-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch new file mode 100644 index 00000000000000..6e3e8b09b964aa --- /dev/null +++ b/target/linux/generic/backport-6.1/790-v6.4-0004-net-dsa-mt7530-use-regmap-to-access-switch-register-.patch @@ -0,0 +1,224 @@ +From 743cba4345cb366248f9d375c6a9e50243dc0677 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Mon, 3 Apr 2023 02:17:52 +0100 +Subject: [PATCH 04/13] net: dsa: mt7530: use regmap to access switch register + space + +Use regmap API to access the switch register space. + +Signed-off-by: Daniel Golle +Signed-off-by: David S. Miller +--- + drivers/net/dsa/mt7530.c | 99 ++++++++++++++++++++++++---------------- + drivers/net/dsa/mt7530.h | 2 + + 2 files changed, 62 insertions(+), 39 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -183,9 +183,9 @@ core_clear(struct mt7530_priv *priv, u32 + } + + static int +-mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) ++mt7530_regmap_write(void *context, unsigned int reg, unsigned int val) + { +- struct mii_bus *bus = priv->bus; ++ struct mii_bus *bus = context; + u16 page, r, lo, hi; + int ret; + +@@ -197,24 +197,34 @@ mt7530_mii_write(struct mt7530_priv *pri + /* MT7530 uses 31 as the pseudo port */ + ret = bus->write(bus, 0x1f, 0x1f, page); + if (ret < 0) +- goto err; ++ return ret; + + ret = bus->write(bus, 0x1f, r, lo); + if (ret < 0) +- goto err; ++ return ret; + + ret = bus->write(bus, 0x1f, 0x10, hi); +-err: ++ return ret; ++} ++ ++static int ++mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) ++{ ++ int ret; ++ ++ ret = regmap_write(priv->regmap, reg, val); ++ + if (ret < 0) +- dev_err(&bus->dev, ++ dev_err(priv->dev, + "failed to write mt7530 register\n"); ++ + return ret; + } + +-static u32 +-mt7530_mii_read(struct mt7530_priv *priv, u32 reg) ++static int ++mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val) + { +- struct mii_bus *bus = priv->bus; ++ struct mii_bus *bus = context; + u16 page, r, lo, hi; + int ret; + +@@ -223,17 +233,32 @@ mt7530_mii_read(struct mt7530_priv *priv + + /* MT7530 uses 31 as the pseudo port */ + ret = bus->write(bus, 0x1f, 0x1f, page); +- if (ret < 0) { ++ if (ret < 0) ++ return ret; ++ ++ lo = bus->read(bus, 0x1f, r); ++ hi = bus->read(bus, 0x1f, 0x10); ++ ++ *val = (hi << 16) | (lo & 0xffff); ++ ++ return 0; ++} ++ ++static u32 ++mt7530_mii_read(struct mt7530_priv *priv, u32 reg) ++{ ++ int ret; ++ u32 val; ++ ++ ret = regmap_read(priv->regmap, reg, &val); ++ if (ret) { + WARN_ON_ONCE(1); +- dev_err(&bus->dev, ++ dev_err(priv->dev, + "failed to read mt7530 register\n"); + return 0; + } + +- lo = bus->read(bus, 0x1f, r); +- hi = bus->read(bus, 0x1f, 0x10); +- +- return (hi << 16) | (lo & 0xffff); ++ return val; + } + + static void +@@ -283,14 +308,10 @@ mt7530_rmw(struct mt7530_priv *priv, u32 + u32 mask, u32 set) + { + struct mii_bus *bus = priv->bus; +- u32 val; + + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); + +- val = mt7530_mii_read(priv, reg); +- val &= ~mask; +- val |= set; +- mt7530_mii_write(priv, reg, val); ++ regmap_update_bits(priv->regmap, reg, mask, set); + + mutex_unlock(&bus->mdio_lock); + } +@@ -298,7 +319,7 @@ mt7530_rmw(struct mt7530_priv *priv, u32 + static void + mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) + { +- mt7530_rmw(priv, reg, 0, val); ++ mt7530_rmw(priv, reg, val, val); + } + + static void +@@ -2919,22 +2940,6 @@ static const struct phylink_pcs_ops mt75 + .pcs_an_restart = mt7530_pcs_an_restart, + }; + +-static int mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val) +-{ +- struct mt7530_priv *priv = context; +- +- *val = mt7530_mii_read(priv, reg); +- return 0; +-}; +- +-static int mt7530_regmap_write(void *context, unsigned int reg, unsigned int val) +-{ +- struct mt7530_priv *priv = context; +- +- mt7530_mii_write(priv, reg, val); +- return 0; +-}; +- + static void + mt7530_mdio_regmap_lock(void *mdio_lock) + { +@@ -2947,7 +2952,7 @@ mt7530_mdio_regmap_unlock(void *mdio_loc + mutex_unlock(mdio_lock); + } + +-static const struct regmap_bus mt7531_regmap_bus = { ++static const struct regmap_bus mt7530_regmap_bus = { + .reg_write = mt7530_regmap_write, + .reg_read = mt7530_regmap_read, + }; +@@ -2980,7 +2985,7 @@ mt7531_create_sgmii(struct mt7530_priv * + mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock; + + regmap = devm_regmap_init(priv->dev, +- &mt7531_regmap_bus, priv, ++ &mt7530_regmap_bus, priv->bus, + mt7531_pcs_config[i]); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); +@@ -3145,6 +3150,7 @@ MODULE_DEVICE_TABLE(of, mt7530_of_match) + static int + mt7530_probe(struct mdio_device *mdiodev) + { ++ static struct regmap_config *regmap_config; + struct mt7530_priv *priv; + struct device_node *dn; + +@@ -3224,6 +3230,21 @@ mt7530_probe(struct mdio_device *mdiodev + mutex_init(&priv->reg_mutex); + dev_set_drvdata(&mdiodev->dev, priv); + ++ regmap_config = devm_kzalloc(&mdiodev->dev, sizeof(*regmap_config), ++ GFP_KERNEL); ++ if (!regmap_config) ++ return -ENOMEM; ++ ++ regmap_config->reg_bits = 16; ++ regmap_config->val_bits = 32; ++ regmap_config->reg_stride = 4; ++ regmap_config->max_register = MT7530_CREV; ++ regmap_config->disable_locking = true; ++ priv->regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus, ++ priv->bus, regmap_config); ++ if (IS_ERR(priv->regmap)) ++ return PTR_ERR(priv->regmap); ++ + return dsa_register_switch(priv->ds); + } + +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -747,6 +747,7 @@ struct mt753x_info { + * @dev: The device pointer + * @ds: The pointer to the dsa core structure + * @bus: The bus used for the device and built-in PHY ++ * @regmap: The regmap instance representing all switch registers + * @rstc: The pointer to reset control used by MCM + * @core_pwr: The power supplied into the core + * @io_pwr: The power supplied into the I/O +@@ -767,6 +768,7 @@ struct mt7530_priv { + struct device *dev; + struct dsa_switch *ds; + struct mii_bus *bus; ++ struct regmap *regmap; + struct reset_control *rstc; + struct regulator *core_pwr; + struct regulator *io_pwr; diff --git a/target/linux/generic/backport-6.1/790-v6.4-0005-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch b/target/linux/generic/backport-6.1/790-v6.4-0005-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch new file mode 100644 index 00000000000000..a02702fd687b93 --- /dev/null +++ b/target/linux/generic/backport-6.1/790-v6.4-0005-net-dsa-mt7530-move-SGMII-PCS-creation-to-mt7530_pro.patch @@ -0,0 +1,54 @@ +From f3cf1d06e2aef644b426c23b4bb570780b1f8d47 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Mon, 3 Apr 2023 02:18:04 +0100 +Subject: [PATCH 05/13] net: dsa: mt7530: move SGMII PCS creation to + mt7530_probe function + +Move creating the SGMII PCS from mt753x_setup() to the more appropriate +mt7530_probe() function. +This is done also in preparation of moving all functions related to +MDIO-connected MT753x switches to a separate module. + +Signed-off-by: Daniel Golle +Reviewed-by: Andrew Lunn +Signed-off-by: David S. Miller +--- + drivers/net/dsa/mt7530.c | 13 +++++++------ + 1 file changed, 7 insertions(+), 6 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -3031,12 +3031,6 @@ mt753x_setup(struct dsa_switch *ds) + if (ret && priv->irq) + mt7530_free_irq_common(priv); + +- if (priv->id == ID_MT7531) { +- ret = mt7531_create_sgmii(priv); +- if (ret && priv->irq) +- mt7530_free_irq_common(priv); +- } +- + return ret; + } + +@@ -3153,6 +3147,7 @@ mt7530_probe(struct mdio_device *mdiodev + static struct regmap_config *regmap_config; + struct mt7530_priv *priv; + struct device_node *dn; ++ int ret; + + dn = mdiodev->dev.of_node; + +@@ -3245,6 +3240,12 @@ mt7530_probe(struct mdio_device *mdiodev + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + ++ if (priv->id == ID_MT7531) { ++ ret = mt7531_create_sgmii(priv); ++ if (ret) ++ return ret; ++ } ++ + return dsa_register_switch(priv->ds); + } + diff --git a/target/linux/generic/backport-6.1/790-v6.4-0006-net-dsa-mt7530-introduce-mutex-helpers.patch b/target/linux/generic/backport-6.1/790-v6.4-0006-net-dsa-mt7530-introduce-mutex-helpers.patch new file mode 100644 index 00000000000000..98122caf0904b4 --- /dev/null +++ b/target/linux/generic/backport-6.1/790-v6.4-0006-net-dsa-mt7530-introduce-mutex-helpers.patch @@ -0,0 +1,273 @@ +From e4729ae7c095c0c87794bff47ea43e35d69de986 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Mon, 3 Apr 2023 02:18:16 +0100 +Subject: [PATCH 06/13] net: dsa: mt7530: introduce mutex helpers + +As the MDIO bus lock only needs to be involved if actually operating +on an MDIO-connected switch we will need to skip locking for built-in +switches which are accessed via MMIO. +Create helper functions which simplify that upcoming change. + +Signed-off-by: Daniel Golle +Reviewed-by: Andrew Lunn +Signed-off-by: David S. Miller +--- + drivers/net/dsa/mt7530.c | 73 ++++++++++++++++++++-------------------- + 1 file changed, 36 insertions(+), 37 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -143,31 +143,40 @@ err: + } + + static void +-core_write(struct mt7530_priv *priv, u32 reg, u32 val) ++mt7530_mutex_lock(struct mt7530_priv *priv) + { +- struct mii_bus *bus = priv->bus; ++ mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); ++} + +- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); ++static void ++mt7530_mutex_unlock(struct mt7530_priv *priv) ++{ ++ mutex_unlock(&priv->bus->mdio_lock); ++} ++ ++static void ++core_write(struct mt7530_priv *priv, u32 reg, u32 val) ++{ ++ mt7530_mutex_lock(priv); + + core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); + +- mutex_unlock(&bus->mdio_lock); ++ mt7530_mutex_unlock(priv); + } + + static void + core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) + { +- struct mii_bus *bus = priv->bus; + u32 val; + +- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); ++ mt7530_mutex_lock(priv); + + val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); + val &= ~mask; + val |= set; + core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); + +- mutex_unlock(&bus->mdio_lock); ++ mt7530_mutex_unlock(priv); + } + + static void +@@ -264,13 +273,11 @@ mt7530_mii_read(struct mt7530_priv *priv + static void + mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) + { +- struct mii_bus *bus = priv->bus; +- +- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); ++ mt7530_mutex_lock(priv); + + mt7530_mii_write(priv, reg, val); + +- mutex_unlock(&bus->mdio_lock); ++ mt7530_mutex_unlock(priv); + } + + static u32 +@@ -282,14 +289,13 @@ _mt7530_unlocked_read(struct mt7530_dumm + static u32 + _mt7530_read(struct mt7530_dummy_poll *p) + { +- struct mii_bus *bus = p->priv->bus; + u32 val; + +- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); ++ mt7530_mutex_lock(p->priv); + + val = mt7530_mii_read(p->priv, p->reg); + +- mutex_unlock(&bus->mdio_lock); ++ mt7530_mutex_unlock(p->priv); + + return val; + } +@@ -307,13 +313,11 @@ static void + mt7530_rmw(struct mt7530_priv *priv, u32 reg, + u32 mask, u32 set) + { +- struct mii_bus *bus = priv->bus; +- +- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); ++ mt7530_mutex_lock(priv); + + regmap_update_bits(priv->regmap, reg, mask, set); + +- mutex_unlock(&bus->mdio_lock); ++ mt7530_mutex_unlock(priv); + } + + static void +@@ -645,14 +649,13 @@ static int + mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, + int regnum) + { +- struct mii_bus *bus = priv->bus; + struct mt7530_dummy_poll p; + u32 reg, val; + int ret; + + INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); + +- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); ++ mt7530_mutex_lock(priv); + + ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, + !(val & MT7531_PHY_ACS_ST), 20, 100000); +@@ -685,7 +688,7 @@ mt7531_ind_c45_phy_read(struct mt7530_pr + + ret = val & MT7531_MDIO_RW_DATA_MASK; + out: +- mutex_unlock(&bus->mdio_lock); ++ mt7530_mutex_unlock(priv); + + return ret; + } +@@ -694,14 +697,13 @@ static int + mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, + int regnum, u32 data) + { +- struct mii_bus *bus = priv->bus; + struct mt7530_dummy_poll p; + u32 val, reg; + int ret; + + INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); + +- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); ++ mt7530_mutex_lock(priv); + + ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, + !(val & MT7531_PHY_ACS_ST), 20, 100000); +@@ -733,7 +735,7 @@ mt7531_ind_c45_phy_write(struct mt7530_p + } + + out: +- mutex_unlock(&bus->mdio_lock); ++ mt7530_mutex_unlock(priv); + + return ret; + } +@@ -741,14 +743,13 @@ out: + static int + mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) + { +- struct mii_bus *bus = priv->bus; + struct mt7530_dummy_poll p; + int ret; + u32 val; + + INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); + +- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); ++ mt7530_mutex_lock(priv); + + ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, + !(val & MT7531_PHY_ACS_ST), 20, 100000); +@@ -771,7 +772,7 @@ mt7531_ind_c22_phy_read(struct mt7530_pr + + ret = val & MT7531_MDIO_RW_DATA_MASK; + out: +- mutex_unlock(&bus->mdio_lock); ++ mt7530_mutex_unlock(priv); + + return ret; + } +@@ -780,14 +781,13 @@ static int + mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, + u16 data) + { +- struct mii_bus *bus = priv->bus; + struct mt7530_dummy_poll p; + int ret; + u32 reg; + + INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); + +- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); ++ mt7530_mutex_lock(priv); + + ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, + !(reg & MT7531_PHY_ACS_ST), 20, 100000); +@@ -809,7 +809,7 @@ mt7531_ind_c22_phy_write(struct mt7530_p + } + + out: +- mutex_unlock(&bus->mdio_lock); ++ mt7530_mutex_unlock(priv); + + return ret; + } +@@ -1109,7 +1109,6 @@ static int + mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) + { + struct mt7530_priv *priv = ds->priv; +- struct mii_bus *bus = priv->bus; + int length; + u32 val; + +@@ -1120,7 +1119,7 @@ mt7530_port_change_mtu(struct dsa_switch + if (!dsa_is_cpu_port(ds, port)) + return 0; + +- mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); ++ mt7530_mutex_lock(priv); + + val = mt7530_mii_read(priv, MT7530_GMACCR); + val &= ~MAX_RX_PKT_LEN_MASK; +@@ -1141,7 +1140,7 @@ mt7530_port_change_mtu(struct dsa_switch + + mt7530_mii_write(priv, MT7530_GMACCR, val); + +- mutex_unlock(&bus->mdio_lock); ++ mt7530_mutex_unlock(priv); + + return 0; + } +@@ -1942,10 +1941,10 @@ mt7530_irq_thread_fn(int irq, void *dev_ + u32 val; + int p; + +- mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); ++ mt7530_mutex_lock(priv); + val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); + mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); +- mutex_unlock(&priv->bus->mdio_lock); ++ mt7530_mutex_unlock(priv); + + for (p = 0; p < MT7530_NUM_PHYS; p++) { + if (BIT(p) & val) { +@@ -1981,7 +1980,7 @@ mt7530_irq_bus_lock(struct irq_data *d) + { + struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); + +- mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); ++ mt7530_mutex_lock(priv); + } + + static void +@@ -1990,7 +1989,7 @@ mt7530_irq_bus_sync_unlock(struct irq_da + struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); + + mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); +- mutex_unlock(&priv->bus->mdio_lock); ++ mt7530_mutex_unlock(priv); + } + + static struct irq_chip mt7530_irq_chip = { diff --git a/target/linux/generic/backport-6.1/790-v6.4-0007-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch b/target/linux/generic/backport-6.1/790-v6.4-0007-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch new file mode 100644 index 00000000000000..5065d7352326e2 --- /dev/null +++ b/target/linux/generic/backport-6.1/790-v6.4-0007-net-dsa-mt7530-move-p5_intf_modes-function-to-mt7530.patch @@ -0,0 +1,75 @@ +From 0d7ae94a0c581f86939bebec0b6ccd66e640d1d8 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Mon, 3 Apr 2023 02:18:28 +0100 +Subject: [PATCH 07/13] net: dsa: mt7530: move p5_intf_modes() function to + mt7530.c + +In preparation of splitting mt7530.c into a driver for MDIO-connected +as well as MDIO-accessed built-in switches on one hand and MMIO-accessed +built-in switches move the p5_inft_modes() function from mt7530.h to +mt7530.c. The function is only needed there and will trigger a compiler +warning about a defined but unused function otherwise when including +mt7530.h in the to-be-introduced bus-specific drivers. + +Signed-off-by: Daniel Golle +Reviewed-by: Andrew Lunn +Signed-off-by: David S. Miller +--- + drivers/net/dsa/mt7530.c | 18 ++++++++++++++++++ + drivers/net/dsa/mt7530.h | 18 ------------------ + 2 files changed, 18 insertions(+), 18 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -950,6 +950,24 @@ mt7530_set_ageing_time(struct dsa_switch + return 0; + } + ++static const char *p5_intf_modes(unsigned int p5_interface) ++{ ++ switch (p5_interface) { ++ case P5_DISABLED: ++ return "DISABLED"; ++ case P5_INTF_SEL_PHY_P0: ++ return "PHY P0"; ++ case P5_INTF_SEL_PHY_P4: ++ return "PHY P4"; ++ case P5_INTF_SEL_GMAC5: ++ return "GMAC5"; ++ case P5_INTF_SEL_GMAC5_SGMII: ++ return "GMAC5_SGMII"; ++ default: ++ return "unknown"; ++ } ++} ++ + static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) + { + struct mt7530_priv *priv = ds->priv; +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -682,24 +682,6 @@ enum p5_interface_select { + P5_INTF_SEL_GMAC5_SGMII, + }; + +-static const char *p5_intf_modes(unsigned int p5_interface) +-{ +- switch (p5_interface) { +- case P5_DISABLED: +- return "DISABLED"; +- case P5_INTF_SEL_PHY_P0: +- return "PHY P0"; +- case P5_INTF_SEL_PHY_P4: +- return "PHY P4"; +- case P5_INTF_SEL_GMAC5: +- return "GMAC5"; +- case P5_INTF_SEL_GMAC5_SGMII: +- return "GMAC5_SGMII"; +- default: +- return "unknown"; +- } +-} +- + struct mt7530_priv; + + struct mt753x_pcs { diff --git a/target/linux/generic/backport-6.1/790-v6.4-0008-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch b/target/linux/generic/backport-6.1/790-v6.4-0008-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch new file mode 100644 index 00000000000000..761aa1d9797bbb --- /dev/null +++ b/target/linux/generic/backport-6.1/790-v6.4-0008-net-dsa-mt7530-introduce-mt7530_probe_common-helper-.patch @@ -0,0 +1,155 @@ +From 4d632005c90e253c000d0db73b7cdb9d8dc2e2dd Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Mon, 3 Apr 2023 02:18:39 +0100 +Subject: [PATCH 08/13] net: dsa: mt7530: introduce mt7530_probe_common helper + function + +Move commonly used parts from mt7530_probe into new mt7530_probe_common +helper function which will be used by both, mt7530_probe and the +to-be-introduced mt7988_probe. + +Signed-off-by: Daniel Golle +Reviewed-by: Andrew Lunn +Signed-off-by: David S. Miller +--- + drivers/net/dsa/mt7530.c | 98 ++++++++++++++++++++++------------------ + 1 file changed, 54 insertions(+), 44 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -3159,44 +3159,21 @@ static const struct of_device_id mt7530_ + MODULE_DEVICE_TABLE(of, mt7530_of_match); + + static int +-mt7530_probe(struct mdio_device *mdiodev) ++mt7530_probe_common(struct mt7530_priv *priv) + { +- static struct regmap_config *regmap_config; +- struct mt7530_priv *priv; +- struct device_node *dn; +- int ret; ++ struct device *dev = priv->dev; + +- dn = mdiodev->dev.of_node; +- +- priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); +- if (!priv) +- return -ENOMEM; +- +- priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); ++ priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); + if (!priv->ds) + return -ENOMEM; + +- priv->ds->dev = &mdiodev->dev; ++ priv->ds->dev = dev; + priv->ds->num_ports = MT7530_NUM_PORTS; + +- /* Use medatek,mcm property to distinguish hardware type that would +- * casues a little bit differences on power-on sequence. +- */ +- priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); +- if (priv->mcm) { +- dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); +- +- priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); +- if (IS_ERR(priv->rstc)) { +- dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); +- return PTR_ERR(priv->rstc); +- } +- } +- + /* Get the hardware identifier from the devicetree node. + * We will need it for some of the clock and regulator setup. + */ +- priv->info = of_device_get_match_data(&mdiodev->dev); ++ priv->info = of_device_get_match_data(dev); + if (!priv->info) + return -EINVAL; + +@@ -3210,23 +3187,53 @@ mt7530_probe(struct mdio_device *mdiodev + return -EINVAL; + + priv->id = priv->info->id; ++ priv->dev = dev; ++ priv->ds->priv = priv; ++ priv->ds->ops = &mt7530_switch_ops; ++ mutex_init(&priv->reg_mutex); ++ dev_set_drvdata(dev, priv); + +- if (priv->id == ID_MT7530) { +- priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); +- if (IS_ERR(priv->core_pwr)) +- return PTR_ERR(priv->core_pwr); ++ return 0; ++} + +- priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); +- if (IS_ERR(priv->io_pwr)) +- return PTR_ERR(priv->io_pwr); +- } ++static int ++mt7530_probe(struct mdio_device *mdiodev) ++{ ++ static struct regmap_config *regmap_config; ++ struct mt7530_priv *priv; ++ struct device_node *dn; ++ int ret; ++ ++ dn = mdiodev->dev.of_node; ++ ++ priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; + +- /* Not MCM that indicates switch works as the remote standalone ++ priv->bus = mdiodev->bus; ++ priv->dev = &mdiodev->dev; ++ ++ ret = mt7530_probe_common(priv); ++ if (ret) ++ return ret; ++ ++ /* Use medatek,mcm property to distinguish hardware type that would ++ * cause a little bit differences on power-on sequence. ++ * Not MCM that indicates switch works as the remote standalone + * integrated circuit so the GPIO pin would be used to complete + * the reset, otherwise memory-mapped register accessing used + * through syscon provides in the case of MCM. + */ +- if (!priv->mcm) { ++ priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); ++ if (priv->mcm) { ++ dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); ++ ++ priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); ++ if (IS_ERR(priv->rstc)) { ++ dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); ++ return PTR_ERR(priv->rstc); ++ } ++ } else { + priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", + GPIOD_OUT_LOW); + if (IS_ERR(priv->reset)) { +@@ -3235,12 +3242,15 @@ mt7530_probe(struct mdio_device *mdiodev + } + } + +- priv->bus = mdiodev->bus; +- priv->dev = &mdiodev->dev; +- priv->ds->priv = priv; +- priv->ds->ops = &mt7530_switch_ops; +- mutex_init(&priv->reg_mutex); +- dev_set_drvdata(&mdiodev->dev, priv); ++ if (priv->id == ID_MT7530) { ++ priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); ++ if (IS_ERR(priv->core_pwr)) ++ return PTR_ERR(priv->core_pwr); ++ ++ priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); ++ if (IS_ERR(priv->io_pwr)) ++ return PTR_ERR(priv->io_pwr); ++ } + + regmap_config = devm_kzalloc(&mdiodev->dev, sizeof(*regmap_config), + GFP_KERNEL); diff --git a/target/linux/generic/backport-6.1/790-v6.4-0009-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch b/target/linux/generic/backport-6.1/790-v6.4-0009-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch new file mode 100644 index 00000000000000..d3c2a7e2c9b8d4 --- /dev/null +++ b/target/linux/generic/backport-6.1/790-v6.4-0009-net-dsa-mt7530-introduce-mt7530_remove_common-helper.patch @@ -0,0 +1,54 @@ +From 69b838d2629e6b82bcd9e0ab3c1c03f46e5e01d3 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Mon, 3 Apr 2023 02:18:50 +0100 +Subject: [PATCH 09/13] net: dsa: mt7530: introduce mt7530_remove_common helper + function + +Move commonly used parts from mt7530_remove into new +mt7530_remove_common helper function which will be used by both, +mt7530_remove and the to-be-introduced mt7988_remove. + +Signed-off-by: Daniel Golle +Reviewed-by: Andrew Lunn +Signed-off-by: David S. Miller +--- + drivers/net/dsa/mt7530.c | 18 ++++++++++++------ + 1 file changed, 12 insertions(+), 6 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -3277,6 +3277,17 @@ mt7530_probe(struct mdio_device *mdiodev + } + + static void ++mt7530_remove_common(struct mt7530_priv *priv) ++{ ++ if (priv->irq) ++ mt7530_free_irq(priv); ++ ++ dsa_unregister_switch(priv->ds); ++ ++ mutex_destroy(&priv->reg_mutex); ++} ++ ++static void + mt7530_remove(struct mdio_device *mdiodev) + { + struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); +@@ -3295,15 +3306,10 @@ mt7530_remove(struct mdio_device *mdiode + dev_err(priv->dev, "Failed to disable io pwr: %d\n", + ret); + +- if (priv->irq) +- mt7530_free_irq(priv); +- +- dsa_unregister_switch(priv->ds); ++ mt7530_remove_common(priv); + + for (i = 0; i < 2; ++i) + mtk_pcs_lynxi_destroy(priv->ports[5 + i].sgmii_pcs); +- +- mutex_destroy(&priv->reg_mutex); + } + + static void mt7530_shutdown(struct mdio_device *mdiodev) diff --git a/target/linux/generic/backport-6.1/790-v6.4-0010-net-dsa-mt7530-introduce-separate-MDIO-driver.patch b/target/linux/generic/backport-6.1/790-v6.4-0010-net-dsa-mt7530-introduce-separate-MDIO-driver.patch new file mode 100644 index 00000000000000..55378ca016b5b5 --- /dev/null +++ b/target/linux/generic/backport-6.1/790-v6.4-0010-net-dsa-mt7530-introduce-separate-MDIO-driver.patch @@ -0,0 +1,691 @@ +From 8eceed6dbd74067dbf4d8e39f14734f4d2f35176 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Mon, 3 Apr 2023 02:19:13 +0100 +Subject: [PATCH 10/13] net: dsa: mt7530: introduce separate MDIO driver + +Split MT7530 switch driver into a common part and a part specific +for MDIO connected switches and multi-chip modules. +Move MDIO-specific functions to newly introduced mt7530-mdio.c while +keeping the common parts in mt7530.c. +Introduce new Kconfig symbol CONFIG_NET_DSA_MT7530_MDIO which is +implied by CONFIG_NET_DSA_MT7530. + +Signed-off-by: Daniel Golle +Reviewed-by: Andrew Lunn +Signed-off-by: David S. Miller +--- + MAINTAINERS | 1 + + drivers/net/dsa/Kconfig | 16 +- + drivers/net/dsa/Makefile | 1 + + drivers/net/dsa/mt7530-mdio.c | 271 ++++++++++++++++++++++++++++++++++ + drivers/net/dsa/mt7530.c | 264 +-------------------------------- + drivers/net/dsa/mt7530.h | 6 + + 6 files changed, 301 insertions(+), 258 deletions(-) + create mode 100644 drivers/net/dsa/mt7530-mdio.c + +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -13060,6 +13060,7 @@ M: Landen Chao + L: netdev@vger.kernel.org + S: Maintained ++F: drivers/net/dsa/mt7530-mdio.c + F: drivers/net/dsa/mt7530.* + F: net/dsa/tag_mtk.c + +--- a/drivers/net/dsa/Kconfig ++++ b/drivers/net/dsa/Kconfig +@@ -37,10 +37,22 @@ config NET_DSA_MT7530 + tristate "MediaTek MT753x and MT7621 Ethernet switch support" + select NET_DSA_TAG_MTK + select MEDIATEK_GE_PHY ++ imply NET_DSA_MT7530_MDIO ++ help ++ This enables support for the MediaTek MT7530 and MT7531 Ethernet ++ switch chips. Multi-chip module MT7530 in MT7621AT, MT7621DAT, ++ MT7621ST and MT7623AI SoCs, and built-in switch in MT7988 SoC are ++ supported as well. ++ ++config NET_DSA_MT7530_MDIO ++ tristate "MediaTek MT7530 MDIO interface driver" ++ depends on NET_DSA_MT7530 + select PCS_MTK_LYNXI + help +- This enables support for the MediaTek MT7530, MT7531, and MT7621 +- Ethernet switch chips. ++ This enables support for the MediaTek MT7530 and MT7531 switch ++ chips which are connected via MDIO, as well as multi-chip ++ module MT7530 which can be found in the MT7621AT, MT7621DAT, ++ MT7621ST and MT7623AI SoCs. + + config NET_DSA_MV88E6060 + tristate "Marvell 88E6060 ethernet switch chip support" +--- a/drivers/net/dsa/Makefile ++++ b/drivers/net/dsa/Makefile +@@ -7,6 +7,7 @@ obj-$(CONFIG_FIXED_PHY) += dsa_loop_bdi + endif + obj-$(CONFIG_NET_DSA_LANTIQ_GSWIP) += lantiq_gswip.o + obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o ++obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o + obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o + obj-$(CONFIG_NET_DSA_RZN1_A5PSW) += rzn1_a5psw.o + obj-$(CONFIG_NET_DSA_SMSC_LAN9303) += lan9303-core.o +--- /dev/null ++++ b/drivers/net/dsa/mt7530-mdio.c +@@ -0,0 +1,271 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mt7530.h" ++ ++static int ++mt7530_regmap_write(void *context, unsigned int reg, unsigned int val) ++{ ++ struct mii_bus *bus = context; ++ u16 page, r, lo, hi; ++ int ret; ++ ++ page = (reg >> 6) & 0x3ff; ++ r = (reg >> 2) & 0xf; ++ lo = val & 0xffff; ++ hi = val >> 16; ++ ++ /* MT7530 uses 31 as the pseudo port */ ++ ret = bus->write(bus, 0x1f, 0x1f, page); ++ if (ret < 0) ++ return ret; ++ ++ ret = bus->write(bus, 0x1f, r, lo); ++ if (ret < 0) ++ return ret; ++ ++ ret = bus->write(bus, 0x1f, 0x10, hi); ++ return ret; ++} ++ ++static int ++mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val) ++{ ++ struct mii_bus *bus = context; ++ u16 page, r, lo, hi; ++ int ret; ++ ++ page = (reg >> 6) & 0x3ff; ++ r = (reg >> 2) & 0xf; ++ ++ /* MT7530 uses 31 as the pseudo port */ ++ ret = bus->write(bus, 0x1f, 0x1f, page); ++ if (ret < 0) ++ return ret; ++ ++ lo = bus->read(bus, 0x1f, r); ++ hi = bus->read(bus, 0x1f, 0x10); ++ ++ *val = (hi << 16) | (lo & 0xffff); ++ ++ return 0; ++} ++ ++static void ++mt7530_mdio_regmap_lock(void *mdio_lock) ++{ ++ mutex_lock_nested(mdio_lock, MDIO_MUTEX_NESTED); ++} ++ ++static void ++mt7530_mdio_regmap_unlock(void *mdio_lock) ++{ ++ mutex_unlock(mdio_lock); ++} ++ ++static const struct regmap_bus mt7530_regmap_bus = { ++ .reg_write = mt7530_regmap_write, ++ .reg_read = mt7530_regmap_read, ++}; ++ ++static int ++mt7531_create_sgmii(struct mt7530_priv *priv) ++{ ++ struct regmap_config *mt7531_pcs_config[2]; ++ struct phylink_pcs *pcs; ++ struct regmap *regmap; ++ int i, ret = 0; ++ ++ for (i = 0; i < 2; i++) { ++ mt7531_pcs_config[i] = devm_kzalloc(priv->dev, ++ sizeof(struct regmap_config), ++ GFP_KERNEL); ++ if (!mt7531_pcs_config[i]) { ++ ret = -ENOMEM; ++ break; ++ } ++ ++ mt7531_pcs_config[i]->name = i ? "port6" : "port5"; ++ mt7531_pcs_config[i]->reg_bits = 16; ++ mt7531_pcs_config[i]->val_bits = 32; ++ mt7531_pcs_config[i]->reg_stride = 4; ++ mt7531_pcs_config[i]->reg_base = MT7531_SGMII_REG_BASE(5 + i); ++ mt7531_pcs_config[i]->max_register = 0x17c; ++ mt7531_pcs_config[i]->lock = mt7530_mdio_regmap_lock; ++ mt7531_pcs_config[i]->unlock = mt7530_mdio_regmap_unlock; ++ mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock; ++ ++ regmap = devm_regmap_init(priv->dev, ++ &mt7530_regmap_bus, priv->bus, ++ mt7531_pcs_config[i]); ++ if (IS_ERR(regmap)) { ++ ret = PTR_ERR(regmap); ++ break; ++ } ++ pcs = mtk_pcs_lynxi_create(priv->dev, regmap, ++ MT7531_PHYA_CTRL_SIGNAL3, 0); ++ if (!pcs) { ++ ret = -ENXIO; ++ break; ++ } ++ priv->ports[5 + i].sgmii_pcs = pcs; ++ } ++ ++ if (ret && i) ++ mtk_pcs_lynxi_destroy(priv->ports[5].sgmii_pcs); ++ ++ return ret; ++} ++ ++static const struct of_device_id mt7530_of_match[] = { ++ { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], }, ++ { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], }, ++ { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], }, ++ { /* sentinel */ }, ++}; ++MODULE_DEVICE_TABLE(of, mt7530_of_match); ++ ++static int ++mt7530_probe(struct mdio_device *mdiodev) ++{ ++ static struct regmap_config *regmap_config; ++ struct mt7530_priv *priv; ++ struct device_node *dn; ++ int ret; ++ ++ dn = mdiodev->dev.of_node; ++ ++ priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ priv->bus = mdiodev->bus; ++ priv->dev = &mdiodev->dev; ++ ++ ret = mt7530_probe_common(priv); ++ if (ret) ++ return ret; ++ ++ /* Use medatek,mcm property to distinguish hardware type that would ++ * cause a little bit differences on power-on sequence. ++ * Not MCM that indicates switch works as the remote standalone ++ * integrated circuit so the GPIO pin would be used to complete ++ * the reset, otherwise memory-mapped register accessing used ++ * through syscon provides in the case of MCM. ++ */ ++ priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); ++ if (priv->mcm) { ++ dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); ++ ++ priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); ++ if (IS_ERR(priv->rstc)) { ++ dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); ++ return PTR_ERR(priv->rstc); ++ } ++ } else { ++ priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", ++ GPIOD_OUT_LOW); ++ if (IS_ERR(priv->reset)) { ++ dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); ++ return PTR_ERR(priv->reset); ++ } ++ } ++ ++ if (priv->id == ID_MT7530) { ++ priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); ++ if (IS_ERR(priv->core_pwr)) ++ return PTR_ERR(priv->core_pwr); ++ ++ priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); ++ if (IS_ERR(priv->io_pwr)) ++ return PTR_ERR(priv->io_pwr); ++ } ++ ++ regmap_config = devm_kzalloc(&mdiodev->dev, sizeof(*regmap_config), ++ GFP_KERNEL); ++ if (!regmap_config) ++ return -ENOMEM; ++ ++ regmap_config->reg_bits = 16; ++ regmap_config->val_bits = 32; ++ regmap_config->reg_stride = 4; ++ regmap_config->max_register = MT7530_CREV; ++ regmap_config->disable_locking = true; ++ priv->regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus, ++ priv->bus, regmap_config); ++ if (IS_ERR(priv->regmap)) ++ return PTR_ERR(priv->regmap); ++ ++ if (priv->id == ID_MT7531) { ++ ret = mt7531_create_sgmii(priv); ++ if (ret) ++ return ret; ++ } ++ ++ return dsa_register_switch(priv->ds); ++} ++ ++static void ++mt7530_remove(struct mdio_device *mdiodev) ++{ ++ struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); ++ int ret = 0, i; ++ ++ if (!priv) ++ return; ++ ++ ret = regulator_disable(priv->core_pwr); ++ if (ret < 0) ++ dev_err(priv->dev, ++ "Failed to disable core power: %d\n", ret); ++ ++ ret = regulator_disable(priv->io_pwr); ++ if (ret < 0) ++ dev_err(priv->dev, "Failed to disable io pwr: %d\n", ++ ret); ++ ++ mt7530_remove_common(priv); ++ ++ for (i = 0; i < 2; ++i) ++ mtk_pcs_lynxi_destroy(priv->ports[5 + i].sgmii_pcs); ++} ++ ++static void mt7530_shutdown(struct mdio_device *mdiodev) ++{ ++ struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); ++ ++ if (!priv) ++ return; ++ ++ dsa_switch_shutdown(priv->ds); ++ ++ dev_set_drvdata(&mdiodev->dev, NULL); ++} ++ ++static struct mdio_driver mt7530_mdio_driver = { ++ .probe = mt7530_probe, ++ .remove = mt7530_remove, ++ .shutdown = mt7530_shutdown, ++ .mdiodrv.driver = { ++ .name = "mt7530-mdio", ++ .of_match_table = mt7530_of_match, ++ }, ++}; ++ ++mdio_module_driver(mt7530_mdio_driver); ++ ++MODULE_AUTHOR("Sean Wang "); ++MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch (MDIO)"); ++MODULE_LICENSE("GPL"); +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -14,7 +14,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -192,31 +191,6 @@ core_clear(struct mt7530_priv *priv, u32 + } + + static int +-mt7530_regmap_write(void *context, unsigned int reg, unsigned int val) +-{ +- struct mii_bus *bus = context; +- u16 page, r, lo, hi; +- int ret; +- +- page = (reg >> 6) & 0x3ff; +- r = (reg >> 2) & 0xf; +- lo = val & 0xffff; +- hi = val >> 16; +- +- /* MT7530 uses 31 as the pseudo port */ +- ret = bus->write(bus, 0x1f, 0x1f, page); +- if (ret < 0) +- return ret; +- +- ret = bus->write(bus, 0x1f, r, lo); +- if (ret < 0) +- return ret; +- +- ret = bus->write(bus, 0x1f, 0x10, hi); +- return ret; +-} +- +-static int + mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) + { + int ret; +@@ -230,29 +204,6 @@ mt7530_mii_write(struct mt7530_priv *pri + return ret; + } + +-static int +-mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val) +-{ +- struct mii_bus *bus = context; +- u16 page, r, lo, hi; +- int ret; +- +- page = (reg >> 6) & 0x3ff; +- r = (reg >> 2) & 0xf; +- +- /* MT7530 uses 31 as the pseudo port */ +- ret = bus->write(bus, 0x1f, 0x1f, page); +- if (ret < 0) +- return ret; +- +- lo = bus->read(bus, 0x1f, r); +- hi = bus->read(bus, 0x1f, 0x10); +- +- *val = (hi << 16) | (lo & 0xffff); +- +- return 0; +-} +- + static u32 + mt7530_mii_read(struct mt7530_priv *priv, u32 reg) + { +@@ -2957,72 +2908,6 @@ static const struct phylink_pcs_ops mt75 + .pcs_an_restart = mt7530_pcs_an_restart, + }; + +-static void +-mt7530_mdio_regmap_lock(void *mdio_lock) +-{ +- mutex_lock_nested(mdio_lock, MDIO_MUTEX_NESTED); +-} +- +-static void +-mt7530_mdio_regmap_unlock(void *mdio_lock) +-{ +- mutex_unlock(mdio_lock); +-} +- +-static const struct regmap_bus mt7530_regmap_bus = { +- .reg_write = mt7530_regmap_write, +- .reg_read = mt7530_regmap_read, +-}; +- +-static int +-mt7531_create_sgmii(struct mt7530_priv *priv) +-{ +- struct regmap_config *mt7531_pcs_config[2]; +- struct phylink_pcs *pcs; +- struct regmap *regmap; +- int i, ret = 0; +- +- for (i = 0; i < 2; i++) { +- mt7531_pcs_config[i] = devm_kzalloc(priv->dev, +- sizeof(struct regmap_config), +- GFP_KERNEL); +- if (!mt7531_pcs_config[i]) { +- ret = -ENOMEM; +- break; +- } +- +- mt7531_pcs_config[i]->name = i ? "port6" : "port5"; +- mt7531_pcs_config[i]->reg_bits = 16; +- mt7531_pcs_config[i]->val_bits = 32; +- mt7531_pcs_config[i]->reg_stride = 4; +- mt7531_pcs_config[i]->reg_base = MT7531_SGMII_REG_BASE(5 + i); +- mt7531_pcs_config[i]->max_register = 0x17c; +- mt7531_pcs_config[i]->lock = mt7530_mdio_regmap_lock; +- mt7531_pcs_config[i]->unlock = mt7530_mdio_regmap_unlock; +- mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock; +- +- regmap = devm_regmap_init(priv->dev, +- &mt7530_regmap_bus, priv->bus, +- mt7531_pcs_config[i]); +- if (IS_ERR(regmap)) { +- ret = PTR_ERR(regmap); +- break; +- } +- pcs = mtk_pcs_lynxi_create(priv->dev, regmap, +- MT7531_PHYA_CTRL_SIGNAL3, 0); +- if (!pcs) { +- ret = -ENXIO; +- break; +- } +- priv->ports[5 + i].sgmii_pcs = pcs; +- } +- +- if (ret && i) +- mtk_pcs_lynxi_destroy(priv->ports[5].sgmii_pcs); +- +- return ret; +-} +- + static int + mt753x_setup(struct dsa_switch *ds) + { +@@ -3081,7 +2966,7 @@ static int mt753x_set_mac_eee(struct dsa + return 0; + } + +-static const struct dsa_switch_ops mt7530_switch_ops = { ++const struct dsa_switch_ops mt7530_switch_ops = { + .get_tag_protocol = mtk_get_tag_protocol, + .setup = mt753x_setup, + .get_strings = mt7530_get_strings, +@@ -3115,8 +3000,9 @@ static const struct dsa_switch_ops mt753 + .get_mac_eee = mt753x_get_mac_eee, + .set_mac_eee = mt753x_set_mac_eee, + }; ++EXPORT_SYMBOL_GPL(mt7530_switch_ops); + +-static const struct mt753x_info mt753x_table[] = { ++const struct mt753x_info mt753x_table[] = { + [ID_MT7621] = { + .id = ID_MT7621, + .pcs_ops = &mt7530_pcs_ops, +@@ -3149,16 +3035,9 @@ static const struct mt753x_info mt753x_t + .mac_port_config = mt7531_mac_config, + }, + }; ++EXPORT_SYMBOL_GPL(mt753x_table); + +-static const struct of_device_id mt7530_of_match[] = { +- { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], }, +- { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], }, +- { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], }, +- { /* sentinel */ }, +-}; +-MODULE_DEVICE_TABLE(of, mt7530_of_match); +- +-static int ++int + mt7530_probe_common(struct mt7530_priv *priv) + { + struct device *dev = priv->dev; +@@ -3195,88 +3074,9 @@ mt7530_probe_common(struct mt7530_priv * + + return 0; + } ++EXPORT_SYMBOL_GPL(mt7530_probe_common); + +-static int +-mt7530_probe(struct mdio_device *mdiodev) +-{ +- static struct regmap_config *regmap_config; +- struct mt7530_priv *priv; +- struct device_node *dn; +- int ret; +- +- dn = mdiodev->dev.of_node; +- +- priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); +- if (!priv) +- return -ENOMEM; +- +- priv->bus = mdiodev->bus; +- priv->dev = &mdiodev->dev; +- +- ret = mt7530_probe_common(priv); +- if (ret) +- return ret; +- +- /* Use medatek,mcm property to distinguish hardware type that would +- * cause a little bit differences on power-on sequence. +- * Not MCM that indicates switch works as the remote standalone +- * integrated circuit so the GPIO pin would be used to complete +- * the reset, otherwise memory-mapped register accessing used +- * through syscon provides in the case of MCM. +- */ +- priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); +- if (priv->mcm) { +- dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); +- +- priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); +- if (IS_ERR(priv->rstc)) { +- dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); +- return PTR_ERR(priv->rstc); +- } +- } else { +- priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", +- GPIOD_OUT_LOW); +- if (IS_ERR(priv->reset)) { +- dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); +- return PTR_ERR(priv->reset); +- } +- } +- +- if (priv->id == ID_MT7530) { +- priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); +- if (IS_ERR(priv->core_pwr)) +- return PTR_ERR(priv->core_pwr); +- +- priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); +- if (IS_ERR(priv->io_pwr)) +- return PTR_ERR(priv->io_pwr); +- } +- +- regmap_config = devm_kzalloc(&mdiodev->dev, sizeof(*regmap_config), +- GFP_KERNEL); +- if (!regmap_config) +- return -ENOMEM; +- +- regmap_config->reg_bits = 16; +- regmap_config->val_bits = 32; +- regmap_config->reg_stride = 4; +- regmap_config->max_register = MT7530_CREV; +- regmap_config->disable_locking = true; +- priv->regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus, +- priv->bus, regmap_config); +- if (IS_ERR(priv->regmap)) +- return PTR_ERR(priv->regmap); +- +- if (priv->id == ID_MT7531) { +- ret = mt7531_create_sgmii(priv); +- if (ret) +- return ret; +- } +- +- return dsa_register_switch(priv->ds); +-} +- +-static void ++void + mt7530_remove_common(struct mt7530_priv *priv) + { + if (priv->irq) +@@ -3286,55 +3086,7 @@ mt7530_remove_common(struct mt7530_priv + + mutex_destroy(&priv->reg_mutex); + } +- +-static void +-mt7530_remove(struct mdio_device *mdiodev) +-{ +- struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); +- int ret = 0, i; +- +- if (!priv) +- return; +- +- ret = regulator_disable(priv->core_pwr); +- if (ret < 0) +- dev_err(priv->dev, +- "Failed to disable core power: %d\n", ret); +- +- ret = regulator_disable(priv->io_pwr); +- if (ret < 0) +- dev_err(priv->dev, "Failed to disable io pwr: %d\n", +- ret); +- +- mt7530_remove_common(priv); +- +- for (i = 0; i < 2; ++i) +- mtk_pcs_lynxi_destroy(priv->ports[5 + i].sgmii_pcs); +-} +- +-static void mt7530_shutdown(struct mdio_device *mdiodev) +-{ +- struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); +- +- if (!priv) +- return; +- +- dsa_switch_shutdown(priv->ds); +- +- dev_set_drvdata(&mdiodev->dev, NULL); +-} +- +-static struct mdio_driver mt7530_mdio_driver = { +- .probe = mt7530_probe, +- .remove = mt7530_remove, +- .shutdown = mt7530_shutdown, +- .mdiodrv.driver = { +- .name = "mt7530", +- .of_match_table = mt7530_of_match, +- }, +-}; +- +-mdio_module_driver(mt7530_mdio_driver); ++EXPORT_SYMBOL_GPL(mt7530_remove_common); + + MODULE_AUTHOR("Sean Wang "); + MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -807,4 +807,10 @@ static inline void INIT_MT7530_DUMMY_POL + p->reg = reg; + } + ++int mt7530_probe_common(struct mt7530_priv *priv); ++void mt7530_remove_common(struct mt7530_priv *priv); ++ ++extern const struct dsa_switch_ops mt7530_switch_ops; ++extern const struct mt753x_info mt753x_table[]; ++ + #endif /* __MT7530_H */ diff --git a/target/linux/generic/backport-6.1/790-v6.4-0011-net-dsa-mt7530-skip-locking-if-MDIO-bus-isn-t-presen.patch b/target/linux/generic/backport-6.1/790-v6.4-0011-net-dsa-mt7530-skip-locking-if-MDIO-bus-isn-t-presen.patch new file mode 100644 index 00000000000000..01011ed1a001c4 --- /dev/null +++ b/target/linux/generic/backport-6.1/790-v6.4-0011-net-dsa-mt7530-skip-locking-if-MDIO-bus-isn-t-presen.patch @@ -0,0 +1,47 @@ +From a52cadbf76593f8fcb2f4f62cb006e3f2a22ad06 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Mon, 3 Apr 2023 02:19:28 +0100 +Subject: [PATCH 11/13] net: dsa: mt7530: skip locking if MDIO bus isn't + present + +As MT7530 and MT7531 internally use 32-bit wide registers, each access +to any register of the switch requires several operations on the MDIO +bus. Hence if there is congruent access, e.g. due to PCS or PHY +polling, this can mess up and interfere with another ongoing register +access sequence. + +However, the MDIO bus mutex is only relevant for MDIO-connected +switches. Prepare switches which have there registers directly mapped +into the SoCs register space via MMIO which do not require such +locking. There we can simply use regmap's default locking mechanism. + +Hence guard mutex operations to only be performed in case of MDIO +connected switches. + +Signed-off-by: Daniel Golle +Reviewed-by: Andrew Lunn +Signed-off-by: David S. Miller +--- + drivers/net/dsa/mt7530.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -144,13 +144,15 @@ err: + static void + mt7530_mutex_lock(struct mt7530_priv *priv) + { +- mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); ++ if (priv->bus) ++ mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); + } + + static void + mt7530_mutex_unlock(struct mt7530_priv *priv) + { +- mutex_unlock(&priv->bus->mdio_lock); ++ if (priv->bus) ++ mutex_unlock(&priv->bus->mdio_lock); + } + + static void diff --git a/target/linux/generic/backport-6.1/790-v6.4-0012-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch b/target/linux/generic/backport-6.1/790-v6.4-0012-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch new file mode 100644 index 00000000000000..aeaf9f84678e57 --- /dev/null +++ b/target/linux/generic/backport-6.1/790-v6.4-0012-net-dsa-mt7530-introduce-driver-for-MT7988-built-in-.patch @@ -0,0 +1,421 @@ +From b361015763fedea439f13b336b15ef7bdf1f7d4f Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Mon, 3 Apr 2023 02:19:40 +0100 +Subject: [PATCH 12/13] net: dsa: mt7530: introduce driver for MT7988 built-in + switch + +Add driver for the built-in Gigabit Ethernet switch which can be found +in the MediaTek MT7988 SoC. + +The switch shares most of its design with MT7530 and MT7531, but has +it's registers mapped into the SoCs register space rather than being +connected externally or internally via MDIO. + +Introduce a new platform driver to support that. + +Signed-off-by: Daniel Golle +Reviewed-by: Andrew Lunn +Signed-off-by: David S. Miller +--- + MAINTAINERS | 2 + + drivers/net/dsa/Kconfig | 12 +++ + drivers/net/dsa/Makefile | 1 + + drivers/net/dsa/mt7530-mmio.c | 101 +++++++++++++++++++++++++ + drivers/net/dsa/mt7530.c | 137 +++++++++++++++++++++++++++++++++- + drivers/net/dsa/mt7530.h | 12 +-- + 6 files changed, 255 insertions(+), 10 deletions(-) + create mode 100644 drivers/net/dsa/mt7530-mmio.c + +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -13058,9 +13058,11 @@ MEDIATEK SWITCH DRIVER + M: Sean Wang + M: Landen Chao + M: DENG Qingfang ++M: Daniel Golle + L: netdev@vger.kernel.org + S: Maintained + F: drivers/net/dsa/mt7530-mdio.c ++F: drivers/net/dsa/mt7530-mmio.c + F: drivers/net/dsa/mt7530.* + F: net/dsa/tag_mtk.c + +--- a/drivers/net/dsa/Kconfig ++++ b/drivers/net/dsa/Kconfig +@@ -38,6 +38,7 @@ config NET_DSA_MT7530 + select NET_DSA_TAG_MTK + select MEDIATEK_GE_PHY + imply NET_DSA_MT7530_MDIO ++ imply NET_DSA_MT7530_MMIO + help + This enables support for the MediaTek MT7530 and MT7531 Ethernet + switch chips. Multi-chip module MT7530 in MT7621AT, MT7621DAT, +@@ -54,6 +55,17 @@ config NET_DSA_MT7530_MDIO + module MT7530 which can be found in the MT7621AT, MT7621DAT, + MT7621ST and MT7623AI SoCs. + ++config NET_DSA_MT7530_MMIO ++ tristate "MediaTek MT7530 MMIO interface driver" ++ depends on NET_DSA_MT7530 ++ depends on HAS_IOMEM ++ help ++ This enables support for the built-in Ethernet switch found ++ in the MediaTek MT7988 SoC. ++ The switch is a similar design as MT7531, but the switch registers ++ are directly mapped into the SoCs register space rather than being ++ accessible via MDIO. ++ + config NET_DSA_MV88E6060 + tristate "Marvell 88E6060 ethernet switch chip support" + select NET_DSA_TAG_TRAILER +--- a/drivers/net/dsa/Makefile ++++ b/drivers/net/dsa/Makefile +@@ -8,6 +8,7 @@ endif + obj-$(CONFIG_NET_DSA_LANTIQ_GSWIP) += lantiq_gswip.o + obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o + obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o ++obj-$(CONFIG_NET_DSA_MT7530_MMIO) += mt7530-mmio.o + obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o + obj-$(CONFIG_NET_DSA_RZN1_A5PSW) += rzn1_a5psw.o + obj-$(CONFIG_NET_DSA_SMSC_LAN9303) += lan9303-core.o +--- /dev/null ++++ b/drivers/net/dsa/mt7530-mmio.c +@@ -0,0 +1,101 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mt7530.h" ++ ++static const struct of_device_id mt7988_of_match[] = { ++ { .compatible = "mediatek,mt7988-switch", .data = &mt753x_table[ID_MT7988], }, ++ { /* sentinel */ }, ++}; ++MODULE_DEVICE_TABLE(of, mt7988_of_match); ++ ++static int ++mt7988_probe(struct platform_device *pdev) ++{ ++ static struct regmap_config *sw_regmap_config; ++ struct mt7530_priv *priv; ++ void __iomem *base_addr; ++ int ret; ++ ++ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ priv->bus = NULL; ++ priv->dev = &pdev->dev; ++ ++ ret = mt7530_probe_common(priv); ++ if (ret) ++ return ret; ++ ++ priv->rstc = devm_reset_control_get(&pdev->dev, NULL); ++ if (IS_ERR(priv->rstc)) { ++ dev_err(&pdev->dev, "Couldn't get our reset line\n"); ++ return PTR_ERR(priv->rstc); ++ } ++ ++ base_addr = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(base_addr)) { ++ dev_err(&pdev->dev, "cannot request I/O memory space\n"); ++ return -ENXIO; ++ } ++ ++ sw_regmap_config = devm_kzalloc(&pdev->dev, sizeof(*sw_regmap_config), GFP_KERNEL); ++ if (!sw_regmap_config) ++ return -ENOMEM; ++ ++ sw_regmap_config->name = "switch"; ++ sw_regmap_config->reg_bits = 16; ++ sw_regmap_config->val_bits = 32; ++ sw_regmap_config->reg_stride = 4; ++ sw_regmap_config->max_register = MT7530_CREV; ++ priv->regmap = devm_regmap_init_mmio(&pdev->dev, base_addr, sw_regmap_config); ++ if (IS_ERR(priv->regmap)) ++ return PTR_ERR(priv->regmap); ++ ++ return dsa_register_switch(priv->ds); ++} ++ ++static int ++mt7988_remove(struct platform_device *pdev) ++{ ++ struct mt7530_priv *priv = platform_get_drvdata(pdev); ++ ++ if (priv) ++ mt7530_remove_common(priv); ++ ++ return 0; ++} ++ ++static void mt7988_shutdown(struct platform_device *pdev) ++{ ++ struct mt7530_priv *priv = platform_get_drvdata(pdev); ++ ++ if (!priv) ++ return; ++ ++ dsa_switch_shutdown(priv->ds); ++ ++ dev_set_drvdata(&pdev->dev, NULL); ++} ++ ++static struct platform_driver mt7988_platform_driver = { ++ .probe = mt7988_probe, ++ .remove = mt7988_remove, ++ .shutdown = mt7988_shutdown, ++ .driver = { ++ .name = "mt7530-mmio", ++ .of_match_table = mt7988_of_match, ++ }, ++}; ++module_platform_driver(mt7988_platform_driver); ++ ++MODULE_AUTHOR("Daniel Golle "); ++MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch (MMIO)"); ++MODULE_LICENSE("GPL"); +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -1989,6 +1989,47 @@ static const struct irq_domain_ops mt753 + }; + + static void ++mt7988_irq_mask(struct irq_data *d) ++{ ++ struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); ++ ++ priv->irq_enable &= ~BIT(d->hwirq); ++ mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); ++} ++ ++static void ++mt7988_irq_unmask(struct irq_data *d) ++{ ++ struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); ++ ++ priv->irq_enable |= BIT(d->hwirq); ++ mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); ++} ++ ++static struct irq_chip mt7988_irq_chip = { ++ .name = KBUILD_MODNAME, ++ .irq_mask = mt7988_irq_mask, ++ .irq_unmask = mt7988_irq_unmask, ++}; ++ ++static int ++mt7988_irq_map(struct irq_domain *domain, unsigned int irq, ++ irq_hw_number_t hwirq) ++{ ++ irq_set_chip_data(irq, domain->host_data); ++ irq_set_chip_and_handler(irq, &mt7988_irq_chip, handle_simple_irq); ++ irq_set_nested_thread(irq, true); ++ irq_set_noprobe(irq); ++ ++ return 0; ++} ++ ++static const struct irq_domain_ops mt7988_irq_domain_ops = { ++ .map = mt7988_irq_map, ++ .xlate = irq_domain_xlate_onecell, ++}; ++ ++static void + mt7530_setup_mdio_irq(struct mt7530_priv *priv) + { + struct dsa_switch *ds = priv->ds; +@@ -2022,8 +2063,15 @@ mt7530_setup_irq(struct mt7530_priv *pri + return priv->irq ? : -EINVAL; + } + +- priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, +- &mt7530_irq_domain_ops, priv); ++ if (priv->id == ID_MT7988) ++ priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, ++ &mt7988_irq_domain_ops, ++ priv); ++ else ++ priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, ++ &mt7530_irq_domain_ops, ++ priv); ++ + if (!priv->irq_domain) { + dev_err(dev, "failed to create IRQ domain\n"); + return -ENOMEM; +@@ -2520,6 +2568,25 @@ static void mt7531_mac_port_get_caps(str + } + } + ++static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, ++ struct phylink_config *config) ++{ ++ phy_interface_zero(config->supported_interfaces); ++ ++ switch (port) { ++ case 0 ... 4: /* Internal phy */ ++ __set_bit(PHY_INTERFACE_MODE_INTERNAL, ++ config->supported_interfaces); ++ break; ++ ++ case 6: ++ __set_bit(PHY_INTERFACE_MODE_INTERNAL, ++ config->supported_interfaces); ++ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | ++ MAC_10000FD; ++ } ++} ++ + static int + mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) + { +@@ -2596,6 +2663,17 @@ static bool mt753x_is_mac_port(u32 port) + } + + static int ++mt7988_mac_config(struct dsa_switch *ds, int port, unsigned int mode, ++ phy_interface_t interface) ++{ ++ if (dsa_is_cpu_port(ds, port) && ++ interface == PHY_INTERFACE_MODE_INTERNAL) ++ return 0; ++ ++ return -EINVAL; ++} ++ ++static int + mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, + phy_interface_t interface) + { +@@ -2665,7 +2743,8 @@ mt753x_phylink_mac_config(struct dsa_swi + + switch (port) { + case 0 ... 4: /* Internal phy */ +- if (state->interface != PHY_INTERFACE_MODE_GMII) ++ if (state->interface != PHY_INTERFACE_MODE_GMII && ++ state->interface != PHY_INTERFACE_MODE_INTERNAL) + goto unsupported; + break; + case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ +@@ -2743,7 +2822,8 @@ static void mt753x_phylink_mac_link_up(s + /* MT753x MAC works in 1G full duplex mode for all up-clocked + * variants. + */ +- if (interface == PHY_INTERFACE_MODE_TRGMII || ++ if (interface == PHY_INTERFACE_MODE_INTERNAL || ++ interface == PHY_INTERFACE_MODE_TRGMII || + (phy_interface_mode_is_8023z(interface))) { + speed = SPEED_1000; + duplex = DUPLEX_FULL; +@@ -2823,6 +2903,21 @@ mt7531_cpu_port_config(struct dsa_switch + return 0; + } + ++static int ++mt7988_cpu_port_config(struct dsa_switch *ds, int port) ++{ ++ struct mt7530_priv *priv = ds->priv; ++ ++ mt7530_write(priv, MT7530_PMCR_P(port), ++ PMCR_CPU_PORT_SETTING(priv->id)); ++ ++ mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, ++ PHY_INTERFACE_MODE_INTERNAL, NULL, ++ SPEED_10000, DUPLEX_FULL, true, true); ++ ++ return 0; ++} ++ + static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, + struct phylink_config *config) + { +@@ -2968,6 +3063,27 @@ static int mt753x_set_mac_eee(struct dsa + return 0; + } + ++static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface) ++{ ++ return 0; ++} ++ ++static int mt7988_setup(struct dsa_switch *ds) ++{ ++ struct mt7530_priv *priv = ds->priv; ++ ++ /* Reset the switch */ ++ reset_control_assert(priv->rstc); ++ usleep_range(20, 50); ++ reset_control_deassert(priv->rstc); ++ usleep_range(20, 50); ++ ++ /* Reset the switch PHYs */ ++ mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST); ++ ++ return mt7531_setup_common(ds); ++} ++ + const struct dsa_switch_ops mt7530_switch_ops = { + .get_tag_protocol = mtk_get_tag_protocol, + .setup = mt753x_setup, +@@ -3036,6 +3152,17 @@ const struct mt753x_info mt753x_table[] + .mac_port_get_caps = mt7531_mac_port_get_caps, + .mac_port_config = mt7531_mac_config, + }, ++ [ID_MT7988] = { ++ .id = ID_MT7988, ++ .pcs_ops = &mt7530_pcs_ops, ++ .sw_setup = mt7988_setup, ++ .phy_read = mt7531_ind_phy_read, ++ .phy_write = mt7531_ind_phy_write, ++ .pad_setup = mt7988_pad_setup, ++ .cpu_port_config = mt7988_cpu_port_config, ++ .mac_port_get_caps = mt7988_mac_port_get_caps, ++ .mac_port_config = mt7988_mac_config, ++ }, + }; + EXPORT_SYMBOL_GPL(mt753x_table); + +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -18,6 +18,7 @@ enum mt753x_id { + ID_MT7530 = 0, + ID_MT7621 = 1, + ID_MT7531 = 2, ++ ID_MT7988 = 3, + }; + + #define NUM_TRGMII_CTRL 5 +@@ -54,11 +55,11 @@ enum mt753x_id { + #define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16) + #define MT7531_CPU_PMAP_MASK GENMASK(7, 0) + +-#define MT753X_MIRROR_REG(id) (((id) == ID_MT7531) ? \ ++#define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ + MT7531_CFC : MT7530_MFC) +-#define MT753X_MIRROR_EN(id) (((id) == ID_MT7531) ? \ ++#define MT753X_MIRROR_EN(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ + MT7531_MIRROR_EN : MIRROR_EN) +-#define MT753X_MIRROR_MASK(id) (((id) == ID_MT7531) ? \ ++#define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ + MT7531_MIRROR_MASK : MIRROR_MASK) + + /* Registers for BPDU and PAE frame control*/ +@@ -295,9 +296,8 @@ enum mt7530_vlan_port_acc_frm { + MT7531_FORCE_DPX | \ + MT7531_FORCE_RX_FC | \ + MT7531_FORCE_TX_FC) +-#define PMCR_FORCE_MODE_ID(id) (((id) == ID_MT7531) ? \ +- MT7531_FORCE_MODE : \ +- PMCR_FORCE_MODE) ++#define PMCR_FORCE_MODE_ID(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \ ++ MT7531_FORCE_MODE : PMCR_FORCE_MODE) + #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \ + PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \ + PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ diff --git a/target/linux/generic/backport-6.1/790-v6.4-0013-net-dsa-mt7530-fix-support-for-MT7531BE.patch b/target/linux/generic/backport-6.1/790-v6.4-0013-net-dsa-mt7530-fix-support-for-MT7531BE.patch new file mode 100644 index 00000000000000..074472f6dcb09a --- /dev/null +++ b/target/linux/generic/backport-6.1/790-v6.4-0013-net-dsa-mt7530-fix-support-for-MT7531BE.patch @@ -0,0 +1,118 @@ +From eb1dd407b4be7ca38166a38c56c8edf52c6a399f Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Sun, 16 Apr 2023 13:08:14 +0100 +Subject: [PATCH 13/13] net: dsa: mt7530: fix support for MT7531BE +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +There are two variants of the MT7531 switch IC which got different +features (and pins) regarding port 5: + * MT7531AE: SGMII/1000Base-X/2500Base-X SerDes PCS + * MT7531BE: RGMII + +Moving the creation of the SerDes PCS from mt753x_setup to mt7530_probe +with commit 6de285229773 ("net: dsa: mt7530: move SGMII PCS creation +to mt7530_probe function") works fine for MT7531AE which got two +instances of mtk-pcs-lynxi, however, MT7531BE requires mt7531_pll_setup +to setup clocks before the single PCS on port 6 (usually used as CPU +port) starts to work and hence the PCS creation failed on MT7531BE. + +Fix this by introducing a pointer to mt7531_create_sgmii function in +struct mt7530_priv and call it again at the end of mt753x_setup like it +was before commit 6de285229773 ("net: dsa: mt7530: move SGMII PCS +creation to mt7530_probe function"). + +Fixes: 6de285229773 ("net: dsa: mt7530: move SGMII PCS creation to mt7530_probe function") +Signed-off-by: Daniel Golle +Acked-by: Arınç ÜNAL +Link: https://lore.kernel.org/r/ZDvlLhhqheobUvOK@makrotopia.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/dsa/mt7530-mdio.c | 16 ++++++++-------- + drivers/net/dsa/mt7530.c | 6 ++++++ + drivers/net/dsa/mt7530.h | 4 ++-- + 3 files changed, 16 insertions(+), 10 deletions(-) + +--- a/drivers/net/dsa/mt7530-mdio.c ++++ b/drivers/net/dsa/mt7530-mdio.c +@@ -81,14 +81,17 @@ static const struct regmap_bus mt7530_re + }; + + static int +-mt7531_create_sgmii(struct mt7530_priv *priv) ++mt7531_create_sgmii(struct mt7530_priv *priv, bool dual_sgmii) + { +- struct regmap_config *mt7531_pcs_config[2]; ++ struct regmap_config *mt7531_pcs_config[2] = {}; + struct phylink_pcs *pcs; + struct regmap *regmap; + int i, ret = 0; + +- for (i = 0; i < 2; i++) { ++ /* MT7531AE has two SGMII units for port 5 and port 6 ++ * MT7531BE has only one SGMII unit for port 6 ++ */ ++ for (i = dual_sgmii ? 0 : 1; i < 2; i++) { + mt7531_pcs_config[i] = devm_kzalloc(priv->dev, + sizeof(struct regmap_config), + GFP_KERNEL); +@@ -208,11 +211,8 @@ mt7530_probe(struct mdio_device *mdiodev + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + +- if (priv->id == ID_MT7531) { +- ret = mt7531_create_sgmii(priv); +- if (ret) +- return ret; +- } ++ if (priv->id == ID_MT7531) ++ priv->create_sgmii = mt7531_create_sgmii; + + return dsa_register_switch(priv->ds); + } +--- a/drivers/net/dsa/mt7530.c ++++ b/drivers/net/dsa/mt7530.c +@@ -3030,6 +3030,12 @@ mt753x_setup(struct dsa_switch *ds) + if (ret && priv->irq) + mt7530_free_irq_common(priv); + ++ if (priv->create_sgmii) { ++ ret = priv->create_sgmii(priv, mt7531_dual_sgmii_supported(priv)); ++ if (ret && priv->irq) ++ mt7530_free_irq(priv); ++ } ++ + return ret; + } + +--- a/drivers/net/dsa/mt7530.h ++++ b/drivers/net/dsa/mt7530.h +@@ -741,10 +741,10 @@ struct mt753x_info { + * registers + * @p6_interface Holding the current port 6 interface + * @p5_intf_sel: Holding the current port 5 interface select +- * + * @irq: IRQ number of the switch + * @irq_domain: IRQ domain of the switch irq_chip + * @irq_enable: IRQ enable bits, synced to SYS_INT_EN ++ * @create_sgmii: Pointer to function creating SGMII PCS instance(s) + */ + struct mt7530_priv { + struct device *dev; +@@ -763,7 +763,6 @@ struct mt7530_priv { + unsigned int p5_intf_sel; + u8 mirror_rx; + u8 mirror_tx; +- + struct mt7530_port ports[MT7530_NUM_PORTS]; + struct mt753x_pcs pcs[MT7530_NUM_PORTS]; + /* protect among processes for registers access*/ +@@ -771,6 +770,7 @@ struct mt7530_priv { + int irq; + struct irq_domain *irq_domain; + u32 irq_enable; ++ int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii); + }; + + struct mt7530_hw_vlan_entry { diff --git a/target/linux/generic/backport-6.1/795-v6.3-01-r8152-add-USB-device-driver-for-config-selection.patch b/target/linux/generic/backport-6.1/795-v6.3-01-r8152-add-USB-device-driver-for-config-selection.patch deleted file mode 100644 index 605faeec035dfb..00000000000000 --- a/target/linux/generic/backport-6.1/795-v6.3-01-r8152-add-USB-device-driver-for-config-selection.patch +++ /dev/null @@ -1,229 +0,0 @@ -From ec51fbd1b8a2bca2948dede99c14ec63dc57ff6b Mon Sep 17 00:00:00 2001 -From: Bjørn Mork -Date: Fri, 6 Jan 2023 17:07:38 +0100 -Subject: [PATCH] r8152: add USB device driver for config selection -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Subclassing the generic USB device driver to override the -default configuration selection regardless of matching interface -drivers. - -The r815x family devices expose a vendor specific function which -the r8152 interface driver wants to handle. This is the preferred -device mode. Additionally one or more USB class functions are -usually supported for hosts lacking a vendor specific driver. The -choice is USB configuration based, with one alternate function per -configuration. - -Example device with both NCM and ECM alternate cfgs: - -T: Bus=02 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#= 4 Spd=5000 MxCh= 0 -D: Ver= 3.20 Cls=00(>ifc ) Sub=00 Prot=00 MxPS= 9 #Cfgs= 3 -P: Vendor=0bda ProdID=8156 Rev=31.00 -S: Manufacturer=Realtek -S: Product=USB 10/100/1G/2.5G LAN -S: SerialNumber=001000001 -C:* #Ifs= 1 Cfg#= 1 Atr=a0 MxPwr=256mA -I:* If#= 0 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=00 Driver=r8152 -E: Ad=81(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms -E: Ad=02(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms -E: Ad=83(I) Atr=03(Int.) MxPS= 2 Ivl=128ms -C: #Ifs= 2 Cfg#= 2 Atr=a0 MxPwr=256mA -I: If#= 0 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=0d Prot=00 Driver= -E: Ad=83(I) Atr=03(Int.) MxPS= 16 Ivl=128ms -I: If#= 1 Alt= 0 #EPs= 0 Cls=0a(data ) Sub=00 Prot=01 Driver= -I: If#= 1 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=01 Driver= -E: Ad=81(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms -E: Ad=02(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms -C: #Ifs= 2 Cfg#= 3 Atr=a0 MxPwr=256mA -I: If#= 0 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=06 Prot=00 Driver= -E: Ad=83(I) Atr=03(Int.) MxPS= 16 Ivl=128ms -I: If#= 1 Alt= 0 #EPs= 0 Cls=0a(data ) Sub=00 Prot=00 Driver= -I: If#= 1 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=00 Driver= -E: Ad=81(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms -E: Ad=02(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms - -A problem with this is that Linux will prefer class functions over -vendor specific functions. Using the above example, Linux defaults -to cfg #2, running the device in a sub-optimal NCM mode. - -Previously we've attempted to work around the problem by -blacklisting the devices in the ECM class driver "cdc_ether", and -matching on the ECM class function in the vendor specific interface -driver. The latter has been used to switch back to the vendor -specific configuration when the driver is probed for a class -function. - -This workaround has several issues; -- class driver blacklists is additional maintanence cruft in an - unrelated driver -- class driver blacklists prevents users from optionally running - the devices in class mode -- each device needs double match entries in the vendor driver -- the initial probing as a class function slows down device - discovery - -Now these issues have become even worse with the introduction of -firmware supporting both NCM and ECM, where NCM ends up as the -default mode in Linux. To use the same workaround, we now have -to blacklist the devices in to two different class drivers and -add yet another match entry to the vendor specific driver. - -This patch implements an alternative workaround strategy - -independent of the interface drivers. It avoids adding a -blacklist to the cdc_ncm driver and will let us remove the -existing blacklist from the cdc_ether driver. - -As an additional bonus, removing the blacklists allow users to -select one of the other device modes if wanted. - -Signed-off-by: Bjørn Mork -Signed-off-by: David S. Miller ---- - drivers/net/usb/r8152.c | 113 ++++++++++++++++++++++++++++------------ - 1 file changed, 81 insertions(+), 32 deletions(-) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -9661,6 +9661,9 @@ static int rtl8152_probe(struct usb_inte - if (version == RTL_VER_UNKNOWN) - return -ENODEV; - -+ if (intf->cur_altsetting->desc.bInterfaceClass != USB_CLASS_VENDOR_SPEC) -+ return -ENODEV; -+ - if (!rtl_vendor_mode(intf)) - return -ENODEV; - -@@ -9861,43 +9864,35 @@ static void rtl8152_disconnect(struct us - } - } - --#define REALTEK_USB_DEVICE(vend, prod) { \ -- USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC), \ --}, \ --{ \ -- USB_DEVICE_AND_INTERFACE_INFO(vend, prod, USB_CLASS_COMM, \ -- USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE), \ --} - - /* table of devices that work with this driver */ - static const struct usb_device_id rtl8152_table[] = { - /* Realtek */ -- REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050), -- REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8053), -- REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152), -- REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153), -- REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8155), -- REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8156), -+ { USB_DEVICE(VENDOR_ID_REALTEK, 0x8050) }, -+ { USB_DEVICE(VENDOR_ID_REALTEK, 0x8053) }, -+ { USB_DEVICE(VENDOR_ID_REALTEK, 0x8152) }, -+ { USB_DEVICE(VENDOR_ID_REALTEK, 0x8153) }, -+ { USB_DEVICE(VENDOR_ID_REALTEK, 0x8155) }, -+ { USB_DEVICE(VENDOR_ID_REALTEK, 0x8156) }, - - /* Microsoft */ -- REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab), -- REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6), -- REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927), -- REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0c5e), -- REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101), -- REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f), -- REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3054), -- REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062), -- REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069), -- REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3082), -- REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205), -- REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c), -- REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214), -- REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x721e), -- REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0xa387), -- REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041), -- REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff), -- REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601), -+ { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab) }, -+ { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6) }, -+ { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927) }, -+ { USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101) }, -+ { USB_DEVICE(VENDOR_ID_LENOVO, 0x304f) }, -+ { USB_DEVICE(VENDOR_ID_LENOVO, 0x3054) }, -+ { USB_DEVICE(VENDOR_ID_LENOVO, 0x3062) }, -+ { USB_DEVICE(VENDOR_ID_LENOVO, 0x3069) }, -+ { USB_DEVICE(VENDOR_ID_LENOVO, 0x3082) }, -+ { USB_DEVICE(VENDOR_ID_LENOVO, 0x7205) }, -+ { USB_DEVICE(VENDOR_ID_LENOVO, 0x720c) }, -+ { USB_DEVICE(VENDOR_ID_LENOVO, 0x7214) }, -+ { USB_DEVICE(VENDOR_ID_LENOVO, 0x721e) }, -+ { USB_DEVICE(VENDOR_ID_LENOVO, 0xa387) }, -+ { USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041) }, -+ { USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff) }, -+ { USB_DEVICE(VENDOR_ID_TPLINK, 0x0601) }, - {} - }; - -@@ -9917,7 +9912,61 @@ static struct usb_driver rtl8152_driver - .disable_hub_initiated_lpm = 1, - }; - --module_usb_driver(rtl8152_driver); -+static int rtl8152_cfgselector_probe(struct usb_device *udev) -+{ -+ struct usb_host_config *c; -+ int i, num_configs; -+ -+ /* The vendor mode is not always config #1, so to find it out. */ -+ c = udev->config; -+ num_configs = udev->descriptor.bNumConfigurations; -+ for (i = 0; i < num_configs; (i++, c++)) { -+ struct usb_interface_descriptor *desc = NULL; -+ -+ if (!c->desc.bNumInterfaces) -+ continue; -+ desc = &c->intf_cache[0]->altsetting->desc; -+ if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC) -+ break; -+ } -+ -+ if (i == num_configs) -+ return -ENODEV; -+ -+ if (usb_set_configuration(udev, c->desc.bConfigurationValue)) { -+ dev_err(&udev->dev, "Failed to set configuration %d\n", -+ c->desc.bConfigurationValue); -+ return -ENODEV; -+ } -+ -+ return 0; -+} -+ -+static struct usb_device_driver rtl8152_cfgselector_driver = { -+ .name = MODULENAME "-cfgselector", -+ .probe = rtl8152_cfgselector_probe, -+ .id_table = rtl8152_table, -+ .generic_subclass = 1, -+}; -+ -+static int __init rtl8152_driver_init(void) -+{ -+ int ret; -+ -+ ret = usb_register_device_driver(&rtl8152_cfgselector_driver, THIS_MODULE); -+ if (ret) -+ return ret; -+ return usb_register(&rtl8152_driver); -+} -+ -+static void __exit rtl8152_driver_exit(void) -+{ -+ usb_deregister(&rtl8152_driver); -+ usb_deregister_device_driver(&rtl8152_cfgselector_driver); -+} -+ -+module_init(rtl8152_driver_init); -+module_exit(rtl8152_driver_exit); - - MODULE_AUTHOR(DRIVER_AUTHOR); - MODULE_DESCRIPTION(DRIVER_DESC); diff --git a/target/linux/generic/backport-6.1/795-v6.3-03-r8152-avoid-to-change-cfg-for-all-devices.patch b/target/linux/generic/backport-6.1/795-v6.3-03-r8152-avoid-to-change-cfg-for-all-devices.patch deleted file mode 100644 index a5b01f7b0829a3..00000000000000 --- a/target/linux/generic/backport-6.1/795-v6.3-03-r8152-avoid-to-change-cfg-for-all-devices.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 0d4cda805a183bbe523f2407edb5c14ade50b841 Mon Sep 17 00:00:00 2001 -From: Hayes Wang -Date: Tue, 17 Jan 2023 11:03:44 +0800 -Subject: [PATCH] r8152: avoid to change cfg for all devices - -The rtl8152_cfgselector_probe() should set the USB configuration to the -vendor mode only for the devices which the driver (r8152) supports. -Otherwise, no driver would be used for such devices. - -Fixes: ec51fbd1b8a2 ("r8152: add USB device driver for config selection") -Signed-off-by: Hayes Wang -Reviewed-by: Simon Horman -Signed-off-by: David S. Miller ---- - drivers/net/usb/r8152.c | 20 +++++++++++++++++--- - 1 file changed, 17 insertions(+), 3 deletions(-) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -9542,9 +9542,8 @@ static int rtl_fw_init(struct r8152 *tp) - return 0; - } - --u8 rtl8152_get_version(struct usb_interface *intf) -+static u8 __rtl_get_hw_ver(struct usb_device *udev) - { -- struct usb_device *udev = interface_to_usbdev(intf); - u32 ocp_data = 0; - __le32 *tmp; - u8 version; -@@ -9614,10 +9613,19 @@ u8 rtl8152_get_version(struct usb_interf - break; - default: - version = RTL_VER_UNKNOWN; -- dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data); -+ dev_info(&udev->dev, "Unknown version 0x%04x\n", ocp_data); - break; - } - -+ return version; -+} -+ -+u8 rtl8152_get_version(struct usb_interface *intf) -+{ -+ u8 version; -+ -+ version = __rtl_get_hw_ver(interface_to_usbdev(intf)); -+ - dev_dbg(&intf->dev, "Detected version 0x%04x\n", version); - - return version; -@@ -9917,6 +9925,12 @@ static int rtl8152_cfgselector_probe(str - struct usb_host_config *c; - int i, num_configs; - -+ /* Switch the device to vendor mode, if and only if the vendor mode -+ * driver supports it. -+ */ -+ if (__rtl_get_hw_ver(udev) == RTL_VER_UNKNOWN) -+ return 0; -+ - /* The vendor mode is not always config #1, so to find it out. */ - c = udev->config; - num_configs = udev->descriptor.bNumConfigurations; diff --git a/target/linux/generic/backport-6.1/795-v6.3-04-r8152-remove-rtl_vendor_mode-function.patch b/target/linux/generic/backport-6.1/795-v6.3-04-r8152-remove-rtl_vendor_mode-function.patch deleted file mode 100644 index f97750861c3e4d..00000000000000 --- a/target/linux/generic/backport-6.1/795-v6.3-04-r8152-remove-rtl_vendor_mode-function.patch +++ /dev/null @@ -1,71 +0,0 @@ -From 95a4c1d617b92cdc4522297741b56e8f6cd01a1e Mon Sep 17 00:00:00 2001 -From: Hayes Wang -Date: Thu, 19 Jan 2023 15:40:42 +0800 -Subject: [PATCH] r8152: remove rtl_vendor_mode function - -After commit ec51fbd1b8a2 ("r8152: add USB device driver for -config selection"), the code about changing USB configuration -in rtl_vendor_mode() wouldn't be run anymore. Therefore, the -function could be removed. - -Signed-off-by: Hayes Wang -Signed-off-by: Jakub Kicinski ---- - drivers/net/usb/r8152.c | 39 +-------------------------------------- - 1 file changed, 1 insertion(+), 38 deletions(-) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -8274,43 +8274,6 @@ static bool rtl_check_vendor_ok(struct u - return true; - } - --static bool rtl_vendor_mode(struct usb_interface *intf) --{ -- struct usb_host_interface *alt = intf->cur_altsetting; -- struct usb_device *udev; -- struct usb_host_config *c; -- int i, num_configs; -- -- if (alt->desc.bInterfaceClass == USB_CLASS_VENDOR_SPEC) -- return rtl_check_vendor_ok(intf); -- -- /* The vendor mode is not always config #1, so to find it out. */ -- udev = interface_to_usbdev(intf); -- c = udev->config; -- num_configs = udev->descriptor.bNumConfigurations; -- if (num_configs < 2) -- return false; -- -- for (i = 0; i < num_configs; (i++, c++)) { -- struct usb_interface_descriptor *desc = NULL; -- -- if (c->desc.bNumInterfaces > 0) -- desc = &c->intf_cache[0]->altsetting->desc; -- else -- continue; -- -- if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC) { -- usb_driver_set_configuration(udev, c->desc.bConfigurationValue); -- break; -- } -- } -- -- if (i == num_configs) -- dev_err(&intf->dev, "Unexpected Device\n"); -- -- return false; --} -- - static int rtl8152_pre_reset(struct usb_interface *intf) - { - struct r8152 *tp = usb_get_intfdata(intf); -@@ -9672,7 +9635,7 @@ static int rtl8152_probe(struct usb_inte - if (intf->cur_altsetting->desc.bInterfaceClass != USB_CLASS_VENDOR_SPEC) - return -ENODEV; - -- if (!rtl_vendor_mode(intf)) -+ if (!rtl_check_vendor_ok(intf)) - return -ENODEV; - - usb_reset_device(udev); diff --git a/target/linux/generic/backport-6.1/795-v6.3-05-r8152-reduce-the-control-transfer-of-rtl8152_get_ver.patch b/target/linux/generic/backport-6.1/795-v6.3-05-r8152-reduce-the-control-transfer-of-rtl8152_get_ver.patch index 421f2c7f8f51dc..565fbb3074f979 100644 --- a/target/linux/generic/backport-6.1/795-v6.3-05-r8152-reduce-the-control-transfer-of-rtl8152_get_ver.patch +++ b/target/linux/generic/backport-6.1/795-v6.3-05-r8152-reduce-the-control-transfer-of-rtl8152_get_ver.patch @@ -18,7 +18,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c -@@ -9624,20 +9624,21 @@ static int rtl8152_probe(struct usb_inte +@@ -9638,20 +9638,21 @@ static int rtl8152_probe(struct usb_inte const struct usb_device_id *id) { struct usb_device *udev = interface_to_usbdev(intf); diff --git a/target/linux/generic/backport-6.1/795-v6.4-07-r8152-fix-the-autosuspend-doesn-t-work.patch b/target/linux/generic/backport-6.1/795-v6.4-07-r8152-fix-the-autosuspend-doesn-t-work.patch deleted file mode 100644 index b4d5b8bdb91519..00000000000000 --- a/target/linux/generic/backport-6.1/795-v6.4-07-r8152-fix-the-autosuspend-doesn-t-work.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 0fbd79c01a9a657348f7032df70c57a406468c86 Mon Sep 17 00:00:00 2001 -From: Hayes Wang -Date: Tue, 2 May 2023 11:36:27 +0800 -Subject: [PATCH] r8152: fix the autosuspend doesn't work - -Set supports_autosuspend = 1 for the rtl8152_cfgselector_driver. - -Fixes: ec51fbd1b8a2 ("r8152: add USB device driver for config selection") -Signed-off-by: Hayes Wang -Signed-off-by: David S. Miller ---- - drivers/net/usb/r8152.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -9925,6 +9925,7 @@ static struct usb_device_driver rtl8152_ - .probe = rtl8152_cfgselector_probe, - .id_table = rtl8152_table, - .generic_subclass = 1, -+ .supports_autosuspend = 1, - }; - - static int __init rtl8152_driver_init(void) diff --git a/target/linux/generic/backport-6.1/795-v6.6-09-r8152-set-bp-in-bulk.patch b/target/linux/generic/backport-6.1/795-v6.6-09-r8152-set-bp-in-bulk.patch index 485a005b174bdd..bc70c5af02c708 100644 --- a/target/linux/generic/backport-6.1/795-v6.6-09-r8152-set-bp-in-bulk.patch +++ b/target/linux/generic/backport-6.1/795-v6.6-09-r8152-set-bp-in-bulk.patch @@ -15,7 +15,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c -@@ -3984,29 +3984,10 @@ static void rtl_reset_bmu(struct r8152 * +@@ -3990,29 +3990,10 @@ static void rtl_reset_bmu(struct r8152 * /* Clear the bp to stop the firmware before loading a new one */ static void rtl_clear_bp(struct r8152 *tp, u16 type) { @@ -48,7 +48,7 @@ Signed-off-by: Jakub Kicinski case RTL_VER_08: case RTL_VER_09: case RTL_VER_10: -@@ -4014,32 +3995,31 @@ static void rtl_clear_bp(struct r8152 *t +@@ -4020,32 +4001,31 @@ static void rtl_clear_bp(struct r8152 *t case RTL_VER_12: case RTL_VER_13: case RTL_VER_15: @@ -100,7 +100,7 @@ Signed-off-by: Jakub Kicinski /* wait 3 ms to make sure the firmware is stopped */ usleep_range(3000, 6000); -@@ -5016,10 +4996,9 @@ static void rtl8152_fw_phy_nc_apply(stru +@@ -5022,10 +5002,9 @@ static void rtl8152_fw_phy_nc_apply(stru static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac) { @@ -112,7 +112,7 @@ Signed-off-by: Jakub Kicinski switch (__le32_to_cpu(mac->blk_hdr.type)) { case RTL_FW_PLA: -@@ -5061,12 +5040,8 @@ static void rtl8152_fw_mac_apply(struct +@@ -5067,12 +5046,8 @@ static void rtl8152_fw_mac_apply(struct ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr), __le16_to_cpu(mac->bp_ba_value)); diff --git a/target/linux/generic/backport-6.1/795-v6.6-10-eth-r8152-try-to-use-a-normal-budget.patch b/target/linux/generic/backport-6.1/795-v6.6-10-eth-r8152-try-to-use-a-normal-budget.patch index 864671bb32f16e..d7fdcdb2c63000 100644 --- a/target/linux/generic/backport-6.1/795-v6.6-10-eth-r8152-try-to-use-a-normal-budget.patch +++ b/target/linux/generic/backport-6.1/795-v6.6-10-eth-r8152-try-to-use-a-normal-budget.patch @@ -27,7 +27,7 @@ Signed-off-by: Jakub Kicinski --- a/drivers/net/usb/r8152.c +++ b/drivers/net/usb/r8152.c -@@ -9770,8 +9770,7 @@ static int rtl8152_probe(struct usb_inte +@@ -9784,8 +9784,7 @@ static int rtl8152_probe(struct usb_inte usb_set_intfdata(intf, tp); diff --git a/target/linux/generic/backport-6.1/795-v6.6-11-r8152-add-vendor-device-ID-pair-for-D-Link-DUB-E250.patch b/target/linux/generic/backport-6.1/795-v6.6-11-r8152-add-vendor-device-ID-pair-for-D-Link-DUB-E250.patch deleted file mode 100644 index ab6563d5c43628..00000000000000 --- a/target/linux/generic/backport-6.1/795-v6.6-11-r8152-add-vendor-device-ID-pair-for-D-Link-DUB-E250.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 72f93a3136ee18fd59fa6579f84c07e93424681e Mon Sep 17 00:00:00 2001 -From: Antonio Napolitano -Date: Sat, 26 Aug 2023 01:05:50 +0200 -Subject: [PATCH] r8152: add vendor/device ID pair for D-Link DUB-E250 - -The D-Link DUB-E250 is an RTL8156 based 2.5G Ethernet controller. - -Add the vendor and product ID values to the driver. This makes Ethernet -work with the adapter. - -Signed-off-by: Antonio Napolitano -Link: https://lore.kernel.org/r/CV200KJEEUPC.WPKAHXCQJ05I@mercurius -Signed-off-by: Jakub Kicinski ---- - drivers/net/usb/r8152.c | 1 + - include/linux/usb/r8152.h | 1 + - 2 files changed, 2 insertions(+) - - ---- a/include/linux/usb/r8152.h -+++ b/include/linux/usb/r8152.h -@@ -29,6 +29,7 @@ - #define VENDOR_ID_LINKSYS 0x13b1 - #define VENDOR_ID_NVIDIA 0x0955 - #define VENDOR_ID_TPLINK 0x2357 -+#define VENDOR_ID_DLINK 0x2001 - - #if IS_REACHABLE(CONFIG_USB_RTL8152) - extern u8 rtl8152_get_version(struct usb_interface *intf); ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -9846,6 +9846,7 @@ static const struct usb_device_id rtl815 - { USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041) }, - { USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff) }, - { USB_DEVICE(VENDOR_ID_TPLINK, 0x0601) }, -+ { USB_DEVICE(VENDOR_ID_DLINK, 0xb301) }, - {} - }; - diff --git a/target/linux/generic/backport-6.1/795-v6.6-12-r8152-Rename-RTL8152_UNPLUG-to-RTL8152_INACCESSIBLE.patch b/target/linux/generic/backport-6.1/795-v6.6-12-r8152-Rename-RTL8152_UNPLUG-to-RTL8152_INACCESSIBLE.patch deleted file mode 100644 index 480a60212ae611..00000000000000 --- a/target/linux/generic/backport-6.1/795-v6.6-12-r8152-Rename-RTL8152_UNPLUG-to-RTL8152_INACCESSIBLE.patch +++ /dev/null @@ -1,447 +0,0 @@ -From 715f67f33af45ce2cc3a5b1ef133cc8c8e7787b0 Mon Sep 17 00:00:00 2001 -From: Douglas Anderson -Date: Fri, 20 Oct 2023 14:06:58 -0700 -Subject: [PATCH] r8152: Rename RTL8152_UNPLUG to RTL8152_INACCESSIBLE - -Whenever the RTL8152_UNPLUG is set that just tells the driver that all -accesses will fail and we should just immediately bail. A future patch -will use this same concept at a time when the driver hasn't actually -been unplugged but is about to be reset. Rename the flag in -preparation for the future patch. - -This is a no-op change and just a search and replace. - -Signed-off-by: Douglas Anderson -Reviewed-by: Grant Grundler -Signed-off-by: David S. Miller ---- - drivers/net/usb/r8152.c | 96 ++++++++++++++++++++--------------------- - 1 file changed, 48 insertions(+), 48 deletions(-) - ---- a/drivers/net/usb/r8152.c -+++ b/drivers/net/usb/r8152.c -@@ -763,7 +763,7 @@ enum rtl_register_content { - - /* rtl8152 flags */ - enum rtl8152_flags { -- RTL8152_UNPLUG = 0, -+ RTL8152_INACCESSIBLE = 0, - RTL8152_SET_RX_MODE, - WORK_ENABLE, - RTL8152_LINK_CHG, -@@ -1244,7 +1244,7 @@ int set_registers(struct r8152 *tp, u16 - static void rtl_set_unplug(struct r8152 *tp) - { - if (tp->udev->state == USB_STATE_NOTATTACHED) { -- set_bit(RTL8152_UNPLUG, &tp->flags); -+ set_bit(RTL8152_INACCESSIBLE, &tp->flags); - smp_mb__after_atomic(); - } - } -@@ -1255,7 +1255,7 @@ static int generic_ocp_read(struct r8152 - u16 limit = 64; - int ret = 0; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return -ENODEV; - - /* both size and indix must be 4 bytes align */ -@@ -1299,7 +1299,7 @@ static int generic_ocp_write(struct r815 - u16 byteen_start, byteen_end, byen; - u16 limit = 512; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return -ENODEV; - - /* both size and indix must be 4 bytes align */ -@@ -1536,7 +1536,7 @@ static int read_mii_word(struct net_devi - struct r8152 *tp = netdev_priv(netdev); - int ret; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return -ENODEV; - - if (phy_id != R8152_PHY_ID) -@@ -1552,7 +1552,7 @@ void write_mii_word(struct net_device *n - { - struct r8152 *tp = netdev_priv(netdev); - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - if (phy_id != R8152_PHY_ID) -@@ -1757,7 +1757,7 @@ static void read_bulk_callback(struct ur - if (!tp) - return; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - if (!test_bit(WORK_ENABLE, &tp->flags)) -@@ -1849,7 +1849,7 @@ static void write_bulk_callback(struct u - if (!test_bit(WORK_ENABLE, &tp->flags)) - return; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - if (!skb_queue_empty(&tp->tx_queue)) -@@ -1870,7 +1870,7 @@ static void intr_callback(struct urb *ur - if (!test_bit(WORK_ENABLE, &tp->flags)) - return; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - switch (status) { -@@ -2614,7 +2614,7 @@ static void bottom_half(struct tasklet_s - { - struct r8152 *tp = from_tasklet(tp, t, tx_tl); - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - if (!test_bit(WORK_ENABLE, &tp->flags)) -@@ -2657,7 +2657,7 @@ int r8152_submit_rx(struct r8152 *tp, st - int ret; - - /* The rx would be stopped, so skip submitting */ -- if (test_bit(RTL8152_UNPLUG, &tp->flags) || -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) || - !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) - return 0; - -@@ -3057,7 +3057,7 @@ static int rtl_enable(struct r8152 *tp) - - static int rtl8152_enable(struct r8152 *tp) - { -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return -ENODEV; - - set_tx_qlen(tp); -@@ -3144,7 +3144,7 @@ static int rtl8153_enable(struct r8152 * - { - u32 ocp_data; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return -ENODEV; - - set_tx_qlen(tp); -@@ -3176,7 +3176,7 @@ static void rtl_disable(struct r8152 *tp - u32 ocp_data; - int i; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) { -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { - rtl_drop_queued_tx(tp); - return; - } -@@ -3630,7 +3630,7 @@ static u16 r8153_phy_status(struct r8152 - } - - msleep(20); -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - break; - } - -@@ -3662,7 +3662,7 @@ static void r8153b_ups_en(struct r8152 * - int i; - - for (i = 0; i < 500; i++) { -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & - AUTOLOAD_DONE) -@@ -3704,7 +3704,7 @@ static void r8153c_ups_en(struct r8152 * - int i; - - for (i = 0; i < 500; i++) { -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & - AUTOLOAD_DONE) -@@ -4049,8 +4049,8 @@ static int rtl_phy_patch_request(struct - for (i = 0; wait && i < 5000; i++) { - u32 ocp_data; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -- break; -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) -+ return -ENODEV; - - usleep_range(1000, 2000); - ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT); -@@ -6008,7 +6008,7 @@ static int rtl8156_enable(struct r8152 * - u32 ocp_data; - u16 speed; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return -ENODEV; - - r8156_fc_parameter(tp); -@@ -6066,7 +6066,7 @@ static int rtl8156b_enable(struct r8152 - u32 ocp_data; - u16 speed; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return -ENODEV; - - set_tx_qlen(tp); -@@ -6252,7 +6252,7 @@ out: - - static void rtl8152_up(struct r8152 *tp) - { -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - r8152_aldps_en(tp, false); -@@ -6262,7 +6262,7 @@ static void rtl8152_up(struct r8152 *tp) - - static void rtl8152_down(struct r8152 *tp) - { -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) { -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { - rtl_drop_queued_tx(tp); - return; - } -@@ -6277,7 +6277,7 @@ static void rtl8153_up(struct r8152 *tp) - { - u32 ocp_data; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - r8153_u1u2en(tp, false); -@@ -6317,7 +6317,7 @@ static void rtl8153_down(struct r8152 *t - { - u32 ocp_data; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) { -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { - rtl_drop_queued_tx(tp); - return; - } -@@ -6338,7 +6338,7 @@ static void rtl8153b_up(struct r8152 *tp - { - u32 ocp_data; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - r8153b_u1u2en(tp, false); -@@ -6362,7 +6362,7 @@ static void rtl8153b_down(struct r8152 * - { - u32 ocp_data; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) { -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { - rtl_drop_queued_tx(tp); - return; - } -@@ -6399,7 +6399,7 @@ static void rtl8153c_up(struct r8152 *tp - { - u32 ocp_data; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - r8153b_u1u2en(tp, false); -@@ -6480,7 +6480,7 @@ static void rtl8156_up(struct r8152 *tp) - { - u32 ocp_data; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - r8153b_u1u2en(tp, false); -@@ -6553,7 +6553,7 @@ static void rtl8156_down(struct r8152 *t - { - u32 ocp_data; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) { -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { - rtl_drop_queued_tx(tp); - return; - } -@@ -6691,7 +6691,7 @@ static void rtl_work_func_t(struct work_ - /* If the device is unplugged or !netif_running(), the workqueue - * doesn't need to wake the device, and could return directly. - */ -- if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) || !netif_running(tp->netdev)) - return; - - if (usb_autopm_get_interface(tp->intf) < 0) -@@ -6730,7 +6730,7 @@ static void rtl_hw_phy_work_func_t(struc - { - struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work); - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - if (usb_autopm_get_interface(tp->intf) < 0) -@@ -6857,7 +6857,7 @@ static int rtl8152_close(struct net_devi - netif_stop_queue(netdev); - - res = usb_autopm_get_interface(tp->intf); -- if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { -+ if (res < 0 || test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { - rtl_drop_queued_tx(tp); - rtl_stop_rx(tp); - } else { -@@ -6890,7 +6890,7 @@ static void r8152b_init(struct r8152 *tp - u32 ocp_data; - u16 data; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - data = r8152_mdio_read(tp, MII_BMCR); -@@ -6934,7 +6934,7 @@ static void r8153_init(struct r8152 *tp) - u16 data; - int i; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - r8153_u1u2en(tp, false); -@@ -6945,7 +6945,7 @@ static void r8153_init(struct r8152 *tp) - break; - - msleep(20); -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - break; - } - -@@ -7074,7 +7074,7 @@ static void r8153b_init(struct r8152 *tp - u16 data; - int i; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - r8153b_u1u2en(tp, false); -@@ -7085,7 +7085,7 @@ static void r8153b_init(struct r8152 *tp - break; - - msleep(20); -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - break; - } - -@@ -7156,7 +7156,7 @@ static void r8153c_init(struct r8152 *tp - u16 data; - int i; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - r8153b_u1u2en(tp, false); -@@ -7176,7 +7176,7 @@ static void r8153c_init(struct r8152 *tp - break; - - msleep(20); -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - } - -@@ -8005,7 +8005,7 @@ static void r8156_init(struct r8152 *tp) - u16 data; - int i; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP); -@@ -8026,7 +8026,7 @@ static void r8156_init(struct r8152 *tp) - break; - - msleep(20); -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - } - -@@ -8101,7 +8101,7 @@ static void r8156b_init(struct r8152 *tp - u16 data; - int i; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP); -@@ -8135,7 +8135,7 @@ static void r8156b_init(struct r8152 *tp - break; - - msleep(20); -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - } - -@@ -9164,7 +9164,7 @@ static int rtl8152_ioctl(struct net_devi - struct mii_ioctl_data *data = if_mii(rq); - int res; - -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return -ENODEV; - - res = usb_autopm_get_interface(tp->intf); -@@ -9266,7 +9266,7 @@ static const struct net_device_ops rtl81 - - static void rtl8152_unload(struct r8152 *tp) - { -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - if (tp->version != RTL_VER_01) -@@ -9275,7 +9275,7 @@ static void rtl8152_unload(struct r8152 - - static void rtl8153_unload(struct r8152 *tp) - { -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - r8153_power_cut_en(tp, false); -@@ -9283,7 +9283,7 @@ static void rtl8153_unload(struct r8152 - - static void rtl8153b_unload(struct r8152 *tp) - { -- if (test_bit(RTL8152_UNPLUG, &tp->flags)) -+ if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) - return; - - r8153b_power_cut_en(tp, false); diff --git a/target/linux/generic/backport-6.1/795-v6.6-13-r8152-Block-future-register-access-if-register-acces.patch b/target/linux/generic/backport-6.1/795-v6.6-13-r8152-Block-future-register-access-if-register-acces.patch index 2cbe3650352d6b..8901767be5239e 100644 --- a/target/linux/generic/backport-6.1/795-v6.6-13-r8152-Block-future-register-access-if-register-acces.patch +++ b/target/linux/generic/backport-6.1/795-v6.6-13-r8152-Block-future-register-access-if-register-acces.patch @@ -232,7 +232,7 @@ Signed-off-by: David S. Miller } static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, -@@ -8261,7 +8355,7 @@ static int rtl8152_pre_reset(struct usb_ +@@ -8275,7 +8369,7 @@ static int rtl8152_pre_reset(struct usb_ struct r8152 *tp = usb_get_intfdata(intf); struct net_device *netdev; @@ -241,7 +241,7 @@ Signed-off-by: David S. Miller return 0; netdev = tp->netdev; -@@ -8276,7 +8370,9 @@ static int rtl8152_pre_reset(struct usb_ +@@ -8290,7 +8384,9 @@ static int rtl8152_pre_reset(struct usb_ napi_disable(&tp->napi); if (netif_carrier_ok(netdev)) { mutex_lock(&tp->control); @@ -251,7 +251,7 @@ Signed-off-by: David S. Miller mutex_unlock(&tp->control); } -@@ -8289,9 +8385,11 @@ static int rtl8152_post_reset(struct usb +@@ -8303,9 +8399,11 @@ static int rtl8152_post_reset(struct usb struct net_device *netdev; struct sockaddr sa; @@ -264,7 +264,7 @@ Signed-off-by: David S. Miller /* reset the MAC address in case of policy change */ if (determine_ethernet_addr(tp, &sa) >= 0) { rtnl_lock(); -@@ -9493,17 +9591,29 @@ static u8 __rtl_get_hw_ver(struct usb_de +@@ -9507,17 +9605,29 @@ static u8 __rtl_get_hw_ver(struct usb_de __le32 *tmp; u8 version; int ret; @@ -300,7 +300,7 @@ Signed-off-by: David S. Miller kfree(tmp); -@@ -9602,25 +9712,14 @@ static bool rtl8152_supports_lenovo_macp +@@ -9616,25 +9726,14 @@ static bool rtl8152_supports_lenovo_macp return 0; } @@ -328,7 +328,7 @@ Signed-off-by: David S. Miller usb_reset_device(udev); netdev = alloc_etherdev(sizeof(struct r8152)); if (!netdev) { -@@ -9783,10 +9882,20 @@ static int rtl8152_probe(struct usb_inte +@@ -9797,10 +9896,20 @@ static int rtl8152_probe(struct usb_inte else device_set_wakeup_enable(&udev->dev, false); @@ -349,7 +349,7 @@ Signed-off-by: David S. Miller out1: tasklet_kill(&tp->tx_tl); cancel_delayed_work_sync(&tp->hw_phy_work); -@@ -9795,10 +9904,46 @@ out1: +@@ -9809,10 +9918,46 @@ out1: rtl8152_release_firmware(tp); usb_set_intfdata(intf, NULL); out: diff --git a/target/linux/generic/hack-5.10/204-module_strip.patch b/target/linux/generic/hack-5.10/204-module_strip.patch index 82936749681bc7..17e34524c1a741 100644 --- a/target/linux/generic/hack-5.10/204-module_strip.patch +++ b/target/linux/generic/hack-5.10/204-module_strip.patch @@ -104,7 +104,7 @@ Signed-off-by: Felix Fietkau config MODULES_TREE_LOOKUP --- a/kernel/module.c +++ b/kernel/module.c -@@ -3251,9 +3251,11 @@ static int setup_load_info(struct load_i +@@ -3262,9 +3262,11 @@ static int setup_load_info(struct load_i static int check_modinfo(struct module *mod, struct load_info *info, int flags) { @@ -117,7 +117,7 @@ Signed-off-by: Felix Fietkau if (flags & MODULE_INIT_IGNORE_VERMAGIC) modmagic = NULL; -@@ -3274,6 +3276,7 @@ static int check_modinfo(struct module * +@@ -3285,6 +3287,7 @@ static int check_modinfo(struct module * mod->name); add_taint_module(mod, TAINT_OOT_MODULE, LOCKDEP_STILL_OK); } diff --git a/target/linux/generic/hack-5.10/259-regmap_dynamic.patch b/target/linux/generic/hack-5.10/259-regmap_dynamic.patch index bc81a7285c007a..cf55076ecb3682 100644 --- a/target/linux/generic/hack-5.10/259-regmap_dynamic.patch +++ b/target/linux/generic/hack-5.10/259-regmap_dynamic.patch @@ -116,7 +116,7 @@ Signed-off-by: Felix Fietkau #include #include #include -@@ -3298,3 +3299,5 @@ static int __init regmap_initcall(void) +@@ -3300,3 +3301,5 @@ static int __init regmap_initcall(void) return 0; } postcore_initcall(regmap_initcall); diff --git a/target/linux/generic/hack-5.10/301-mips_image_cmdline_hack.patch b/target/linux/generic/hack-5.10/301-mips_image_cmdline_hack.patch index ea72094cee02aa..f6b44b2a403b39 100644 --- a/target/linux/generic/hack-5.10/301-mips_image_cmdline_hack.patch +++ b/target/linux/generic/hack-5.10/301-mips_image_cmdline_hack.patch @@ -10,7 +10,7 @@ Signed-off-by: Gabor Juhos --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -1171,6 +1171,10 @@ config MIPS_MSC +@@ -1172,6 +1172,10 @@ config MIPS_MSC config SYNC_R4K bool diff --git a/target/linux/generic/hack-5.10/661-use_fq_codel_by_default.patch b/target/linux/generic/hack-5.10/661-use_fq_codel_by_default.patch index 4fbbfa63373193..a18daff5b0317c 100644 --- a/target/linux/generic/hack-5.10/661-use_fq_codel_by_default.patch +++ b/target/linux/generic/hack-5.10/661-use_fq_codel_by_default.patch @@ -44,7 +44,7 @@ Signed-off-by: Felix Fietkau device, it has to decide which ones to send first, which ones to --- a/net/sched/sch_api.c +++ b/net/sched/sch_api.c -@@ -2310,7 +2310,7 @@ static int __init pktsched_init(void) +@@ -2337,7 +2337,7 @@ static int __init pktsched_init(void) return err; } diff --git a/target/linux/generic/hack-5.10/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch b/target/linux/generic/hack-5.10/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch index 37aa2d007a3333..89e48e9aadf564 100644 --- a/target/linux/generic/hack-5.10/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch +++ b/target/linux/generic/hack-5.10/711-net-dsa-mv88e6xxx-disable-ATU-violation.patch @@ -1,6 +1,6 @@ --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c -@@ -2716,6 +2716,9 @@ static int mv88e6xxx_setup_port(struct m +@@ -2726,6 +2726,9 @@ static int mv88e6xxx_setup_port(struct m if (dsa_is_cpu_port(ds, port)) reg = 0; diff --git a/target/linux/generic/hack-5.10/800-GPIO-add-named-gpio-exports.patch b/target/linux/generic/hack-5.10/800-GPIO-add-named-gpio-exports.patch index 6367ee9a0b6ad6..0a041c783801e0 100644 --- a/target/linux/generic/hack-5.10/800-GPIO-add-named-gpio-exports.patch +++ b/target/linux/generic/hack-5.10/800-GPIO-add-named-gpio-exports.patch @@ -129,7 +129,7 @@ Signed-off-by: John Crispin { --- a/drivers/gpio/gpiolib-sysfs.c +++ b/drivers/gpio/gpiolib-sysfs.c -@@ -572,7 +572,7 @@ static struct class gpio_class = { +@@ -575,7 +575,7 @@ static struct class gpio_class = { * * Returns zero on success, else an error. */ @@ -138,7 +138,7 @@ Signed-off-by: John Crispin { struct gpio_chip *chip; struct gpio_device *gdev; -@@ -634,6 +634,8 @@ int gpiod_export(struct gpio_desc *desc, +@@ -637,6 +637,8 @@ int gpiod_export(struct gpio_desc *desc, offset = gpio_chip_hwgpio(desc); if (chip->names && chip->names[offset]) ioname = chip->names[offset]; @@ -147,7 +147,7 @@ Signed-off-by: John Crispin dev = device_create_with_groups(&gpio_class, &gdev->dev, MKDEV(0, 0), data, gpio_groups, -@@ -655,6 +657,12 @@ err_unlock: +@@ -658,6 +660,12 @@ err_unlock: gpiod_dbg(desc, "%s: status %d\n", __func__, status); return status; } diff --git a/target/linux/generic/hack-5.10/901-debloat_sock_diag.patch b/target/linux/generic/hack-5.10/901-debloat_sock_diag.patch index 3c10805e9d2049..fdedc957858b95 100644 --- a/target/linux/generic/hack-5.10/901-debloat_sock_diag.patch +++ b/target/linux/generic/hack-5.10/901-debloat_sock_diag.patch @@ -77,7 +77,7 @@ Signed-off-by: Felix Fietkau struct dst_entry *__sk_dst_check(struct sock *sk, u32 cookie) { struct dst_entry *dst = __sk_dst_get(sk); -@@ -1837,9 +1851,11 @@ static void __sk_free(struct sock *sk) +@@ -1838,9 +1852,11 @@ static void __sk_free(struct sock *sk) if (likely(sk->sk_net_refcnt)) sock_inuse_add(sock_net(sk), -1); diff --git a/target/linux/generic/hack-5.10/902-debloat_proc.patch b/target/linux/generic/hack-5.10/902-debloat_proc.patch index 4819b6002dd16d..a7e3d843159755 100644 --- a/target/linux/generic/hack-5.10/902-debloat_proc.patch +++ b/target/linux/generic/hack-5.10/902-debloat_proc.patch @@ -235,7 +235,7 @@ Signed-off-by: Felix Fietkau if (!pe) --- a/mm/vmalloc.c +++ b/mm/vmalloc.c -@@ -3572,6 +3572,8 @@ static const struct seq_operations vmall +@@ -3576,6 +3576,8 @@ static const struct seq_operations vmall static int __init proc_vmalloc_init(void) { @@ -330,7 +330,7 @@ Signed-off-by: Felix Fietkau --- a/net/core/sock.c +++ b/net/core/sock.c -@@ -3724,6 +3724,8 @@ static __net_initdata struct pernet_oper +@@ -3725,6 +3725,8 @@ static __net_initdata struct pernet_oper static int __init proto_init(void) { diff --git a/target/linux/generic/hack-5.10/920-device_tree_cmdline.patch b/target/linux/generic/hack-5.10/920-device_tree_cmdline.patch index 27d4d7f1e5e25d..efd8dbeb2910b3 100644 --- a/target/linux/generic/hack-5.10/920-device_tree_cmdline.patch +++ b/target/linux/generic/hack-5.10/920-device_tree_cmdline.patch @@ -1,6 +1,6 @@ --- a/drivers/of/fdt.c +++ b/drivers/of/fdt.c -@@ -1055,6 +1055,9 @@ int __init early_init_dt_scan_chosen(uns +@@ -1054,6 +1054,9 @@ int __init early_init_dt_scan_chosen(uns p = of_get_flat_dt_prop(node, "bootargs", &l); if (p != NULL && l > 0) strlcpy(data, p, min(l, COMMAND_LINE_SIZE)); diff --git a/target/linux/generic/hack-5.10/994-mhi-use-irq-flags.patch b/target/linux/generic/hack-5.10/994-mhi-use-irq-flags.patch index b55ad97821d370..a0e14a702b8beb 100644 --- a/target/linux/generic/hack-5.10/994-mhi-use-irq-flags.patch +++ b/target/linux/generic/hack-5.10/994-mhi-use-irq-flags.patch @@ -30,7 +30,7 @@ dev_err(dev, "Error requesting irq:%d for ev:%d\n", --- a/include/linux/mhi.h +++ b/include/linux/mhi.h -@@ -353,6 +353,7 @@ struct mhi_controller_config { +@@ -354,6 +354,7 @@ struct mhi_controller_config { * @fbc_download: MHI host needs to do complete image transfer (optional) * @pre_init: MHI host needs to do pre-initialization before power up * @wake_set: Device wakeup set flag @@ -38,7 +38,7 @@ * * Fields marked as (required) need to be populated by the controller driver * before calling mhi_register_controller(). For the fields marked as (optional) -@@ -442,6 +443,7 @@ struct mhi_controller { +@@ -444,6 +445,7 @@ struct mhi_controller { bool fbc_download; bool pre_init; bool wake_set; diff --git a/target/linux/generic/hack-5.10/995-add-support-for-forced-PM-resume.patch b/target/linux/generic/hack-5.10/995-add-support-for-forced-PM-resume.patch index bcbe99cc2452e6..9524e356234e52 100644 --- a/target/linux/generic/hack-5.10/995-add-support-for-forced-PM-resume.patch +++ b/target/linux/generic/hack-5.10/995-add-support-for-forced-PM-resume.patch @@ -1,6 +1,6 @@ --- a/drivers/bus/mhi/host/pm.c +++ b/drivers/bus/mhi/host/pm.c -@@ -768,7 +768,7 @@ int mhi_pm_suspend(struct mhi_controller +@@ -773,7 +773,7 @@ int mhi_pm_suspend(struct mhi_controller } EXPORT_SYMBOL_GPL(mhi_pm_suspend); @@ -9,7 +9,7 @@ { struct mhi_chan *itr, *tmp; struct device *dev = &mhi_cntrl->mhi_dev->dev; -@@ -784,6 +784,13 @@ int mhi_pm_resume(struct mhi_controller +@@ -789,6 +789,13 @@ int mhi_pm_resume(struct mhi_controller if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) return -EIO; @@ -23,7 +23,7 @@ /* Notify clients about exiting LPM */ list_for_each_entry_safe(itr, tmp, &mhi_cntrl->lpm_chans, node) { -@@ -824,8 +831,19 @@ int mhi_pm_resume(struct mhi_controller +@@ -829,8 +836,19 @@ int mhi_pm_resume(struct mhi_controller return 0; } @@ -59,7 +59,7 @@ ret = mhi_force_rddm_mode(ab_pci->mhi_ctrl); --- a/include/linux/mhi.h +++ b/include/linux/mhi.h -@@ -647,6 +647,19 @@ int mhi_pm_suspend(struct mhi_controller +@@ -649,6 +649,19 @@ int mhi_pm_suspend(struct mhi_controller int mhi_pm_resume(struct mhi_controller *mhi_cntrl); /** diff --git a/target/linux/generic/hack-5.15/259-regmap_dynamic.patch b/target/linux/generic/hack-5.15/259-regmap_dynamic.patch index 76a5ace6f31536..e0820ccfc0dbf3 100644 --- a/target/linux/generic/hack-5.15/259-regmap_dynamic.patch +++ b/target/linux/generic/hack-5.15/259-regmap_dynamic.patch @@ -125,7 +125,7 @@ Signed-off-by: Felix Fietkau #include #include #include -@@ -3358,3 +3359,5 @@ static int __init regmap_initcall(void) +@@ -3360,3 +3361,5 @@ static int __init regmap_initcall(void) return 0; } postcore_initcall(regmap_initcall); diff --git a/target/linux/generic/hack-5.15/301-mips_image_cmdline_hack.patch b/target/linux/generic/hack-5.15/301-mips_image_cmdline_hack.patch index 785fc1273c3faf..c88b864da56787 100644 --- a/target/linux/generic/hack-5.15/301-mips_image_cmdline_hack.patch +++ b/target/linux/generic/hack-5.15/301-mips_image_cmdline_hack.patch @@ -10,7 +10,7 @@ Signed-off-by: Gabor Juhos --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -1182,6 +1182,10 @@ config MIPS_MSC +@@ -1183,6 +1183,10 @@ config MIPS_MSC config SYNC_R4K bool diff --git a/target/linux/generic/hack-5.15/760-net-usb-r8152-add-LED-configuration-from-OF.patch b/target/linux/generic/hack-5.15/760-net-usb-r8152-add-LED-configuration-from-OF.patch index 26c5af8510e53c..5c5bd99b4504f6 100644 --- a/target/linux/generic/hack-5.15/760-net-usb-r8152-add-LED-configuration-from-OF.patch +++ b/target/linux/generic/hack-5.15/760-net-usb-r8152-add-LED-configuration-from-OF.patch @@ -22,7 +22,7 @@ Signed-off-by: David Bauer #include #include #include -@@ -6980,6 +6981,22 @@ static void rtl_tally_reset(struct r8152 +@@ -6994,6 +6995,22 @@ static void rtl_tally_reset(struct r8152 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); } @@ -45,7 +45,7 @@ Signed-off-by: David Bauer static void r8152b_init(struct r8152 *tp) { u32 ocp_data; -@@ -7021,6 +7038,8 @@ static void r8152b_init(struct r8152 *tp +@@ -7035,6 +7052,8 @@ static void r8152b_init(struct r8152 *tp ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); @@ -54,7 +54,7 @@ Signed-off-by: David Bauer } static void r8153_init(struct r8152 *tp) -@@ -7161,6 +7180,8 @@ static void r8153_init(struct r8152 *tp) +@@ -7175,6 +7194,8 @@ static void r8153_init(struct r8152 *tp) tp->coalesce = COALESCE_SLOW; break; } @@ -63,7 +63,7 @@ Signed-off-by: David Bauer } static void r8153b_init(struct r8152 *tp) -@@ -7243,6 +7264,8 @@ static void r8153b_init(struct r8152 *tp +@@ -7257,6 +7278,8 @@ static void r8153b_init(struct r8152 *tp rtl_tally_reset(tp); tp->coalesce = 15000; /* 15 us */ diff --git a/target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch b/target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch index 304f5480a3febf..60f02f71436e6c 100644 --- a/target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch +++ b/target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch @@ -43,7 +43,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support #define QUECTEL_VENDOR_ID 0x2c7c /* These Quectel products use Quectel's vendor ID */ -@@ -1144,6 +1149,11 @@ static const struct usb_device_id option +@@ -1146,6 +1151,11 @@ static const struct usb_device_id option { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x0023)}, /* ONYX 3G device */ { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x9000), /* SIMCom SIM5218 */ .driver_info = NCTRL(0) | NCTRL(1) | NCTRL(2) | NCTRL(3) | RSVD(4) }, @@ -55,7 +55,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support /* Quectel products using Qualcomm vendor ID */ { USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC15)}, { USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC20), -@@ -1185,6 +1195,11 @@ static const struct usb_device_id option +@@ -1187,6 +1197,11 @@ static const struct usb_device_id option .driver_info = ZLP }, { USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96), .driver_info = RSVD(4) }, diff --git a/target/linux/generic/hack-5.15/781-usb-net-rndis-support-asr.patch b/target/linux/generic/hack-5.15/781-usb-net-rndis-support-asr.patch index 9934bb8078efe4..0f4e31e7a0ef22 100644 --- a/target/linux/generic/hack-5.15/781-usb-net-rndis-support-asr.patch +++ b/target/linux/generic/hack-5.15/781-usb-net-rndis-support-asr.patch @@ -1,6 +1,6 @@ --- a/drivers/net/usb/rndis_host.c +++ b/drivers/net/usb/rndis_host.c -@@ -630,6 +630,16 @@ static const struct driver_info zte_rndi +@@ -601,6 +601,16 @@ static const struct driver_info rndis_po .tx_fixup = rndis_tx_fixup, }; @@ -17,7 +17,7 @@ /*-------------------------------------------------------------------------*/ static const struct usb_device_id products [] = { -@@ -666,6 +676,36 @@ static const struct usb_device_id produc +@@ -627,6 +637,36 @@ static const struct usb_device_id produc USB_INTERFACE_INFO(USB_CLASS_WIRELESS_CONTROLLER, 1, 3), .driver_info = (unsigned long) &rndis_info, }, { diff --git a/target/linux/generic/hack-5.15/795-backport-phylink_pcs-helpers.patch b/target/linux/generic/hack-5.15/795-backport-phylink_pcs-helpers.patch index 604ebe396094f0..3e05241cde1368 100644 --- a/target/linux/generic/hack-5.15/795-backport-phylink_pcs-helpers.patch +++ b/target/linux/generic/hack-5.15/795-backport-phylink_pcs-helpers.patch @@ -48,7 +48,7 @@ static void phylink_mac_pcs_get_state(struct phylink *pl, struct phylink_link_state *state) { -@@ -2977,6 +2976,52 @@ void phylink_mii_c22_pcs_get_state(struc +@@ -2978,6 +2977,52 @@ void phylink_mii_c22_pcs_get_state(struc EXPORT_SYMBOL_GPL(phylink_mii_c22_pcs_get_state); /** @@ -101,7 +101,7 @@ * phylink_mii_c22_pcs_set_advertisement() - configure the clause 37 PCS * advertisement * @pcs: a pointer to a &struct mdio_device. -@@ -3048,6 +3093,46 @@ int phylink_mii_c22_pcs_set_advertisemen +@@ -3049,6 +3094,46 @@ int phylink_mii_c22_pcs_set_advertisemen EXPORT_SYMBOL_GPL(phylink_mii_c22_pcs_set_advertisement); /** diff --git a/target/linux/generic/hack-5.15/800-GPIO-add-named-gpio-exports.patch b/target/linux/generic/hack-5.15/800-GPIO-add-named-gpio-exports.patch index 0a2c82cacbc11f..00ce48c38445a9 100644 --- a/target/linux/generic/hack-5.15/800-GPIO-add-named-gpio-exports.patch +++ b/target/linux/generic/hack-5.15/800-GPIO-add-named-gpio-exports.patch @@ -129,7 +129,7 @@ Signed-off-by: John Crispin { --- a/drivers/gpio/gpiolib-sysfs.c +++ b/drivers/gpio/gpiolib-sysfs.c -@@ -561,7 +561,7 @@ static struct class gpio_class = { +@@ -564,7 +564,7 @@ static struct class gpio_class = { * * Returns zero on success, else an error. */ @@ -138,7 +138,7 @@ Signed-off-by: John Crispin { struct gpio_chip *chip; struct gpio_device *gdev; -@@ -623,6 +623,8 @@ int gpiod_export(struct gpio_desc *desc, +@@ -626,6 +626,8 @@ int gpiod_export(struct gpio_desc *desc, offset = gpio_chip_hwgpio(desc); if (chip->names && chip->names[offset]) ioname = chip->names[offset]; @@ -147,7 +147,7 @@ Signed-off-by: John Crispin dev = device_create_with_groups(&gpio_class, &gdev->dev, MKDEV(0, 0), data, gpio_groups, -@@ -644,6 +646,12 @@ err_unlock: +@@ -647,6 +649,12 @@ err_unlock: gpiod_dbg(desc, "%s: status %d\n", __func__, status); return status; } diff --git a/target/linux/generic/hack-5.15/904-debloat_dma_buf.patch b/target/linux/generic/hack-5.15/904-debloat_dma_buf.patch index 0291a5e9bd8c42..71546bf942da4e 100644 --- a/target/linux/generic/hack-5.15/904-debloat_dma_buf.patch +++ b/target/linux/generic/hack-5.15/904-debloat_dma_buf.patch @@ -72,7 +72,7 @@ Signed-off-by: Felix Fietkau +MODULE_LICENSE("GPL"); --- a/kernel/sched/core.c +++ b/kernel/sched/core.c -@@ -4216,6 +4216,7 @@ int wake_up_state(struct task_struct *p, +@@ -4220,6 +4220,7 @@ int wake_up_state(struct task_struct *p, { return try_to_wake_up(p, state, 0); } diff --git a/target/linux/generic/hack-5.4/259-regmap_dynamic.patch b/target/linux/generic/hack-5.4/259-regmap_dynamic.patch index 872c2ea01bc231..73afc327553a6d 100644 --- a/target/linux/generic/hack-5.4/259-regmap_dynamic.patch +++ b/target/linux/generic/hack-5.4/259-regmap_dynamic.patch @@ -106,7 +106,7 @@ Signed-off-by: Felix Fietkau #include #include #include -@@ -3120,3 +3121,5 @@ static int __init regmap_initcall(void) +@@ -3122,3 +3123,5 @@ static int __init regmap_initcall(void) return 0; } postcore_initcall(regmap_initcall); diff --git a/target/linux/generic/hack-5.4/995-usb-serial-option-add-ec200a.patch b/target/linux/generic/hack-5.4/995-usb-serial-option-add-ec200a.patch index a87531c0360340..a6324c0236dcf4 100644 --- a/target/linux/generic/hack-5.4/995-usb-serial-option-add-ec200a.patch +++ b/target/linux/generic/hack-5.4/995-usb-serial-option-add-ec200a.patch @@ -8,7 +8,7 @@ #define QUECTEL_PRODUCT_RM500K 0x7001 #define CMOTECH_VENDOR_ID 0x16d8 -@@ -1242,6 +1243,7 @@ static const struct usb_device_id option +@@ -1244,6 +1245,7 @@ static const struct usb_device_id option { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200U, 0xff, 0, 0) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200S_CN, 0xff, 0, 0) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200T, 0xff, 0, 0) }, diff --git a/target/linux/generic/hack-6.1/259-regmap_dynamic.patch b/target/linux/generic/hack-6.1/259-regmap_dynamic.patch index 407bc72ac8dbd1..8d25f59ce2823a 100644 --- a/target/linux/generic/hack-6.1/259-regmap_dynamic.patch +++ b/target/linux/generic/hack-6.1/259-regmap_dynamic.patch @@ -125,7 +125,7 @@ Signed-off-by: Felix Fietkau #include #include #include -@@ -3511,3 +3512,5 @@ static int __init regmap_initcall(void) +@@ -3513,3 +3514,5 @@ static int __init regmap_initcall(void) return 0; } postcore_initcall(regmap_initcall); diff --git a/target/linux/generic/hack-6.1/760-net-usb-r8152-add-LED-configuration-from-OF.patch b/target/linux/generic/hack-6.1/760-net-usb-r8152-add-LED-configuration-from-OF.patch index c842639792f120..48d4626ed632ef 100644 --- a/target/linux/generic/hack-6.1/760-net-usb-r8152-add-LED-configuration-from-OF.patch +++ b/target/linux/generic/hack-6.1/760-net-usb-r8152-add-LED-configuration-from-OF.patch @@ -22,7 +22,7 @@ Signed-off-by: David Bauer #include #include #include -@@ -7020,6 +7021,22 @@ static void rtl_tally_reset(struct r8152 +@@ -7034,6 +7035,22 @@ static void rtl_tally_reset(struct r8152 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); } @@ -45,7 +45,7 @@ Signed-off-by: David Bauer static void r8152b_init(struct r8152 *tp) { u32 ocp_data; -@@ -7061,6 +7078,8 @@ static void r8152b_init(struct r8152 *tp +@@ -7075,6 +7092,8 @@ static void r8152b_init(struct r8152 *tp ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); @@ -54,7 +54,7 @@ Signed-off-by: David Bauer } static void r8153_init(struct r8152 *tp) -@@ -7201,6 +7220,8 @@ static void r8153_init(struct r8152 *tp) +@@ -7215,6 +7234,8 @@ static void r8153_init(struct r8152 *tp) tp->coalesce = COALESCE_SLOW; break; } @@ -63,7 +63,7 @@ Signed-off-by: David Bauer } static void r8153b_init(struct r8152 *tp) -@@ -7283,6 +7304,8 @@ static void r8153b_init(struct r8152 *tp +@@ -7297,6 +7318,8 @@ static void r8153b_init(struct r8152 *tp rtl_tally_reset(tp); tp->coalesce = 15000; /* 15 us */ diff --git a/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch b/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch index 98b5433d063e1d..51f939356f176b 100644 --- a/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch +++ b/target/linux/generic/hack-6.1/780-usb-net-MeigLink_modem_support.patch @@ -43,7 +43,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support #define QUECTEL_VENDOR_ID 0x2c7c /* These Quectel products use Quectel's vendor ID */ -@@ -1144,6 +1149,11 @@ static const struct usb_device_id option +@@ -1147,6 +1152,11 @@ static const struct usb_device_id option { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x0023)}, /* ONYX 3G device */ { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x9000), /* SIMCom SIM5218 */ .driver_info = NCTRL(0) | NCTRL(1) | NCTRL(2) | NCTRL(3) | RSVD(4) }, @@ -55,7 +55,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support /* Quectel products using Qualcomm vendor ID */ { USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC15)}, { USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC20), -@@ -1185,6 +1195,11 @@ static const struct usb_device_id option +@@ -1188,6 +1198,11 @@ static const struct usb_device_id option .driver_info = ZLP }, { USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96), .driver_info = RSVD(4) }, diff --git a/target/linux/generic/hack-6.1/800-GPIO-add-named-gpio-exports.patch b/target/linux/generic/hack-6.1/800-GPIO-add-named-gpio-exports.patch index 658d9c38069178..a892195e682641 100644 --- a/target/linux/generic/hack-6.1/800-GPIO-add-named-gpio-exports.patch +++ b/target/linux/generic/hack-6.1/800-GPIO-add-named-gpio-exports.patch @@ -129,7 +129,7 @@ Signed-off-by: John Crispin { --- a/drivers/gpio/gpiolib-sysfs.c +++ b/drivers/gpio/gpiolib-sysfs.c -@@ -544,7 +544,7 @@ static struct class gpio_class = { +@@ -547,7 +547,7 @@ static struct class gpio_class = { * * Returns zero on success, else an error. */ @@ -138,7 +138,7 @@ Signed-off-by: John Crispin { struct gpio_chip *chip; struct gpio_device *gdev; -@@ -606,6 +606,8 @@ int gpiod_export(struct gpio_desc *desc, +@@ -609,6 +609,8 @@ int gpiod_export(struct gpio_desc *desc, offset = gpio_chip_hwgpio(desc); if (chip->names && chip->names[offset]) ioname = chip->names[offset]; @@ -147,7 +147,7 @@ Signed-off-by: John Crispin dev = device_create_with_groups(&gpio_class, &gdev->dev, MKDEV(0, 0), data, gpio_groups, -@@ -627,6 +629,12 @@ err_unlock: +@@ -630,6 +632,12 @@ err_unlock: gpiod_dbg(desc, "%s: status %d\n", __func__, status); return status; } diff --git a/target/linux/generic/hack-6.1/904-debloat_dma_buf.patch b/target/linux/generic/hack-6.1/904-debloat_dma_buf.patch index 8b6bd6a7862af4..105eb3da4bb67b 100644 --- a/target/linux/generic/hack-6.1/904-debloat_dma_buf.patch +++ b/target/linux/generic/hack-6.1/904-debloat_dma_buf.patch @@ -73,7 +73,7 @@ Signed-off-by: Felix Fietkau +MODULE_LICENSE("GPL"); --- a/kernel/sched/core.c +++ b/kernel/sched/core.c -@@ -4363,6 +4363,7 @@ int wake_up_state(struct task_struct *p, +@@ -4367,6 +4367,7 @@ int wake_up_state(struct task_struct *p, { return try_to_wake_up(p, state, 0); } diff --git a/target/linux/generic/pending-5.10/300-mips_expose_boot_raw.patch b/target/linux/generic/pending-5.10/300-mips_expose_boot_raw.patch index ee3fc5e108c708..a10ce95222a794 100644 --- a/target/linux/generic/pending-5.10/300-mips_expose_boot_raw.patch +++ b/target/linux/generic/pending-5.10/300-mips_expose_boot_raw.patch @@ -9,7 +9,7 @@ Acked-by: Rob Landley --- --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -1086,9 +1086,6 @@ config FW_ARC +@@ -1087,9 +1087,6 @@ config FW_ARC config ARCH_MAY_HAVE_PC_FDC bool @@ -19,7 +19,7 @@ Acked-by: Rob Landley config CEVT_BCM1480 bool -@@ -3183,6 +3180,18 @@ choice +@@ -3185,6 +3182,18 @@ choice bool "Extend builtin kernel arguments with bootloader arguments" endchoice diff --git a/target/linux/generic/pending-5.10/470-mtd-spi-nor-support-limiting-4K-sectors-support-base.patch b/target/linux/generic/pending-5.10/470-mtd-spi-nor-support-limiting-4K-sectors-support-base.patch index 85cc53c4511d97..42b61c9093f5f8 100644 --- a/target/linux/generic/pending-5.10/470-mtd-spi-nor-support-limiting-4K-sectors-support-base.patch +++ b/target/linux/generic/pending-5.10/470-mtd-spi-nor-support-limiting-4K-sectors-support-base.patch @@ -39,7 +39,7 @@ Signed-off-by: Felix Fietkau endif # MTD_SPI_NOR --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c -@@ -2806,6 +2806,21 @@ static void spi_nor_info_init_params(str +@@ -2807,6 +2807,21 @@ static void spi_nor_info_init_params(str */ erase_mask = 0; i = 0; @@ -61,7 +61,7 @@ Signed-off-by: Felix Fietkau if (info->flags & SECT_4K_PMC) { erase_mask |= BIT(i); spi_nor_set_erase_type(&map->erase_type[i], 4096u, -@@ -2817,6 +2832,7 @@ static void spi_nor_info_init_params(str +@@ -2818,6 +2833,7 @@ static void spi_nor_info_init_params(str SPINOR_OP_BE_4K); i++; } diff --git a/target/linux/generic/pending-5.10/479-mtd-spi-nor-add-xtx-xt25f128b.patch b/target/linux/generic/pending-5.10/479-mtd-spi-nor-add-xtx-xt25f128b.patch index 394f9a18dfc0b7..8853327154fc94 100644 --- a/target/linux/generic/pending-5.10/479-mtd-spi-nor-add-xtx-xt25f128b.patch +++ b/target/linux/generic/pending-5.10/479-mtd-spi-nor-add-xtx-xt25f128b.patch @@ -59,7 +59,7 @@ Signed-off-by: Felix Fietkau +}; --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c -@@ -2037,6 +2037,7 @@ static const struct spi_nor_manufacturer +@@ -2038,6 +2038,7 @@ static const struct spi_nor_manufacturer &spi_nor_winbond, &spi_nor_xilinx, &spi_nor_xmc, diff --git a/target/linux/generic/pending-5.10/630-packet_socket_type.patch b/target/linux/generic/pending-5.10/630-packet_socket_type.patch index bab1e48d840949..1f21ced0ab52b7 100644 --- a/target/linux/generic/pending-5.10/630-packet_socket_type.patch +++ b/target/linux/generic/pending-5.10/630-packet_socket_type.patch @@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau #define PACKET_FANOUT_LB 1 --- a/net/packet/af_packet.c +++ b/net/packet/af_packet.c -@@ -1823,6 +1823,7 @@ static int packet_rcv_spkt(struct sk_buf +@@ -1827,6 +1827,7 @@ static int packet_rcv_spkt(struct sk_buf { struct sock *sk; struct sockaddr_pkt *spkt; @@ -38,7 +38,7 @@ Signed-off-by: Felix Fietkau /* * When we registered the protocol we saved the socket in the data -@@ -1830,6 +1831,7 @@ static int packet_rcv_spkt(struct sk_buf +@@ -1834,6 +1835,7 @@ static int packet_rcv_spkt(struct sk_buf */ sk = pt->af_packet_priv; @@ -46,7 +46,7 @@ Signed-off-by: Felix Fietkau /* * Yank back the headers [hope the device set this -@@ -1842,7 +1844,7 @@ static int packet_rcv_spkt(struct sk_buf +@@ -1846,7 +1848,7 @@ static int packet_rcv_spkt(struct sk_buf * so that this procedure is noop. */ @@ -55,7 +55,7 @@ Signed-off-by: Felix Fietkau goto out; if (!net_eq(dev_net(dev), sock_net(sk))) -@@ -2088,12 +2090,12 @@ static int packet_rcv(struct sk_buff *sk +@@ -2092,12 +2094,12 @@ static int packet_rcv(struct sk_buff *sk unsigned int snaplen, res; bool is_drop_n_account = false; @@ -71,7 +71,7 @@ Signed-off-by: Felix Fietkau if (!net_eq(dev_net(dev), sock_net(sk))) goto drop; -@@ -2219,12 +2221,12 @@ static int tpacket_rcv(struct sk_buff *s +@@ -2223,12 +2225,12 @@ static int tpacket_rcv(struct sk_buff *s BUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h2)) != 32); BUILD_BUG_ON(TPACKET_ALIGN(sizeof(*h.h3)) != 48); @@ -87,7 +87,7 @@ Signed-off-by: Felix Fietkau if (!net_eq(dev_net(dev), sock_net(sk))) goto drop; -@@ -3342,6 +3344,7 @@ static int packet_create(struct net *net +@@ -3346,6 +3348,7 @@ static int packet_create(struct net *net mutex_init(&po->pg_vec_lock); po->rollover = NULL; po->prot_hook.func = packet_rcv; @@ -95,7 +95,7 @@ Signed-off-by: Felix Fietkau if (sock->type == SOCK_PACKET) po->prot_hook.func = packet_rcv_spkt; -@@ -3982,6 +3985,16 @@ packet_setsockopt(struct socket *sock, i +@@ -3986,6 +3989,16 @@ packet_setsockopt(struct socket *sock, i WRITE_ONCE(po->xmit, val ? packet_direct_xmit : dev_queue_xmit); return 0; } @@ -112,7 +112,7 @@ Signed-off-by: Felix Fietkau default: return -ENOPROTOOPT; } -@@ -4038,6 +4051,13 @@ static int packet_getsockopt(struct sock +@@ -4042,6 +4055,13 @@ static int packet_getsockopt(struct sock case PACKET_VNET_HDR: val = po->has_vnet_hdr; break; diff --git a/target/linux/generic/pending-5.10/701-00-net-ethernet-mtk_eth_soc-add-support-for-coherent-DM.patch b/target/linux/generic/pending-5.10/701-00-net-ethernet-mtk_eth_soc-add-support-for-coherent-DM.patch index a9491c62f0dc57..650af6208c4e90 100644 --- a/target/linux/generic/pending-5.10/701-00-net-ethernet-mtk_eth_soc-add-support-for-coherent-DM.patch +++ b/target/linux/generic/pending-5.10/701-00-net-ethernet-mtk_eth_soc-add-support-for-coherent-DM.patch @@ -196,7 +196,7 @@ Signed-off-by: Felix Fietkau ring->dma_size * sizeof(*ring->dma), ring->dma, ring->phys); -@@ -2155,7 +2156,7 @@ static void mtk_dma_free(struct mtk_eth +@@ -2158,7 +2159,7 @@ static void mtk_dma_free(struct mtk_eth if (eth->netdev[i]) netdev_reset_queue(eth->netdev[i]); if (eth->scratch_ring) { @@ -205,7 +205,7 @@ Signed-off-by: Felix Fietkau MTK_DMA_SIZE * sizeof(struct mtk_tx_dma), eth->scratch_ring, eth->phy_scratch_ring); -@@ -2506,6 +2507,8 @@ static void mtk_dim_tx(struct work_struc +@@ -2509,6 +2510,8 @@ static void mtk_dim_tx(struct work_struc static int mtk_hw_init(struct mtk_eth *eth) { @@ -214,7 +214,7 @@ Signed-off-by: Felix Fietkau int i, val, ret; if (test_and_set_bit(MTK_HW_INIT, ð->state)) -@@ -2518,6 +2521,10 @@ static int mtk_hw_init(struct mtk_eth *e +@@ -2521,6 +2524,10 @@ static int mtk_hw_init(struct mtk_eth *e if (ret) goto err_disable_pm; @@ -225,7 +225,7 @@ Signed-off-by: Felix Fietkau if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { ret = device_reset(eth->dev); if (ret) { -@@ -3067,6 +3074,35 @@ free_netdev: +@@ -3070,6 +3077,35 @@ free_netdev: return err; } @@ -261,7 +261,7 @@ Signed-off-by: Felix Fietkau static int mtk_probe(struct platform_device *pdev) { struct device_node *mac_np; -@@ -3080,6 +3116,7 @@ static int mtk_probe(struct platform_dev +@@ -3083,6 +3119,7 @@ static int mtk_probe(struct platform_dev eth->soc = of_device_get_match_data(&pdev->dev); eth->dev = &pdev->dev; @@ -269,7 +269,7 @@ Signed-off-by: Felix Fietkau eth->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(eth->base)) return PTR_ERR(eth->base); -@@ -3128,6 +3165,16 @@ static int mtk_probe(struct platform_dev +@@ -3131,6 +3168,16 @@ static int mtk_probe(struct platform_dev } } diff --git a/target/linux/generic/pending-5.10/701-02-net-ethernet-mtk_eth_soc-add-support-for-Wireless-Et.patch b/target/linux/generic/pending-5.10/701-02-net-ethernet-mtk_eth_soc-add-support-for-Wireless-Et.patch index d1729c640cc4e5..00ef4a8cdc0933 100644 --- a/target/linux/generic/pending-5.10/701-02-net-ethernet-mtk_eth_soc-add-support-for-Wireless-Et.patch +++ b/target/linux/generic/pending-5.10/701-02-net-ethernet-mtk_eth_soc-add-support-for-Wireless-Et.patch @@ -56,7 +56,7 @@ Signed-off-by: Felix Fietkau static int mtk_msg_level = -1; module_param_named(msg_level, mtk_msg_level, int, 0); -@@ -3197,6 +3198,22 @@ static int mtk_probe(struct platform_dev +@@ -3200,6 +3201,22 @@ static int mtk_probe(struct platform_dev } } diff --git a/target/linux/generic/pending-5.10/701-07-net-ethernet-mtk_eth_soc-allocate-struct-mtk_ppe-sep.patch b/target/linux/generic/pending-5.10/701-07-net-ethernet-mtk_eth_soc-allocate-struct-mtk_ppe-sep.patch index c67547caeb2d1d..c2dfd8b571c987 100644 --- a/target/linux/generic/pending-5.10/701-07-net-ethernet-mtk_eth_soc-allocate-struct-mtk_ppe-sep.patch +++ b/target/linux/generic/pending-5.10/701-07-net-ethernet-mtk_eth_soc-allocate-struct-mtk_ppe-sep.patch @@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -2329,7 +2329,7 @@ static int mtk_open(struct net_device *d +@@ -2332,7 +2332,7 @@ static int mtk_open(struct net_device *d return err; } @@ -19,7 +19,7 @@ Signed-off-by: Felix Fietkau gdm_config = MTK_GDMA_TO_PPE; mtk_gdm_config(eth, gdm_config); -@@ -2403,7 +2403,7 @@ static int mtk_stop(struct net_device *d +@@ -2406,7 +2406,7 @@ static int mtk_stop(struct net_device *d mtk_dma_free(eth); if (eth->soc->offload_version) @@ -28,7 +28,7 @@ Signed-off-by: Felix Fietkau return 0; } -@@ -3289,10 +3289,11 @@ static int mtk_probe(struct platform_dev +@@ -3292,10 +3292,11 @@ static int mtk_probe(struct platform_dev } if (eth->soc->offload_version) { diff --git a/target/linux/generic/pending-5.10/701-08-net-ethernet-mtk_eth_soc-rework-hardware-flow-table-.patch b/target/linux/generic/pending-5.10/701-08-net-ethernet-mtk_eth_soc-rework-hardware-flow-table-.patch index 9b36265fc7b6a5..5a6eb0d44ba30e 100644 --- a/target/linux/generic/pending-5.10/701-08-net-ethernet-mtk_eth_soc-rework-hardware-flow-table-.patch +++ b/target/linux/generic/pending-5.10/701-08-net-ethernet-mtk_eth_soc-rework-hardware-flow-table-.patch @@ -54,7 +54,7 @@ Signed-off-by: Felix Fietkau if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && (trxd.rxd2 & RX_DMA_VTAG)) __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), -@@ -3289,7 +3295,7 @@ static int mtk_probe(struct platform_dev +@@ -3292,7 +3298,7 @@ static int mtk_probe(struct platform_dev } if (eth->soc->offload_version) { diff --git a/target/linux/generic/pending-5.10/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch b/target/linux/generic/pending-5.10/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch index 4075acc67ec700..d6c4e8e99cdb3c 100644 --- a/target/linux/generic/pending-5.10/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch +++ b/target/linux/generic/pending-5.10/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch @@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -2200,8 +2200,8 @@ static irqreturn_t mtk_handle_irq_rx(int +@@ -2203,8 +2203,8 @@ static irqreturn_t mtk_handle_irq_rx(int eth->rx_events++; if (likely(napi_schedule_prep(ð->rx_napi))) { @@ -20,7 +20,7 @@ Signed-off-by: Felix Fietkau } return IRQ_HANDLED; -@@ -2213,8 +2213,8 @@ static irqreturn_t mtk_handle_irq_tx(int +@@ -2216,8 +2216,8 @@ static irqreturn_t mtk_handle_irq_tx(int eth->tx_events++; if (likely(napi_schedule_prep(ð->tx_napi))) { @@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau } return IRQ_HANDLED; -@@ -3324,6 +3324,8 @@ static int mtk_probe(struct platform_dev +@@ -3327,6 +3327,8 @@ static int mtk_probe(struct platform_dev * for NAPI to work */ init_dummy_netdev(ð->dummy_dev); diff --git a/target/linux/generic/pending-5.10/750-skb-Do-mix-page-pool-and-page-referenced-frags-in-GR.patch b/target/linux/generic/pending-5.10/750-skb-Do-mix-page-pool-and-page-referenced-frags-in-GR.patch index 532b8ac6fb52d3..b3ef413eaf19b0 100644 --- a/target/linux/generic/pending-5.10/750-skb-Do-mix-page-pool-and-page-referenced-frags-in-GR.patch +++ b/target/linux/generic/pending-5.10/750-skb-Do-mix-page-pool-and-page-referenced-frags-in-GR.patch @@ -17,7 +17,7 @@ Signed-off-by: Alexander Duyck --- a/net/core/skbuff.c +++ b/net/core/skbuff.c -@@ -4169,6 +4169,15 @@ int skb_gro_receive(struct sk_buff *p, s +@@ -4175,6 +4175,15 @@ int skb_gro_receive(struct sk_buff *p, s if (unlikely(p->len + len >= 65536 || NAPI_GRO_CB(skb)->flush)) return -E2BIG; diff --git a/target/linux/generic/pending-5.10/760-net-dsa-mv88e6xxx-fix-vlan-setup.patch b/target/linux/generic/pending-5.10/760-net-dsa-mv88e6xxx-fix-vlan-setup.patch index 9c3b81fefb4e00..4e63af0b88139f 100644 --- a/target/linux/generic/pending-5.10/760-net-dsa-mv88e6xxx-fix-vlan-setup.patch +++ b/target/linux/generic/pending-5.10/760-net-dsa-mv88e6xxx-fix-vlan-setup.patch @@ -17,7 +17,7 @@ Signed-off-by: DENG Qingfang --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c -@@ -2934,6 +2934,7 @@ static int mv88e6xxx_setup(struct dsa_sw +@@ -2944,6 +2944,7 @@ static int mv88e6xxx_setup(struct dsa_sw chip->ds = ds; ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); diff --git a/target/linux/generic/pending-5.10/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch b/target/linux/generic/pending-5.10/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch index 5c8b26a972e5c0..6513a88017a0ec 100644 --- a/target/linux/generic/pending-5.10/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch +++ b/target/linux/generic/pending-5.10/768-net-dsa-mv88e6xxx-Request-assisted-learning-on-CPU-port.patch @@ -17,7 +17,7 @@ Signed-off-by: Tobias Waldekranz --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c -@@ -5504,6 +5504,7 @@ static int mv88e6xxx_register_switch(str +@@ -5514,6 +5514,7 @@ static int mv88e6xxx_register_switch(str ds->ops = &mv88e6xxx_switch_ops; ds->ageing_time_min = chip->info->age_time_coeff; ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; diff --git a/target/linux/generic/pending-5.10/810-pci_disable_common_quirks.patch b/target/linux/generic/pending-5.10/810-pci_disable_common_quirks.patch index ac232c71973319..95b2600aa6a524 100644 --- a/target/linux/generic/pending-5.10/810-pci_disable_common_quirks.patch +++ b/target/linux/generic/pending-5.10/810-pci_disable_common_quirks.patch @@ -33,7 +33,7 @@ Signed-off-by: Gabor Juhos /* * The Mellanox Tavor device gives false positive parity errors. Mark this * device with a broken_parity_status to allow PCI scanning code to "skip" -@@ -3335,6 +3336,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I +@@ -3337,6 +3338,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); @@ -42,7 +42,7 @@ Signed-off-by: Gabor Juhos /* * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. * To work around this, query the size it should be configured to by the -@@ -3360,6 +3363,8 @@ static void quirk_intel_ntb(struct pci_d +@@ -3362,6 +3365,8 @@ static void quirk_intel_ntb(struct pci_d DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); @@ -51,7 +51,7 @@ Signed-off-by: Gabor Juhos /* * Some BIOS implementations leave the Intel GPU interrupts enabled, even * though no one is handling them (e.g., if the i915 driver is never -@@ -3398,6 +3403,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN +@@ -3400,6 +3405,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); diff --git a/target/linux/generic/pending-5.10/834-ledtrig-libata.patch b/target/linux/generic/pending-5.10/834-ledtrig-libata.patch index 636fe24aea571b..a39aef640b9d80 100644 --- a/target/linux/generic/pending-5.10/834-ledtrig-libata.patch +++ b/target/linux/generic/pending-5.10/834-ledtrig-libata.patch @@ -134,7 +134,7 @@ Signed-off-by: Daniel Golle /* * Define if arch has non-standard setup. This is a _PCI_ standard -@@ -883,6 +886,12 @@ struct ata_port { +@@ -887,6 +890,12 @@ struct ata_port { #ifdef CONFIG_ATA_ACPI struct ata_acpi_gtm __acpi_init_gtm; /* use ata_acpi_init_gtm() */ #endif diff --git a/target/linux/generic/pending-5.15/300-mips_expose_boot_raw.patch b/target/linux/generic/pending-5.15/300-mips_expose_boot_raw.patch index 0fcd415966ef90..be4dacf0945861 100644 --- a/target/linux/generic/pending-5.15/300-mips_expose_boot_raw.patch +++ b/target/linux/generic/pending-5.15/300-mips_expose_boot_raw.patch @@ -9,7 +9,7 @@ Acked-by: Rob Landley --- --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -1102,9 +1102,6 @@ config FW_ARC +@@ -1103,9 +1103,6 @@ config FW_ARC config ARCH_MAY_HAVE_PC_FDC bool @@ -19,7 +19,7 @@ Acked-by: Rob Landley config CEVT_BCM1480 bool -@@ -3184,6 +3181,18 @@ choice +@@ -3186,6 +3183,18 @@ choice bool "Extend builtin kernel arguments with bootloader arguments" endchoice diff --git a/target/linux/generic/pending-5.15/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch b/target/linux/generic/pending-5.15/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch index 7eaa65067ffb0e..4ff7f321de93e8 100644 --- a/target/linux/generic/pending-5.15/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch +++ b/target/linux/generic/pending-5.15/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch @@ -15,7 +15,7 @@ Signed-off-by: Alexander Couzens --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2382,7 +2382,7 @@ mt7531_setup(struct dsa_switch *ds) +@@ -2422,7 +2422,7 @@ mt7531_setup(struct dsa_switch *ds) struct mt7530_priv *priv = ds->priv; struct mt7530_dummy_poll p; u32 val, id; @@ -24,7 +24,7 @@ Signed-off-by: Alexander Couzens /* Reset whole chip through gpio pin or memory-mapped registers for * different type of hardware -@@ -2414,6 +2414,10 @@ mt7531_setup(struct dsa_switch *ds) +@@ -2454,6 +2454,10 @@ mt7531_setup(struct dsa_switch *ds) return -ENODEV; } diff --git a/target/linux/generic/pending-5.15/737-01-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V1-capabilit.patch b/target/linux/generic/pending-5.15/737-01-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V1-capabilit.patch index 621a7b0fcf0839..6071ee5e479ea0 100644 --- a/target/linux/generic/pending-5.15/737-01-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V1-capabilit.patch +++ b/target/linux/generic/pending-5.15/737-01-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V1-capabilit.patch @@ -108,7 +108,7 @@ Signed-off-by: Daniel Golle rxd->rxd5 = 0; rxd->rxd6 = 0; rxd->rxd7 = 0; -@@ -3063,7 +3063,7 @@ static int mtk_start_dma(struct mtk_eth +@@ -3066,7 +3066,7 @@ static int mtk_start_dma(struct mtk_eth MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; @@ -117,7 +117,7 @@ Signed-off-by: Daniel Golle val |= MTK_MUTLI_CNT | MTK_RESV_BUF | MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN; -@@ -3475,7 +3475,7 @@ static void mtk_hw_reset(struct mtk_eth +@@ -3478,7 +3478,7 @@ static void mtk_hw_reset(struct mtk_eth { u32 val; @@ -126,7 +126,7 @@ Signed-off-by: Daniel Golle regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); val = RSTCTRL_PPE0_V2; } else { -@@ -3487,7 +3487,7 @@ static void mtk_hw_reset(struct mtk_eth +@@ -3490,7 +3490,7 @@ static void mtk_hw_reset(struct mtk_eth ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val); @@ -135,7 +135,7 @@ Signed-off-by: Daniel Golle regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0x3ffffff); } -@@ -3683,7 +3683,7 @@ static int mtk_hw_init(struct mtk_eth *e +@@ -3686,7 +3686,7 @@ static int mtk_hw_init(struct mtk_eth *e else mtk_hw_reset(eth); @@ -144,7 +144,7 @@ Signed-off-by: Daniel Golle /* Set FE to PDMAv2 if necessary */ val = mtk_r32(eth, MTK_FE_GLO_MISC); mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); -@@ -3720,7 +3720,7 @@ static int mtk_hw_init(struct mtk_eth *e +@@ -3723,7 +3723,7 @@ static int mtk_hw_init(struct mtk_eth *e */ val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); diff --git a/target/linux/generic/pending-5.15/737-02-net-ethernet-mtk_eth_soc-move-MAX_DEVS-in-mtk_soc_da.patch b/target/linux/generic/pending-5.15/737-02-net-ethernet-mtk_eth_soc-move-MAX_DEVS-in-mtk_soc_da.patch index a8debc41bfb3ce..4103f98e9ffda0 100644 --- a/target/linux/generic/pending-5.15/737-02-net-ethernet-mtk_eth_soc-move-MAX_DEVS-in-mtk_soc_da.patch +++ b/target/linux/generic/pending-5.15/737-02-net-ethernet-mtk_eth_soc-move-MAX_DEVS-in-mtk_soc_da.patch @@ -15,7 +15,7 @@ Signed-off-by: Daniel Golle --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -3989,7 +3989,10 @@ static void mtk_sgmii_destroy(struct mtk +@@ -3975,7 +3975,10 @@ static void mtk_sgmii_destroy(struct mtk { int i; @@ -27,7 +27,7 @@ Signed-off-by: Daniel Golle mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]); } -@@ -4432,7 +4435,12 @@ static int mtk_sgmii_init(struct mtk_eth +@@ -4428,7 +4431,12 @@ static int mtk_sgmii_init(struct mtk_eth u32 flags; int i; @@ -41,7 +41,7 @@ Signed-off-by: Daniel Golle np = of_parse_phandle(eth->dev->of_node, "mediatek,sgmiisys", i); if (!np) break; -@@ -4477,6 +4485,18 @@ static int mtk_probe(struct platform_dev +@@ -4473,6 +4481,18 @@ static int mtk_probe(struct platform_dev if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) eth->ip_align = NET_IP_ALIGN; @@ -60,7 +60,7 @@ Signed-off-by: Daniel Golle spin_lock_init(ð->page_lock); spin_lock_init(ð->tx_irq_lock); spin_lock_init(ð->rx_irq_lock); -@@ -4662,7 +4682,7 @@ static int mtk_probe(struct platform_dev +@@ -4658,7 +4678,7 @@ static int mtk_probe(struct platform_dev goto err_free_dev; } @@ -69,7 +69,7 @@ Signed-off-by: Daniel Golle if (!eth->netdev[i]) continue; -@@ -4739,6 +4759,7 @@ static const struct mtk_soc_data mt2701_ +@@ -4735,6 +4755,7 @@ static const struct mtk_soc_data mt2701_ .hw_features = MTK_HW_FEATURES, .required_clks = MT7623_CLKS_BITMAP, .required_pctl = true, @@ -77,7 +77,7 @@ Signed-off-by: Daniel Golle .txrx = { .txd_size = sizeof(struct mtk_tx_dma), .rxd_size = sizeof(struct mtk_rx_dma), -@@ -4757,6 +4778,7 @@ static const struct mtk_soc_data mt7621_ +@@ -4753,6 +4774,7 @@ static const struct mtk_soc_data mt7621_ .required_pctl = false, .offload_version = 1, .hash_offset = 2, @@ -85,7 +85,7 @@ Signed-off-by: Daniel Golle .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, .txrx = { .txd_size = sizeof(struct mtk_tx_dma), -@@ -4778,6 +4800,7 @@ static const struct mtk_soc_data mt7622_ +@@ -4774,6 +4796,7 @@ static const struct mtk_soc_data mt7622_ .offload_version = 2, .hash_offset = 2, .has_accounting = true, @@ -93,7 +93,7 @@ Signed-off-by: Daniel Golle .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, .txrx = { .txd_size = sizeof(struct mtk_tx_dma), -@@ -4797,6 +4820,7 @@ static const struct mtk_soc_data mt7623_ +@@ -4793,6 +4816,7 @@ static const struct mtk_soc_data mt7623_ .required_pctl = true, .offload_version = 1, .hash_offset = 2, @@ -101,7 +101,7 @@ Signed-off-by: Daniel Golle .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, .txrx = { .txd_size = sizeof(struct mtk_tx_dma), -@@ -4816,6 +4840,7 @@ static const struct mtk_soc_data mt7629_ +@@ -4812,6 +4836,7 @@ static const struct mtk_soc_data mt7629_ .required_clks = MT7629_CLKS_BITMAP, .required_pctl = false, .has_accounting = true, @@ -109,7 +109,7 @@ Signed-off-by: Daniel Golle .txrx = { .txd_size = sizeof(struct mtk_tx_dma), .rxd_size = sizeof(struct mtk_rx_dma), -@@ -4837,6 +4862,7 @@ static const struct mtk_soc_data mt7981_ +@@ -4833,6 +4858,7 @@ static const struct mtk_soc_data mt7981_ .hash_offset = 4, .foe_entry_size = sizeof(struct mtk_foe_entry), .has_accounting = true, @@ -117,7 +117,7 @@ Signed-off-by: Daniel Golle .txrx = { .txd_size = sizeof(struct mtk_tx_dma_v2), .rxd_size = sizeof(struct mtk_rx_dma_v2), -@@ -4856,6 +4882,7 @@ static const struct mtk_soc_data mt7986_ +@@ -4852,6 +4878,7 @@ static const struct mtk_soc_data mt7986_ .required_pctl = false, .offload_version = 2, .hash_offset = 4, @@ -125,7 +125,7 @@ Signed-off-by: Daniel Golle .foe_entry_size = sizeof(struct mtk_foe_entry), .has_accounting = true, .txrx = { -@@ -4874,6 +4901,7 @@ static const struct mtk_soc_data rt5350_ +@@ -4870,6 +4897,7 @@ static const struct mtk_soc_data rt5350_ .hw_features = MTK_HW_FEATURES_MT7628, .required_clks = MT7628_CLKS_BITMAP, .required_pctl = false, diff --git a/target/linux/generic/pending-5.15/737-03-net-ethernet-mtk_eth_soc-rely-on-num_devs-and-remove.patch b/target/linux/generic/pending-5.15/737-03-net-ethernet-mtk_eth_soc-rely-on-num_devs-and-remove.patch index d6b36bf6368933..30234cc628b92d 100644 --- a/target/linux/generic/pending-5.15/737-03-net-ethernet-mtk_eth_soc-rely-on-num_devs-and-remove.patch +++ b/target/linux/generic/pending-5.15/737-03-net-ethernet-mtk_eth_soc-rely-on-num_devs-and-remove.patch @@ -51,7 +51,7 @@ Signed-off-by: Daniel Golle !eth->netdev[mac])) goto release_desc; -@@ -2937,7 +2937,7 @@ static void mtk_dma_free(struct mtk_eth +@@ -2940,7 +2940,7 @@ static void mtk_dma_free(struct mtk_eth const struct mtk_soc_data *soc = eth->soc; int i; @@ -60,7 +60,7 @@ Signed-off-by: Daniel Golle if (eth->netdev[i]) netdev_reset_queue(eth->netdev[i]); if (eth->scratch_ring) { -@@ -3091,7 +3091,7 @@ static void mtk_gdm_config(struct mtk_et +@@ -3094,7 +3094,7 @@ static void mtk_gdm_config(struct mtk_et if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) return; @@ -69,7 +69,7 @@ Signed-off-by: Daniel Golle u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); /* default setup the forward port to send frame to PDMA */ -@@ -3704,7 +3704,7 @@ static int mtk_hw_init(struct mtk_eth *e +@@ -3707,7 +3707,7 @@ static int mtk_hw_init(struct mtk_eth *e * up with the more appropriate value when mtk_mac_config call is being * invoked. */ @@ -78,7 +78,7 @@ Signed-off-by: Daniel Golle struct net_device *dev = eth->netdev[i]; mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); -@@ -3909,7 +3909,7 @@ static void mtk_pending_work(struct work +@@ -3895,7 +3895,7 @@ static void mtk_pending_work(struct work mtk_prepare_for_reset(eth); /* stop all devices to make sure that dma is properly shut down */ @@ -87,7 +87,7 @@ Signed-off-by: Daniel Golle if (!eth->netdev[i] || !netif_running(eth->netdev[i])) continue; -@@ -3925,7 +3925,7 @@ static void mtk_pending_work(struct work +@@ -3911,7 +3911,7 @@ static void mtk_pending_work(struct work mtk_hw_init(eth, true); /* restart DMA and enable IRQs */ @@ -96,7 +96,7 @@ Signed-off-by: Daniel Golle if (!test_bit(i, &restart)) continue; -@@ -3953,7 +3953,7 @@ static int mtk_free_dev(struct mtk_eth * +@@ -3939,7 +3939,7 @@ static int mtk_free_dev(struct mtk_eth * { int i; @@ -105,7 +105,7 @@ Signed-off-by: Daniel Golle if (!eth->netdev[i]) continue; free_netdev(eth->netdev[i]); -@@ -3972,7 +3972,7 @@ static int mtk_unreg_dev(struct mtk_eth +@@ -3958,7 +3958,7 @@ static int mtk_unreg_dev(struct mtk_eth { int i; @@ -114,7 +114,7 @@ Signed-off-by: Daniel Golle struct mtk_mac *mac; if (!eth->netdev[i]) continue; -@@ -4277,7 +4277,7 @@ static int mtk_add_mac(struct mtk_eth *e +@@ -4262,7 +4262,7 @@ static int mtk_add_mac(struct mtk_eth *e } id = be32_to_cpup(_id); @@ -123,7 +123,7 @@ Signed-off-by: Daniel Golle dev_err(eth->dev, "%d is not a valid mac id\n", id); return -EINVAL; } -@@ -4407,7 +4407,7 @@ void mtk_eth_set_dma_device(struct mtk_e +@@ -4403,7 +4403,7 @@ void mtk_eth_set_dma_device(struct mtk_e rtnl_lock(); @@ -132,7 +132,7 @@ Signed-off-by: Daniel Golle dev = eth->netdev[i]; if (!dev || !(dev->flags & IFF_UP)) -@@ -4734,7 +4734,7 @@ static int mtk_remove(struct platform_de +@@ -4730,7 +4730,7 @@ static int mtk_remove(struct platform_de int i; /* stop all devices to make sure that dma is properly shut down */ diff --git a/target/linux/generic/pending-5.15/737-04-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V3-capabilit.patch b/target/linux/generic/pending-5.15/737-04-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V3-capabilit.patch index 80d729db17ff16..8fe8c2805322fa 100644 --- a/target/linux/generic/pending-5.15/737-04-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V3-capabilit.patch +++ b/target/linux/generic/pending-5.15/737-04-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V3-capabilit.patch @@ -154,7 +154,7 @@ Signed-off-by: Daniel Golle if (!tx_buf->data) break; -@@ -3742,7 +3788,26 @@ static int mtk_hw_init(struct mtk_eth *e +@@ -3745,7 +3791,26 @@ static int mtk_hw_init(struct mtk_eth *e mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4); mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); @@ -182,7 +182,7 @@ Signed-off-by: Daniel Golle /* PSE should not drop port8 and port9 packets from WDMA Tx */ mtk_w32(eth, 0x00000300, PSE_DROP_CFG); -@@ -4314,7 +4379,11 @@ static int mtk_add_mac(struct mtk_eth *e +@@ -4310,7 +4375,11 @@ static int mtk_add_mac(struct mtk_eth *e } spin_lock_init(&mac->hw_stats->stats_lock); u64_stats_init(&mac->hw_stats->syncp); diff --git a/target/linux/generic/pending-5.15/737-06-net-ethernet-mtk_eth_soc-add-support-for-MT7988-SoC.patch b/target/linux/generic/pending-5.15/737-06-net-ethernet-mtk_eth_soc-add-support-for-MT7988-SoC.patch index 504d2ea22664d6..cbc4785f0d4fe8 100644 --- a/target/linux/generic/pending-5.15/737-06-net-ethernet-mtk_eth_soc-add-support-for-MT7988-SoC.patch +++ b/target/linux/generic/pending-5.15/737-06-net-ethernet-mtk_eth_soc-add-support-for-MT7988-SoC.patch @@ -150,7 +150,7 @@ mtk_eth_soc driver. data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); WRITE_ONCE(desc->txd4, data); -@@ -4964,6 +5065,25 @@ static const struct mtk_soc_data mt7986_ +@@ -4960,6 +5061,25 @@ static const struct mtk_soc_data mt7986_ }, }; @@ -176,7 +176,7 @@ mtk_eth_soc driver. static const struct mtk_soc_data rt5350_data = { .reg_map = &mt7628_reg_map, .caps = MT7628_CAPS, -@@ -4982,14 +5102,15 @@ static const struct mtk_soc_data rt5350_ +@@ -4978,14 +5098,15 @@ static const struct mtk_soc_data rt5350_ }; const struct of_device_id of_mtk_match[] = { diff --git a/target/linux/generic/pending-5.15/737-07-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch b/target/linux/generic/pending-5.15/737-07-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch index 0185bed089774d..d7195c4205018c 100644 --- a/target/linux/generic/pending-5.15/737-07-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch +++ b/target/linux/generic/pending-5.15/737-07-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch @@ -607,7 +607,7 @@ Signed-off-by: Daniel Golle mtk_w32(eth, val, MTK_PPSC); dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider); -@@ -4433,8 +4636,8 @@ static int mtk_add_mac(struct mtk_eth *e +@@ -4418,8 +4621,8 @@ static int mtk_add_mac(struct mtk_eth *e const __be32 *_id = of_get_property(np, "reg", NULL); phy_interface_t phy_mode; struct phylink *phylink; @@ -617,7 +617,7 @@ Signed-off-by: Daniel Golle int txqs = 1; if (!_id) { -@@ -4525,6 +4728,32 @@ static int mtk_add_mac(struct mtk_eth *e +@@ -4521,6 +4724,32 @@ static int mtk_add_mac(struct mtk_eth *e mac->phylink_config.supported_interfaces); } @@ -650,7 +650,7 @@ Signed-off-by: Daniel Golle phylink = phylink_create(&mac->phylink_config, of_fwnode_handle(mac->of_node), phy_mode, &mtk_phylink_ops); -@@ -4712,6 +4941,13 @@ static int mtk_probe(struct platform_dev +@@ -4708,6 +4937,13 @@ static int mtk_probe(struct platform_dev if (err) return err; diff --git a/target/linux/generic/pending-5.15/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch b/target/linux/generic/pending-5.15/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch index 8a64a2a985eaf4..98fd6e9c7a7c1d 100644 --- a/target/linux/generic/pending-5.15/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch +++ b/target/linux/generic/pending-5.15/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch @@ -16,7 +16,7 @@ Signed-off-by: David Bauer --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2121,10 +2121,13 @@ mt7530_setup_mdio(struct mt7530_priv *pr +@@ -2129,10 +2129,13 @@ mt7530_setup_mdio(struct mt7530_priv *pr { struct dsa_switch *ds = priv->ds; struct device *dev = priv->dev; @@ -30,7 +30,7 @@ Signed-off-by: David Bauer bus = devm_mdiobus_alloc(dev); if (!bus) return -ENOMEM; -@@ -2141,7 +2144,9 @@ mt7530_setup_mdio(struct mt7530_priv *pr +@@ -2149,7 +2152,9 @@ mt7530_setup_mdio(struct mt7530_priv *pr if (priv->irq) mt7530_setup_mdio_irq(priv); diff --git a/target/linux/generic/pending-5.15/901-usb-add-more-modem-support.patch b/target/linux/generic/pending-5.15/901-usb-add-more-modem-support.patch index 3f0f061c219d13..c717b771fb383e 100644 --- a/target/linux/generic/pending-5.15/901-usb-add-more-modem-support.patch +++ b/target/linux/generic/pending-5.15/901-usb-add-more-modem-support.patch @@ -1,6 +1,6 @@ --- a/drivers/net/usb/qmi_wwan.c +++ b/drivers/net/usb/qmi_wwan.c -@@ -1419,6 +1419,9 @@ static const struct usb_device_id produc +@@ -1420,6 +1420,9 @@ static const struct usb_device_id produc {QMI_FIXED_INTF(0x0489, 0xe0b5, 0)}, /* Foxconn T77W968 LTE with eSIM support*/ {QMI_FIXED_INTF(0x2692, 0x9025, 4)}, /* Cellient MPL200 (rebranded Qualcomm 05c6:9025) */ {QMI_QUIRK_SET_DTR(0x1546, 0x1342, 4)}, /* u-blox LARA-L6 */ @@ -12,7 +12,7 @@ {QMI_GOBI1K_DEVICE(0x05c6, 0x9212)}, /* Acer Gobi Modem Device */ --- a/drivers/usb/serial/option.c +++ b/drivers/usb/serial/option.c -@@ -2262,6 +2262,12 @@ static const struct usb_device_id option +@@ -2266,6 +2266,12 @@ static const struct usb_device_id option { USB_DEVICE_INTERFACE_CLASS(0x2cb7, 0x01a2, 0xff) }, /* Fibocom FM101-GL (laptop MBIM) */ { USB_DEVICE_INTERFACE_CLASS(0x2cb7, 0x01a4, 0xff), /* Fibocom FM101-GL (laptop MBIM) */ .driver_info = RSVD(4) }, diff --git a/target/linux/generic/pending-5.15/920-mangle_bootargs.patch b/target/linux/generic/pending-5.15/920-mangle_bootargs.patch index 7e1f26d243f027..5f2bb8c37f446a 100644 --- a/target/linux/generic/pending-5.15/920-mangle_bootargs.patch +++ b/target/linux/generic/pending-5.15/920-mangle_bootargs.patch @@ -31,7 +31,7 @@ Signed-off-by: Imre Kaloz help --- a/init/main.c +++ b/init/main.c -@@ -614,6 +614,29 @@ static inline void setup_nr_cpu_ids(void +@@ -618,6 +618,29 @@ static inline void setup_nr_cpu_ids(void static inline void smp_prepare_cpus(unsigned int maxcpus) { } #endif @@ -61,7 +61,7 @@ Signed-off-by: Imre Kaloz /* * We need to store the untouched command line for future reference. * We also need to store the touched command line since the parameter -@@ -953,6 +976,7 @@ asmlinkage __visible void __init __no_sa +@@ -957,6 +980,7 @@ asmlinkage __visible void __init __no_sa pr_notice("%s", linux_banner); early_security_init(); setup_arch(&command_line); diff --git a/target/linux/generic/pending-5.4/640-netfilter-nf_flow_table-add-hardware-offload-support.patch b/target/linux/generic/pending-5.4/640-netfilter-nf_flow_table-add-hardware-offload-support.patch index ba2f5966086c2f..48d7864a46fbfa 100644 --- a/target/linux/generic/pending-5.4/640-netfilter-nf_flow_table-add-hardware-offload-support.patch +++ b/target/linux/generic/pending-5.4/640-netfilter-nf_flow_table-add-hardware-offload-support.patch @@ -110,7 +110,7 @@ Signed-off-by: Pablo Neira Ayuso --- a/include/uapi/linux/netfilter/nf_tables.h +++ b/include/uapi/linux/netfilter/nf_tables.h -@@ -1516,6 +1516,7 @@ enum nft_object_attributes { +@@ -1517,6 +1517,7 @@ enum nft_object_attributes { * @NFTA_FLOWTABLE_HOOK: netfilter hook configuration(NLA_U32) * @NFTA_FLOWTABLE_USE: number of references to this flow table (NLA_U32) * @NFTA_FLOWTABLE_HANDLE: object handle (NLA_U64) @@ -118,7 +118,7 @@ Signed-off-by: Pablo Neira Ayuso */ enum nft_flowtable_attributes { NFTA_FLOWTABLE_UNSPEC, -@@ -1525,6 +1526,7 @@ enum nft_flowtable_attributes { +@@ -1526,6 +1527,7 @@ enum nft_flowtable_attributes { NFTA_FLOWTABLE_USE, NFTA_FLOWTABLE_HANDLE, NFTA_FLOWTABLE_PAD, @@ -506,7 +506,7 @@ Signed-off-by: Pablo Neira Ayuso +MODULE_ALIAS("nf-flow-table-hw"); --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c -@@ -5889,6 +5889,13 @@ static int nf_tables_flowtable_parse_hoo +@@ -5974,6 +5974,13 @@ static int nf_tables_flowtable_parse_hoo if (err < 0) return err; @@ -520,7 +520,7 @@ Signed-off-by: Pablo Neira Ayuso ops = kcalloc(n, sizeof(struct nf_hook_ops), GFP_KERNEL); if (!ops) return -ENOMEM; -@@ -6024,10 +6031,19 @@ static int nf_tables_newflowtable(struct +@@ -6118,10 +6125,19 @@ static int nf_tables_newflowtable(struct } flowtable->data.type = type; @@ -540,7 +540,7 @@ Signed-off-by: Pablo Neira Ayuso err = nf_tables_flowtable_parse_hook(&ctx, nla[NFTA_FLOWTABLE_HOOK], flowtable); if (err < 0) -@@ -6150,7 +6166,8 @@ static int nf_tables_fill_flowtable_info +@@ -6247,7 +6263,8 @@ static int nf_tables_fill_flowtable_info nla_put_string(skb, NFTA_FLOWTABLE_NAME, flowtable->name) || nla_put_be32(skb, NFTA_FLOWTABLE_USE, htonl(flowtable->use)) || nla_put_be64(skb, NFTA_FLOWTABLE_HANDLE, cpu_to_be64(flowtable->handle), diff --git a/target/linux/generic/pending-6.1/102-MIPS-only-process-negative-stack-offsets-on-stack-tr.patch b/target/linux/generic/pending-6.1/102-MIPS-only-process-negative-stack-offsets-on-stack-tr.patch index 7ce3d491cd3270..d79d03defb3ad4 100644 --- a/target/linux/generic/pending-6.1/102-MIPS-only-process-negative-stack-offsets-on-stack-tr.patch +++ b/target/linux/generic/pending-6.1/102-MIPS-only-process-negative-stack-offsets-on-stack-tr.patch @@ -46,7 +46,7 @@ Signed-off-by: Felix Fietkau --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c -@@ -394,6 +394,8 @@ static inline int is_sp_move_ins(union m +@@ -395,6 +395,8 @@ static inline int is_sp_move_ins(union m if (ip->i_format.opcode == addiu_op || ip->i_format.opcode == daddiu_op) { diff --git a/target/linux/generic/pending-6.1/300-mips_expose_boot_raw.patch b/target/linux/generic/pending-6.1/300-mips_expose_boot_raw.patch index 9e571a6d875b18..d222ec060e8b7d 100644 --- a/target/linux/generic/pending-6.1/300-mips_expose_boot_raw.patch +++ b/target/linux/generic/pending-6.1/300-mips_expose_boot_raw.patch @@ -9,7 +9,7 @@ Acked-by: Rob Landley --- --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -1034,9 +1034,6 @@ config FW_ARC +@@ -1035,9 +1035,6 @@ config FW_ARC config ARCH_MAY_HAVE_PC_FDC bool @@ -19,7 +19,7 @@ Acked-by: Rob Landley config CEVT_BCM1480 bool -@@ -3091,6 +3088,18 @@ choice +@@ -3093,6 +3090,18 @@ choice bool "Extend builtin kernel arguments with bootloader arguments" endchoice diff --git a/target/linux/generic/pending-6.1/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch b/target/linux/generic/pending-6.1/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch index 32c2ce1831db85..00a43e3e55187b 100644 --- a/target/linux/generic/pending-6.1/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch +++ b/target/linux/generic/pending-6.1/723-net-mt7531-ensure-all-MACs-are-powered-down-before-r.patch @@ -15,7 +15,7 @@ Signed-off-by: Alexander Couzens --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2212,6 +2212,10 @@ mt7530_setup(struct dsa_switch *ds) +@@ -2236,6 +2236,10 @@ mt7530_setup(struct dsa_switch *ds) return -ENODEV; } diff --git a/target/linux/generic/pending-6.1/737-01-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V1-capabilit.patch b/target/linux/generic/pending-6.1/737-01-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V1-capabilit.patch new file mode 100644 index 00000000000000..bf1bc78b23aec6 --- /dev/null +++ b/target/linux/generic/pending-6.1/737-01-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V1-capabilit.patch @@ -0,0 +1,223 @@ +From 663fa1b7e0cb2c929008482014a70c6625caad75 Mon Sep 17 00:00:00 2001 +From: Lorenzo Bianconi +Date: Tue, 7 Mar 2023 15:55:13 +0000 +Subject: [PATCH 1/7] net: ethernet: mtk_eth_soc: add MTK_NETSYS_V1 capability + bit + +Introduce MTK_NETSYS_V1 bit in the device capabilities for +MT7621/MT7622/MT7623/MT7628/MT7629 SoCs. +Use !MTK_NETSYS_V1 instead of MTK_NETSYS_V2 in the driver codebase. +This is a preliminary patch to introduce support for MT7988 SoC. + +Signed-off-by: Lorenzo Bianconi +Signed-off-by: Daniel Golle +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 30 +++++++------- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 45 ++++++++++++--------- + 2 files changed, 41 insertions(+), 34 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -640,7 +640,7 @@ static void mtk_set_queue_speed(struct m + FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | + FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | + MTK_QTX_SCH_LEAKY_BUCKET_SIZE; +- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) + val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; + + if (IS_ENABLED(CONFIG_SOC_MT7621)) { +@@ -1018,7 +1018,7 @@ static bool mtk_rx_get_desc(struct mtk_e + rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); + rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); + rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { + rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); + rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); + } +@@ -1076,7 +1076,7 @@ static int mtk_init_fq_dma(struct mtk_et + + txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); + txd->txd4 = 0; +- if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { ++ if (!MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V1)) { + txd->txd5 = 0; + txd->txd6 = 0; + txd->txd7 = 0; +@@ -1267,7 +1267,7 @@ static void mtk_tx_set_dma_desc(struct n + struct mtk_mac *mac = netdev_priv(dev); + struct mtk_eth *eth = mac->hw; + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) + mtk_tx_set_dma_desc_v2(dev, txd, info); + else + mtk_tx_set_dma_desc_v1(dev, txd, info); +@@ -1950,7 +1950,7 @@ static int mtk_poll_rx(struct napi_struc + break; + + /* find out which mac the packet come from. values start at 1 */ +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) + mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1; + else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && + !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) +@@ -2046,7 +2046,7 @@ static int mtk_poll_rx(struct napi_struc + skb->dev = netdev; + bytes += skb->len; + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { + reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5); + hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY; + if (hash != MTK_RXD5_FOE_ENTRY) +@@ -2071,7 +2071,7 @@ static int mtk_poll_rx(struct napi_struc + /* When using VLAN untagging in combination with DSA, the + * hardware treats the MTK special tag as a VLAN and untags it. + */ +- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) && ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1) && + (trxd.rxd2 & RX_DMA_VTAG) && netdev_uses_dsa(netdev)) { + unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0); + +@@ -2382,7 +2382,7 @@ static int mtk_tx_alloc(struct mtk_eth * + txd->txd2 = next_ptr; + txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; + txd->txd4 = 0; +- if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { ++ if (!MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V1)) { + txd->txd5 = 0; + txd->txd6 = 0; + txd->txd7 = 0; +@@ -2435,7 +2435,7 @@ static int mtk_tx_alloc(struct mtk_eth * + FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | + FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | + MTK_QTX_SCH_LEAKY_BUCKET_SIZE; +- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) + val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; + mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); + ofs += MTK_QTX_OFFSET; +@@ -2571,7 +2571,7 @@ static int mtk_rx_alloc(struct mtk_eth * + + rxd->rxd3 = 0; + rxd->rxd4 = 0; +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { + rxd->rxd5 = 0; + rxd->rxd6 = 0; + rxd->rxd7 = 0; +@@ -3119,7 +3119,7 @@ static int mtk_start_dma(struct mtk_eth + MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | + MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) + val |= MTK_MUTLI_CNT | MTK_RESV_BUF | + MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | + MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN; +@@ -3529,7 +3529,7 @@ static void mtk_hw_reset(struct mtk_eth + { + u32 val; + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { + regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); + val = RSTCTRL_PPE0_V2; + } else { +@@ -3541,7 +3541,7 @@ static void mtk_hw_reset(struct mtk_eth + + ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val); + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) ++ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) + regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, + 0x3ffffff); + } +@@ -3737,7 +3737,7 @@ static int mtk_hw_init(struct mtk_eth *e + else + mtk_hw_reset(eth); + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { + /* Set FE to PDMAv2 if necessary */ + val = mtk_r32(eth, MTK_FE_GLO_MISC); + mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); +@@ -3774,7 +3774,7 @@ static int mtk_hw_init(struct mtk_eth *e + */ + val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); + mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); +- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { + val = mtk_r32(eth, MTK_CDMP_IG_CTRL); + mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL); + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -819,6 +819,7 @@ enum mkt_eth_capabilities { + MTK_SHARED_INT_BIT, + MTK_TRGMII_MT7621_CLK_BIT, + MTK_QDMA_BIT, ++ MTK_NETSYS_V1_BIT, + MTK_NETSYS_V2_BIT, + MTK_SOC_MT7628_BIT, + MTK_RSTCTRL_PPE1_BIT, +@@ -854,6 +855,7 @@ enum mkt_eth_capabilities { + #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) + #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) + #define MTK_QDMA BIT(MTK_QDMA_BIT) ++#define MTK_NETSYS_V1 BIT(MTK_NETSYS_V1_BIT) + #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) + #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) + #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) +@@ -916,25 +918,30 @@ enum mkt_eth_capabilities { + + #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x) & ~(MTK_CAP_MASK)) == (_x)) + +-#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ +- MTK_GMAC2_RGMII | MTK_SHARED_INT | \ +- MTK_TRGMII_MT7621_CLK | MTK_QDMA) +- +-#define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII | \ +- MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ +- MTK_MUX_GDM1_TO_GMAC1_ESW | \ +- MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) +- +-#define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII | \ +- MTK_QDMA) +- +-#define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) +- +-#define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ +- MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ +- MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ +- MTK_MUX_U3_GMAC2_TO_QPHY | \ +- MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) ++#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ ++ MTK_GMAC2_RGMII | MTK_SHARED_INT | \ ++ MTK_TRGMII_MT7621_CLK | MTK_QDMA | \ ++ MTK_NETSYS_V1) ++ ++#define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | \ ++ MTK_GMAC2_RGMII | MTK_GMAC2_SGMII | \ ++ MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW |\ ++ MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | \ ++ MTK_QDMA | MTK_NETSYS_V1) ++ ++#define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ ++ MTK_GMAC2_RGMII | MTK_QDMA | \ ++ MTK_NETSYS_V1) ++ ++#define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628 | \ ++ MTK_NETSYS_V1) ++ ++#define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ ++ MTK_GMAC2_GEPHY | MTK_GDM1_ESW | \ ++ MTK_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_QDMA | \ ++ MTK_MUX_U3_GMAC2_TO_QPHY | MTK_NETSYS_V1 |\ ++ MTK_MUX_GDM1_TO_GMAC1_ESW | \ ++ MTK_MUX_GMAC12_TO_GEPHY_SGMII) + + #define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ + MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ diff --git a/target/linux/generic/pending-6.1/737-02-net-ethernet-mtk_eth_soc-move-MAX_DEVS-in-mtk_soc_da.patch b/target/linux/generic/pending-6.1/737-02-net-ethernet-mtk_eth_soc-move-MAX_DEVS-in-mtk_soc_da.patch new file mode 100644 index 00000000000000..82848a7c972425 --- /dev/null +++ b/target/linux/generic/pending-6.1/737-02-net-ethernet-mtk_eth_soc-move-MAX_DEVS-in-mtk_soc_da.patch @@ -0,0 +1,181 @@ +From 5af2b2dc4d6ba0ff7696e79f18e5b2bf862194eb Mon Sep 17 00:00:00 2001 +From: Lorenzo Bianconi +Date: Tue, 7 Mar 2023 15:55:24 +0000 +Subject: [PATCH 2/7] net: ethernet: mtk_eth_soc: move MAX_DEVS in mtk_soc_data + +This is a preliminary patch to add MT7988 SoC support since it runs 3 +macs instead of 2. + +Signed-off-by: Lorenzo Bianconi +Signed-off-by: Daniel Golle +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 34 +++++++++++++++++++-- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 11 +++---- + 2 files changed, 36 insertions(+), 9 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -4043,7 +4043,10 @@ static void mtk_sgmii_destroy(struct mtk + { + int i; + +- for (i = 0; i < MTK_MAX_DEVS; i++) ++ if (!eth->sgmii_pcs) ++ return; ++ ++ for (i = 0; i < eth->soc->num_devs; i++) + mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]); + } + +@@ -4486,7 +4489,12 @@ static int mtk_sgmii_init(struct mtk_eth + u32 flags; + int i; + +- for (i = 0; i < MTK_MAX_DEVS; i++) { ++ eth->sgmii_pcs = devm_kzalloc(eth->dev, ++ sizeof(*eth->sgmii_pcs) * ++ eth->soc->num_devs, ++ GFP_KERNEL); ++ ++ for (i = 0; i < eth->soc->num_devs; i++) { + np = of_parse_phandle(eth->dev->of_node, "mediatek,sgmiisys", i); + if (!np) + break; +@@ -4531,6 +4539,18 @@ static int mtk_probe(struct platform_dev + if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) + eth->ip_align = NET_IP_ALIGN; + ++ eth->netdev = devm_kzalloc(eth->dev, ++ sizeof(*eth->netdev) * eth->soc->num_devs, ++ GFP_KERNEL); ++ if (!eth->netdev) ++ return -ENOMEM; ++ ++ eth->mac = devm_kzalloc(eth->dev, ++ sizeof(*eth->mac) * eth->soc->num_devs, ++ GFP_KERNEL); ++ if (!eth->mac) ++ return -ENOMEM; ++ + spin_lock_init(ð->page_lock); + spin_lock_init(ð->tx_irq_lock); + spin_lock_init(ð->rx_irq_lock); +@@ -4716,7 +4736,7 @@ static int mtk_probe(struct platform_dev + goto err_deinit_ppe; + } + +- for (i = 0; i < MTK_MAX_DEVS; i++) { ++ for (i = 0; i < eth->soc->num_devs; i++) { + if (!eth->netdev[i]) + continue; + +@@ -4792,6 +4812,7 @@ static const struct mtk_soc_data mt2701_ + .hw_features = MTK_HW_FEATURES, + .required_clks = MT7623_CLKS_BITMAP, + .required_pctl = true, ++ .num_devs = 2, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), +@@ -4810,6 +4831,7 @@ static const struct mtk_soc_data mt7621_ + .required_pctl = false, + .offload_version = 1, + .hash_offset = 2, ++ .num_devs = 2, + .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), +@@ -4831,6 +4853,7 @@ static const struct mtk_soc_data mt7622_ + .offload_version = 2, + .hash_offset = 2, + .has_accounting = true, ++ .num_devs = 2, + .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), +@@ -4850,6 +4873,7 @@ static const struct mtk_soc_data mt7623_ + .required_pctl = true, + .offload_version = 1, + .hash_offset = 2, ++ .num_devs = 2, + .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), +@@ -4869,6 +4893,7 @@ static const struct mtk_soc_data mt7629_ + .required_clks = MT7629_CLKS_BITMAP, + .required_pctl = false, + .has_accounting = true, ++ .num_devs = 2, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), +@@ -4890,6 +4915,7 @@ static const struct mtk_soc_data mt7981_ + .hash_offset = 4, + .foe_entry_size = sizeof(struct mtk_foe_entry), + .has_accounting = true, ++ .num_devs = 2, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma_v2), + .rxd_size = sizeof(struct mtk_rx_dma_v2), +@@ -4908,6 +4934,7 @@ static const struct mtk_soc_data mt7986_ + .required_clks = MT7986_CLKS_BITMAP, + .required_pctl = false, + .hash_offset = 4, ++ .num_devs = 2, + .foe_entry_size = sizeof(struct mtk_foe_entry), + .has_accounting = true, + .txrx = { +@@ -4926,6 +4953,7 @@ static const struct mtk_soc_data rt5350_ + .hw_features = MTK_HW_FEATURES_MT7628, + .required_clks = MT7628_CLKS_BITMAP, + .required_pctl = false, ++ .num_devs = 2, + .txrx = { + .txd_size = sizeof(struct mtk_tx_dma), + .rxd_size = sizeof(struct mtk_rx_dma), +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -1021,6 +1021,7 @@ struct mtk_reg_map { + * @required_pctl A bool value to show whether the SoC requires + * the extra setup for those pins used by GMAC. + * @hash_offset Flow table hash offset. ++ * @num_devs SoC number of macs. + * @foe_entry_size Foe table entry size. + * @has_accounting Bool indicating support for accounting of + * offloaded flows. +@@ -1039,6 +1040,7 @@ struct mtk_soc_data { + bool required_pctl; + u8 offload_version; + u8 hash_offset; ++ u8 num_devs; + u16 foe_entry_size; + netdev_features_t hw_features; + bool has_accounting; +@@ -1054,9 +1056,6 @@ struct mtk_soc_data { + + #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000) + +-/* currently no SoC has more than 2 macs */ +-#define MTK_MAX_DEVS 2 +- + /* struct mtk_eth - This is the main datasructure for holding the state + * of the driver + * @dev: The device pointer +@@ -1111,14 +1110,14 @@ struct mtk_eth { + spinlock_t tx_irq_lock; + spinlock_t rx_irq_lock; + struct net_device dummy_dev; +- struct net_device *netdev[MTK_MAX_DEVS]; +- struct mtk_mac *mac[MTK_MAX_DEVS]; ++ struct net_device **netdev; ++ struct mtk_mac **mac; + int irq[3]; + u32 msg_enable; + unsigned long sysclk; + struct regmap *ethsys; + struct regmap *infra; +- struct phylink_pcs *sgmii_pcs[MTK_MAX_DEVS]; ++ struct phylink_pcs **sgmii_pcs; + struct regmap *pctl; + bool hwlro; + refcount_t dma_refcnt; diff --git a/target/linux/generic/pending-6.1/737-03-net-ethernet-mtk_eth_soc-rely-on-num_devs-and-remove.patch b/target/linux/generic/pending-6.1/737-03-net-ethernet-mtk_eth_soc-rely-on-num_devs-and-remove.patch new file mode 100644 index 00000000000000..be12aa5c06672e --- /dev/null +++ b/target/linux/generic/pending-6.1/737-03-net-ethernet-mtk_eth_soc-rely-on-num_devs-and-remove.patch @@ -0,0 +1,153 @@ +From 4e35e80750b33727e606be9e7ce447bde2e0deb7 Mon Sep 17 00:00:00 2001 +From: Lorenzo Bianconi +Date: Tue, 7 Mar 2023 15:55:35 +0000 +Subject: [PATCH 3/7] net: ethernet: mtk_eth_soc: rely on num_devs and remove + MTK_MAC_COUNT + +Get rid of MTK_MAC_COUNT since it is a duplicated of eth->soc->num_devs. + +Signed-off-by: Lorenzo Bianconi +Signed-off-by: Daniel Golle +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 30 ++++++++++----------- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 - + 2 files changed, 15 insertions(+), 16 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -944,7 +944,7 @@ static void mtk_stats_update(struct mtk_ + { + int i; + +- for (i = 0; i < MTK_MAC_COUNT; i++) { ++ for (i = 0; i < eth->soc->num_devs; i++) { + if (!eth->mac[i] || !eth->mac[i]->hw_stats) + continue; + if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { +@@ -1449,7 +1449,7 @@ static int mtk_queue_stopped(struct mtk_ + { + int i; + +- for (i = 0; i < MTK_MAC_COUNT; i++) { ++ for (i = 0; i < eth->soc->num_devs; i++) { + if (!eth->netdev[i]) + continue; + if (netif_queue_stopped(eth->netdev[i])) +@@ -1463,7 +1463,7 @@ static void mtk_wake_queue(struct mtk_et + { + int i; + +- for (i = 0; i < MTK_MAC_COUNT; i++) { ++ for (i = 0; i < eth->soc->num_devs; i++) { + if (!eth->netdev[i]) + continue; + netif_tx_wake_all_queues(eth->netdev[i]); +@@ -1956,7 +1956,7 @@ static int mtk_poll_rx(struct napi_struc + !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) + mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; + +- if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || ++ if (unlikely(mac < 0 || mac >= eth->soc->num_devs || + !eth->netdev[mac])) + goto release_desc; + +@@ -2993,7 +2993,7 @@ static void mtk_dma_free(struct mtk_eth + const struct mtk_soc_data *soc = eth->soc; + int i; + +- for (i = 0; i < MTK_MAC_COUNT; i++) ++ for (i = 0; i < soc->num_devs; i++) + if (eth->netdev[i]) + netdev_reset_queue(eth->netdev[i]); + if (eth->scratch_ring) { +@@ -3147,7 +3147,7 @@ static void mtk_gdm_config(struct mtk_et + if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) + return; + +- for (i = 0; i < MTK_MAC_COUNT; i++) { ++ for (i = 0; i < eth->soc->num_devs; i++) { + u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); + + /* default setup the forward port to send frame to PDMA */ +@@ -3758,7 +3758,7 @@ static int mtk_hw_init(struct mtk_eth *e + * up with the more appropriate value when mtk_mac_config call is being + * invoked. + */ +- for (i = 0; i < MTK_MAC_COUNT; i++) { ++ for (i = 0; i < eth->soc->num_devs; i++) { + struct net_device *dev = eth->netdev[i]; + + mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); +@@ -3963,7 +3963,7 @@ static void mtk_pending_work(struct work + mtk_prepare_for_reset(eth); + + /* stop all devices to make sure that dma is properly shut down */ +- for (i = 0; i < MTK_MAC_COUNT; i++) { ++ for (i = 0; i < eth->soc->num_devs; i++) { + if (!eth->netdev[i] || !netif_running(eth->netdev[i])) + continue; + +@@ -3979,7 +3979,7 @@ static void mtk_pending_work(struct work + mtk_hw_init(eth, true); + + /* restart DMA and enable IRQs */ +- for (i = 0; i < MTK_MAC_COUNT; i++) { ++ for (i = 0; i < eth->soc->num_devs; i++) { + if (!test_bit(i, &restart)) + continue; + +@@ -4007,7 +4007,7 @@ static int mtk_free_dev(struct mtk_eth * + { + int i; + +- for (i = 0; i < MTK_MAC_COUNT; i++) { ++ for (i = 0; i < eth->soc->num_devs; i++) { + if (!eth->netdev[i]) + continue; + free_netdev(eth->netdev[i]); +@@ -4026,7 +4026,7 @@ static int mtk_unreg_dev(struct mtk_eth + { + int i; + +- for (i = 0; i < MTK_MAC_COUNT; i++) { ++ for (i = 0; i < eth->soc->num_devs; i++) { + struct mtk_mac *mac; + if (!eth->netdev[i]) + continue; +@@ -4331,7 +4331,7 @@ static int mtk_add_mac(struct mtk_eth *e + } + + id = be32_to_cpup(_id); +- if (id >= MTK_MAC_COUNT) { ++ if (id >= eth->soc->num_devs) { + dev_err(eth->dev, "%d is not a valid mac id\n", id); + return -EINVAL; + } +@@ -4461,7 +4461,7 @@ void mtk_eth_set_dma_device(struct mtk_e + + rtnl_lock(); + +- for (i = 0; i < MTK_MAC_COUNT; i++) { ++ for (i = 0; i < eth->soc->num_devs; i++) { + dev = eth->netdev[i]; + + if (!dev || !(dev->flags & IFF_UP)) +@@ -4787,7 +4787,7 @@ static int mtk_remove(struct platform_de + int i; + + /* stop all devices to make sure that dma is properly shut down */ +- for (i = 0; i < MTK_MAC_COUNT; i++) { ++ for (i = 0; i < eth->soc->num_devs; i++) { + if (!eth->netdev[i]) + continue; + mtk_stop(eth->netdev[i]); +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -33,7 +33,6 @@ + #define MTK_TX_DMA_BUF_LEN_V2 0xffff + #define MTK_QDMA_RING_SIZE 2048 + #define MTK_DMA_SIZE 512 +-#define MTK_MAC_COUNT 2 + #define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + ETH_FCS_LEN) + #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) + #define MTK_DMA_DUMMY_DESC 0xffffffff diff --git a/target/linux/generic/pending-6.1/737-04-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V3-capabilit.patch b/target/linux/generic/pending-6.1/737-04-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V3-capabilit.patch new file mode 100644 index 00000000000000..a383a5e4ef8808 --- /dev/null +++ b/target/linux/generic/pending-6.1/737-04-net-ethernet-mtk_eth_soc-add-MTK_NETSYS_V3-capabilit.patch @@ -0,0 +1,292 @@ +From ab817f559d505329d8a413c7d29250f6d87d77a0 Mon Sep 17 00:00:00 2001 +From: Lorenzo Bianconi +Date: Tue, 7 Mar 2023 15:55:47 +0000 +Subject: [PATCH 4/7] net: ethernet: mtk_eth_soc: add MTK_NETSYS_V3 capability + bit + +Introduce MTK_NETSYS_V3 bit in the device capabilities. +This is a preliminary patch to introduce support for MT7988 SoC. + +Signed-off-by: Lorenzo Bianconi +Signed-off-by: Daniel Golle +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 115 ++++++++++++++++---- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 44 +++++++- + 2 files changed, 134 insertions(+), 25 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -924,17 +924,32 @@ void mtk_stats_update_mac(struct mtk_mac + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); + hw_stats->rx_flow_control_packets += + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); +- hw_stats->tx_skip += +- mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); +- hw_stats->tx_collisions += +- mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); +- hw_stats->tx_bytes += +- mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); +- stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); +- if (stats) +- hw_stats->tx_bytes += (stats << 32); +- hw_stats->tx_packets += +- mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); ++ ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { ++ hw_stats->tx_skip += ++ mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs); ++ hw_stats->tx_collisions += ++ mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x54 + offs); ++ hw_stats->tx_bytes += ++ mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x40 + offs); ++ stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x44 + offs); ++ if (stats) ++ hw_stats->tx_bytes += (stats << 32); ++ hw_stats->tx_packets += ++ mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x48 + offs); ++ } else { ++ hw_stats->tx_skip += ++ mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); ++ hw_stats->tx_collisions += ++ mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); ++ hw_stats->tx_bytes += ++ mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); ++ stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); ++ if (stats) ++ hw_stats->tx_bytes += (stats << 32); ++ hw_stats->tx_packets += ++ mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); ++ } + } + + u64_stats_update_end(&hw_stats->syncp); +@@ -1238,7 +1253,10 @@ static void mtk_tx_set_dma_desc_v2(struc + data |= TX_DMA_LS0; + WRITE_ONCE(desc->txd3, data); + +- data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */ ++ if (mac->id == MTK_GMAC3_ID) ++ data = PSE_GDM3_PORT; ++ else ++ data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */ + data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); + WRITE_ONCE(desc->txd4, data); + +@@ -1249,6 +1267,9 @@ static void mtk_tx_set_dma_desc_v2(struc + /* tx checksum offload */ + if (info->csum) + data |= TX_DMA_CHKSUM_V2; ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) && ++ netdev_uses_dsa(dev)) ++ data |= TX_DMA_SPTAG_V3; + } + WRITE_ONCE(desc->txd5, data); + +@@ -1314,8 +1335,13 @@ static int mtk_tx_map(struct sk_buff *sk + mtk_tx_set_dma_desc(dev, itxd, &txd_info); + + itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; +- itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : +- MTK_TX_FLAGS_FPORT1; ++ if (mac->id == MTK_GMAC1_ID) ++ itx_buf->flags |= MTK_TX_FLAGS_FPORT0; ++ else if (mac->id == MTK_GMAC2_ID) ++ itx_buf->flags |= MTK_TX_FLAGS_FPORT1; ++ else ++ itx_buf->flags |= MTK_TX_FLAGS_FPORT2; ++ + setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size, + k++); + +@@ -1363,8 +1389,13 @@ static int mtk_tx_map(struct sk_buff *sk + memset(tx_buf, 0, sizeof(*tx_buf)); + tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; + tx_buf->flags |= MTK_TX_FLAGS_PAGE0; +- tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : +- MTK_TX_FLAGS_FPORT1; ++ ++ if (mac->id == MTK_GMAC1_ID) ++ tx_buf->flags |= MTK_TX_FLAGS_FPORT0; ++ else if (mac->id == MTK_GMAC2_ID) ++ tx_buf->flags |= MTK_TX_FLAGS_FPORT1; ++ else ++ tx_buf->flags |= MTK_TX_FLAGS_FPORT2; + + setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr, + txd_info.size, k++); +@@ -1950,11 +1981,24 @@ static int mtk_poll_rx(struct napi_struc + break; + + /* find out which mac the packet come from. values start at 1 */ +- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) +- mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1; +- else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && +- !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) ++ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { ++ u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5); ++ ++ switch (val) { ++ case PSE_GDM1_PORT: ++ case PSE_GDM2_PORT: ++ mac = val - 1; ++ break; ++ case PSE_GDM3_PORT: ++ mac = MTK_GMAC3_ID; ++ break; ++ default: ++ break; ++ } ++ } else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && ++ !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) { + mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; ++ } + + if (unlikely(mac < 0 || mac >= eth->soc->num_devs || + !eth->netdev[mac])) +@@ -2185,7 +2229,9 @@ static int mtk_poll_tx_qdma(struct mtk_e + tx_buf = mtk_desc_to_tx_buf(ring, desc, + eth->soc->txrx.txd_size); + if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) +- mac = 1; ++ mac = MTK_GMAC2_ID; ++ else if (tx_buf->flags & MTK_TX_FLAGS_FPORT2) ++ mac = MTK_GMAC3_ID; + + if (!tx_buf->data) + break; +@@ -3796,7 +3842,26 @@ static int mtk_hw_init(struct mtk_eth *e + mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4); + mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); + +- if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { ++ /* PSE should not drop port1, port8 and port9 packets */ ++ mtk_w32(eth, 0x00000302, PSE_DROP_CFG); ++ ++ /* GDM and CDM Threshold */ ++ mtk_w32(eth, 0x00000707, MTK_CDMW0_THRES); ++ mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES); ++ ++ /* Disable GDM1 RX CRC stripping */ ++ val = mtk_r32(eth, MTK_GDMA_FWD_CFG(0)); ++ val &= ~MTK_GDMA_STRP_CRC; ++ mtk_w32(eth, val, MTK_GDMA_FWD_CFG(0)); ++ ++ /* PSE GDM3 MIB counter has incorrect hw default values, ++ * so the driver ought to read clear the values beforehand ++ * in case ethtool retrieve wrong mib values. ++ */ ++ for (i = 0; i < 0x80; i += 0x4) ++ mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i); ++ } else if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { + /* PSE should not drop port8 and port9 packets from WDMA Tx */ + mtk_w32(eth, 0x00000300, PSE_DROP_CFG); + +@@ -4368,7 +4433,11 @@ static int mtk_add_mac(struct mtk_eth *e + } + spin_lock_init(&mac->hw_stats->stats_lock); + u64_stats_init(&mac->hw_stats->syncp); +- mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; ++ ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) ++ mac->hw_stats->reg_offset = id * 0x80; ++ else ++ mac->hw_stats->reg_offset = id * 0x40; + + /* phylink create */ + err = of_get_phy_mode(np, &phy_mode); +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -121,6 +121,7 @@ + #define MTK_GDMA_ICS_EN BIT(22) + #define MTK_GDMA_TCS_EN BIT(21) + #define MTK_GDMA_UCS_EN BIT(20) ++#define MTK_GDMA_STRP_CRC BIT(16) + #define MTK_GDMA_TO_PDMA 0x0 + #define MTK_GDMA_DROP_ALL 0x7777 + +@@ -286,8 +287,6 @@ + /* QDMA Interrupt grouping registers */ + #define MTK_RLS_DONE_INT BIT(0) + +-#define MTK_STAT_OFFSET 0x40 +- + /* QDMA TX NUM */ + #define QID_BITS_V2(x) (((x) & 0x3f) << 16) + #define MTK_QDMA_GMAC2_QID 8 +@@ -300,6 +299,8 @@ + #define TX_DMA_CHKSUM_V2 (0x7 << 28) + #define TX_DMA_TSO_V2 BIT(31) + ++#define TX_DMA_SPTAG_V3 BIT(27) ++ + /* QDMA V2 descriptor txd4 */ + #define TX_DMA_FPORT_SHIFT_V2 8 + #define TX_DMA_FPORT_MASK_V2 0xf +@@ -639,6 +640,7 @@ enum mtk_tx_flags { + */ + MTK_TX_FLAGS_FPORT0 = 0x04, + MTK_TX_FLAGS_FPORT1 = 0x08, ++ MTK_TX_FLAGS_FPORT2 = 0x10, + }; + + /* This enum allows us to identify how the clock is defined on the array of the +@@ -724,6 +726,42 @@ enum mtk_dev_state { + MTK_RESETTING + }; + ++/* PSE Port Definition */ ++enum mtk_pse_port { ++ PSE_ADMA_PORT = 0, ++ PSE_GDM1_PORT, ++ PSE_GDM2_PORT, ++ PSE_PPE0_PORT, ++ PSE_PPE1_PORT, ++ PSE_QDMA_TX_PORT, ++ PSE_QDMA_RX_PORT, ++ PSE_DROP_PORT, ++ PSE_WDMA0_PORT, ++ PSE_WDMA1_PORT, ++ PSE_TDMA_PORT, ++ PSE_NONE_PORT, ++ PSE_PPE2_PORT, ++ PSE_WDMA2_PORT, ++ PSE_EIP197_PORT, ++ PSE_GDM3_PORT, ++ PSE_PORT_MAX ++}; ++ ++/* GMAC Identifier */ ++enum mtk_gmac_id { ++ MTK_GMAC1_ID = 0, ++ MTK_GMAC2_ID, ++ MTK_GMAC3_ID, ++ MTK_GMAC_ID_MAX ++}; ++ ++/* GDM Type */ ++enum mtk_gdm_type { ++ MTK_GDM_TYPE = 0, ++ MTK_XGDM_TYPE, ++ MTK_GDM_TYPE_MAX ++}; ++ + enum mtk_tx_buf_type { + MTK_TYPE_SKB, + MTK_TYPE_XDP_TX, +@@ -820,6 +858,7 @@ enum mkt_eth_capabilities { + MTK_QDMA_BIT, + MTK_NETSYS_V1_BIT, + MTK_NETSYS_V2_BIT, ++ MTK_NETSYS_V3_BIT, + MTK_SOC_MT7628_BIT, + MTK_RSTCTRL_PPE1_BIT, + MTK_U3_COPHY_V2_BIT, +@@ -856,6 +895,7 @@ enum mkt_eth_capabilities { + #define MTK_QDMA BIT(MTK_QDMA_BIT) + #define MTK_NETSYS_V1 BIT(MTK_NETSYS_V1_BIT) + #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) ++#define MTK_NETSYS_V3 BIT(MTK_NETSYS_V3_BIT) + #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) + #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) + #define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT) diff --git a/target/linux/generic/pending-6.1/737-05-net-ethernet-mtk_eth_soc-convert-caps-in-mtk_soc_dat.patch b/target/linux/generic/pending-6.1/737-05-net-ethernet-mtk_eth_soc-convert-caps-in-mtk_soc_dat.patch new file mode 100644 index 00000000000000..068201cf7dfb24 --- /dev/null +++ b/target/linux/generic/pending-6.1/737-05-net-ethernet-mtk_eth_soc-convert-caps-in-mtk_soc_dat.patch @@ -0,0 +1,197 @@ +From 45b575fd9e6a455090820248bf1b98b1f2c7b6c8 Mon Sep 17 00:00:00 2001 +From: Lorenzo Bianconi +Date: Tue, 7 Mar 2023 15:56:00 +0000 +Subject: [PATCH 5/7] net: ethernet: mtk_eth_soc: convert caps in mtk_soc_data + struct to u64 + +This is a preliminary patch to introduce support for MT7988 SoC. + +Signed-off-by: Lorenzo Bianconi +Signed-off-by: Daniel Golle +--- + drivers/net/ethernet/mediatek/mtk_eth_path.c | 22 +++---- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 62 ++++++++++---------- + 2 files changed, 42 insertions(+), 42 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_path.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c +@@ -15,10 +15,10 @@ + struct mtk_eth_muxc { + const char *name; + int cap_bit; +- int (*set_path)(struct mtk_eth *eth, int path); ++ int (*set_path)(struct mtk_eth *eth, u64 path); + }; + +-static const char *mtk_eth_path_name(int path) ++static const char *mtk_eth_path_name(u64 path) + { + switch (path) { + case MTK_ETH_PATH_GMAC1_RGMII: +@@ -40,7 +40,7 @@ static const char *mtk_eth_path_name(int + } + } + +-static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, int path) ++static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, u64 path) + { + bool updated = true; + u32 val, mask, set; +@@ -71,7 +71,7 @@ static int set_mux_gdm1_to_gmac1_esw(str + return 0; + } + +-static int set_mux_gmac2_gmac0_to_gephy(struct mtk_eth *eth, int path) ++static int set_mux_gmac2_gmac0_to_gephy(struct mtk_eth *eth, u64 path) + { + unsigned int val = 0; + bool updated = true; +@@ -94,7 +94,7 @@ static int set_mux_gmac2_gmac0_to_gephy( + return 0; + } + +-static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, int path) ++static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, u64 path) + { + unsigned int val = 0, mask = 0, reg = 0; + bool updated = true; +@@ -125,7 +125,7 @@ static int set_mux_u3_gmac2_to_qphy(stru + return 0; + } + +-static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, int path) ++static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, u64 path) + { + unsigned int val = 0; + bool updated = true; +@@ -163,7 +163,7 @@ static int set_mux_gmac1_gmac2_to_sgmii_ + return 0; + } + +-static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, int path) ++static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, u64 path) + { + unsigned int val = 0; + bool updated = true; +@@ -218,7 +218,7 @@ static const struct mtk_eth_muxc mtk_eth + }, + }; + +-static int mtk_eth_mux_setup(struct mtk_eth *eth, int path) ++static int mtk_eth_mux_setup(struct mtk_eth *eth, u64 path) + { + int i, err = 0; + +@@ -249,7 +249,7 @@ out: + + int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id) + { +- int path; ++ u64 path; + + path = (mac_id == 0) ? MTK_ETH_PATH_GMAC1_SGMII : + MTK_ETH_PATH_GMAC2_SGMII; +@@ -260,7 +260,7 @@ int mtk_gmac_sgmii_path_setup(struct mtk + + int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id) + { +- int path = 0; ++ u64 path = 0; + + if (mac_id == 1) + path = MTK_ETH_PATH_GMAC2_GEPHY; +@@ -274,7 +274,7 @@ int mtk_gmac_gephy_path_setup(struct mtk + + int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id) + { +- int path; ++ u64 path; + + path = (mac_id == 0) ? MTK_ETH_PATH_GMAC1_RGMII : + MTK_ETH_PATH_GMAC2_RGMII; +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -881,44 +881,44 @@ enum mkt_eth_capabilities { + }; + + /* Supported hardware group on SoCs */ +-#define MTK_RGMII BIT(MTK_RGMII_BIT) +-#define MTK_TRGMII BIT(MTK_TRGMII_BIT) +-#define MTK_SGMII BIT(MTK_SGMII_BIT) +-#define MTK_ESW BIT(MTK_ESW_BIT) +-#define MTK_GEPHY BIT(MTK_GEPHY_BIT) +-#define MTK_MUX BIT(MTK_MUX_BIT) +-#define MTK_INFRA BIT(MTK_INFRA_BIT) +-#define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT) +-#define MTK_HWLRO BIT(MTK_HWLRO_BIT) +-#define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) +-#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) +-#define MTK_QDMA BIT(MTK_QDMA_BIT) +-#define MTK_NETSYS_V1 BIT(MTK_NETSYS_V1_BIT) +-#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) +-#define MTK_NETSYS_V3 BIT(MTK_NETSYS_V3_BIT) +-#define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) +-#define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) +-#define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT) ++#define MTK_RGMII BIT_ULL(MTK_RGMII_BIT) ++#define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT) ++#define MTK_SGMII BIT_ULL(MTK_SGMII_BIT) ++#define MTK_ESW BIT_ULL(MTK_ESW_BIT) ++#define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT) ++#define MTK_MUX BIT_ULL(MTK_MUX_BIT) ++#define MTK_INFRA BIT_ULL(MTK_INFRA_BIT) ++#define MTK_SHARED_SGMII BIT_ULL(MTK_SHARED_SGMII_BIT) ++#define MTK_HWLRO BIT_ULL(MTK_HWLRO_BIT) ++#define MTK_SHARED_INT BIT_ULL(MTK_SHARED_INT_BIT) ++#define MTK_TRGMII_MT7621_CLK BIT_ULL(MTK_TRGMII_MT7621_CLK_BIT) ++#define MTK_QDMA BIT_ULL(MTK_QDMA_BIT) ++#define MTK_NETSYS_V1 BIT_ULL(MTK_NETSYS_V1_BIT) ++#define MTK_NETSYS_V2 BIT_ULL(MTK_NETSYS_V2_BIT) ++#define MTK_NETSYS_V3 BIT_ULL(MTK_NETSYS_V3_BIT) ++#define MTK_SOC_MT7628 BIT_ULL(MTK_SOC_MT7628_BIT) ++#define MTK_RSTCTRL_PPE1 BIT_ULL(MTK_RSTCTRL_PPE1_BIT) ++#define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT) + + #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ +- BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) ++ BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) + #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ +- BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) ++ BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) + #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ +- BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) ++ BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) + #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ +- BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) ++ BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) + #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ +- BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) ++ BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) + + /* Supported path present on SoCs */ +-#define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT) +-#define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) +-#define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT) +-#define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT) +-#define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) +-#define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT) +-#define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT) ++#define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT) ++#define MTK_ETH_PATH_GMAC1_TRGMII BIT_ULL(MTK_ETH_PATH_GMAC1_TRGMII_BIT) ++#define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT) ++#define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT) ++#define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT) ++#define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT) ++#define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT) + + #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) + #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) +@@ -1074,7 +1074,7 @@ struct mtk_reg_map { + struct mtk_soc_data { + const struct mtk_reg_map *reg_map; + u32 ana_rgc3; +- u32 caps; ++ u64 caps; + u32 required_clks; + bool required_pctl; + u8 offload_version; diff --git a/target/linux/generic/pending-6.1/737-06-net-ethernet-mtk_eth_soc-add-support-for-MT7988-SoC.patch b/target/linux/generic/pending-6.1/737-06-net-ethernet-mtk_eth_soc-add-support-for-MT7988-SoC.patch new file mode 100644 index 00000000000000..4e52e0da547a46 --- /dev/null +++ b/target/linux/generic/pending-6.1/737-06-net-ethernet-mtk_eth_soc-add-support-for-MT7988-SoC.patch @@ -0,0 +1,495 @@ +From 661bacf4363ca68939c15e20056b5f72fbd034e7 Mon Sep 17 00:00:00 2001 +From: Lorenzo Bianconi +Date: Sat, 25 Feb 2023 00:08:24 +0100 +Subject: [PATCH 6/7] net: ethernet: mtk_eth_soc: add support for MT7988 SoC + +Introduce support for ethernet chip available in MT7988 SoC to +mtk_eth_soc driver. +--- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 153 ++++++++++++++-- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 193 ++++++++++++++------ + 2 files changed, 279 insertions(+), 67 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -152,6 +152,54 @@ static const struct mtk_reg_map mt7986_r + .pse_oq_sta = 0x01a0, + }; + ++static const struct mtk_reg_map mt7988_reg_map = { ++ .tx_irq_mask = 0x461c, ++ .tx_irq_status = 0x4618, ++ .pdma = { ++ .rx_ptr = 0x6900, ++ .rx_cnt_cfg = 0x6904, ++ .pcrx_ptr = 0x6908, ++ .glo_cfg = 0x6a04, ++ .rst_idx = 0x6a08, ++ .delay_irq = 0x6a0c, ++ .irq_status = 0x6a20, ++ .irq_mask = 0x6a28, ++ .adma_rx_dbg0 = 0x6a38, ++ .int_grp = 0x6a50, ++ }, ++ .qdma = { ++ .qtx_cfg = 0x4400, ++ .qtx_sch = 0x4404, ++ .rx_ptr = 0x4500, ++ .rx_cnt_cfg = 0x4504, ++ .qcrx_ptr = 0x4508, ++ .glo_cfg = 0x4604, ++ .rst_idx = 0x4608, ++ .delay_irq = 0x460c, ++ .fc_th = 0x4610, ++ .int_grp = 0x4620, ++ .hred = 0x4644, ++ .ctx_ptr = 0x4700, ++ .dtx_ptr = 0x4704, ++ .crx_ptr = 0x4710, ++ .drx_ptr = 0x4714, ++ .fq_head = 0x4720, ++ .fq_tail = 0x4724, ++ .fq_count = 0x4728, ++ .fq_blen = 0x472c, ++ .tx_sch_rate = 0x4798, ++ }, ++ .gdm1_cnt = 0x1c00, ++ .gdma_to_ppe = 0x3333, ++ .ppe_base = 0x2200, ++ .wdma_base = { ++ [0] = 0x4800, ++ [1] = 0x4c00, ++ }, ++ .pse_iq_sta = 0x0180, ++ .pse_oq_sta = 0x01a0, ++}; ++ + /* strings used by ethtool */ + static const struct mtk_ethtool_stats { + char str[ETH_GSTRING_LEN]; +@@ -179,10 +227,54 @@ static const struct mtk_ethtool_stats { + }; + + static const char * const mtk_clks_source_name[] = { +- "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", +- "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", +- "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", +- "sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1" ++ "ethif", ++ "sgmiitop", ++ "esw", ++ "gp0", ++ "gp1", ++ "gp2", ++ "gp3", ++ "xgp1", ++ "xgp2", ++ "xgp3", ++ "crypto", ++ "fe", ++ "trgpll", ++ "sgmii_tx250m", ++ "sgmii_rx250m", ++ "sgmii_cdr_ref", ++ "sgmii_cdr_fb", ++ "sgmii2_tx250m", ++ "sgmii2_rx250m", ++ "sgmii2_cdr_ref", ++ "sgmii2_cdr_fb", ++ "sgmii_ck", ++ "eth2pll", ++ "wocpu0", ++ "wocpu1", ++ "netsys0", ++ "netsys1", ++ "ethwarp_wocpu2", ++ "ethwarp_wocpu1", ++ "ethwarp_wocpu0", ++ "top_usxgmii0_sel", ++ "top_usxgmii1_sel", ++ "top_sgm0_sel", ++ "top_sgm1_sel", ++ "top_xfi_phy0_xtal_sel", ++ "top_xfi_phy1_xtal_sel", ++ "top_eth_gmii_sel", ++ "top_eth_refck_50m_sel", ++ "top_eth_sys_200m_sel", ++ "top_eth_sys_sel", ++ "top_eth_xgmii_sel", ++ "top_eth_mii_sel", ++ "top_netsys_sel", ++ "top_netsys_500m_sel", ++ "top_netsys_pao_2x_sel", ++ "top_netsys_sync_250m_sel", ++ "top_netsys_ppefb_250m_sel", ++ "top_netsys_warp_sel", + }; + + void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) +@@ -1253,10 +1345,19 @@ static void mtk_tx_set_dma_desc_v2(struc + data |= TX_DMA_LS0; + WRITE_ONCE(desc->txd3, data); + +- if (mac->id == MTK_GMAC3_ID) +- data = PSE_GDM3_PORT; +- else +- data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */ ++ /* set forward port */ ++ switch (mac->id) { ++ case MTK_GMAC1_ID: ++ data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2; ++ break; ++ case MTK_GMAC2_ID: ++ data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2; ++ break; ++ case MTK_GMAC3_ID: ++ data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2; ++ break; ++ } ++ + data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); + WRITE_ONCE(desc->txd4, data); + +@@ -5016,6 +5117,25 @@ static const struct mtk_soc_data mt7986_ + }, + }; + ++static const struct mtk_soc_data mt7988_data = { ++ .reg_map = &mt7988_reg_map, ++ .ana_rgc3 = 0x128, ++ .caps = MT7988_CAPS, ++ .hw_features = MTK_HW_FEATURES, ++ .required_clks = MT7988_CLKS_BITMAP, ++ .required_pctl = false, ++ .num_devs = 3, ++ .txrx = { ++ .txd_size = sizeof(struct mtk_tx_dma_v2), ++ .rxd_size = sizeof(struct mtk_rx_dma_v2), ++ .rx_irq_done_mask = MTK_RX_DONE_INT_V2, ++ .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, ++ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, ++ .dma_len_offset = 8, ++ }, ++}; ++ ++ + static const struct mtk_soc_data rt5350_data = { + .reg_map = &mt7628_reg_map, + .caps = MT7628_CAPS, +@@ -5034,14 +5154,15 @@ static const struct mtk_soc_data rt5350_ + }; + + const struct of_device_id of_mtk_match[] = { +- { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, +- { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, +- { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, +- { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, +- { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, +- { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data}, +- { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data}, +- { .compatible = "ralink,rt5350-eth", .data = &rt5350_data}, ++ { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data }, ++ { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data }, ++ { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data }, ++ { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data }, ++ { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data }, ++ { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data }, ++ { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data }, ++ { .compatible = "mediatek,mt7988-eth", .data = &mt7988_data }, ++ { .compatible = "ralink,rt5350-eth", .data = &rt5350_data }, + {}, + }; + MODULE_DEVICE_TABLE(of, of_mtk_match); +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -116,7 +116,8 @@ + #define MTK_CDMP_EG_CTRL 0x404 + + /* GDM Exgress Control Register */ +-#define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) ++#define MTK_GDMA_FWD_CFG(x) ((x == MTK_GMAC3_ID) ? \ ++ 0x540 : 0x500 + (x * 0x1000)) + #define MTK_GDMA_SPECIAL_TAG BIT(24) + #define MTK_GDMA_ICS_EN BIT(22) + #define MTK_GDMA_TCS_EN BIT(21) +@@ -653,6 +654,11 @@ enum mtk_clks_map { + MTK_CLK_GP0, + MTK_CLK_GP1, + MTK_CLK_GP2, ++ MTK_CLK_GP3, ++ MTK_CLK_XGP1, ++ MTK_CLK_XGP2, ++ MTK_CLK_XGP3, ++ MTK_CLK_CRYPTO, + MTK_CLK_FE, + MTK_CLK_TRGPLL, + MTK_CLK_SGMII_TX_250M, +@@ -669,57 +675,108 @@ enum mtk_clks_map { + MTK_CLK_WOCPU1, + MTK_CLK_NETSYS0, + MTK_CLK_NETSYS1, ++ MTK_CLK_ETHWARP_WOCPU2, ++ MTK_CLK_ETHWARP_WOCPU1, ++ MTK_CLK_ETHWARP_WOCPU0, ++ MTK_CLK_TOP_USXGMII_SBUS_0_SEL, ++ MTK_CLK_TOP_USXGMII_SBUS_1_SEL, ++ MTK_CLK_TOP_SGM_0_SEL, ++ MTK_CLK_TOP_SGM_1_SEL, ++ MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL, ++ MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL, ++ MTK_CLK_TOP_ETH_GMII_SEL, ++ MTK_CLK_TOP_ETH_REFCK_50M_SEL, ++ MTK_CLK_TOP_ETH_SYS_200M_SEL, ++ MTK_CLK_TOP_ETH_SYS_SEL, ++ MTK_CLK_TOP_ETH_XGMII_SEL, ++ MTK_CLK_TOP_ETH_MII_SEL, ++ MTK_CLK_TOP_NETSYS_SEL, ++ MTK_CLK_TOP_NETSYS_500M_SEL, ++ MTK_CLK_TOP_NETSYS_PAO_2X_SEL, ++ MTK_CLK_TOP_NETSYS_SYNC_250M_SEL, ++ MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL, ++ MTK_CLK_TOP_NETSYS_WARP_SEL, + MTK_CLK_MAX + }; + +-#define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ +- BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ +- BIT(MTK_CLK_TRGPLL)) +-#define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ +- BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ +- BIT(MTK_CLK_GP2) | \ +- BIT(MTK_CLK_SGMII_TX_250M) | \ +- BIT(MTK_CLK_SGMII_RX_250M) | \ +- BIT(MTK_CLK_SGMII_CDR_REF) | \ +- BIT(MTK_CLK_SGMII_CDR_FB) | \ +- BIT(MTK_CLK_SGMII_CK) | \ +- BIT(MTK_CLK_ETH2PLL)) ++#define MT7623_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ ++ BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ ++ BIT_ULL(MTK_CLK_TRGPLL)) ++#define MT7622_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ ++ BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \ ++ BIT_ULL(MTK_CLK_GP2) | \ ++ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ ++ BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ ++ BIT_ULL(MTK_CLK_SGMII_CK) | \ ++ BIT_ULL(MTK_CLK_ETH2PLL)) + #define MT7621_CLKS_BITMAP (0) + #define MT7628_CLKS_BITMAP (0) +-#define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ +- BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ +- BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ +- BIT(MTK_CLK_SGMII_TX_250M) | \ +- BIT(MTK_CLK_SGMII_RX_250M) | \ +- BIT(MTK_CLK_SGMII_CDR_REF) | \ +- BIT(MTK_CLK_SGMII_CDR_FB) | \ +- BIT(MTK_CLK_SGMII2_TX_250M) | \ +- BIT(MTK_CLK_SGMII2_RX_250M) | \ +- BIT(MTK_CLK_SGMII2_CDR_REF) | \ +- BIT(MTK_CLK_SGMII2_CDR_FB) | \ +- BIT(MTK_CLK_SGMII_CK) | \ +- BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) +-#define MT7981_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ +- BIT(MTK_CLK_WOCPU0) | \ +- BIT(MTK_CLK_SGMII_TX_250M) | \ +- BIT(MTK_CLK_SGMII_RX_250M) | \ +- BIT(MTK_CLK_SGMII_CDR_REF) | \ +- BIT(MTK_CLK_SGMII_CDR_FB) | \ +- BIT(MTK_CLK_SGMII2_TX_250M) | \ +- BIT(MTK_CLK_SGMII2_RX_250M) | \ +- BIT(MTK_CLK_SGMII2_CDR_REF) | \ +- BIT(MTK_CLK_SGMII2_CDR_FB) | \ +- BIT(MTK_CLK_SGMII_CK)) +-#define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ +- BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \ +- BIT(MTK_CLK_SGMII_TX_250M) | \ +- BIT(MTK_CLK_SGMII_RX_250M) | \ +- BIT(MTK_CLK_SGMII_CDR_REF) | \ +- BIT(MTK_CLK_SGMII_CDR_FB) | \ +- BIT(MTK_CLK_SGMII2_TX_250M) | \ +- BIT(MTK_CLK_SGMII2_RX_250M) | \ +- BIT(MTK_CLK_SGMII2_CDR_REF) | \ +- BIT(MTK_CLK_SGMII2_CDR_FB)) ++#define MT7629_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ ++ BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \ ++ BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \ ++ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ ++ BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ ++ BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ ++ BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \ ++ BIT_ULL(MTK_CLK_SGMII_CK) | \ ++ BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP)) ++#define MT7981_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_GP1) | \ ++ BIT_ULL(MTK_CLK_WOCPU0) | \ ++ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ ++ BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ ++ BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ ++ BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \ ++ BIT_ULL(MTK_CLK_SGMII_CK)) ++#define MT7986_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_GP1) | \ ++ BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \ ++ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ ++ BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ ++ BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ ++ BIT_ULL(MTK_CLK_SGMII2_CDR_FB)) ++#define MT7988_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \ ++ BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ ++ BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \ ++ BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \ ++ BIT_ULL(MTK_CLK_CRYPTO) | \ ++ BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ ++ BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ ++ BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \ ++ BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \ ++ BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \ ++ BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \ ++ BIT_ULL(MTK_CLK_TOP_NETSYS_WARP_SEL)) + + enum mtk_dev_state { + MTK_HW_INIT, +@@ -847,6 +904,7 @@ enum mkt_eth_capabilities { + MTK_RGMII_BIT = 0, + MTK_TRGMII_BIT, + MTK_SGMII_BIT, ++ MTK_USXGMII_BIT, + MTK_ESW_BIT, + MTK_GEPHY_BIT, + MTK_MUX_BIT, +@@ -869,6 +927,8 @@ enum mkt_eth_capabilities { + MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, + MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, + MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, ++ MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT, ++ MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT, + + /* PATH BITS */ + MTK_ETH_PATH_GMAC1_RGMII_BIT, +@@ -877,13 +937,18 @@ enum mkt_eth_capabilities { + MTK_ETH_PATH_GMAC2_RGMII_BIT, + MTK_ETH_PATH_GMAC2_SGMII_BIT, + MTK_ETH_PATH_GMAC2_GEPHY_BIT, ++ MTK_ETH_PATH_GMAC3_SGMII_BIT, + MTK_ETH_PATH_GDM1_ESW_BIT, ++ MTK_ETH_PATH_GMAC1_USXGMII_BIT, ++ MTK_ETH_PATH_GMAC2_USXGMII_BIT, ++ MTK_ETH_PATH_GMAC3_USXGMII_BIT, + }; + + /* Supported hardware group on SoCs */ + #define MTK_RGMII BIT_ULL(MTK_RGMII_BIT) + #define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT) + #define MTK_SGMII BIT_ULL(MTK_SGMII_BIT) ++#define MTK_USXGMII BIT_ULL(MTK_USXGMII_BIT) + #define MTK_ESW BIT_ULL(MTK_ESW_BIT) + #define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT) + #define MTK_MUX BIT_ULL(MTK_MUX_BIT) +@@ -910,6 +975,10 @@ enum mkt_eth_capabilities { + BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) + #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ + BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) ++#define MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII \ ++ BIT_ULL(MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT) ++#define MTK_ETH_MUX_GMAC123_TO_USXGMII \ ++ BIT_ULL(MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT) + + /* Supported path present on SoCs */ + #define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT) +@@ -918,7 +987,11 @@ enum mkt_eth_capabilities { + #define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT) + #define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT) + #define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT) ++#define MTK_ETH_PATH_GMAC3_SGMII BIT_ULL(MTK_ETH_PATH_GMAC3_SGMII_BIT) + #define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT) ++#define MTK_ETH_PATH_GMAC1_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC1_USXGMII_BIT) ++#define MTK_ETH_PATH_GMAC2_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC2_USXGMII_BIT) ++#define MTK_ETH_PATH_GMAC3_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC3_USXGMII_BIT) + + #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) + #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) +@@ -926,7 +999,11 @@ enum mkt_eth_capabilities { + #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) + #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) + #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) ++#define MTK_GMAC3_SGMII (MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII) + #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) ++#define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII) ++#define MTK_GMAC2_USXGMII (MTK_ETH_PATH_GMAC2_USXGMII | MTK_USXGMII) ++#define MTK_GMAC3_USXGMII (MTK_ETH_PATH_GMAC3_USXGMII | MTK_USXGMII) + + /* MUXes present on SoCs */ + /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */ +@@ -949,6 +1026,12 @@ enum mkt_eth_capabilities { + #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ + (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) + ++#define MTK_MUX_GMAC123_TO_GEPHY_SGMII \ ++ (MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII | MTK_MUX) ++ ++#define MTK_MUX_GMAC123_TO_USXGMII \ ++ (MTK_ETH_MUX_GMAC123_TO_USXGMII | MTK_MUX | MTK_INFRA) ++ + #ifdef CONFIG_SOC_MT7621 + #define MTK_CAP_MASK MTK_NETSYS_V2 + #else +@@ -987,9 +1070,17 @@ enum mkt_eth_capabilities { + MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \ + MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) + +-#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ +- MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ +- MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) ++#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ ++ MTK_MUX_GMAC12_TO_GEPHY_SGMII | \ ++ MTK_QDMA | MTK_NETSYS_V2 | \ ++ MTK_RSTCTRL_PPE1) ++ ++#define MT7988_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ ++ MTK_GMAC3_SGMII | MTK_QDMA | \ ++ MTK_MUX_GMAC123_TO_GEPHY_SGMII | \ ++ MTK_NETSYS_V3 | MTK_RSTCTRL_PPE1 | \ ++ MTK_GMAC1_USXGMII | MTK_GMAC2_USXGMII | \ ++ MTK_GMAC3_USXGMII | MTK_MUX_GMAC123_TO_USXGMII) + + struct mtk_tx_dma_desc_info { + dma_addr_t addr; +@@ -1075,7 +1166,7 @@ struct mtk_soc_data { + const struct mtk_reg_map *reg_map; + u32 ana_rgc3; + u64 caps; +- u32 required_clks; ++ u64 required_clks; + bool required_pctl; + u8 offload_version; + u8 hash_offset; diff --git a/target/linux/generic/pending-6.1/737-07-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch b/target/linux/generic/pending-6.1/737-07-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch new file mode 100644 index 00000000000000..abde00cf617c00 --- /dev/null +++ b/target/linux/generic/pending-6.1/737-07-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch @@ -0,0 +1,1867 @@ +From 3d833ad2cfc1ab503d9aae2967b7f10811bb3c9c Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Wed, 1 Mar 2023 11:56:04 +0000 +Subject: [PATCH 7/7] net: ethernet: mtk_eth_soc: add paths and SerDes modes + for MT7988 + +MT7988 comes with a built-in 2.5G PHY as well as +USXGMII/10GBase-KR/5GBase-KR compatible SerDes lanes for external PHYs. +Add support for configuring the MAC and SerDes parts for the new paths. + +Signed-off-by: Daniel Golle +--- + drivers/net/ethernet/mediatek/Kconfig | 7 + + drivers/net/ethernet/mediatek/Makefile | 1 + + drivers/net/ethernet/mediatek/mtk_eth_path.c | 154 +++- + drivers/net/ethernet/mediatek/mtk_eth_soc.c | 270 +++++- + drivers/net/ethernet/mediatek/mtk_eth_soc.h | 194 ++++- + drivers/net/ethernet/mediatek/mtk_usxgmii.c | 835 +++++++++++++++++++ + 6 files changed, 1428 insertions(+), 33 deletions(-) + create mode 100644 drivers/net/ethernet/mediatek/mtk_usxgmii.c + +--- a/drivers/net/ethernet/mediatek/Kconfig ++++ b/drivers/net/ethernet/mediatek/Kconfig +@@ -25,6 +25,13 @@ config NET_MEDIATEK_SOC + This driver supports the gigabit ethernet MACs in the + MediaTek SoC family. + ++config NET_MEDIATEK_SOC_USXGMII ++ bool "Support USXGMII SerDes on MT7988" ++ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST ++ def_bool NET_MEDIATEK_SOC != n ++ help ++ Include support for 10G SerDes which can be found on MT7988. ++ + config NET_MEDIATEK_STAR_EMAC + tristate "MediaTek STAR Ethernet MAC support" + select PHYLIB +--- a/drivers/net/ethernet/mediatek/Makefile ++++ b/drivers/net/ethernet/mediatek/Makefile +@@ -5,6 +5,7 @@ + + obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o + mtk_eth-y := mtk_eth_soc.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o ++mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_USXGMII) += mtk_usxgmii.o + mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o mtk_wed_wo.o + ifdef CONFIG_DEBUG_FS + mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o +--- a/drivers/net/ethernet/mediatek/mtk_eth_path.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c +@@ -31,10 +31,20 @@ static const char *mtk_eth_path_name(u64 + return "gmac2_rgmii"; + case MTK_ETH_PATH_GMAC2_SGMII: + return "gmac2_sgmii"; ++ case MTK_ETH_PATH_GMAC2_2P5GPHY: ++ return "gmac2_2p5gphy"; + case MTK_ETH_PATH_GMAC2_GEPHY: + return "gmac2_gephy"; ++ case MTK_ETH_PATH_GMAC3_SGMII: ++ return "gmac3_sgmii"; + case MTK_ETH_PATH_GDM1_ESW: + return "gdm1_esw"; ++ case MTK_ETH_PATH_GMAC1_USXGMII: ++ return "gmac1_usxgmii"; ++ case MTK_ETH_PATH_GMAC2_USXGMII: ++ return "gmac2_usxgmii"; ++ case MTK_ETH_PATH_GMAC3_USXGMII: ++ return "gmac3_usxgmii"; + default: + return "unknown path"; + } +@@ -42,8 +52,8 @@ static const char *mtk_eth_path_name(u64 + + static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, u64 path) + { ++ u32 val, mask, set, reg; + bool updated = true; +- u32 val, mask, set; + + switch (path) { + case MTK_ETH_PATH_GMAC1_SGMII: +@@ -59,10 +69,15 @@ static int set_mux_gdm1_to_gmac1_esw(str + break; + } + ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) ++ reg = MTK_MAC_MISC_V3; ++ else ++ reg = MTK_MAC_MISC; ++ + if (updated) { +- val = mtk_r32(eth, MTK_MAC_MISC); ++ val = mtk_r32(eth, reg); + val = (val & mask) | set; +- mtk_w32(eth, val, MTK_MAC_MISC); ++ mtk_w32(eth, val, reg); + } + + dev_dbg(eth->dev, "path %s in %s updated = %d\n", +@@ -125,6 +140,31 @@ static int set_mux_u3_gmac2_to_qphy(stru + return 0; + } + ++static int set_mux_gmac2_to_2p5gphy(struct mtk_eth *eth, u64 path) ++{ ++ unsigned int val = 0; ++ bool updated = true; ++ int mac_id = 0; ++ ++ regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); ++ ++ switch (path) { ++ case MTK_ETH_PATH_GMAC2_2P5GPHY: ++ val &= ~(u32)SYSCFG0_SGMII_GMAC2_V2; ++ mac_id = MTK_GMAC2_ID; ++ break; ++ default: ++ updated = false; ++ break; ++ }; ++ ++ if (updated) ++ regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, ++ SYSCFG0_SGMII_MASK, val); ++ ++ return 0; ++} ++ + static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, u64 path) + { + unsigned int val = 0; +@@ -163,7 +203,61 @@ static int set_mux_gmac1_gmac2_to_sgmii_ + return 0; + } + +-static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, u64 path) ++static int set_mux_gmac123_to_usxgmii(struct mtk_eth *eth, u64 path) ++{ ++ unsigned int val = 0; ++ bool updated = true; ++ int mac_id = 0; ++ ++ dev_dbg(eth->dev, "path %s in %s updated = %d\n", ++ mtk_eth_path_name(path), __func__, updated); ++ ++ /* Disable SYSCFG1 SGMII */ ++ regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); ++ ++ switch (path) { ++ case MTK_ETH_PATH_GMAC1_USXGMII: ++ val &= ~(u32)SYSCFG0_SGMII_GMAC1_V2; ++ mac_id = MTK_GMAC1_ID; ++ break; ++ case MTK_ETH_PATH_GMAC2_USXGMII: ++ val &= ~(u32)SYSCFG0_SGMII_GMAC2_V2; ++ mac_id = MTK_GMAC2_ID; ++ break; ++ case MTK_ETH_PATH_GMAC3_USXGMII: ++ val &= ~(u32)SYSCFG0_SGMII_GMAC3_V2; ++ mac_id = MTK_GMAC3_ID; ++ break; ++ default: ++ updated = false; ++ }; ++ ++ if (updated) { ++ regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, ++ SYSCFG0_SGMII_MASK, val); ++ ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) && ++ mac_id == MTK_GMAC2_ID) { ++ regmap_update_bits(eth->infra, ++ TOP_MISC_NETSYS_PCS_MUX, ++ NETSYS_PCS_MUX_MASK, ++ MUX_G2_USXGMII_SEL); ++ } ++ } ++ ++ /* Enable XGDM Path */ ++ val = mtk_r32(eth, MTK_GDMA_EG_CTRL(mac_id)); ++ val |= MTK_GDMA_XGDM_SEL; ++ mtk_w32(eth, val, MTK_GDMA_EG_CTRL(mac_id)); ++ ++ dev_dbg(eth->dev, "path %s in %s updated = %d\n", ++ mtk_eth_path_name(path), __func__, updated); ++ ++ ++ return 0; ++} ++ ++static int set_mux_gmac123_to_gephy_sgmii(struct mtk_eth *eth, u64 path) + { + unsigned int val = 0; + bool updated = true; +@@ -180,6 +274,9 @@ static int set_mux_gmac12_to_gephy_sgmii + case MTK_ETH_PATH_GMAC2_SGMII: + val |= SYSCFG0_SGMII_GMAC2_V2; + break; ++ case MTK_ETH_PATH_GMAC3_SGMII: ++ val |= SYSCFG0_SGMII_GMAC3_V2; ++ break; + default: + updated = false; + } +@@ -208,13 +305,25 @@ static const struct mtk_eth_muxc mtk_eth + .cap_bit = MTK_ETH_MUX_U3_GMAC2_TO_QPHY, + .set_path = set_mux_u3_gmac2_to_qphy, + }, { ++ .name = "mux_gmac2_to_2p5gphy", ++ .cap_bit = MTK_ETH_MUX_GMAC2_TO_2P5GPHY, ++ .set_path = set_mux_gmac2_to_2p5gphy, ++ }, { + .name = "mux_gmac1_gmac2_to_sgmii_rgmii", + .cap_bit = MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII, + .set_path = set_mux_gmac1_gmac2_to_sgmii_rgmii, + }, { + .name = "mux_gmac12_to_gephy_sgmii", + .cap_bit = MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII, +- .set_path = set_mux_gmac12_to_gephy_sgmii, ++ .set_path = set_mux_gmac123_to_gephy_sgmii, ++ }, { ++ .name = "mux_gmac123_to_gephy_sgmii", ++ .cap_bit = MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII, ++ .set_path = set_mux_gmac123_to_gephy_sgmii, ++ }, { ++ .name = "mux_gmac123_to_usxgmii", ++ .cap_bit = MTK_ETH_MUX_GMAC123_TO_USXGMII, ++ .set_path = set_mux_gmac123_to_usxgmii, + }, + }; + +@@ -243,16 +352,46 @@ static int mtk_eth_mux_setup(struct mtk_ + } + } + ++ dev_dbg(eth->dev, "leaving mux_setup %s\n", ++ mtk_eth_path_name(path)); ++ + out: + return err; + } + ++int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id) ++{ ++ u64 path; ++ ++ path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_USXGMII : ++ (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_USXGMII : ++ MTK_ETH_PATH_GMAC3_USXGMII; ++ ++ /* Setup proper MUXes along the path */ ++ return mtk_eth_mux_setup(eth, path); ++} ++ + int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id) + { + u64 path; + +- path = (mac_id == 0) ? MTK_ETH_PATH_GMAC1_SGMII : +- MTK_ETH_PATH_GMAC2_SGMII; ++ path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_SGMII : ++ (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_SGMII : ++ MTK_ETH_PATH_GMAC3_SGMII; ++ ++ /* Setup proper MUXes along the path */ ++ return mtk_eth_mux_setup(eth, path); ++} ++ ++int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id) ++{ ++ u64 path = 0; ++ ++ if (mac_id == MTK_GMAC2_ID) ++ path = MTK_ETH_PATH_GMAC2_2P5GPHY; ++ ++ if (!path) ++ return -EINVAL; + + /* Setup proper MUXes along the path */ + return mtk_eth_mux_setup(eth, path); +@@ -282,4 +421,3 @@ int mtk_gmac_rgmii_path_setup(struct mtk + /* Setup proper MUXes along the path */ + return mtk_eth_mux_setup(eth, path); + } +- +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c +@@ -480,6 +480,23 @@ static void mtk_gmac0_rgmii_adjust(struc + mtk_w32(eth, val, TRGMII_TCK_CTRL); + } + ++static void mtk_setup_bridge_switch(struct mtk_eth *eth) ++{ ++ int val; ++ ++ /* Force Port1 XGMAC Link Up */ ++ val = mtk_r32(eth, MTK_XGMAC_STS(MTK_GMAC1_ID)); ++ mtk_w32(eth, val | MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID), ++ MTK_XGMAC_STS(MTK_GMAC1_ID)); ++ ++ /* Adjust GSW bridge IPG to 11*/ ++ val = mtk_r32(eth, MTK_GSW_CFG); ++ val &= ~(GSWTX_IPG_MASK | GSWRX_IPG_MASK); ++ val |= (GSW_IPG_11 << GSWTX_IPG_SHIFT) | ++ (GSW_IPG_11 << GSWRX_IPG_SHIFT); ++ mtk_w32(eth, val, MTK_GSW_CFG); ++} ++ + static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, + phy_interface_t interface) + { +@@ -494,6 +511,12 @@ static struct phylink_pcs *mtk_mac_selec + 0 : mac->id; + + return eth->sgmii_pcs[sid]; ++ } else if ((interface == PHY_INTERFACE_MODE_USXGMII || ++ interface == PHY_INTERFACE_MODE_10GKR || ++ interface == PHY_INTERFACE_MODE_5GBASER) && ++ MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) && ++ mac->id != MTK_GMAC1_ID) { ++ return mtk_usxgmii_select_pcs(eth, mac->id); + } + + return NULL; +@@ -505,7 +528,7 @@ static void mtk_mac_config(struct phylin + struct mtk_mac *mac = container_of(config, struct mtk_mac, + phylink_config); + struct mtk_eth *eth = mac->hw; +- int val, ge_mode, err = 0; ++ int val, ge_mode, force_link, err = 0; + u32 i; + + /* MT76x8 has no hardware settings between for the MAC */ +@@ -549,6 +572,23 @@ static void mtk_mac_config(struct phylin + goto init_err; + } + break; ++ case PHY_INTERFACE_MODE_USXGMII: ++ case PHY_INTERFACE_MODE_10GKR: ++ case PHY_INTERFACE_MODE_5GBASER: ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) { ++ err = mtk_gmac_usxgmii_path_setup(eth, mac->id); ++ if (err) ++ goto init_err; ++ } ++ break; ++ case PHY_INTERFACE_MODE_INTERNAL: ++ if (mac->id == MTK_GMAC2_ID && ++ MTK_HAS_CAPS(eth->soc->caps, MTK_2P5GPHY)) { ++ err = mtk_gmac_2p5gphy_path_setup(eth, mac->id); ++ if (err) ++ goto init_err; ++ } ++ break; + default: + goto err_phy; + } +@@ -627,14 +667,78 @@ static void mtk_mac_config(struct phylin + SYSCFG0_SGMII_MASK, + ~(u32)SYSCFG0_SGMII_MASK); + ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { ++ mtk_xfi_pll_enable(eth); ++ mtk_sgmii_reset(eth, mac->id); ++ if (phylink_autoneg_inband(mode)) ++ mtk_sgmii_setup_phya_gen1(eth, mac->id); ++ else ++ mtk_sgmii_setup_phya_gen2(eth, mac->id); ++ } + /* Save the syscfg0 value for mac_finish */ + mac->syscfg0 = val; +- } else if (phylink_autoneg_inband(mode)) { ++ } else if (state->interface != PHY_INTERFACE_MODE_USXGMII && ++ state->interface != PHY_INTERFACE_MODE_10GKR && ++ state->interface != PHY_INTERFACE_MODE_5GBASER && ++ phylink_autoneg_inband(mode)) { + dev_err(eth->dev, +- "In-band mode not supported in non SGMII mode!\n"); ++ "In-band mode not supported in non-SerDes modes!\n"); + return; + } + ++ /* Setup gmac */ ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) && ++ (mtk_interface_mode_is_xgmii(state->interface) || ++ mac->interface == PHY_INTERFACE_MODE_INTERNAL)) { ++ mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id)); ++ mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id)); ++ ++ switch (mac->id) { ++ case MTK_GMAC1_ID: ++ mtk_setup_bridge_switch(eth); ++ break; ++ case MTK_GMAC2_ID: ++ force_link = (mac->interface == ++ PHY_INTERFACE_MODE_INTERNAL) ? ++ MTK_XGMAC_FORCE_LINK(mac->id) : 0; ++ val = mtk_r32(eth, MTK_XGMAC_STS(mac->id)); ++ mtk_w32(eth, val | force_link, ++ MTK_XGMAC_STS(mac->id)); ++ break; ++ case MTK_GMAC3_ID: ++ val = mtk_r32(eth, MTK_XGMAC_STS(mac->id)); ++ mtk_w32(eth, val | MTK_XGMAC_FORCE_LINK(mac->id), ++ MTK_XGMAC_STS(mac->id)); ++ break; ++ } ++ } else { ++ val = mtk_r32(eth, MTK_GDMA_EG_CTRL(mac->id)); ++ mtk_w32(eth, val & ~MTK_GDMA_XGDM_SEL, ++ MTK_GDMA_EG_CTRL(mac->id)); ++ ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { ++ switch (mac->id) { ++ case MTK_GMAC2_ID: ++ case MTK_GMAC3_ID: ++ val = mtk_r32(eth, MTK_XGMAC_STS(mac->id)); ++ mtk_w32(eth, ++ val & ~MTK_XGMAC_FORCE_LINK(mac->id), ++ MTK_XGMAC_STS(mac->id)); ++ break; ++ } ++ } ++ ++/* ++ if (mac->type != mac_type) { ++ if (atomic_read(&reset_pending) == 0) { ++ atomic_inc(&force); ++ schedule_work(ð->pending_work); ++ atomic_inc(&reset_pending); ++ } else ++ atomic_dec(&reset_pending); ++ } ++*/ ++ } + return; + + err_phy: +@@ -675,11 +779,40 @@ static int mtk_mac_finish(struct phylink + return 0; + } + +-static void mtk_mac_pcs_get_state(struct phylink_config *config, ++static void mtk_xgdm_pcs_get_state(struct mtk_mac *mac, ++ struct phylink_link_state *state) ++{ ++ u32 sts = mtk_r32(mac->hw, MTK_XGMAC_STS(mac->id)); ++ ++ if (mac->id == MTK_GMAC2_ID) ++ sts = sts >> 16; ++ ++ state->link = FIELD_GET(MTK_USXGMII_PCS_LINK, sts); ++ if (!state->link) ++ return; ++ ++ state->duplex = DUPLEX_FULL; ++ state->interface = mac->interface; ++ ++ switch (FIELD_GET(MTK_USXGMII_PCS_MODE, sts)) { ++ case 0: ++ state->speed = SPEED_10000; ++ break; ++ case 1: ++ state->speed = SPEED_5000; ++ break; ++ case 2: ++ state->speed = SPEED_2500; ++ break; ++ case 3: ++ state->speed = SPEED_1000; ++ break; ++ } ++} ++ ++static void mtk_gdm_pcs_get_state(struct mtk_mac *mac, + struct phylink_link_state *state) + { +- struct mtk_mac *mac = container_of(config, struct mtk_mac, +- phylink_config); + u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id)); + + state->link = (pmsr & MAC_MSR_LINK); +@@ -707,15 +840,35 @@ static void mtk_mac_pcs_get_state(struct + state->pause |= MLO_PAUSE_TX; + } + ++static void mtk_mac_pcs_get_state(struct phylink_config *config, ++ struct phylink_link_state *state) ++{ ++ struct mtk_mac *mac = container_of(config, struct mtk_mac, ++ phylink_config); ++ ++ if (mtk_interface_mode_is_xgmii(state->interface)) ++ mtk_xgdm_pcs_get_state(mac, state); ++ else ++ mtk_gdm_pcs_get_state(mac, state); ++} ++ + static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, + phy_interface_t interface) + { + struct mtk_mac *mac = container_of(config, struct mtk_mac, + phylink_config); +- u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); ++ u32 mcr; + +- mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); +- mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); ++ if (!mtk_interface_mode_is_xgmii(interface)) { ++ mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); ++ mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); ++ mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); ++ } else if (mac->id != MTK_GMAC1_ID) { ++ mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id)); ++ mcr &= 0xfffffff0; ++ mcr |= XMAC_MCR_TRX_DISABLE; ++ mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id)); ++ } + } + + static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx, +@@ -787,13 +940,11 @@ static void mtk_set_queue_speed(struct m + mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); + } + +-static void mtk_mac_link_up(struct phylink_config *config, +- struct phy_device *phy, +- unsigned int mode, phy_interface_t interface, +- int speed, int duplex, bool tx_pause, bool rx_pause) ++static void mtk_gdm_mac_link_up(struct mtk_mac *mac, ++ struct phy_device *phy, ++ unsigned int mode, phy_interface_t interface, ++ int speed, int duplex, bool tx_pause, bool rx_pause) + { +- struct mtk_mac *mac = container_of(config, struct mtk_mac, +- phylink_config); + u32 mcr; + + mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); +@@ -827,6 +978,47 @@ static void mtk_mac_link_up(struct phyli + mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); + } + ++static void mtk_xgdm_mac_link_up(struct mtk_mac *mac, ++ struct phy_device *phy, ++ unsigned int mode, phy_interface_t interface, ++ int speed, int duplex, bool tx_pause, bool rx_pause) ++{ ++ u32 mcr; ++ ++ if (mac->id == MTK_GMAC1_ID) ++ return; ++ ++ mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id)); ++ ++ mcr &= ~(XMAC_MCR_FORCE_TX_FC | XMAC_MCR_FORCE_RX_FC); ++ /* Configure pause modes - ++ * phylink will avoid these for half duplex ++ */ ++ if (tx_pause) ++ mcr |= XMAC_MCR_FORCE_TX_FC; ++ if (rx_pause) ++ mcr |= XMAC_MCR_FORCE_RX_FC; ++ ++ mcr &= ~(XMAC_MCR_TRX_DISABLE); ++ mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id)); ++} ++ ++static void mtk_mac_link_up(struct phylink_config *config, ++ struct phy_device *phy, ++ unsigned int mode, phy_interface_t interface, ++ int speed, int duplex, bool tx_pause, bool rx_pause) ++{ ++ struct mtk_mac *mac = container_of(config, struct mtk_mac, ++ phylink_config); ++ ++ if (mtk_interface_mode_is_xgmii(interface)) ++ mtk_xgdm_mac_link_up(mac, phy, mode, interface, speed, duplex, ++ tx_pause, rx_pause); ++ else ++ mtk_gdm_mac_link_up(mac, phy, mode, interface, speed, duplex, ++ tx_pause, rx_pause); ++} ++ + static const struct phylink_mac_ops mtk_phylink_ops = { + .validate = phylink_generic_validate, + .mac_select_pcs = mtk_mac_select_pcs, +@@ -880,10 +1072,21 @@ static int mtk_mdio_init(struct mtk_eth + } + divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63); + ++ /* Configure MDC Turbo Mode */ ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { ++ val = mtk_r32(eth, MTK_MAC_MISC_V3); ++ val |= MISC_MDC_TURBO; ++ mtk_w32(eth, val, MTK_MAC_MISC_V3); ++ } else { ++ val = mtk_r32(eth, MTK_PPSC); ++ val |= PPSC_MDC_TURBO; ++ mtk_w32(eth, val, MTK_PPSC); ++ } ++ + /* Configure MDC Divider */ + val = mtk_r32(eth, MTK_PPSC); + val &= ~PPSC_MDC_CFG; +- val |= FIELD_PREP(PPSC_MDC_CFG, divider) | PPSC_MDC_TURBO; ++ val |= FIELD_PREP(PPSC_MDC_CFG, divider); + mtk_w32(eth, val, MTK_PPSC); + + dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider); +@@ -4487,8 +4690,8 @@ static int mtk_add_mac(struct mtk_eth *e + const __be32 *_id = of_get_property(np, "reg", NULL); + phy_interface_t phy_mode; + struct phylink *phylink; +- struct mtk_mac *mac; + int id, err; ++ struct mtk_mac *mac; + int txqs = 1; + + if (!_id) { +@@ -4579,6 +4782,32 @@ static int mtk_add_mac(struct mtk_eth *e + mac->phylink_config.supported_interfaces); + } + ++ if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_USXGMII)) { ++ if (id == MTK_GMAC1_ID) { ++ mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | ++ MAC_SYM_PAUSE | ++ MAC_10000FD; ++ phy_interface_zero( ++ mac->phylink_config.supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_INTERNAL, ++ mac->phylink_config.supported_interfaces); ++ } else { ++ mac->phylink_config.mac_capabilities |= MAC_5000FD | MAC_10000FD; ++ __set_bit(PHY_INTERFACE_MODE_5GBASER, ++ mac->phylink_config.supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_10GKR, ++ mac->phylink_config.supported_interfaces); ++ __set_bit(PHY_INTERFACE_MODE_USXGMII, ++ mac->phylink_config.supported_interfaces); ++ } ++ } ++ ++ if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_2P5GPHY)) { ++ if (id == MTK_GMAC2_ID) ++ __set_bit(PHY_INTERFACE_MODE_INTERNAL, ++ mac->phylink_config.supported_interfaces); ++ } ++ + phylink = phylink_create(&mac->phylink_config, + of_fwnode_handle(mac->of_node), + phy_mode, &mtk_phylink_ops); +@@ -4766,6 +4995,13 @@ static int mtk_probe(struct platform_dev + + if (err) + return err; ++ } ++ ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) { ++ err = mtk_usxgmii_init(eth); ++ ++ if (err) ++ return err; + } + + if (eth->soc->required_pctl) { +--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h ++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h +@@ -126,6 +126,11 @@ + #define MTK_GDMA_TO_PDMA 0x0 + #define MTK_GDMA_DROP_ALL 0x7777 + ++/* GDM Egress Control Register */ ++#define MTK_GDMA_EG_CTRL(x) ((x == MTK_GMAC3_ID) ? \ ++ 0x544 : 0x504 + (x * 0x1000)) ++#define MTK_GDMA_XGDM_SEL BIT(31) ++ + /* Unicast Filter MAC Address Register - Low */ + #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) + +@@ -389,7 +394,26 @@ + #define PHY_IAC_TIMEOUT HZ + + #define MTK_MAC_MISC 0x1000c ++#define MTK_MAC_MISC_V3 0x10010 + #define MTK_MUX_TO_ESW BIT(0) ++#define MISC_MDC_TURBO BIT(4) ++ ++/* XMAC status registers */ ++#define MTK_XGMAC_STS(x) ((x == MTK_GMAC3_ID) ? 0x1001C : 0x1000C) ++#define MTK_XGMAC_FORCE_LINK(x) ((x == MTK_GMAC2_ID) ? BIT(31) : BIT(15)) ++#define MTK_USXGMII_PCS_LINK BIT(8) ++#define MTK_XGMAC_RX_FC BIT(5) ++#define MTK_XGMAC_TX_FC BIT(4) ++#define MTK_USXGMII_PCS_MODE GENMASK(3, 1) ++#define MTK_XGMAC_LINK_STS BIT(0) ++ ++/* GSW bridge registers */ ++#define MTK_GSW_CFG (0x10080) ++#define GSWTX_IPG_MASK GENMASK(19, 16) ++#define GSWTX_IPG_SHIFT 16 ++#define GSWRX_IPG_MASK GENMASK(3, 0) ++#define GSWRX_IPG_SHIFT 0 ++#define GSW_IPG_11 11 + + /* Mac control registers */ + #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) +@@ -414,6 +438,17 @@ + #define MAC_MCR_FORCE_LINK BIT(0) + #define MAC_MCR_FORCE_LINK_DOWN (MAC_MCR_FORCE_MODE) + ++/* Mac EEE control registers */ ++#define MTK_MAC_EEE(x) (0x10104 + (x * 0x100)) ++#define MAC_EEE_WAKEUP_TIME_1000 GENMASK(31, 24) ++#define MAC_EEE_WAKEUP_TIME_100 GENMASK(23, 16) ++#define MAC_EEE_LPI_TXIDLE_THD GENMASK(15, 8) ++#define MAC_EEE_RESV0 GENMASK(7, 4) ++#define MAC_EEE_CKG_TXILDE BIT(3) ++#define MAC_EEE_CKG_RXLPI BIT(2) ++#define MAC_EEE_TX_DOWN_REQ BIT(1) ++#define MAC_EEE_LPI_MODE BIT(0) ++ + /* Mac status registers */ + #define MTK_MAC_MSR(x) (0x10108 + (x * 0x100)) + #define MAC_MSR_EEE1G BIT(7) +@@ -458,6 +493,12 @@ + #define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED) + #define INTF_MODE_RGMII_10_100 0 + ++/* XFI Mac control registers */ ++#define MTK_XMAC_MCR(x) (0x12000 + ((x - 1) * 0x1000)) ++#define XMAC_MCR_TRX_DISABLE 0xf ++#define XMAC_MCR_FORCE_TX_FC BIT(5) ++#define XMAC_MCR_FORCE_RX_FC BIT(4) ++ + /* GPIO port control registers for GMAC 2*/ + #define GPIO_OD33_CTRL8 0x4c0 + #define GPIO_BIAS_CTRL 0xed0 +@@ -483,6 +524,7 @@ + #define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK) + #define SYSCFG0_SGMII_GMAC1_V2 BIT(9) + #define SYSCFG0_SGMII_GMAC2_V2 BIT(8) ++#define SYSCFG0_SGMII_GMAC3_V2 BIT(7) + + + /* ethernet subsystem clock register */ +@@ -509,16 +551,91 @@ + #define ETHSYS_DMA_AG_MAP_QDMA BIT(1) + #define ETHSYS_DMA_AG_MAP_PPE BIT(2) + ++/* USXGMII subsystem config registers */ ++/* Register to control speed */ ++#define RG_PHY_TOP_SPEED_CTRL1 0x80C ++#define USXGMII_RATE_UPDATE_MODE BIT(31) ++#define USXGMII_MAC_CK_GATED BIT(29) ++#define USXGMII_IF_FORCE_EN BIT(28) ++#define USXGMII_RATE_ADAPT_MODE GENMASK(10, 8) ++#define USXGMII_RATE_ADAPT_MODE_X1 0 ++#define USXGMII_RATE_ADAPT_MODE_X2 1 ++#define USXGMII_RATE_ADAPT_MODE_X4 2 ++#define USXGMII_RATE_ADAPT_MODE_X10 3 ++#define USXGMII_RATE_ADAPT_MODE_X100 4 ++#define USXGMII_RATE_ADAPT_MODE_X5 5 ++#define USXGMII_RATE_ADAPT_MODE_X50 6 ++#define USXGMII_XFI_RX_MODE GENMASK(6, 4) ++#define USXGMII_XFI_RX_MODE_10G 0 ++#define USXGMII_XFI_RX_MODE_5G 1 ++#define USXGMII_XFI_TX_MODE GENMASK(2, 0) ++#define USXGMII_XFI_TX_MODE_10G 0 ++#define USXGMII_XFI_TX_MODE_5G 1 ++ ++/* Register to control PCS AN */ ++#define RG_PCS_AN_CTRL0 0x810 ++#define USXGMII_AN_RESTART BIT(31) ++#define USXGMII_AN_SYNC_CNT GENMASK(30, 11) ++#define USXGMII_AN_ENABLE BIT(0) ++ ++#define RG_PCS_AN_CTRL2 0x818 ++#define USXGMII_LINK_TIMER_IDLE_DETECT GENMASK(29, 20) ++#define USXGMII_LINK_TIMER_COMP_ACK_DETECT GENMASK(19, 10) ++#define USXGMII_LINK_TIMER_AN_RESTART GENMASK(9, 0) ++ ++/* Register to read PCS AN status */ ++#define RG_PCS_AN_STS0 0x81c ++#define USXGMII_LPA_SPEED_MASK GENMASK(11, 9) ++#define USXGMII_LPA_SPEED_10 0 ++#define USXGMII_LPA_SPEED_100 1 ++#define USXGMII_LPA_SPEED_1000 2 ++#define USXGMII_LPA_SPEED_10000 3 ++#define USXGMII_LPA_SPEED_2500 4 ++#define USXGMII_LPA_SPEED_5000 5 ++#define USXGMII_LPA_DUPLEX BIT(12) ++#define USXGMII_LPA_LINK BIT(15) ++#define USXGMII_LPA_LATCH BIT(31) ++ ++/* Register to control USXGMII XFI PLL digital */ ++#define XFI_PLL_DIG_GLB8 0x08 ++#define RG_XFI_PLL_EN BIT(31) ++ ++/* Register to control USXGMII XFI PLL analog */ ++#define XFI_PLL_ANA_GLB8 0x108 ++#define RG_XFI_PLL_ANA_SWWA 0x02283248 ++ + /* Infrasys subsystem config registers */ + #define INFRA_MISC2 0x70c + #define CO_QPHY_SEL BIT(0) + #define GEPHY_MAC_SEL BIT(1) + ++/* Toprgu subsystem config registers */ ++#define TOPRGU_SWSYSRST 0x18 ++#define SWSYSRST_UNLOCK_KEY GENMASK(31, 24) ++#define SWSYSRST_XFI_PLL_GRST BIT(16) ++#define SWSYSRST_XFI_PEXPT1_GRST BIT(15) ++#define SWSYSRST_XFI_PEXPT0_GRST BIT(14) ++#define SWSYSRST_XFI1_GRST BIT(13) ++#define SWSYSRST_XFI0_GRST BIT(12) ++#define SWSYSRST_SGMII1_GRST BIT(2) ++#define SWSYSRST_SGMII0_GRST BIT(1) ++#define TOPRGU_SWSYSRST_EN 0xFC ++ + /* Top misc registers */ ++#define TOP_MISC_NETSYS_PCS_MUX 0x84 ++#define NETSYS_PCS_MUX_MASK GENMASK(1, 0) ++#define MUX_G2_USXGMII_SEL BIT(1) ++#define MUX_HSGMII1_G1_SEL BIT(0) ++ + #define USB_PHY_SWITCH_REG 0x218 + #define QPHY_SEL_MASK GENMASK(1, 0) + #define SGMII_QPHY_SEL 0x2 + ++/* MDIO control */ ++#define MII_MMD_ACC_CTL_REG 0x0d ++#define MII_MMD_ADDR_DATA_REG 0x0e ++#define MMD_OP_MODE_DATA BIT(14) ++ + /* MT7628/88 specific stuff */ + #define MT7628_PDMA_OFFSET 0x0800 + #define MT7628_SDM_OFFSET 0x0c00 +@@ -812,13 +929,6 @@ enum mtk_gmac_id { + MTK_GMAC_ID_MAX + }; + +-/* GDM Type */ +-enum mtk_gdm_type { +- MTK_GDM_TYPE = 0, +- MTK_XGDM_TYPE, +- MTK_GDM_TYPE_MAX +-}; +- + enum mtk_tx_buf_type { + MTK_TYPE_SKB, + MTK_TYPE_XDP_TX, +@@ -905,6 +1015,7 @@ enum mkt_eth_capabilities { + MTK_TRGMII_BIT, + MTK_SGMII_BIT, + MTK_USXGMII_BIT, ++ MTK_2P5GPHY_BIT, + MTK_ESW_BIT, + MTK_GEPHY_BIT, + MTK_MUX_BIT, +@@ -925,6 +1036,7 @@ enum mkt_eth_capabilities { + MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT, + MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT, + MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT, ++ MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT, + MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT, + MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT, + MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT, +@@ -936,6 +1048,7 @@ enum mkt_eth_capabilities { + MTK_ETH_PATH_GMAC1_SGMII_BIT, + MTK_ETH_PATH_GMAC2_RGMII_BIT, + MTK_ETH_PATH_GMAC2_SGMII_BIT, ++ MTK_ETH_PATH_GMAC2_2P5GPHY_BIT, + MTK_ETH_PATH_GMAC2_GEPHY_BIT, + MTK_ETH_PATH_GMAC3_SGMII_BIT, + MTK_ETH_PATH_GDM1_ESW_BIT, +@@ -949,6 +1062,7 @@ enum mkt_eth_capabilities { + #define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT) + #define MTK_SGMII BIT_ULL(MTK_SGMII_BIT) + #define MTK_USXGMII BIT_ULL(MTK_USXGMII_BIT) ++#define MTK_2P5GPHY BIT_ULL(MTK_2P5GPHY_BIT) + #define MTK_ESW BIT_ULL(MTK_ESW_BIT) + #define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT) + #define MTK_MUX BIT_ULL(MTK_MUX_BIT) +@@ -971,6 +1085,8 @@ enum mkt_eth_capabilities { + BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) + #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ + BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) ++#define MTK_ETH_MUX_GMAC2_TO_2P5GPHY \ ++ BIT_ULL(MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT) + #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ + BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) + #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ +@@ -986,6 +1102,7 @@ enum mkt_eth_capabilities { + #define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT) + #define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT) + #define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT) ++#define MTK_ETH_PATH_GMAC2_2P5GPHY BIT_ULL(MTK_ETH_PATH_GMAC2_2P5GPHY_BIT) + #define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT) + #define MTK_ETH_PATH_GMAC3_SGMII BIT_ULL(MTK_ETH_PATH_GMAC3_SGMII_BIT) + #define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT) +@@ -999,6 +1116,7 @@ enum mkt_eth_capabilities { + #define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII) + #define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII) + #define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY) ++#define MTK_GMAC2_2P5GPHY (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY) + #define MTK_GMAC3_SGMII (MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII) + #define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW) + #define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII) +@@ -1022,6 +1140,10 @@ enum mkt_eth_capabilities { + (MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \ + MTK_SHARED_SGMII) + ++/* 2: GMAC2 -> XGMII */ ++#define MTK_MUX_GMAC2_TO_2P5GPHY \ ++ (MTK_ETH_MUX_GMAC2_TO_2P5GPHY | MTK_MUX | MTK_INFRA) ++ + /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */ + #define MTK_MUX_GMAC12_TO_GEPHY_SGMII \ + (MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX) +@@ -1080,7 +1202,8 @@ enum mkt_eth_capabilities { + MTK_MUX_GMAC123_TO_GEPHY_SGMII | \ + MTK_NETSYS_V3 | MTK_RSTCTRL_PPE1 | \ + MTK_GMAC1_USXGMII | MTK_GMAC2_USXGMII | \ +- MTK_GMAC3_USXGMII | MTK_MUX_GMAC123_TO_USXGMII) ++ MTK_GMAC3_USXGMII | MTK_MUX_GMAC123_TO_USXGMII | \ ++ MTK_GMAC2_2P5GPHY | MTK_MUX_GMAC2_TO_2P5GPHY) + + struct mtk_tx_dma_desc_info { + dma_addr_t addr; +@@ -1186,6 +1309,22 @@ struct mtk_soc_data { + + #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000) + ++/* struct mtk_usxgmii_pcs - This structure holds each usxgmii regmap and ++ * associated data ++ * @regmap: The register map pointing at the range used to setup ++ * USXGMII modes ++ * @interface: Currently selected interface mode ++ * @id: The element is used to record the index of PCS ++ * @pcs: Phylink PCS structure ++ */ ++struct mtk_usxgmii_pcs { ++ struct mtk_eth *eth; ++ struct regmap *regmap; ++ phy_interface_t interface; ++ u8 id; ++ struct phylink_pcs pcs; ++}; ++ + /* struct mtk_eth - This is the main datasructure for holding the state + * of the driver + * @dev: The device pointer +@@ -1206,6 +1345,11 @@ struct mtk_soc_data { + * @infra: The register map pointing at the range used to setup + * SGMII and GePHY path + * @sgmii_pcs: Pointers to mtk-pcs-lynxi phylink_pcs instances ++ * @usxgmii_pll: The register map pointing at the range used to control ++ * the USXGMII SerDes PLL ++ * @regmap_pextp: The register map pointing at the range used to setup ++ * PHYA ++ * @usxgmii_pcs: Pointer to array of pointers to struct for USXGMII PCS + * @pctl: The register map pointing at the range used to setup + * GMAC port drive/slew values + * @dma_refcnt: track how many netdevs are using the DMA engine +@@ -1247,7 +1391,11 @@ struct mtk_eth { + unsigned long sysclk; + struct regmap *ethsys; + struct regmap *infra; ++ struct regmap *toprgu; + struct phylink_pcs **sgmii_pcs; ++ struct regmap *usxgmii_pll; ++ struct regmap **regmap_pextp; ++ struct mtk_usxgmii_pcs **usxgmii_pcs; + struct regmap *pctl; + bool hwlro; + refcount_t dma_refcnt; +@@ -1403,6 +1551,19 @@ static inline u32 mtk_get_ib2_multicast_ + return MTK_FOE_IB2_MULTICAST; + } + ++static inline bool mtk_interface_mode_is_xgmii(phy_interface_t interface) ++{ ++ switch (interface) { ++ case PHY_INTERFACE_MODE_USXGMII: ++ case PHY_INTERFACE_MODE_10GKR: ++ case PHY_INTERFACE_MODE_5GBASER: ++ return true; ++ break; ++ default: ++ return false; ++ } ++} ++ + /* read the hardware status register */ + void mtk_stats_update_mac(struct mtk_mac *mac); + +@@ -1410,8 +1571,10 @@ void mtk_w32(struct mtk_eth *eth, u32 va + u32 mtk_r32(struct mtk_eth *eth, unsigned reg); + + int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); ++int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id); + int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); + int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); ++int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id); + + int mtk_eth_offload_init(struct mtk_eth *eth); + int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, +@@ -1421,5 +1584,20 @@ int mtk_flow_offload_cmd(struct mtk_eth + void mtk_flow_offload_cleanup(struct mtk_eth *eth, struct list_head *list); + void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev); + ++#ifdef CONFIG_NET_MEDIATEK_SOC_USXGMII ++struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id); ++int mtk_usxgmii_init(struct mtk_eth *eth); ++int mtk_xfi_pll_enable(struct mtk_eth *eth); ++void mtk_sgmii_setup_phya_gen1(struct mtk_eth *eth, int mac_id); ++void mtk_sgmii_setup_phya_gen2(struct mtk_eth *eth, int mac_id); ++void mtk_sgmii_reset(struct mtk_eth *eth, int mac_id); ++#else ++static inline struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id) { return NULL; } ++static inline int mtk_usxgmii_init(struct mtk_eth *eth) { return 0; } ++static inline int mtk_xfi_pll_enable(struct mtk_eth *eth) { return 0; } ++static inline void mtk_sgmii_setup_phya_gen1(struct mtk_eth *eth, int mac_id) { } ++static inline void mtk_sgmii_setup_phya_gen2(struct mtk_eth *eth, int mac_id) { } ++static inline void mtk_sgmii_reset(struct mtk_eth *eth, int mac_id) { } ++#endif /* NET_MEDIATEK_SOC_USXGMII */ + + #endif /* MTK_ETH_H */ +--- /dev/null ++++ b/drivers/net/ethernet/mediatek/mtk_usxgmii.c +@@ -0,0 +1,835 @@ ++/* SPDX-License-Identifier: GPL-2.0 ++ * ++ * Copyright (c) 2022 MediaTek Inc. ++ * Author: Henry Yen ++ * Daniel Golle ++ */ ++ ++#include ++#include ++#include ++#include "mtk_eth_soc.h" ++ ++static struct mtk_usxgmii_pcs *pcs_to_mtk_usxgmii_pcs(struct phylink_pcs *pcs) ++{ ++ return container_of(pcs, struct mtk_usxgmii_pcs, pcs); ++} ++ ++static int mtk_xfi_pextp_init(struct mtk_eth *eth) ++{ ++ struct device *dev = eth->dev; ++ struct device_node *r = dev->of_node; ++ struct device_node *np; ++ int i; ++ ++ eth->regmap_pextp = devm_kcalloc(dev, eth->soc->num_devs, sizeof(eth->regmap_pextp), GFP_KERNEL); ++ if (!eth->regmap_pextp) ++ return -ENOMEM; ++ ++ for (i = 0; i < eth->soc->num_devs; i++) { ++ np = of_parse_phandle(r, "mediatek,xfi_pextp", i); ++ if (!np) ++ break; ++ ++ eth->regmap_pextp[i] = syscon_node_to_regmap(np); ++ if (IS_ERR(eth->regmap_pextp[i])) ++ return PTR_ERR(eth->regmap_pextp[i]); ++ } ++ ++ return 0; ++} ++ ++static int mtk_xfi_pll_init(struct mtk_eth *eth) ++{ ++ struct device_node *r = eth->dev->of_node; ++ struct device_node *np; ++ ++ np = of_parse_phandle(r, "mediatek,xfi_pll", 0); ++ if (!np) ++ return -1; ++ ++ eth->usxgmii_pll = syscon_node_to_regmap(np); ++ if (IS_ERR(eth->usxgmii_pll)) ++ return PTR_ERR(eth->usxgmii_pll); ++ ++ return 0; ++} ++ ++static int mtk_toprgu_init(struct mtk_eth *eth) ++{ ++ struct device_node *r = eth->dev->of_node; ++ struct device_node *np; ++ ++ np = of_parse_phandle(r, "mediatek,toprgu", 0); ++ if (!np) ++ return -1; ++ ++ eth->toprgu = syscon_node_to_regmap(np); ++ if (IS_ERR(eth->toprgu)) ++ return PTR_ERR(eth->toprgu); ++ ++ return 0; ++} ++ ++int mtk_xfi_pll_enable(struct mtk_eth *eth) ++{ ++ u32 val = 0; ++ ++ if (!eth->usxgmii_pll) ++ return -EINVAL; ++ ++ /* Add software workaround for USXGMII PLL TCL issue */ ++ regmap_write(eth->usxgmii_pll, XFI_PLL_ANA_GLB8, RG_XFI_PLL_ANA_SWWA); ++ ++ regmap_read(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, &val); ++ val |= RG_XFI_PLL_EN; ++ regmap_write(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, val); ++ ++ return 0; ++} ++ ++static int mtk_mac2xgmii_id(struct mtk_eth *eth, int mac_id) ++{ ++ int xgmii_id = mac_id; ++ ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { ++ switch (mac_id) { ++ case MTK_GMAC1_ID: ++ case MTK_GMAC2_ID: ++ xgmii_id = 1; ++ break; ++ case MTK_GMAC3_ID: ++ xgmii_id = 0; ++ break; ++ default: ++ xgmii_id = -1; ++ } ++ } ++ ++ return xgmii_id; ++} ++ ++static int mtk_xgmii2mac_id(struct mtk_eth *eth, int xgmii_id) ++{ ++ int mac_id = xgmii_id; ++ ++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { ++ switch (xgmii_id) { ++ case 0: ++ mac_id = 2; ++ break; ++ case 1: ++ mac_id = 1; ++ break; ++ default: ++ mac_id = -1; ++ } ++ } ++ ++ return mac_id; ++} ++ ++ ++static void mtk_usxgmii_setup_phya_usxgmii(struct mtk_usxgmii_pcs *mpcs) ++{ ++ struct regmap *pextp; ++ ++ if (!mpcs->eth) ++ return; ++ ++ pextp = mpcs->eth->regmap_pextp[mpcs->id]; ++ if (!pextp) ++ return; ++ ++ /* Setup operation mode */ ++ regmap_write(pextp, 0x9024, 0x00C9071C); ++ regmap_write(pextp, 0x2020, 0xAA8585AA); ++ regmap_write(pextp, 0x2030, 0x0C020707); ++ regmap_write(pextp, 0x2034, 0x0E050F0F); ++ regmap_write(pextp, 0x2040, 0x00140032); ++ regmap_write(pextp, 0x50F0, 0x00C014AA); ++ regmap_write(pextp, 0x50E0, 0x3777C12B); ++ regmap_write(pextp, 0x506C, 0x005F9CFF); ++ regmap_write(pextp, 0x5070, 0x9D9DFAFA); ++ regmap_write(pextp, 0x5074, 0x27273F3F); ++ regmap_write(pextp, 0x5078, 0xA7883C68); ++ regmap_write(pextp, 0x507C, 0x11661166); ++ regmap_write(pextp, 0x5080, 0x0E000AAF); ++ regmap_write(pextp, 0x5084, 0x08080D0D); ++ regmap_write(pextp, 0x5088, 0x02030909); ++ regmap_write(pextp, 0x50E4, 0x0C0C0000); ++ regmap_write(pextp, 0x50E8, 0x04040000); ++ regmap_write(pextp, 0x50EC, 0x0F0F0C06); ++ regmap_write(pextp, 0x50A8, 0x506E8C8C); ++ regmap_write(pextp, 0x6004, 0x18190000); ++ regmap_write(pextp, 0x00F8, 0x01423342); ++ /* Force SGDT_OUT off and select PCS */ ++ regmap_write(pextp, 0x00F4, 0x80201F20); ++ /* Force GLB_CKDET_OUT */ ++ regmap_write(pextp, 0x0030, 0x00050C00); ++ /* Force AEQ on */ ++ regmap_write(pextp, 0x0070, 0x02002800); ++ ndelay(1020); ++ /* Setup DA default value */ ++ regmap_write(pextp, 0x30B0, 0x00000020); ++ regmap_write(pextp, 0x3028, 0x00008A01); ++ regmap_write(pextp, 0x302C, 0x0000A884); ++ regmap_write(pextp, 0x3024, 0x00083002); ++ regmap_write(pextp, 0x3010, 0x00022220); ++ regmap_write(pextp, 0x5064, 0x0F020A01); ++ regmap_write(pextp, 0x50B4, 0x06100600); ++ regmap_write(pextp, 0x3048, 0x40704000); ++ regmap_write(pextp, 0x3050, 0xA8000000); ++ regmap_write(pextp, 0x3054, 0x000000AA); ++ regmap_write(pextp, 0x306C, 0x00000F00); ++ regmap_write(pextp, 0xA060, 0x00040000); ++ regmap_write(pextp, 0x90D0, 0x00000001); ++ /* Release reset */ ++ regmap_write(pextp, 0x0070, 0x0200E800); ++ udelay(150); ++ /* Switch to P0 */ ++ regmap_write(pextp, 0x0070, 0x0200C111); ++ ndelay(1020); ++ regmap_write(pextp, 0x0070, 0x0200C101); ++ udelay(15); ++ /* Switch to Gen3 */ ++ regmap_write(pextp, 0x0070, 0x0202C111); ++ ndelay(1020); ++ regmap_write(pextp, 0x0070, 0x0202C101); ++ udelay(100); ++ regmap_write(pextp, 0x30B0, 0x00000030); ++ regmap_write(pextp, 0x00F4, 0x80201F00); ++ regmap_write(pextp, 0x3040, 0x30000000); ++ udelay(400); ++} ++ ++static void mtk_usxgmii_setup_phya_5gbaser(struct mtk_usxgmii_pcs *mpcs) ++{ ++ struct regmap *pextp; ++ ++ if (!mpcs->eth) ++ return; ++ ++ pextp = mpcs->eth->regmap_pextp[mpcs->id]; ++ if (!pextp) ++ return; ++ ++ /* Setup operation mode */ ++ regmap_write(pextp, 0x9024, 0x00D9071C); ++ regmap_write(pextp, 0x2020, 0xAAA5A5AA); ++ regmap_write(pextp, 0x2030, 0x0C020707); ++ regmap_write(pextp, 0x2034, 0x0E050F0F); ++ regmap_write(pextp, 0x2040, 0x00140032); ++ regmap_write(pextp, 0x50F0, 0x00C018AA); ++ regmap_write(pextp, 0x50E0, 0x3777812B); ++ regmap_write(pextp, 0x506C, 0x005C9CFF); ++ regmap_write(pextp, 0x5070, 0x9DFAFAFA); ++ regmap_write(pextp, 0x5074, 0x273F3F3F); ++ regmap_write(pextp, 0x5078, 0xA8883868); ++ regmap_write(pextp, 0x507C, 0x14661466); ++ regmap_write(pextp, 0x5080, 0x0E001ABF); ++ regmap_write(pextp, 0x5084, 0x080B0D0D); ++ regmap_write(pextp, 0x5088, 0x02050909); ++ regmap_write(pextp, 0x50E4, 0x0C000000); ++ regmap_write(pextp, 0x50E8, 0x04000000); ++ regmap_write(pextp, 0x50EC, 0x0F0F0C06); ++ regmap_write(pextp, 0x50A8, 0x50808C8C); ++ regmap_write(pextp, 0x6004, 0x18000000); ++ regmap_write(pextp, 0x00F8, 0x00A132A1); ++ /* Force SGDT_OUT off and select PCS */ ++ regmap_write(pextp, 0x00F4, 0x80201F20); ++ /* Force GLB_CKDET_OUT */ ++ regmap_write(pextp, 0x0030, 0x00050C00); ++ /* Force AEQ on */ ++ regmap_write(pextp, 0x0070, 0x02002800); ++ ndelay(1020); ++ /* Setup DA default value */ ++ regmap_write(pextp, 0x30B0, 0x00000020); ++ regmap_write(pextp, 0x3028, 0x00008A01); ++ regmap_write(pextp, 0x302C, 0x0000A884); ++ regmap_write(pextp, 0x3024, 0x00083002); ++ regmap_write(pextp, 0x3010, 0x00022220); ++ regmap_write(pextp, 0x5064, 0x0F020A01); ++ regmap_write(pextp, 0x50B4, 0x06100600); ++ regmap_write(pextp, 0x3048, 0x40704000); ++ regmap_write(pextp, 0x3050, 0xA8000000); ++ regmap_write(pextp, 0x3054, 0x000000AA); ++ regmap_write(pextp, 0x306C, 0x00000F00); ++ regmap_write(pextp, 0xA060, 0x00040000); ++ regmap_write(pextp, 0x90D0, 0x00000003); ++ /* Release reset */ ++ regmap_write(pextp, 0x0070, 0x0200E800); ++ udelay(150); ++ /* Switch to P0 */ ++ regmap_write(pextp, 0x0070, 0x0200C111); ++ ndelay(1020); ++ regmap_write(pextp, 0x0070, 0x0200C101); ++ udelay(15); ++ /* Switch to Gen3 */ ++ regmap_write(pextp, 0x0070, 0x0202C111); ++ ndelay(1020); ++ regmap_write(pextp, 0x0070, 0x0202C101); ++ udelay(100); ++ regmap_write(pextp, 0x30B0, 0x00000030); ++ regmap_write(pextp, 0x00F4, 0x80201F00); ++ regmap_write(pextp, 0x3040, 0x30000000); ++ udelay(400); ++} ++ ++static void mtk_usxgmii_setup_phya_10gbaser(struct mtk_usxgmii_pcs *mpcs) ++{ ++ struct regmap *pextp; ++ ++ if (!mpcs->eth) ++ return; ++ ++ pextp = mpcs->eth->regmap_pextp[mpcs->id]; ++ if (!pextp) ++ return; ++ ++ /* Setup operation mode */ ++ regmap_write(pextp, 0x9024, 0x00C9071C); ++ regmap_write(pextp, 0x2020, 0xAA8585AA); ++ regmap_write(pextp, 0x2030, 0x0C020707); ++ regmap_write(pextp, 0x2034, 0x0E050F0F); ++ regmap_write(pextp, 0x2040, 0x00140032); ++ regmap_write(pextp, 0x50F0, 0x00C014AA); ++ regmap_write(pextp, 0x50E0, 0x3777C12B); ++ regmap_write(pextp, 0x506C, 0x005F9CFF); ++ regmap_write(pextp, 0x5070, 0x9D9DFAFA); ++ regmap_write(pextp, 0x5074, 0x27273F3F); ++ regmap_write(pextp, 0x5078, 0xA7883C68); ++ regmap_write(pextp, 0x507C, 0x11661166); ++ regmap_write(pextp, 0x5080, 0x0E000AAF); ++ regmap_write(pextp, 0x5084, 0x08080D0D); ++ regmap_write(pextp, 0x5088, 0x02030909); ++ regmap_write(pextp, 0x50E4, 0x0C0C0000); ++ regmap_write(pextp, 0x50E8, 0x04040000); ++ regmap_write(pextp, 0x50EC, 0x0F0F0C06); ++ regmap_write(pextp, 0x50A8, 0x506E8C8C); ++ regmap_write(pextp, 0x6004, 0x18190000); ++ regmap_write(pextp, 0x00F8, 0x01423342); ++ /* Force SGDT_OUT off and select PCS */ ++ regmap_write(pextp, 0x00F4, 0x80201F20); ++ /* Force GLB_CKDET_OUT */ ++ regmap_write(pextp, 0x0030, 0x00050C00); ++ /* Force AEQ on */ ++ regmap_write(pextp, 0x0070, 0x02002800); ++ ndelay(1020); ++ /* Setup DA default value */ ++ regmap_write(pextp, 0x30B0, 0x00000020); ++ regmap_write(pextp, 0x3028, 0x00008A01); ++ regmap_write(pextp, 0x302C, 0x0000A884); ++ regmap_write(pextp, 0x3024, 0x00083002); ++ regmap_write(pextp, 0x3010, 0x00022220); ++ regmap_write(pextp, 0x5064, 0x0F020A01); ++ regmap_write(pextp, 0x50B4, 0x06100600); ++ regmap_write(pextp, 0x3048, 0x47684100); ++ regmap_write(pextp, 0x3050, 0x00000000); ++ regmap_write(pextp, 0x3054, 0x00000000); ++ regmap_write(pextp, 0x306C, 0x00000F00); ++ if (mpcs->id == 0) ++ regmap_write(pextp, 0xA008, 0x0007B400); ++ ++ regmap_write(pextp, 0xA060, 0x00040000); ++ regmap_write(pextp, 0x90D0, 0x00000001); ++ /* Release reset */ ++ regmap_write(pextp, 0x0070, 0x0200E800); ++ udelay(150); ++ /* Switch to P0 */ ++ regmap_write(pextp, 0x0070, 0x0200C111); ++ ndelay(1020); ++ regmap_write(pextp, 0x0070, 0x0200C101); ++ udelay(15); ++ /* Switch to Gen3 */ ++ regmap_write(pextp, 0x0070, 0x0202C111); ++ ndelay(1020); ++ regmap_write(pextp, 0x0070, 0x0202C101); ++ udelay(100); ++ regmap_write(pextp, 0x30B0, 0x00000030); ++ regmap_write(pextp, 0x00F4, 0x80201F00); ++ regmap_write(pextp, 0x3040, 0x30000000); ++ udelay(400); ++} ++ ++void mtk_sgmii_setup_phya_gen1(struct mtk_eth *eth, int mac_id) ++{ ++ u32 id = mtk_mac2xgmii_id(eth, mac_id); ++ struct regmap *pextp; ++ ++ if (id >= eth->soc->num_devs) ++ return; ++ ++ pextp = eth->regmap_pextp[id]; ++ if (!pextp) ++ return; ++ ++ /* Setup operation mode */ ++ regmap_write(pextp, 0x9024, 0x00D9071C); ++ regmap_write(pextp, 0x2020, 0xAA8585AA); ++ regmap_write(pextp, 0x2030, 0x0C020207); ++ regmap_write(pextp, 0x2034, 0x0E05050F); ++ regmap_write(pextp, 0x2040, 0x00200032); ++ regmap_write(pextp, 0x50F0, 0x00C014BA); ++ regmap_write(pextp, 0x50E0, 0x3777C12B); ++ regmap_write(pextp, 0x506C, 0x005F9CFF); ++ regmap_write(pextp, 0x5070, 0x9D9DFAFA); ++ regmap_write(pextp, 0x5074, 0x27273F3F); ++ regmap_write(pextp, 0x5078, 0xA7883C68); ++ regmap_write(pextp, 0x507C, 0x11661166); ++ regmap_write(pextp, 0x5080, 0x0E000EAF); ++ regmap_write(pextp, 0x5084, 0x08080E0D); ++ regmap_write(pextp, 0x5088, 0x02030B09); ++ regmap_write(pextp, 0x50E4, 0x0C0C0000); ++ regmap_write(pextp, 0x50E8, 0x04040000); ++ regmap_write(pextp, 0x50EC, 0x0F0F0606); ++ regmap_write(pextp, 0x50A8, 0x506E8C8C); ++ regmap_write(pextp, 0x6004, 0x18190000); ++ regmap_write(pextp, 0x00F8, 0x00FA32FA); ++ /* Force SGDT_OUT off and select PCS */ ++ regmap_write(pextp, 0x00F4, 0x80201F21); ++ /* Force GLB_CKDET_OUT */ ++ regmap_write(pextp, 0x0030, 0x00050C00); ++ /* Force AEQ on */ ++ regmap_write(pextp, 0x0070, 0x02002800); ++ ndelay(1020); ++ /* Setup DA default value */ ++ regmap_write(pextp, 0x30B0, 0x00000020); ++ regmap_write(pextp, 0x3028, 0x00008A01); ++ regmap_write(pextp, 0x302C, 0x0000A884); ++ regmap_write(pextp, 0x3024, 0x00083002); ++ regmap_write(pextp, 0x3010, 0x00011110); ++ regmap_write(pextp, 0x3048, 0x40704000); ++ regmap_write(pextp, 0x3064, 0x0000C000); ++ regmap_write(pextp, 0x3050, 0xA8000000); ++ regmap_write(pextp, 0x3054, 0x000000AA); ++ regmap_write(pextp, 0x306C, 0x20200F00); ++ regmap_write(pextp, 0xA060, 0x00050000); ++ regmap_write(pextp, 0x90D0, 0x00000007); ++ /* Release reset */ ++ regmap_write(pextp, 0x0070, 0x0200E800); ++ udelay(150); ++ /* Switch to P0 */ ++ regmap_write(pextp, 0x0070, 0x0200C111); ++ ndelay(1020); ++ regmap_write(pextp, 0x0070, 0x0200C101); ++ udelay(15); ++ /* Switch to Gen2 */ ++ regmap_write(pextp, 0x0070, 0x0201C111); ++ ndelay(1020); ++ regmap_write(pextp, 0x0070, 0x0201C101); ++ udelay(100); ++ regmap_write(pextp, 0x30B0, 0x00000030); ++ regmap_write(pextp, 0x00F4, 0x80201F01); ++ regmap_write(pextp, 0x3040, 0x30000000); ++ udelay(400); ++} ++ ++void mtk_sgmii_setup_phya_gen2(struct mtk_eth *eth, int mac_id) ++{ ++ u32 id = mtk_mac2xgmii_id(eth, mac_id); ++ struct regmap *pextp; ++ ++ if (id >= eth->soc->num_devs) ++ return; ++ ++ pextp = eth->regmap_pextp[id]; ++ if (!pextp) ++ return; ++ ++ /* Setup operation mode */ ++ regmap_write(pextp, 0x9024, 0x00D9071C); ++ regmap_write(pextp, 0x2020, 0xAA8585AA); ++ regmap_write(pextp, 0x2030, 0x0C020707); ++ regmap_write(pextp, 0x2034, 0x0E050F0F); ++ regmap_write(pextp, 0x2040, 0x00140032); ++ regmap_write(pextp, 0x50F0, 0x00C014AA); ++ regmap_write(pextp, 0x50E0, 0x3777C12B); ++ regmap_write(pextp, 0x506C, 0x005F9CFF); ++ regmap_write(pextp, 0x5070, 0x9D9DFAFA); ++ regmap_write(pextp, 0x5074, 0x27273F3F); ++ regmap_write(pextp, 0x5078, 0xA7883C68); ++ regmap_write(pextp, 0x507C, 0x11661166); ++ regmap_write(pextp, 0x5080, 0x0E000AAF); ++ regmap_write(pextp, 0x5084, 0x08080D0D); ++ regmap_write(pextp, 0x5088, 0x02030909); ++ regmap_write(pextp, 0x50E4, 0x0C0C0000); ++ regmap_write(pextp, 0x50E8, 0x04040000); ++ regmap_write(pextp, 0x50EC, 0x0F0F0C06); ++ regmap_write(pextp, 0x50A8, 0x506E8C8C); ++ regmap_write(pextp, 0x6004, 0x18190000); ++ regmap_write(pextp, 0x00F8, 0x009C329C); ++ /* Force SGDT_OUT off and select PCS */ ++ regmap_write(pextp, 0x00F4, 0x80201F21); ++ /* Force GLB_CKDET_OUT */ ++ regmap_write(pextp, 0x0030, 0x00050C00); ++ /* Force AEQ on */ ++ regmap_write(pextp, 0x0070, 0x02002800); ++ ndelay(1020); ++ /* Setup DA default value */ ++ regmap_write(pextp, 0x30B0, 0x00000020); ++ regmap_write(pextp, 0x3028, 0x00008A01); ++ regmap_write(pextp, 0x302C, 0x0000A884); ++ regmap_write(pextp, 0x3024, 0x00083002); ++ regmap_write(pextp, 0x3010, 0x00011110); ++ regmap_write(pextp, 0x3048, 0x40704000); ++ regmap_write(pextp, 0x3050, 0xA8000000); ++ regmap_write(pextp, 0x3054, 0x000000AA); ++ regmap_write(pextp, 0x306C, 0x22000F00); ++ regmap_write(pextp, 0xA060, 0x00050000); ++ regmap_write(pextp, 0x90D0, 0x00000005); ++ /* Release reset */ ++ regmap_write(pextp, 0x0070, 0x0200E800); ++ udelay(150); ++ /* Switch to P0 */ ++ regmap_write(pextp, 0x0070, 0x0200C111); ++ ndelay(1020); ++ regmap_write(pextp, 0x0070, 0x0200C101); ++ udelay(15); ++ /* Switch to Gen2 */ ++ regmap_write(pextp, 0x0070, 0x0201C111); ++ ndelay(1020); ++ regmap_write(pextp, 0x0070, 0x0201C101); ++ udelay(100); ++ regmap_write(pextp, 0x30B0, 0x00000030); ++ regmap_write(pextp, 0x00F4, 0x80201F01); ++ regmap_write(pextp, 0x3040, 0x30000000); ++ udelay(400); ++} ++ ++static void mtk_usxgmii_reset(struct mtk_eth *eth, int id) ++{ ++ u32 val = 0; ++ ++ if (id >= eth->soc->num_devs || !eth->toprgu) ++ return; ++ ++ switch (id) { ++ case 0: ++ /* Enable software reset */ ++ regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val); ++ val |= SWSYSRST_XFI_PEXPT0_GRST | ++ SWSYSRST_XFI0_GRST; ++ regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val); ++ ++ /* Assert USXGMII reset */ ++ regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val); ++ val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) | ++ SWSYSRST_XFI_PEXPT0_GRST | ++ SWSYSRST_XFI0_GRST; ++ regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val); ++ ++ udelay(100); ++ ++ /* De-assert USXGMII reset */ ++ regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val); ++ val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88); ++ val &= ~(SWSYSRST_XFI_PEXPT0_GRST | ++ SWSYSRST_XFI0_GRST); ++ regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val); ++ ++ /* Disable software reset */ ++ regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val); ++ val &= ~(SWSYSRST_XFI_PEXPT0_GRST | ++ SWSYSRST_XFI0_GRST); ++ regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val); ++ break; ++ case 1: ++ /* Enable software reset */ ++ regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val); ++ val |= SWSYSRST_XFI_PEXPT1_GRST | ++ SWSYSRST_XFI1_GRST; ++ regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val); ++ ++ /* Assert USXGMII reset */ ++ regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val); ++ val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) | ++ SWSYSRST_XFI_PEXPT1_GRST | ++ SWSYSRST_XFI1_GRST; ++ regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val); ++ ++ udelay(100); ++ ++ /* De-assert USXGMII reset */ ++ regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val); ++ val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88); ++ val &= ~(SWSYSRST_XFI_PEXPT1_GRST | ++ SWSYSRST_XFI1_GRST); ++ regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val); ++ ++ /* Disable software reset */ ++ regmap_read(eth->toprgu, TOPRGU_SWSYSRST_EN, &val); ++ val &= ~(SWSYSRST_XFI_PEXPT1_GRST | ++ SWSYSRST_XFI1_GRST); ++ regmap_write(eth->toprgu, TOPRGU_SWSYSRST_EN, val); ++ break; ++ } ++ ++ mdelay(10); ++} ++ ++void mtk_sgmii_reset(struct mtk_eth *eth, int mac_id) ++{ ++ u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id); ++ ++ mtk_usxgmii_reset(eth, xgmii_id); ++} ++ ++ ++static int mtk_usxgmii_pcs_config(struct phylink_pcs *pcs, unsigned int mode, ++ phy_interface_t interface, ++ const unsigned long *advertising, ++ bool permit_pause_to_mac) ++{ ++ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs); ++ struct mtk_eth *eth = mpcs->eth; ++ unsigned int an_ctrl = 0, link_timer = 0, xfi_mode = 0, adapt_mode = 0; ++ bool mode_changed = false; ++ ++ if (interface == PHY_INTERFACE_MODE_USXGMII) { ++ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF) | ++ USXGMII_AN_ENABLE; ++ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) | ++ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) | ++ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B); ++ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) | ++ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G); ++ } else if (interface == PHY_INTERFACE_MODE_10GKR) { ++ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF); ++ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) | ++ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) | ++ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B); ++ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) | ++ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G); ++ adapt_mode = USXGMII_RATE_UPDATE_MODE; ++ } else if (interface == PHY_INTERFACE_MODE_5GBASER) { ++ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0xFF); ++ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x3D) | ++ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x3D) | ++ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x3D); ++ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_5G) | ++ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_5G); ++ adapt_mode = USXGMII_RATE_UPDATE_MODE; ++ } else ++ return -EINVAL; ++ ++ adapt_mode |= FIELD_PREP(USXGMII_RATE_ADAPT_MODE, USXGMII_RATE_ADAPT_MODE_X1); ++ ++ if (mpcs->interface != interface) { ++ mpcs->interface = interface; ++ mode_changed = true; ++ } ++ ++ mtk_xfi_pll_enable(eth); ++ mtk_usxgmii_reset(eth, mpcs->id); ++ ++ /* Setup USXGMII AN ctrl */ ++ regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL0, ++ USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE, ++ an_ctrl); ++ ++ regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL2, ++ USXGMII_LINK_TIMER_IDLE_DETECT | ++ USXGMII_LINK_TIMER_COMP_ACK_DETECT | ++ USXGMII_LINK_TIMER_AN_RESTART, ++ link_timer); ++ ++ /* Gated MAC CK */ ++ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, ++ USXGMII_MAC_CK_GATED, USXGMII_MAC_CK_GATED); ++ ++ /* Enable interface force mode */ ++ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, ++ USXGMII_IF_FORCE_EN, USXGMII_IF_FORCE_EN); ++ ++ /* Setup USXGMII adapt mode */ ++ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, ++ USXGMII_RATE_UPDATE_MODE | USXGMII_RATE_ADAPT_MODE, ++ adapt_mode); ++ ++ /* Setup USXGMII speed */ ++ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, ++ USXGMII_XFI_RX_MODE | USXGMII_XFI_TX_MODE, ++ xfi_mode); ++ ++ udelay(1); ++ ++ /* Un-gated MAC CK */ ++ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, ++ USXGMII_MAC_CK_GATED, 0); ++ ++ udelay(1); ++ ++ /* Disable interface force mode for the AN mode */ ++ if (an_ctrl & USXGMII_AN_ENABLE) ++ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1, ++ USXGMII_IF_FORCE_EN, 0); ++ ++ /* Setup USXGMIISYS with the determined property */ ++ if (interface == PHY_INTERFACE_MODE_USXGMII) ++ mtk_usxgmii_setup_phya_usxgmii(mpcs); ++ else if (interface == PHY_INTERFACE_MODE_10GKR) ++ mtk_usxgmii_setup_phya_10gbaser(mpcs); ++ else if (interface == PHY_INTERFACE_MODE_5GBASER) ++ mtk_usxgmii_setup_phya_5gbaser(mpcs); ++ ++ return mode_changed; ++} ++ ++static void mtk_usxgmii_pcs_get_state(struct phylink_pcs *pcs, ++ struct phylink_link_state *state) ++{ ++ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs); ++ struct mtk_eth *eth = mpcs->eth; ++ struct mtk_mac *mac = eth->mac[mtk_xgmii2mac_id(eth, mpcs->id)]; ++ u32 val = 0; ++ ++ regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val); ++ if (FIELD_GET(USXGMII_AN_ENABLE, val)) { ++ /* Refresh LPA by inverting LPA_LATCH */ ++ regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val); ++ regmap_update_bits(mpcs->regmap, RG_PCS_AN_STS0, ++ USXGMII_LPA_LATCH, ++ !(val & USXGMII_LPA_LATCH)); ++ ++ regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val); ++ ++ state->interface = mpcs->interface; ++ state->link = FIELD_GET(USXGMII_LPA_LINK, val); ++ state->duplex = FIELD_GET(USXGMII_LPA_DUPLEX, val); ++ ++ switch (FIELD_GET(USXGMII_LPA_SPEED_MASK, val)) { ++ case USXGMII_LPA_SPEED_10: ++ state->speed = SPEED_10; ++ break; ++ case USXGMII_LPA_SPEED_100: ++ state->speed = SPEED_100; ++ break; ++ case USXGMII_LPA_SPEED_1000: ++ state->speed = SPEED_1000; ++ break; ++ case USXGMII_LPA_SPEED_2500: ++ state->speed = SPEED_2500; ++ break; ++ case USXGMII_LPA_SPEED_5000: ++ state->speed = SPEED_5000; ++ break; ++ case USXGMII_LPA_SPEED_10000: ++ state->speed = SPEED_10000; ++ break; ++ } ++ } else { ++ val = mtk_r32(mac->hw, MTK_XGMAC_STS(mac->id)); ++ ++ if (mac->id == MTK_GMAC2_ID) ++ val = val >> 16; ++ ++ switch (FIELD_GET(MTK_USXGMII_PCS_MODE, val)) { ++ case 0: ++ state->speed = SPEED_10000; ++ break; ++ case 1: ++ state->speed = SPEED_5000; ++ break; ++ case 2: ++ state->speed = SPEED_2500; ++ break; ++ case 3: ++ state->speed = SPEED_1000; ++ break; ++ } ++ ++ state->interface = mpcs->interface; ++ state->link = FIELD_GET(MTK_USXGMII_PCS_LINK, val); ++ state->duplex = DUPLEX_FULL; ++ } ++ ++ if (state->link == 0) ++ mtk_usxgmii_pcs_config(pcs, MLO_AN_INBAND, ++ state->interface, NULL, false); ++} ++ ++static void mtk_usxgmii_pcs_restart_an(struct phylink_pcs *pcs) ++{ ++ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs); ++ unsigned int val = 0; ++ ++ if (!mpcs->regmap) ++ return; ++ ++ regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val); ++ val |= USXGMII_AN_RESTART; ++ regmap_write(mpcs->regmap, RG_PCS_AN_CTRL0, val); ++} ++ ++static void mtk_usxgmii_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode, ++ phy_interface_t interface, ++ int speed, int duplex) ++{ ++ /* Reconfiguring USXGMII to ensure the quality of the RX signal ++ * after the line side link up. ++ */ ++ mtk_usxgmii_pcs_config(pcs, mode, ++ interface, NULL, false); ++} ++ ++static const struct phylink_pcs_ops mtk_usxgmii_pcs_ops = { ++ .pcs_config = mtk_usxgmii_pcs_config, ++ .pcs_get_state = mtk_usxgmii_pcs_get_state, ++ .pcs_an_restart = mtk_usxgmii_pcs_restart_an, ++ .pcs_link_up = mtk_usxgmii_pcs_link_up, ++}; ++ ++int mtk_usxgmii_init(struct mtk_eth *eth) ++{ ++ struct device_node *r = eth->dev->of_node; ++ struct device *dev = eth->dev; ++ struct device_node *np; ++ int i, ret; ++ ++ eth->usxgmii_pcs = devm_kcalloc(dev, eth->soc->num_devs, sizeof(eth->usxgmii_pcs), GFP_KERNEL); ++ if (!eth->usxgmii_pcs) ++ return -ENOMEM; ++ ++ for (i = 0; i < eth->soc->num_devs; i++) { ++ np = of_parse_phandle(r, "mediatek,usxgmiisys", i); ++ if (!np) ++ break; ++ ++ eth->usxgmii_pcs[i] = devm_kzalloc(dev, sizeof(*eth->usxgmii_pcs), GFP_KERNEL); ++ if (!eth->usxgmii_pcs[i]) ++ return -ENOMEM; ++ ++ eth->usxgmii_pcs[i]->id = i; ++ eth->usxgmii_pcs[i]->eth = eth; ++ eth->usxgmii_pcs[i]->regmap = syscon_node_to_regmap(np); ++ if (IS_ERR(eth->usxgmii_pcs[i]->regmap)) ++ return PTR_ERR(eth->usxgmii_pcs[i]->regmap); ++ ++ eth->usxgmii_pcs[i]->pcs.ops = &mtk_usxgmii_pcs_ops; ++ eth->usxgmii_pcs[i]->pcs.poll = true; ++ eth->usxgmii_pcs[i]->interface = PHY_INTERFACE_MODE_NA; ++ ++ of_node_put(np); ++ } ++ ++ ret = mtk_xfi_pextp_init(eth); ++ if (ret) ++ return ret; ++ ++ ret = mtk_xfi_pll_init(eth); ++ if (ret) ++ return ret; ++ ++ return mtk_toprgu_init(eth); ++} ++ ++struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int mac_id) ++{ ++ u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id); ++ ++ if (!eth->usxgmii_pcs[xgmii_id]->regmap) ++ return NULL; ++ ++ return ð->usxgmii_pcs[xgmii_id]->pcs; ++} diff --git a/target/linux/generic/pending-6.1/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch b/target/linux/generic/pending-6.1/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch index 201beb8d539839..26f40d9f87ba78 100644 --- a/target/linux/generic/pending-6.1/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch +++ b/target/linux/generic/pending-6.1/795-mt7530-register-OF-node-for-internal-MDIO-bus.patch @@ -16,7 +16,7 @@ Signed-off-by: David Bauer --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c -@@ -2102,10 +2102,13 @@ mt7530_setup_mdio(struct mt7530_priv *pr +@@ -2126,10 +2126,13 @@ mt7530_setup_mdio(struct mt7530_priv *pr { struct dsa_switch *ds = priv->ds; struct device *dev = priv->dev; @@ -30,7 +30,7 @@ Signed-off-by: David Bauer bus = devm_mdiobus_alloc(dev); if (!bus) return -ENOMEM; -@@ -2122,7 +2125,9 @@ mt7530_setup_mdio(struct mt7530_priv *pr +@@ -2146,7 +2149,9 @@ mt7530_setup_mdio(struct mt7530_priv *pr if (priv->irq) mt7530_setup_mdio_irq(priv); diff --git a/target/linux/generic/pending-6.1/901-usb-add-more-modem-support.patch b/target/linux/generic/pending-6.1/901-usb-add-more-modem-support.patch index a2a933cf7a6594..6c8cbd6d6996ef 100644 --- a/target/linux/generic/pending-6.1/901-usb-add-more-modem-support.patch +++ b/target/linux/generic/pending-6.1/901-usb-add-more-modem-support.patch @@ -1,6 +1,6 @@ --- a/drivers/net/usb/qmi_wwan.c +++ b/drivers/net/usb/qmi_wwan.c -@@ -1428,6 +1428,9 @@ static const struct usb_device_id produc +@@ -1429,6 +1429,9 @@ static const struct usb_device_id produc {QMI_FIXED_INTF(0x0489, 0xe0b5, 0)}, /* Foxconn T77W968 LTE with eSIM support*/ {QMI_FIXED_INTF(0x2692, 0x9025, 4)}, /* Cellient MPL200 (rebranded Qualcomm 05c6:9025) */ {QMI_QUIRK_SET_DTR(0x1546, 0x1342, 4)}, /* u-blox LARA-L6 */ @@ -12,7 +12,7 @@ {QMI_GOBI1K_DEVICE(0x05c6, 0x9212)}, /* Acer Gobi Modem Device */ --- a/drivers/usb/serial/option.c +++ b/drivers/usb/serial/option.c -@@ -2262,6 +2262,12 @@ static const struct usb_device_id option +@@ -2266,6 +2266,12 @@ static const struct usb_device_id option { USB_DEVICE_INTERFACE_CLASS(0x2cb7, 0x01a2, 0xff) }, /* Fibocom FM101-GL (laptop MBIM) */ { USB_DEVICE_INTERFACE_CLASS(0x2cb7, 0x01a4, 0xff), /* Fibocom FM101-GL (laptop MBIM) */ .driver_info = RSVD(4) }, diff --git a/target/linux/generic/pending-6.1/920-mangle_bootargs.patch b/target/linux/generic/pending-6.1/920-mangle_bootargs.patch index 1015266084e2a4..db7274e7aadb94 100644 --- a/target/linux/generic/pending-6.1/920-mangle_bootargs.patch +++ b/target/linux/generic/pending-6.1/920-mangle_bootargs.patch @@ -31,7 +31,7 @@ Signed-off-by: Imre Kaloz help --- a/init/main.c +++ b/init/main.c -@@ -607,6 +607,29 @@ static inline void setup_nr_cpu_ids(void +@@ -611,6 +611,29 @@ static inline void setup_nr_cpu_ids(void static inline void smp_prepare_cpus(unsigned int maxcpus) { } #endif @@ -61,7 +61,7 @@ Signed-off-by: Imre Kaloz /* * We need to store the untouched command line for future reference. * We also need to store the touched command line since the parameter -@@ -954,6 +977,7 @@ asmlinkage __visible void __init __no_sa +@@ -958,6 +981,7 @@ asmlinkage __visible void __init __no_sa pr_notice("%s", linux_banner); early_security_init(); setup_arch(&command_line); diff --git a/target/linux/generic/pending-6.1/994-add-quectel-rm500u-support.patch b/target/linux/generic/pending-6.1/994-add-quectel-rm500u-support.patch index f68301d3b42273..8c52719649de4a 100644 --- a/target/linux/generic/pending-6.1/994-add-quectel-rm500u-support.patch +++ b/target/linux/generic/pending-6.1/994-add-quectel-rm500u-support.patch @@ -8,7 +8,7 @@ #define QUECTEL_PRODUCT_EC200U 0x0901 #define QUECTEL_PRODUCT_EC200S_CN 0x6002 #define QUECTEL_PRODUCT_EC200A 0x6005 -@@ -1243,6 +1244,7 @@ static const struct usb_device_id option +@@ -1245,6 +1246,7 @@ static const struct usb_device_id option { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200S_CN, 0xff, 0, 0) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200T, 0xff, 0, 0) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_RM500K, 0xff, 0x00, 0x00) }, diff --git a/target/linux/ipq40xx/patches-5.10/707-net-phy-Add-Qualcom-QCA807x-driver.patch b/target/linux/ipq40xx/patches-5.10/707-net-phy-Add-Qualcom-QCA807x-driver.patch index ba441022f32030..12b21a803ce2ae 100644 --- a/target/linux/ipq40xx/patches-5.10/707-net-phy-Add-Qualcom-QCA807x-driver.patch +++ b/target/linux/ipq40xx/patches-5.10/707-net-phy-Add-Qualcom-QCA807x-driver.patch @@ -40,7 +40,7 @@ Signed-off-by: Robert Marko help --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile -@@ -86,6 +86,7 @@ obj-$(CONFIG_MICROSEMI_PHY) += mscc/ +@@ -88,6 +88,7 @@ obj-$(CONFIG_MICROSEMI_PHY) += mscc/ obj-$(CONFIG_NATIONAL_PHY) += national.o obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o obj-$(CONFIG_QSEMI_PHY) += qsemi.o diff --git a/target/linux/ipq40xx/patches-5.10/999-ipq40xx-unlock-cpu-frequency.patch b/target/linux/ipq40xx/patches-5.10/999-ipq40xx-unlock-cpu-frequency.patch index cc5e195d127f6e..73a00d3a72f87b 100644 --- a/target/linux/ipq40xx/patches-5.10/999-ipq40xx-unlock-cpu-frequency.patch +++ b/target/linux/ipq40xx/patches-5.10/999-ipq40xx-unlock-cpu-frequency.patch @@ -10,7 +10,7 @@ Signed-off-by: William --- --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi -@@ -124,20 +124,24 @@ +@@ -115,20 +115,24 @@ opp-48000000 { opp-hz = /bits/ 64 <48000000>; diff --git a/target/linux/ipq60xx/patches-5.15/0022-v6.0-clk-qcom-ipq8074-add-PPE-crypto-clock.patch b/target/linux/ipq60xx/patches-5.15/0022-v6.0-clk-qcom-ipq8074-add-PPE-crypto-clock.patch index 9cdcf171023c0c..88b250a742211b 100644 --- a/target/linux/ipq60xx/patches-5.15/0022-v6.0-clk-qcom-ipq8074-add-PPE-crypto-clock.patch +++ b/target/linux/ipq60xx/patches-5.15/0022-v6.0-clk-qcom-ipq8074-add-PPE-crypto-clock.patch @@ -17,7 +17,7 @@ Link: https://lore.kernel.org/r/20220515210048.483898-5-robimarko@gmail.com --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -3183,6 +3183,24 @@ static struct clk_branch gcc_nss_ptp_ref +@@ -3177,6 +3177,24 @@ static struct clk_branch gcc_nss_ptp_ref }, }; @@ -42,7 +42,7 @@ Link: https://lore.kernel.org/r/20220515210048.483898-5-robimarko@gmail.com static struct clk_branch gcc_nssnoc_ce_apb_clk = { .halt_reg = 0x6830c, .clkr = { -@@ -4655,6 +4673,7 @@ static struct clk_regmap *gcc_ipq8074_cl +@@ -4649,6 +4667,7 @@ static struct clk_regmap *gcc_ipq8074_cl [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr, [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr, [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, diff --git a/target/linux/ipq60xx/patches-5.15/0024-v6.0-clk-qcom-ipq8074-add-USB-GDSCs.patch b/target/linux/ipq60xx/patches-5.15/0024-v6.0-clk-qcom-ipq8074-add-USB-GDSCs.patch index 7eca353d25f104..9e858f53009b9f 100644 --- a/target/linux/ipq60xx/patches-5.15/0024-v6.0-clk-qcom-ipq8074-add-USB-GDSCs.patch +++ b/target/linux/ipq60xx/patches-5.15/0024-v6.0-clk-qcom-ipq8074-add-USB-GDSCs.patch @@ -15,7 +15,7 @@ Link: https://lore.kernel.org/r/20220515210048.483898-9-robimarko@gmail.com --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig -@@ -166,6 +166,7 @@ config IPQ_LCC_806X +@@ -167,6 +167,7 @@ config IPQ_LCC_806X config IPQ_GCC_8074 tristate "IPQ8074 Global Clock Controller" @@ -33,7 +33,7 @@ Link: https://lore.kernel.org/r/20220515210048.483898-9-robimarko@gmail.com #include "reset.h" enum { -@@ -4408,6 +4409,22 @@ static struct clk_branch gcc_pcie0_axi_s +@@ -4402,6 +4403,22 @@ static struct clk_branch gcc_pcie0_axi_s }, }; @@ -56,7 +56,7 @@ Link: https://lore.kernel.org/r/20220515210048.483898-9-robimarko@gmail.com static const struct alpha_pll_config ubi32_pll_config = { .l = 0x4e, .config_ctl_val = 0x200d4aa8, -@@ -4811,6 +4828,11 @@ static const struct qcom_reset_map gcc_i +@@ -4805,6 +4822,11 @@ static const struct qcom_reset_map gcc_i [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, }; @@ -68,7 +68,7 @@ Link: https://lore.kernel.org/r/20220515210048.483898-9-robimarko@gmail.com static const struct of_device_id gcc_ipq8074_match_table[] = { { .compatible = "qcom,gcc-ipq8074" }, { } -@@ -4833,6 +4855,8 @@ static const struct qcom_cc_desc gcc_ipq +@@ -4827,6 +4849,8 @@ static const struct qcom_cc_desc gcc_ipq .num_resets = ARRAY_SIZE(gcc_ipq8074_resets), .clk_hws = gcc_ipq8074_hws, .num_clk_hws = ARRAY_SIZE(gcc_ipq8074_hws), diff --git a/target/linux/ipq60xx/patches-5.15/0042-v6.0-PCI-dwc-tegra-move-GEN3_RELATED-DBI-register-to-comm.patch b/target/linux/ipq60xx/patches-5.15/0042-v6.0-PCI-dwc-tegra-move-GEN3_RELATED-DBI-register-to-comm.patch index 716e3a908bfd15..ad9b6fc98f66e0 100644 --- a/target/linux/ipq60xx/patches-5.15/0042-v6.0-PCI-dwc-tegra-move-GEN3_RELATED-DBI-register-to-comm.patch +++ b/target/linux/ipq60xx/patches-5.15/0042-v6.0-PCI-dwc-tegra-move-GEN3_RELATED-DBI-register-to-comm.patch @@ -30,7 +30,7 @@ Signed-off-by: Baruch Siach --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c -@@ -193,12 +193,6 @@ +@@ -194,12 +194,6 @@ #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK GENMASK(23, 8) #define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK GENMASK(3, 0) diff --git a/target/linux/ipq60xx/patches-5.15/0101-clk-qcom-clk-rcg2-add-rcg2-mux-ops.patch b/target/linux/ipq60xx/patches-5.15/0101-clk-qcom-clk-rcg2-add-rcg2-mux-ops.patch index 6e210c430c13b7..548f1e97d5f4d9 100644 --- a/target/linux/ipq60xx/patches-5.15/0101-clk-qcom-clk-rcg2-add-rcg2-mux-ops.patch +++ b/target/linux/ipq60xx/patches-5.15/0101-clk-qcom-clk-rcg2-add-rcg2-mux-ops.patch @@ -33,7 +33,7 @@ Reviewed-by: Dmitry Baryshkov extern const struct clk_ops clk_byte2_ops; --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c -@@ -477,6 +477,13 @@ const struct clk_ops clk_rcg2_floor_ops +@@ -471,6 +471,13 @@ const struct clk_ops clk_rcg2_floor_ops }; EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops); diff --git a/target/linux/ipq60xx/patches-5.15/0129-clk-qcom-Add-WCSSAON-reset.patch b/target/linux/ipq60xx/patches-5.15/0129-clk-qcom-Add-WCSSAON-reset.patch index c90eb7bef27481..45ebea23035026 100644 --- a/target/linux/ipq60xx/patches-5.15/0129-clk-qcom-Add-WCSSAON-reset.patch +++ b/target/linux/ipq60xx/patches-5.15/0129-clk-qcom-Add-WCSSAON-reset.patch @@ -15,7 +15,7 @@ Acked-by: Stephen Boyd --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -4826,6 +4826,7 @@ static const struct qcom_reset_map gcc_i +@@ -4820,6 +4820,7 @@ static const struct qcom_reset_map gcc_i [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 }, [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 }, [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, diff --git a/target/linux/ipq60xx/patches-5.15/0134-clk-qcom-ipq8074-add-missing-networking-resets.patch b/target/linux/ipq60xx/patches-5.15/0134-clk-qcom-ipq8074-add-missing-networking-resets.patch index 1004880b8fafc0..d5313f146f33d8 100644 --- a/target/linux/ipq60xx/patches-5.15/0134-clk-qcom-ipq8074-add-missing-networking-resets.patch +++ b/target/linux/ipq60xx/patches-5.15/0134-clk-qcom-ipq8074-add-missing-networking-resets.patch @@ -17,7 +17,7 @@ Signed-off-by: Robert Marko --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -4827,6 +4827,20 @@ static const struct qcom_reset_map gcc_i +@@ -4821,6 +4821,20 @@ static const struct qcom_reset_map gcc_i [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 }, [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, [GCC_WCSSAON_RESET] = { 0x59010, 0 }, diff --git a/target/linux/ipq60xx/patches-5.15/0138-arm64-dts-qcom-ipq6018-add-usb3-DT-description.patch b/target/linux/ipq60xx/patches-5.15/0138-arm64-dts-qcom-ipq6018-add-usb3-DT-description.patch index fd4f296334be08..cfb6288bb73e1f 100644 --- a/target/linux/ipq60xx/patches-5.15/0138-arm64-dts-qcom-ipq6018-add-usb3-DT-description.patch +++ b/target/linux/ipq60xx/patches-5.15/0138-arm64-dts-qcom-ipq6018-add-usb3-DT-description.patch @@ -18,7 +18,7 @@ Link: https://lore.kernel.org/r/ebc2d340d566fa2d43127e253d5b8b134a87a78e.1630389 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -669,6 +669,89 @@ +@@ -664,6 +664,89 @@ }; }; diff --git a/target/linux/ipq60xx/patches-5.15/0140-arm64-dts-qcom-ipq6018-Remove-unused-qcom_config-pipe-trust-reg.patch b/target/linux/ipq60xx/patches-5.15/0140-arm64-dts-qcom-ipq6018-Remove-unused-qcom_config-pipe-trust-reg.patch index 36cfa22702d5b8..1f5256a1cdb8e8 100644 --- a/target/linux/ipq60xx/patches-5.15/0140-arm64-dts-qcom-ipq6018-Remove-unused-qcom_config-pipe-trust-reg.patch +++ b/target/linux/ipq60xx/patches-5.15/0140-arm64-dts-qcom-ipq6018-Remove-unused-qcom_config-pipe-trust-reg.patch @@ -32,7 +32,7 @@ Link: https://lore.kernel.org/r/20211013105541.68045-3-bhupesh.sharma@linaro.org --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -201,7 +201,6 @@ +@@ -195,7 +195,6 @@ #dma-cells = <1>; qcom,ee = <1>; qcom,controlled-remotely; diff --git a/target/linux/ipq60xx/patches-5.15/0141-arm64-dts-qcom-ipq6018-Remove-unused-iface_clk-property.patch b/target/linux/ipq60xx/patches-5.15/0141-arm64-dts-qcom-ipq6018-Remove-unused-iface_clk-property.patch index 459ca7ff3a2621..2d328d86bbc35e 100644 --- a/target/linux/ipq60xx/patches-5.15/0141-arm64-dts-qcom-ipq6018-Remove-unused-iface_clk-property.patch +++ b/target/linux/ipq60xx/patches-5.15/0141-arm64-dts-qcom-ipq6018-Remove-unused-iface_clk-property.patch @@ -31,7 +31,7 @@ Link: https://lore.kernel.org/r/20211013105541.68045-4-bhupesh.sharma@linaro.org --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -346,9 +346,8 @@ +@@ -341,9 +341,8 @@ compatible = "qcom,bam-v1.7.0"; reg = <0x0 0x07984000 0x0 0x1a000>; interrupts = ; diff --git a/target/linux/ipq60xx/patches-5.15/0142-arm64-dts-qcom-ipq6018-add-pcie-max-link-speed.patch b/target/linux/ipq60xx/patches-5.15/0142-arm64-dts-qcom-ipq6018-add-pcie-max-link-speed.patch index cc7ca39b61cba3..4fecc77e17eee1 100644 --- a/target/linux/ipq60xx/patches-5.15/0142-arm64-dts-qcom-ipq6018-add-pcie-max-link-speed.patch +++ b/target/linux/ipq60xx/patches-5.15/0142-arm64-dts-qcom-ipq6018-add-pcie-max-link-speed.patch @@ -16,7 +16,7 @@ Link: https://lore.kernel.org/r/fcf41277cf8529437374a5c10b2b1fcad30cd7c2.1640587 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -425,6 +425,7 @@ +@@ -420,6 +420,7 @@ linux,pci-domain = <0>; bus-range = <0x00 0xff>; num-lanes = <1>; diff --git a/target/linux/ipq60xx/patches-5.15/0143-arm64-dts-qcom-ipq6018-fix-usb-reference-period.patch b/target/linux/ipq60xx/patches-5.15/0143-arm64-dts-qcom-ipq6018-fix-usb-reference-period.patch index 04c7b876c429af..5f015ed1e8cd67 100644 --- a/target/linux/ipq60xx/patches-5.15/0143-arm64-dts-qcom-ipq6018-fix-usb-reference-period.patch +++ b/target/linux/ipq60xx/patches-5.15/0143-arm64-dts-qcom-ipq6018-fix-usb-reference-period.patch @@ -18,7 +18,7 @@ Link: https://lore.kernel.org/r/4f4df55cf44cd0fd7d773aca171d4f48662fb1a5.1642704 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -747,7 +747,7 @@ +@@ -742,7 +742,7 @@ snps,hird-threshold = /bits/ 8 <0x0>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; diff --git a/target/linux/ipq60xx/patches-5.15/0144-arm64-dts-ipq6018-Use-reference-clock-to-set-dwc3-period.patch b/target/linux/ipq60xx/patches-5.15/0144-arm64-dts-ipq6018-Use-reference-clock-to-set-dwc3-period.patch index dbee4a8887865d..ea7829d222fd11 100644 --- a/target/linux/ipq60xx/patches-5.15/0144-arm64-dts-ipq6018-Use-reference-clock-to-set-dwc3-period.patch +++ b/target/linux/ipq60xx/patches-5.15/0144-arm64-dts-ipq6018-Use-reference-clock-to-set-dwc3-period.patch @@ -17,7 +17,7 @@ Signed-off-by: Greg Kroah-Hartman --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -742,12 +742,13 @@ +@@ -737,12 +737,13 @@ interrupts = ; phys = <&qusb_phy_0>, <&usb0_ssphy>; phy-names = "usb2-phy", "usb3-phy"; diff --git a/target/linux/ipq60xx/patches-5.15/0145-arm64-dts-qcom-ipq6018-enable-the-GICv2m-supporte.patch b/target/linux/ipq60xx/patches-5.15/0145-arm64-dts-qcom-ipq6018-enable-the-GICv2m-supporte.patch index b2c7f9012ba7b8..90dacf7491190b 100644 --- a/target/linux/ipq60xx/patches-5.15/0145-arm64-dts-qcom-ipq6018-enable-the-GICv2m-supporte.patch +++ b/target/linux/ipq60xx/patches-5.15/0145-arm64-dts-qcom-ipq6018-enable-the-GICv2m-supporte.patch @@ -15,7 +15,7 @@ Link: https://lore.kernel.org/r/1644334525-11577-3-git-send-email-quic_kathirav@ --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -373,6 +373,8 @@ +@@ -368,6 +368,8 @@ intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; @@ -24,7 +24,7 @@ Link: https://lore.kernel.org/r/1644334525-11577-3-git-send-email-quic_kathirav@ interrupt-controller; #interrupt-cells = <0x3>; reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ -@@ -380,6 +382,13 @@ +@@ -375,6 +377,13 @@ <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ interrupts = ; diff --git a/target/linux/ipq60xx/patches-5.15/0146-arm64-dts-qcom-ipq6018-drop-the-clock-frequency-property.patch b/target/linux/ipq60xx/patches-5.15/0146-arm64-dts-qcom-ipq6018-drop-the-clock-frequency-property.patch index e3eed68dd887dd..082a42fe54620b 100644 --- a/target/linux/ipq60xx/patches-5.15/0146-arm64-dts-qcom-ipq6018-drop-the-clock-frequency-property.patch +++ b/target/linux/ipq60xx/patches-5.15/0146-arm64-dts-qcom-ipq6018-drop-the-clock-frequency-property.patch @@ -16,7 +16,7 @@ Link: https://lore.kernel.org/r/1643819709-5410-3-git-send-email-quic_kathirav@q --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -528,7 +528,6 @@ +@@ -523,7 +523,6 @@ ranges; compatible = "arm,armv7-timer-mem"; reg = <0x0 0x0b120000 0x0 0x1000>; diff --git a/target/linux/ipq60xx/patches-5.15/0147-arm64-dts-qcom-align-dmas-in-I2C-SPI-UART-with-DT-schema.patch b/target/linux/ipq60xx/patches-5.15/0147-arm64-dts-qcom-align-dmas-in-I2C-SPI-UART-with-DT-schema.patch index 64078bea783b3b..cd37ec549110b2 100644 --- a/target/linux/ipq60xx/patches-5.15/0147-arm64-dts-qcom-align-dmas-in-I2C-SPI-UART-with-DT-schema.patch +++ b/target/linux/ipq60xx/patches-5.15/0147-arm64-dts-qcom-align-dmas-in-I2C-SPI-UART-with-DT-schema.patch @@ -15,7 +15,7 @@ Link: https://lore.kernel.org/r/20220405063451.12011-2-krzysztof.kozlowski@linar --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -322,8 +322,8 @@ +@@ -317,8 +317,8 @@ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; clock-names = "iface", "core"; clock-frequency = <400000>; @@ -26,7 +26,7 @@ Link: https://lore.kernel.org/r/20220405063451.12011-2-krzysztof.kozlowski@linar status = "disabled"; }; -@@ -337,8 +337,8 @@ +@@ -332,8 +332,8 @@ <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; clock-names = "iface", "core"; clock-frequency = <400000>; diff --git a/target/linux/ipq60xx/patches-5.15/0148-arm64-dts-qcom-align-clocks-in-I2C-SPI-with-DT-schema.patch b/target/linux/ipq60xx/patches-5.15/0148-arm64-dts-qcom-align-clocks-in-I2C-SPI-with-DT-schema.patch index 3f1ee1629f7bfb..2b297d70f8ca45 100644 --- a/target/linux/ipq60xx/patches-5.15/0148-arm64-dts-qcom-align-clocks-in-I2C-SPI-with-DT-schema.patch +++ b/target/linux/ipq60xx/patches-5.15/0148-arm64-dts-qcom-align-clocks-in-I2C-SPI-with-DT-schema.patch @@ -14,7 +14,7 @@ Link: https://lore.kernel.org/r/20220405063451.12011-3-krzysztof.kozlowski@linar --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -318,9 +318,9 @@ +@@ -313,9 +313,9 @@ #size-cells = <0>; reg = <0x0 0x078b6000 0x0 0x600>; interrupts = ; @@ -27,7 +27,7 @@ Link: https://lore.kernel.org/r/20220405063451.12011-3-krzysztof.kozlowski@linar clock-frequency = <400000>; dmas = <&blsp_dma 14>, <&blsp_dma 15>; dma-names = "tx", "rx"; -@@ -333,9 +333,9 @@ +@@ -328,9 +328,9 @@ #size-cells = <0>; reg = <0x0 0x078b7000 0x0 0x600>; interrupts = ; diff --git a/target/linux/ipq60xx/patches-5.15/0149-arm64-dts-qcom-ipq6018-Fix-qmp-usb3-phy-node.patch b/target/linux/ipq60xx/patches-5.15/0149-arm64-dts-qcom-ipq6018-Fix-qmp-usb3-phy-node.patch index 9c7f5eed9a6407..5cd08b7bc3c2fe 100644 --- a/target/linux/ipq60xx/patches-5.15/0149-arm64-dts-qcom-ipq6018-Fix-qmp-usb3-phy-node.patch +++ b/target/linux/ipq60xx/patches-5.15/0149-arm64-dts-qcom-ipq6018-Fix-qmp-usb3-phy-node.patch @@ -23,7 +23,7 @@ Link: https://lore.kernel.org/r/20220228123019.382037-7-bhupesh.sharma@linaro.or --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -681,7 +681,6 @@ +@@ -676,7 +676,6 @@ reg = <0x0 0x78000 0x0 0x1C4>; #address-cells = <2>; #size-cells = <2>; @@ -31,7 +31,7 @@ Link: https://lore.kernel.org/r/20220228123019.382037-7-bhupesh.sharma@linaro.or ranges; clocks = <&gcc GCC_USB0_AUX_CLK>, -@@ -693,12 +692,13 @@ +@@ -688,12 +687,13 @@ reset-names = "phy","common"; status = "disabled"; diff --git a/target/linux/ipq60xx/patches-5.15/0150-arm64-dts-qcom-correct-DWC3-node-names-and-unit-addresses.patch b/target/linux/ipq60xx/patches-5.15/0150-arm64-dts-qcom-correct-DWC3-node-names-and-unit-addresses.patch index 17f3c76f1d3f19..b2e2467fa7889b 100644 --- a/target/linux/ipq60xx/patches-5.15/0150-arm64-dts-qcom-correct-DWC3-node-names-and-unit-addresses.patch +++ b/target/linux/ipq60xx/patches-5.15/0150-arm64-dts-qcom-correct-DWC3-node-names-and-unit-addresses.patch @@ -16,7 +16,7 @@ Signed-off-by: Greg Kroah-Hartman --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -641,7 +641,7 @@ +@@ -636,7 +636,7 @@ status = "disabled"; }; @@ -25,7 +25,7 @@ Signed-off-by: Greg Kroah-Hartman compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; reg = <0x0 0x070F8800 0x0 0x400>; #address-cells = <2>; -@@ -718,7 +718,7 @@ +@@ -713,7 +713,7 @@ status = "disabled"; }; @@ -34,7 +34,7 @@ Signed-off-by: Greg Kroah-Hartman compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; reg = <0x0 0x8AF8800 0x0 0x400>; #address-cells = <2>; -@@ -744,7 +744,7 @@ +@@ -739,7 +739,7 @@ resets = <&gcc GCC_USB0_BCR>; status = "disabled"; diff --git a/target/linux/ipq60xx/patches-5.15/0151-arm64-dts-qcom-align-DWC3-USB-clocks-with-DT-schema.patch b/target/linux/ipq60xx/patches-5.15/0151-arm64-dts-qcom-align-DWC3-USB-clocks-with-DT-schema.patch index 81811c3887143e..833c991a5e4e4f 100644 --- a/target/linux/ipq60xx/patches-5.15/0151-arm64-dts-qcom-align-DWC3-USB-clocks-with-DT-schema.patch +++ b/target/linux/ipq60xx/patches-5.15/0151-arm64-dts-qcom-align-DWC3-USB-clocks-with-DT-schema.patch @@ -15,7 +15,7 @@ Signed-off-by: Greg Kroah-Hartman --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -650,7 +650,7 @@ +@@ -645,7 +645,7 @@ clocks = <&gcc GCC_USB1_MASTER_CLK>, <&gcc GCC_USB1_SLEEP_CLK>, <&gcc GCC_USB1_MOCK_UTMI_CLK>; @@ -24,7 +24,7 @@ Signed-off-by: Greg Kroah-Hartman "sleep", "mock_utmi"; -@@ -729,8 +729,8 @@ +@@ -724,8 +724,8 @@ <&gcc GCC_USB0_MASTER_CLK>, <&gcc GCC_USB0_SLEEP_CLK>, <&gcc GCC_USB0_MOCK_UTMI_CLK>; diff --git a/target/linux/ipq60xx/patches-5.15/0153-arm64-dts-qcom-timer-should-use-only-32-bit-size.patch b/target/linux/ipq60xx/patches-5.15/0153-arm64-dts-qcom-timer-should-use-only-32-bit-size.patch index b832896baa51ef..23df27f9cbb70a 100644 --- a/target/linux/ipq60xx/patches-5.15/0153-arm64-dts-qcom-timer-should-use-only-32-bit-size.patch +++ b/target/linux/ipq60xx/patches-5.15/0153-arm64-dts-qcom-timer-should-use-only-32-bit-size.patch @@ -21,7 +21,7 @@ Link: https://lore.kernel.org/r/20220626105800.35586-1-david@ixit.cz --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -523,9 +523,9 @@ +@@ -518,9 +518,9 @@ }; timer@b120000 { @@ -34,7 +34,7 @@ Link: https://lore.kernel.org/r/20220626105800.35586-1-david@ixit.cz compatible = "arm,armv7-timer-mem"; reg = <0x0 0x0b120000 0x0 0x1000>; -@@ -533,49 +533,49 @@ +@@ -528,49 +528,49 @@ frame-number = <0>; interrupts = , ; diff --git a/target/linux/ipq60xx/patches-5.15/0154-arm64-dts-qcom-adjust-whitespace-around-.patch b/target/linux/ipq60xx/patches-5.15/0154-arm64-dts-qcom-adjust-whitespace-around-.patch index 5d9d0630810fc9..89e5eb2c4f1dea 100644 --- a/target/linux/ipq60xx/patches-5.15/0154-arm64-dts-qcom-adjust-whitespace-around-.patch +++ b/target/linux/ipq60xx/patches-5.15/0154-arm64-dts-qcom-adjust-whitespace-around-.patch @@ -16,7 +16,7 @@ Link: https://lore.kernel.org/r/20220526204248.832139-1-krzysztof.kozlowski@lina --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -321,7 +321,7 @@ +@@ -316,7 +316,7 @@ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; @@ -25,7 +25,7 @@ Link: https://lore.kernel.org/r/20220526204248.832139-1-krzysztof.kozlowski@lina dmas = <&blsp_dma 14>, <&blsp_dma 15>; dma-names = "tx", "rx"; status = "disabled"; -@@ -336,7 +336,7 @@ +@@ -331,7 +331,7 @@ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; diff --git a/target/linux/ipq60xx/patches-5.15/0155-arm64-dts-qcom-ipq6018-add-label-to-remoteproc-node.patch b/target/linux/ipq60xx/patches-5.15/0155-arm64-dts-qcom-ipq6018-add-label-to-remoteproc-node.patch index 508cb6abf786f3..304356d56f4465 100644 --- a/target/linux/ipq60xx/patches-5.15/0155-arm64-dts-qcom-ipq6018-add-label-to-remoteproc-node.patch +++ b/target/linux/ipq60xx/patches-5.15/0155-arm64-dts-qcom-ipq6018-add-label-to-remoteproc-node.patch @@ -16,7 +16,7 @@ Link: https://lore.kernel.org/r/20220517070113.18023-10-krzysztof.kozlowski@lina --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -619,6 +619,7 @@ +@@ -614,6 +614,7 @@ glink-edge { interrupts = ; diff --git a/target/linux/ipq60xx/patches-5.15/0156-arm64-dts-qcom-ipq6018-correct-QUP-peripheral-labels.patch b/target/linux/ipq60xx/patches-5.15/0156-arm64-dts-qcom-ipq6018-correct-QUP-peripheral-labels.patch index 515fa613acabc2..68b24b1a26e05c 100644 --- a/target/linux/ipq60xx/patches-5.15/0156-arm64-dts-qcom-ipq6018-correct-QUP-peripheral-labels.patch +++ b/target/linux/ipq60xx/patches-5.15/0156-arm64-dts-qcom-ipq6018-correct-QUP-peripheral-labels.patch @@ -44,7 +44,7 @@ Link: https://lore.kernel.org/r/20220604153003.55172-1-robimarko@gmail.com pinctrl-names = "default"; --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -282,7 +282,7 @@ +@@ -277,7 +277,7 @@ status = "disabled"; }; @@ -53,7 +53,7 @@ Link: https://lore.kernel.org/r/20220604153003.55172-1-robimarko@gmail.com compatible = "qcom,spi-qup-v2.2.1"; #address-cells = <1>; #size-cells = <0>; -@@ -297,7 +297,7 @@ +@@ -292,7 +292,7 @@ status = "disabled"; }; @@ -62,7 +62,7 @@ Link: https://lore.kernel.org/r/20220604153003.55172-1-robimarko@gmail.com compatible = "qcom,spi-qup-v2.2.1"; #address-cells = <1>; #size-cells = <0>; -@@ -312,7 +312,7 @@ +@@ -307,7 +307,7 @@ status = "disabled"; }; @@ -71,7 +71,7 @@ Link: https://lore.kernel.org/r/20220604153003.55172-1-robimarko@gmail.com compatible = "qcom,i2c-qup-v2.2.1"; #address-cells = <1>; #size-cells = <0>; -@@ -327,7 +327,7 @@ +@@ -322,7 +322,7 @@ status = "disabled"; }; diff --git a/target/linux/ipq60xx/patches-5.15/0158-arm64-dts-qcom-ipq6018-drop-USB-PHY-clock-index.patch b/target/linux/ipq60xx/patches-5.15/0158-arm64-dts-qcom-ipq6018-drop-USB-PHY-clock-index.patch index 45676987d7cd63..04dfd032bdc286 100644 --- a/target/linux/ipq60xx/patches-5.15/0158-arm64-dts-qcom-ipq6018-drop-USB-PHY-clock-index.patch +++ b/target/linux/ipq60xx/patches-5.15/0158-arm64-dts-qcom-ipq6018-drop-USB-PHY-clock-index.patch @@ -16,7 +16,7 @@ Link: https://lore.kernel.org/r/20220705114032.22787-4-johan+linaro@kernel.org --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -699,7 +699,7 @@ +@@ -694,7 +694,7 @@ <0x0 0x00078800 0x0 0x1F8>, /* PCS */ <0x0 0x00078600 0x0 0x044>; /* PCS misc */ #phy-cells = <0>; diff --git a/target/linux/ipq60xx/patches-5.15/0159-arm64-dts-qcom-ipq6018-add-missing-TCSR-syscon-compatible.patch b/target/linux/ipq60xx/patches-5.15/0159-arm64-dts-qcom-ipq6018-add-missing-TCSR-syscon-compatible.patch index 7f9c2368438e43..fc16ae58dc63ef 100644 --- a/target/linux/ipq60xx/patches-5.15/0159-arm64-dts-qcom-ipq6018-add-missing-TCSR-syscon-compatible.patch +++ b/target/linux/ipq60xx/patches-5.15/0159-arm64-dts-qcom-ipq6018-add-missing-TCSR-syscon-compatible.patch @@ -14,7 +14,7 @@ Link: https://lore.kernel.org/r/20220909092035.223915-6-krzysztof.kozlowski@lina --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -258,7 +258,7 @@ +@@ -253,7 +253,7 @@ }; tcsr: syscon@1937000 { diff --git a/target/linux/ipq60xx/patches-5.15/0160-arm64-dts-qcom-ipq6018-switch-TCSR-mutex-to-MMIO.patch b/target/linux/ipq60xx/patches-5.15/0160-arm64-dts-qcom-ipq6018-switch-TCSR-mutex-to-MMIO.patch deleted file mode 100644 index 8b5e1662bc5def..00000000000000 --- a/target/linux/ipq60xx/patches-5.15/0160-arm64-dts-qcom-ipq6018-switch-TCSR-mutex-to-MMIO.patch +++ /dev/null @@ -1,49 +0,0 @@ -From f5e303aefc06b7508d7a490f9a2d80e4dc134c70 Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Fri, 9 Sep 2022 11:20:31 +0200 -Subject: [PATCH] arm64: dts: qcom: ipq6018: switch TCSR mutex to MMIO - -The TCSR mutex bindings allow device to be described only with address -space (so it uses MMIO, not syscon regmap). This seems reasonable as -TCSR mutex is actually a dedicated IO address space and it also fixes DT -schema checks: - - qcom/ipq6018-cp01-c1.dtb: hwlock: 'reg' is a required property - qcom/ipq6018-cp01-c1.dtb: hwlock: 'syscon' does not match any of the regexes: 'pinctrl-[0-9]+' - -Signed-off-by: Krzysztof Kozlowski -Signed-off-by: Bjorn Andersson -Link: https://lore.kernel.org/r/20220909092035.223915-12-krzysztof.kozlowski@linaro.org ---- - arch/arm64/boot/dts/qcom/ipq6018.dtsi | 13 ++++--------- - 1 file changed, 4 insertions(+), 9 deletions(-) - ---- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi -+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi -@@ -129,12 +129,6 @@ - }; - }; - -- tcsr_mutex: hwlock { -- compatible = "qcom,tcsr-mutex"; -- syscon = <&tcsr_mutex_regs 0 0x80>; -- #hwlock-cells = <1>; -- }; -- - pmuv8: pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = ; - }; - -- tcsr_mutex_regs: syscon@1905000 { -- compatible = "syscon"; -- reg = <0x0 0x01905000 0x0 0x8000>; -+ tcsr_mutex: hwlock@1905000 { -+ compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex"; -+ reg = <0x0 0x01905000 0x0 0x1000>; -+ #hwlock-cells = <1>; - }; - - tcsr: syscon@1937000 { diff --git a/target/linux/ipq60xx/patches-5.15/0600-5.15-qca-nss-ecm-support-CORE.patch b/target/linux/ipq60xx/patches-5.15/0600-5.15-qca-nss-ecm-support-CORE.patch index cbdad8fa1edb55..05846cf53ab293 100644 --- a/target/linux/ipq60xx/patches-5.15/0600-5.15-qca-nss-ecm-support-CORE.patch +++ b/target/linux/ipq60xx/patches-5.15/0600-5.15-qca-nss-ecm-support-CORE.patch @@ -55,7 +55,7 @@ #endif --- a/include/linux/if_vlan.h +++ b/include/linux/if_vlan.h -@@ -222,7 +222,28 @@ extern void vlan_vids_del_by_dev(struct +@@ -230,7 +230,28 @@ extern void vlan_vids_del_by_dev(struct extern bool vlan_uses_dev(const struct net_device *dev); @@ -549,7 +549,7 @@ struct fib_table *tb; --- a/include/net/addrconf.h +++ b/include/net/addrconf.h -@@ -504,4 +504,9 @@ int if6_proc_init(void); +@@ -512,4 +512,9 @@ int if6_proc_init(void); void if6_proc_exit(void); #endif diff --git a/target/linux/ipq60xx/patches-5.15/0606-5.15-qca-nss-ecm-bonding-add-bond_get_id.patch b/target/linux/ipq60xx/patches-5.15/0606-5.15-qca-nss-ecm-bonding-add-bond_get_id.patch index 15580dfdf6beac..5480ae631653d6 100644 --- a/target/linux/ipq60xx/patches-5.15/0606-5.15-qca-nss-ecm-bonding-add-bond_get_id.patch +++ b/target/linux/ipq60xx/patches-5.15/0606-5.15-qca-nss-ecm-bonding-add-bond_get_id.patch @@ -10,7 +10,7 @@ static struct flow_dissector flow_keys_bonding __read_mostly; /*-------------------------- Forward declarations ---------------------------*/ -@@ -4109,6 +4112,23 @@ static int bond_get_lowest_level_rcu(str +@@ -4115,6 +4118,23 @@ static int bond_get_lowest_level_rcu(str } #endif @@ -34,7 +34,7 @@ static void bond_get_stats(struct net_device *bond_dev, struct rtnl_link_stats64 *stats) { -@@ -5441,6 +5461,10 @@ static void bond_destructor(struct net_d +@@ -5447,6 +5467,10 @@ static void bond_destructor(struct net_d if (bond->rr_tx_counter) free_percpu(bond->rr_tx_counter); @@ -45,7 +45,7 @@ } void bond_setup(struct net_device *bond_dev) -@@ -6014,7 +6038,14 @@ int bond_create(struct net *net, const c +@@ -6020,7 +6044,14 @@ int bond_create(struct net *net, const c bond_work_init_all(bond); diff --git a/target/linux/ipq60xx/patches-5.15/1002-clk-qcom-add-support-for-hw-controlled-RCG.patch b/target/linux/ipq60xx/patches-5.15/1002-clk-qcom-add-support-for-hw-controlled-RCG.patch index 1bc07952510a2b..3f0ddeb3be88bc 100644 --- a/target/linux/ipq60xx/patches-5.15/1002-clk-qcom-add-support-for-hw-controlled-RCG.patch +++ b/target/linux/ipq60xx/patches-5.15/1002-clk-qcom-add-support-for-hw-controlled-RCG.patch @@ -84,7 +84,7 @@ Signed-off-by: Alexandru Gagniuc } /* -@@ -312,12 +320,19 @@ static int __clk_rcg2_configure(struct c +@@ -306,12 +314,19 @@ static int __clk_rcg2_configure(struct c static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) { int ret; @@ -105,7 +105,7 @@ Signed-off-by: Alexandru Gagniuc } static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate, -@@ -448,7 +463,7 @@ static int clk_rcg2_set_duty_cycle(struc +@@ -442,7 +457,7 @@ static int clk_rcg2_set_duty_cycle(struc if (ret) return ret; @@ -114,7 +114,7 @@ Signed-off-by: Alexandru Gagniuc } const struct clk_ops clk_rcg2_ops = { -@@ -910,7 +925,7 @@ static int clk_gfx3d_set_rate_and_parent +@@ -904,7 +919,7 @@ static int clk_gfx3d_set_rate_and_parent if (ret) return ret; @@ -123,7 +123,7 @@ Signed-off-by: Alexandru Gagniuc } static int clk_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate, -@@ -1022,7 +1037,7 @@ static int clk_rcg2_shared_enable(struct +@@ -1016,7 +1031,7 @@ static int clk_rcg2_shared_enable(struct if (ret) return ret; @@ -132,7 +132,7 @@ Signed-off-by: Alexandru Gagniuc if (ret) return ret; -@@ -1053,7 +1068,7 @@ static void clk_rcg2_shared_disable(stru +@@ -1047,7 +1062,7 @@ static void clk_rcg2_shared_disable(stru regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, rcg->safe_src_index << CFG_SRC_SEL_SHIFT); diff --git a/target/linux/ipq60xx/patches-5.15/1003-clk-qcom-ipq6018-add-missing-clock-flags.patch b/target/linux/ipq60xx/patches-5.15/1003-clk-qcom-ipq6018-add-missing-clock-flags.patch index 4f2b410f439c70..02279a70fe3233 100644 --- a/target/linux/ipq60xx/patches-5.15/1003-clk-qcom-ipq6018-add-missing-clock-flags.patch +++ b/target/linux/ipq60xx/patches-5.15/1003-clk-qcom-ipq6018-add-missing-clock-flags.patch @@ -31,7 +31,7 @@ Signed-off-by: Alexandru Gagniuc }, }, }; -@@ -150,6 +151,7 @@ static struct clk_alpha_pll gpll6_main = +@@ -148,6 +149,7 @@ static struct clk_alpha_pll gpll6_main = }, .num_parents = 1, .ops = &clk_alpha_pll_ops, @@ -39,7 +39,7 @@ Signed-off-by: Alexandru Gagniuc }, }, }; -@@ -181,6 +183,7 @@ static struct clk_alpha_pll gpll4_main = +@@ -178,6 +180,7 @@ static struct clk_alpha_pll gpll4_main = }, .num_parents = 1, .ops = &clk_alpha_pll_ops, @@ -47,7 +47,7 @@ Signed-off-by: Alexandru Gagniuc }, }, }; -@@ -211,6 +214,7 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_s +@@ -207,6 +210,7 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_s .freq_tbl = ftbl_pcnoc_bfdcd_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, @@ -55,7 +55,7 @@ Signed-off-by: Alexandru Gagniuc .clkr.hw.init = &(struct clk_init_data){ .name = "pcnoc_bfdcd_clk_src", .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, -@@ -232,6 +236,7 @@ static struct clk_alpha_pll gpll2_main = +@@ -228,6 +232,7 @@ static struct clk_alpha_pll gpll2_main = }, .num_parents = 1, .ops = &clk_alpha_pll_ops, @@ -63,7 +63,7 @@ Signed-off-by: Alexandru Gagniuc }, }, }; -@@ -456,6 +461,7 @@ static struct clk_branch gcc_sleep_clk_s +@@ -450,6 +455,7 @@ static struct clk_branch gcc_sleep_clk_s }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -71,7 +71,7 @@ Signed-off-by: Alexandru Gagniuc }, }, }; -@@ -960,6 +966,7 @@ static struct clk_rcg2 nss_crypto_clk_sr +@@ -954,6 +960,7 @@ static struct clk_rcg2 nss_crypto_clk_sr .mnd_width = 16, .hid_width = 5, .parent_map = gcc_xo_nss_crypto_pll_gpll0_map, @@ -79,7 +79,7 @@ Signed-off-by: Alexandru Gagniuc .clkr.hw.init = &(struct clk_init_data){ .name = "nss_crypto_clk_src", .parent_data = gcc_xo_nss_crypto_pll_gpll0, -@@ -1131,6 +1138,7 @@ static struct clk_rcg2 nss_ubi0_clk_src +@@ -1125,6 +1132,7 @@ static struct clk_rcg2 nss_ubi0_clk_src .freq_tbl = ftbl_nss_ubi_clk_src, .hid_width = 5, .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map, @@ -87,7 +87,7 @@ Signed-off-by: Alexandru Gagniuc .clkr.hw.init = &(struct clk_init_data){ .name = "nss_ubi0_clk_src", .parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6, -@@ -1869,7 +1877,7 @@ static struct clk_branch gcc_apss_ahb_cl +@@ -1863,7 +1871,7 @@ static struct clk_branch gcc_apss_ahb_cl .parent_hws = (const struct clk_hw *[]){ &apss_ahb_postdiv_clk_src.clkr.hw }, .num_parents = 1, @@ -96,7 +96,7 @@ Signed-off-by: Alexandru Gagniuc .ops = &clk_branch2_ops, }, }, -@@ -1891,11 +1899,13 @@ static struct clk_rcg2 system_noc_bfdcd_ +@@ -1885,11 +1893,13 @@ static struct clk_rcg2 system_noc_bfdcd_ .freq_tbl = ftbl_system_noc_bfdcd_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map, @@ -110,7 +110,7 @@ Signed-off-by: Alexandru Gagniuc }, }; -@@ -1945,7 +1955,7 @@ static struct clk_branch gcc_apss_axi_cl +@@ -1939,7 +1949,7 @@ static struct clk_branch gcc_apss_axi_cl .parent_hws = (const struct clk_hw *[]){ &apss_axi_clk_src.clkr.hw }, .num_parents = 1, @@ -119,7 +119,7 @@ Signed-off-by: Alexandru Gagniuc .ops = &clk_branch2_ops, }, }, -@@ -2314,7 +2324,7 @@ static struct clk_branch gcc_xo_clk = { +@@ -2308,7 +2318,7 @@ static struct clk_branch gcc_xo_clk = { .parent_hws = (const struct clk_hw *[]){ &gcc_xo_clk_src.clkr.hw }, .num_parents = 1, @@ -128,7 +128,7 @@ Signed-off-by: Alexandru Gagniuc .ops = &clk_branch2_ops, }, }, -@@ -3163,6 +3173,7 @@ static struct clk_branch gcc_nssnoc_ppe_ +@@ -3157,6 +3167,7 @@ static struct clk_branch gcc_nssnoc_ppe_ .name = "gcc_nssnoc_ppe_cfg_clk", .parent_hws = (const struct clk_hw *[]){ &nss_ppe_clk_src.clkr.hw }, @@ -136,7 +136,7 @@ Signed-off-by: Alexandru Gagniuc .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, -@@ -3521,7 +3532,7 @@ static struct clk_branch gcc_qdss_dap_cl +@@ -3515,7 +3526,7 @@ static struct clk_branch gcc_qdss_dap_cl .parent_hws = (const struct clk_hw *[]){ &qdss_dap_sync_clk_src.hw }, .num_parents = 1, diff --git a/target/linux/ipq60xx/patches-5.15/1004-clk-qcom-ipq6018-add-missing-clocks.patch b/target/linux/ipq60xx/patches-5.15/1004-clk-qcom-ipq6018-add-missing-clocks.patch index 89f9e5c3535344..54ae9ac336f431 100644 --- a/target/linux/ipq60xx/patches-5.15/1004-clk-qcom-ipq6018-add-missing-clocks.patch +++ b/target/linux/ipq60xx/patches-5.15/1004-clk-qcom-ipq6018-add-missing-clocks.patch @@ -14,7 +14,7 @@ Signed-off-by: Alexandru Gagniuc --- a/drivers/clk/qcom/gcc-ipq6018.c +++ b/drivers/clk/qcom/gcc-ipq6018.c -@@ -223,6 +223,19 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_s +@@ -219,6 +219,19 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_s }, }; @@ -34,7 +34,7 @@ Signed-off-by: Alexandru Gagniuc static struct clk_alpha_pll gpll2_main = { .offset = 0x4a000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], -@@ -505,6 +518,19 @@ static struct clk_rcg2 snoc_nssnoc_bfdcd +@@ -499,6 +512,19 @@ static struct clk_rcg2 snoc_nssnoc_bfdcd }, }; @@ -54,7 +54,7 @@ Signed-off-by: Alexandru Gagniuc static const struct freq_tbl ftbl_apss_ahb_clk_src[] = { F(24000000, P_XO, 1, 0, 0), F(25000000, P_GPLL0_DIV2, 16, 0, 0), -@@ -1909,6 +1935,19 @@ static struct clk_rcg2 system_noc_bfdcd_ +@@ -1903,6 +1929,19 @@ static struct clk_rcg2 system_noc_bfdcd_ }, }; @@ -74,7 +74,7 @@ Signed-off-by: Alexandru Gagniuc static const struct freq_tbl ftbl_ubi32_mem_noc_bfdcd_clk_src[] = { F(24000000, P_XO, 1, 0, 0), F(307670000, P_BIAS_PLL_NSS_NOC, 1.5, 0, 0), -@@ -1944,6 +1983,19 @@ static struct clk_rcg2 ubi32_mem_noc_bfd +@@ -1938,6 +1977,19 @@ static struct clk_rcg2 ubi32_mem_noc_bfd }, }; @@ -94,7 +94,7 @@ Signed-off-by: Alexandru Gagniuc static struct clk_branch gcc_apss_axi_clk = { .halt_reg = 0x46020, .halt_check = BRANCH_HALT_VOTED, -@@ -2138,6 +2190,22 @@ static struct clk_branch gcc_blsp1_qup5_ +@@ -2132,6 +2184,22 @@ static struct clk_branch gcc_blsp1_qup5_ }, }; @@ -117,7 +117,7 @@ Signed-off-by: Alexandru Gagniuc static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { .halt_reg = 0x0700c, .clkr = { -@@ -2681,6 +2749,454 @@ static struct clk_rcg2 lpass_q6_axim_clk +@@ -2675,6 +2743,454 @@ static struct clk_rcg2 lpass_q6_axim_clk }, }; @@ -572,7 +572,7 @@ Signed-off-by: Alexandru Gagniuc static struct freq_tbl ftbl_rbcpr_wcss_clk_src[] = { F(24000000, P_XO, 1, 0, 0), F(50000000, P_GPLL0, 16, 0, 0), -@@ -2700,6 +3216,23 @@ static struct clk_rcg2 rbcpr_wcss_clk_sr +@@ -2694,6 +3210,23 @@ static struct clk_rcg2 rbcpr_wcss_clk_sr }, }; @@ -596,7 +596,7 @@ Signed-off-by: Alexandru Gagniuc static struct clk_branch gcc_lpass_core_axim_clk = { .halt_reg = 0x1F028, .clkr = { -@@ -3522,6 +4055,22 @@ static struct clk_branch gcc_prng_ahb_cl +@@ -3516,6 +4049,22 @@ static struct clk_branch gcc_prng_ahb_cl }, }; @@ -619,7 +619,7 @@ Signed-off-by: Alexandru Gagniuc static struct clk_branch gcc_qdss_dap_clk = { .halt_reg = 0x29084, .clkr = { -@@ -4195,6 +4744,9 @@ static struct clk_hw *gcc_ipq6018_hws[] +@@ -4189,6 +4738,9 @@ static struct clk_hw *gcc_ipq6018_hws[] &gpll6_out_main_div2.hw, &qdss_dap_sync_clk_src.hw, &qdss_tsctr_div2_clk_src.hw, @@ -629,7 +629,7 @@ Signed-off-by: Alexandru Gagniuc }; static struct clk_regmap *gcc_ipq6018_clks[] = { -@@ -4292,6 +4844,7 @@ static struct clk_regmap *gcc_ipq6018_cl +@@ -4286,6 +4838,7 @@ static struct clk_regmap *gcc_ipq6018_cl [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, @@ -637,7 +637,7 @@ Signed-off-by: Alexandru Gagniuc [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, -@@ -4357,6 +4910,7 @@ static struct clk_regmap *gcc_ipq6018_cl +@@ -4351,6 +4904,7 @@ static struct clk_regmap *gcc_ipq6018_cl [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr, [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr, [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, @@ -645,7 +645,7 @@ Signed-off-by: Alexandru Gagniuc [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr, [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr, -@@ -4398,9 +4952,35 @@ static struct clk_regmap *gcc_ipq6018_cl +@@ -4392,9 +4946,35 @@ static struct clk_regmap *gcc_ipq6018_cl [PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr, [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, [PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr, @@ -681,7 +681,7 @@ Signed-off-by: Alexandru Gagniuc [GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr, [LPASS_CORE_AXIM_CLK_SRC] = &lpass_core_axim_clk_src.clkr, [GCC_LPASS_SNOC_CFG_CLK] = &gcc_lpass_snoc_cfg_clk.clkr, -@@ -4416,6 +4996,9 @@ static struct clk_regmap *gcc_ipq6018_cl +@@ -4410,6 +4990,9 @@ static struct clk_regmap *gcc_ipq6018_cl [GCC_MEM_NOC_UBI32_CLK] = &gcc_mem_noc_ubi32_clk.clkr, [GCC_MEM_NOC_LPASS_CLK] = &gcc_mem_noc_lpass_clk.clkr, [GCC_SNOC_LPASS_CFG_CLK] = &gcc_snoc_lpass_cfg_clk.clkr, @@ -691,7 +691,7 @@ Signed-off-by: Alexandru Gagniuc [QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr, [QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr, }; -@@ -4597,6 +5180,10 @@ static const struct qcom_cc_desc gcc_ipq +@@ -4591,6 +5174,10 @@ static const struct qcom_cc_desc gcc_ipq static int gcc_ipq6018_probe(struct platform_device *pdev) { struct regmap *regmap; diff --git a/target/linux/ipq60xx/patches-5.15/1005-clk-qcom-ipq6018-update-Huayra-PLL-settings.patch b/target/linux/ipq60xx/patches-5.15/1005-clk-qcom-ipq6018-update-Huayra-PLL-settings.patch index 9f8ced9bd7a8ea..036fd3e3f5e6dd 100644 --- a/target/linux/ipq60xx/patches-5.15/1005-clk-qcom-ipq6018-update-Huayra-PLL-settings.patch +++ b/target/linux/ipq60xx/patches-5.15/1005-clk-qcom-ipq6018-update-Huayra-PLL-settings.patch @@ -30,7 +30,7 @@ Signed-off-by: Alexandru Gagniuc } --- a/drivers/clk/qcom/gcc-ipq6018.c +++ b/drivers/clk/qcom/gcc-ipq6018.c -@@ -4711,15 +4711,18 @@ static struct clk_branch gcc_dcc_clk = { +@@ -4705,15 +4705,18 @@ static struct clk_branch gcc_dcc_clk = { static const struct alpha_pll_config ubi32_pll_config = { .l = 0x3e, diff --git a/target/linux/ipq60xx/patches-5.15/1006-clk-qcom-pq6018-workaround-networking-clock-parenting.patch b/target/linux/ipq60xx/patches-5.15/1006-clk-qcom-pq6018-workaround-networking-clock-parenting.patch index fdaf3f35981b84..8af6549a8667eb 100644 --- a/target/linux/ipq60xx/patches-5.15/1006-clk-qcom-pq6018-workaround-networking-clock-parenting.patch +++ b/target/linux/ipq60xx/patches-5.15/1006-clk-qcom-pq6018-workaround-networking-clock-parenting.patch @@ -19,7 +19,7 @@ Signed-off-by: Robert Marko --- a/drivers/clk/qcom/gcc-ipq6018.c +++ b/drivers/clk/qcom/gcc-ipq6018.c -@@ -387,7 +387,7 @@ static const struct freq_tbl ftbl_nss_pp +@@ -381,7 +381,7 @@ static const struct freq_tbl ftbl_nss_pp static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = { { .fw_name = "xo" }, @@ -28,7 +28,7 @@ Signed-off-by: Robert Marko { .hw = &gpll0.clkr.hw }, { .hw = &gpll4.clkr.hw }, { .hw = &nss_crypto_pll.clkr.hw }, -@@ -567,12 +567,12 @@ static const struct freq_tbl ftbl_nss_po +@@ -561,12 +561,12 @@ static const struct freq_tbl ftbl_nss_po static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = { { .fw_name = "xo" }, @@ -46,7 +46,7 @@ Signed-off-by: Robert Marko }; static const struct parent_map -@@ -614,12 +614,12 @@ static const struct freq_tbl ftbl_nss_po +@@ -608,12 +608,12 @@ static const struct freq_tbl ftbl_nss_po static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = { { .fw_name = "xo" }, @@ -64,7 +64,7 @@ Signed-off-by: Robert Marko }; static const struct parent_map -@@ -755,10 +755,10 @@ static const struct freq_tbl ftbl_nss_po +@@ -749,10 +749,10 @@ static const struct freq_tbl ftbl_nss_po static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = { { .fw_name = "xo" }, @@ -78,7 +78,7 @@ Signed-off-by: Robert Marko }; static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = { -@@ -791,10 +791,10 @@ static const struct freq_tbl ftbl_nss_po +@@ -785,10 +785,10 @@ static const struct freq_tbl ftbl_nss_po static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = { { .fw_name = "xo" }, @@ -92,7 +92,7 @@ Signed-off-by: Robert Marko }; static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = { -@@ -1955,12 +1955,11 @@ static const struct freq_tbl ftbl_ubi32_ +@@ -1949,12 +1949,11 @@ static const struct freq_tbl ftbl_ubi32_ { } }; diff --git a/target/linux/ipq806x/patches-5.4/850-soc-add-qualcomm-syscon.patch b/target/linux/ipq806x/patches-5.4/850-soc-add-qualcomm-syscon.patch index bd2bc55521f7c6..dfc383684af1d4 100644 --- a/target/linux/ipq806x/patches-5.4/850-soc-add-qualcomm-syscon.patch +++ b/target/linux/ipq806x/patches-5.4/850-soc-add-qualcomm-syscon.patch @@ -8,11 +8,11 @@ Subject: SoC: add qualcomm syscon obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o +obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o obj-$(CONFIG_QCOM_APR) += apr.o - obj-$(CONFIG_QCOM_LLCC) += llcc-slice.o - obj-$(CONFIG_QCOM_SDM845_LLCC) += llcc-sdm845.o + obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o + obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig -@@ -184,6 +184,13 @@ config QCOM_SOCINFO +@@ -176,6 +176,13 @@ config QCOM_SOCINFO Say yes here to support the Qualcomm socinfo driver, providing information about the SoC to user space. diff --git a/target/linux/ipq806x/patches-5.4/900-arm-add-cmdline-override.patch b/target/linux/ipq806x/patches-5.4/900-arm-add-cmdline-override.patch index 87d7015ffc59a5..ecd55ce2f01304 100644 --- a/target/linux/ipq806x/patches-5.4/900-arm-add-cmdline-override.patch +++ b/target/linux/ipq806x/patches-5.4/900-arm-add-cmdline-override.patch @@ -17,7 +17,7 @@ default "" --- a/drivers/of/fdt.c +++ b/drivers/of/fdt.c -@@ -1060,6 +1060,17 @@ int __init early_init_dt_scan_chosen(uns +@@ -1059,6 +1059,17 @@ int __init early_init_dt_scan_chosen(uns if (p != NULL && l > 0) strlcpy(data, p, min(l, COMMAND_LINE_SIZE)); diff --git a/target/linux/ipq806x/patches-5.4/997-device_tree_cmdline.patch b/target/linux/ipq806x/patches-5.4/997-device_tree_cmdline.patch index b6b1b047656a0b..047a098949a88f 100644 --- a/target/linux/ipq806x/patches-5.4/997-device_tree_cmdline.patch +++ b/target/linux/ipq806x/patches-5.4/997-device_tree_cmdline.patch @@ -1,6 +1,6 @@ --- a/drivers/of/fdt.c +++ b/drivers/of/fdt.c -@@ -1059,6 +1059,9 @@ int __init early_init_dt_scan_chosen(uns +@@ -1058,6 +1058,9 @@ int __init early_init_dt_scan_chosen(uns p = of_get_flat_dt_prop(node, "bootargs", &l); if (p != NULL && l > 0) strlcpy(data, p, min(l, COMMAND_LINE_SIZE)); diff --git a/target/linux/ipq806x/patches-5.4/999-03a-qca-nss-ecm-support.patch b/target/linux/ipq806x/patches-5.4/999-03a-qca-nss-ecm-support.patch index 8ebf8fa8e6789a..63a578c0d01708 100644 --- a/target/linux/ipq806x/patches-5.4/999-03a-qca-nss-ecm-support.patch +++ b/target/linux/ipq806x/patches-5.4/999-03a-qca-nss-ecm-support.patch @@ -514,7 +514,7 @@ if (bond_is_lb(bond)) bond_alb_handle_link_change(bond, new_active, BOND_LINK_UP); } else { -@@ -1412,6 +1430,7 @@ int bond_enslave(struct net_device *bond +@@ -1418,6 +1436,7 @@ int bond_enslave(struct net_device *bond const struct net_device_ops *slave_ops = slave_dev->netdev_ops; struct slave *new_slave = NULL, *prev_slave; struct sockaddr_storage ss; @@ -522,7 +522,7 @@ int link_reporting; int res = 0, i; -@@ -1811,6 +1830,13 @@ int bond_enslave(struct net_device *bond +@@ -1817,6 +1836,13 @@ int bond_enslave(struct net_device *bond if (bond_mode_can_use_xmit_hash(bond)) bond_update_slave_arr(bond, NULL); @@ -536,7 +536,7 @@ slave_info(bond_dev, slave_dev, "Enslaving as %s interface with %s link\n", bond_is_active_slave(new_slave) ? "an active" : "a backup", -@@ -1883,6 +1909,14 @@ err_undo_flags: +@@ -1889,6 +1915,14 @@ err_undo_flags: } } @@ -551,7 +551,7 @@ return res; } -@@ -1904,6 +1938,7 @@ static int __bond_release_one(struct net +@@ -1910,6 +1944,7 @@ static int __bond_release_one(struct net struct bonding *bond = netdev_priv(bond_dev); struct slave *slave, *oldcurrent; struct sockaddr_storage ss; @@ -559,7 +559,7 @@ int old_flags = bond_dev->flags; netdev_features_t old_features = bond_dev->features; -@@ -1926,6 +1961,14 @@ static int __bond_release_one(struct net +@@ -1932,6 +1967,14 @@ static int __bond_release_one(struct net bond_set_slave_inactive_flags(slave, BOND_SLAVE_NOTIFY_NOW); @@ -574,7 +574,7 @@ bond_sysfs_slave_del(slave); /* recompute stats just before removing the slave */ -@@ -2231,6 +2274,10 @@ static void bond_miimon_commit(struct bo +@@ -2237,6 +2280,10 @@ static void bond_miimon_commit(struct bo { struct list_head *iter; struct slave *slave, *primary; @@ -585,7 +585,7 @@ bond_for_each_slave(bond, slave, iter) { switch (slave->link_new_state) { -@@ -2274,6 +2321,12 @@ static void bond_miimon_commit(struct bo +@@ -2280,6 +2327,12 @@ static void bond_miimon_commit(struct bo bond_miimon_link_change(bond, slave, BOND_LINK_UP); @@ -598,7 +598,7 @@ if (!bond->curr_active_slave || slave == primary) goto do_failover; -@@ -2315,6 +2368,15 @@ do_failover: +@@ -2321,6 +2374,15 @@ do_failover: } bond_set_carrier(bond); @@ -614,7 +614,7 @@ } /* bond_mii_monitor -@@ -4408,6 +4470,11 @@ static void bond_destructor(struct net_d +@@ -4414,6 +4476,11 @@ static void bond_destructor(struct net_d struct bonding *bond = netdev_priv(bond_dev); if (bond->wq) destroy_workqueue(bond->wq); @@ -626,7 +626,7 @@ } void bond_setup(struct net_device *bond_dev) -@@ -4961,6 +5028,16 @@ int bond_create(struct net *net, const c +@@ -4967,6 +5034,16 @@ int bond_create(struct net *net, const c bond_work_init_all(bond); rtnl_unlock(); @@ -643,7 +643,7 @@ return 0; } -@@ -5056,6 +5133,203 @@ static void __exit bonding_exit(void) +@@ -5062,6 +5139,203 @@ static void __exit bonding_exit(void) #endif } @@ -1283,7 +1283,7 @@ struct fib_table *tb; --- a/net/ipv6/addrconf.c +++ b/net/ipv6/addrconf.c -@@ -7207,3 +7207,35 @@ void addrconf_cleanup(void) +@@ -7203,3 +7203,35 @@ void addrconf_cleanup(void) destroy_workqueue(addrconf_wq); } diff --git a/target/linux/ipq806x/patches-5.4/999-03b-qca-nss-ecm-support.patch b/target/linux/ipq806x/patches-5.4/999-03b-qca-nss-ecm-support.patch index 262c5361b015b2..91c308187b279c 100644 --- a/target/linux/ipq806x/patches-5.4/999-03b-qca-nss-ecm-support.patch +++ b/target/linux/ipq806x/patches-5.4/999-03b-qca-nss-ecm-support.patch @@ -78,7 +78,7 @@ #endif /* _CONNTRACK_PROTO_GRE_H */ --- a/include/net/addrconf.h +++ b/include/net/addrconf.h -@@ -500,4 +500,9 @@ int if6_proc_init(void); +@@ -508,4 +508,9 @@ int if6_proc_init(void); void if6_proc_exit(void); #endif @@ -101,7 +101,7 @@ --- a/net/ipv4/ip_gre.c +++ b/net/ipv4/ip_gre.c -@@ -1302,6 +1302,7 @@ static void ipgre_tap_setup(struct net_d +@@ -1305,6 +1305,7 @@ static void ipgre_tap_setup(struct net_d dev->netdev_ops = &gre_tap_netdev_ops; dev->priv_flags &= ~IFF_TX_SKB_SHARING; dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; diff --git a/target/linux/ipq807x/patches-5.10/010-v5.11-PCI-dwc-Drop-the-.set_num_vectors-host-op.patch b/target/linux/ipq807x/patches-5.10/010-v5.11-PCI-dwc-Drop-the-.set_num_vectors-host-op.patch index 3320ed3a856ea4..18c933c40f9211 100644 --- a/target/linux/ipq807x/patches-5.10/010-v5.11-PCI-dwc-Drop-the-.set_num_vectors-host-op.patch +++ b/target/linux/ipq807x/patches-5.10/010-v5.11-PCI-dwc-Drop-the-.set_num_vectors-host-op.patch @@ -90,7 +90,7 @@ Cc: linux-tegra@vger.kernel.org --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c -@@ -988,11 +988,6 @@ static int tegra_pcie_dw_link_up(struct +@@ -996,11 +996,6 @@ static int tegra_pcie_dw_link_up(struct return !!(val & PCI_EXP_LNKSTA_DLLLA); } @@ -102,7 +102,7 @@ Cc: linux-tegra@vger.kernel.org static int tegra_pcie_dw_start_link(struct dw_pcie *pci) { struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); -@@ -1017,7 +1012,6 @@ static const struct dw_pcie_ops tegra_dw +@@ -1025,7 +1020,6 @@ static const struct dw_pcie_ops tegra_dw static struct dw_pcie_host_ops tegra_pcie_dw_host_ops = { .host_init = tegra_pcie_dw_host_init, @@ -110,7 +110,7 @@ Cc: linux-tegra@vger.kernel.org }; static void tegra_pcie_disable_phy(struct tegra_pcie_dw *pcie) -@@ -2002,6 +1996,7 @@ static int tegra_pcie_dw_probe(struct pl +@@ -2010,6 +2004,7 @@ static int tegra_pcie_dw_probe(struct pl pci->n_fts[1] = FTS_VAL; pp = &pci->pp; diff --git a/target/linux/ipq807x/patches-5.10/011-v5.11-PCI-dwc-Move-MSI-interrupt-setup-into-DWC-common-cod.patch b/target/linux/ipq807x/patches-5.10/011-v5.11-PCI-dwc-Move-MSI-interrupt-setup-into-DWC-common-cod.patch index a900a6f26e24c0..d4d31eb0f54f99 100644 --- a/target/linux/ipq807x/patches-5.10/011-v5.11-PCI-dwc-Move-MSI-interrupt-setup-into-DWC-common-cod.patch +++ b/target/linux/ipq807x/patches-5.10/011-v5.11-PCI-dwc-Move-MSI-interrupt-setup-into-DWC-common-cod.patch @@ -256,7 +256,7 @@ Cc: linux-tegra@vger.kernel.org if (ret) { --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c -@@ -1552,14 +1552,6 @@ static int tegra_pcie_config_rp(struct t +@@ -1560,14 +1560,6 @@ static int tegra_pcie_config_rp(struct t char *name; int ret; diff --git a/target/linux/ipq807x/patches-5.10/013-v5.11-PCI-dwc-Move-link-handling-into-common-code.patch b/target/linux/ipq807x/patches-5.10/013-v5.11-PCI-dwc-Move-link-handling-into-common-code.patch index b2d39cab99afde..383820e23d2185 100644 --- a/target/linux/ipq807x/patches-5.10/013-v5.11-PCI-dwc-Move-link-handling-into-common-code.patch +++ b/target/linux/ipq807x/patches-5.10/013-v5.11-PCI-dwc-Move-link-handling-into-common-code.patch @@ -552,7 +552,7 @@ Cc: linux-tegra@vger.kernel.org static int qcom_pcie_probe(struct platform_device *pdev) --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c -@@ -1547,7 +1547,6 @@ static int tegra_pcie_deinit_controller( +@@ -1555,7 +1555,6 @@ static int tegra_pcie_deinit_controller( static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) { diff --git a/target/linux/ipq807x/patches-5.10/014-v5.11-PCI-dwc-Move-dw_pcie_msi_init-into-core.patch b/target/linux/ipq807x/patches-5.10/014-v5.11-PCI-dwc-Move-dw_pcie_msi_init-into-core.patch index f8218212ceaaa6..425f2ed80d4ccd 100644 --- a/target/linux/ipq807x/patches-5.10/014-v5.11-PCI-dwc-Move-dw_pcie_msi_init-into-core.patch +++ b/target/linux/ipq807x/patches-5.10/014-v5.11-PCI-dwc-Move-dw_pcie_msi_init-into-core.patch @@ -251,7 +251,7 @@ Cc: linux-tegra@vger.kernel.org static int spear13xx_pcie_link_up(struct dw_pcie *pci) --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c -@@ -763,8 +763,6 @@ static void tegra_pcie_enable_msi_interr +@@ -767,8 +767,6 @@ static void tegra_pcie_enable_msi_interr struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); u32 val; diff --git a/target/linux/ipq807x/patches-5.10/109-clk-qcom-Add-WCSSAON-reset.patch b/target/linux/ipq807x/patches-5.10/109-clk-qcom-Add-WCSSAON-reset.patch index 9431dbd21c38a3..b2a95f91d49361 100644 --- a/target/linux/ipq807x/patches-5.10/109-clk-qcom-Add-WCSSAON-reset.patch +++ b/target/linux/ipq807x/patches-5.10/109-clk-qcom-Add-WCSSAON-reset.patch @@ -15,7 +15,7 @@ Acked-by: Stephen Boyd --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -4790,6 +4790,7 @@ static const struct qcom_reset_map gcc_i +@@ -4784,6 +4784,7 @@ static const struct qcom_reset_map gcc_i [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 }, [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 }, [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, diff --git a/target/linux/ipq807x/patches-5.10/116-PCI-dwc-tegra-move-GEN3_RELATED-DBI-register-to-comm.patch b/target/linux/ipq807x/patches-5.10/116-PCI-dwc-tegra-move-GEN3_RELATED-DBI-register-to-comm.patch index fe76db641f2c18..3a6f10e2187464 100644 --- a/target/linux/ipq807x/patches-5.10/116-PCI-dwc-tegra-move-GEN3_RELATED-DBI-register-to-comm.patch +++ b/target/linux/ipq807x/patches-5.10/116-PCI-dwc-tegra-move-GEN3_RELATED-DBI-register-to-comm.patch @@ -29,7 +29,7 @@ Signed-off-by: Baruch Siach --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c -@@ -193,12 +193,6 @@ +@@ -194,12 +194,6 @@ #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK GENMASK(23, 8) #define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK GENMASK(3, 0) diff --git a/target/linux/ipq807x/patches-5.10/125-ipq8074-gcc-Added-support-for-NSS-clocks.patch b/target/linux/ipq807x/patches-5.10/125-ipq8074-gcc-Added-support-for-NSS-clocks.patch index ebdf5f6740aeab..eae85eb55d9361 100644 --- a/target/linux/ipq807x/patches-5.10/125-ipq8074-gcc-Added-support-for-NSS-clocks.patch +++ b/target/linux/ipq807x/patches-5.10/125-ipq8074-gcc-Added-support-for-NSS-clocks.patch @@ -34,7 +34,7 @@ Signed-off-by: Rajkumar Ayyasamy }; --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -3183,6 +3183,24 @@ static struct clk_branch gcc_nss_ptp_ref +@@ -3177,6 +3177,24 @@ static struct clk_branch gcc_nss_ptp_ref }, }; @@ -59,7 +59,7 @@ Signed-off-by: Rajkumar Ayyasamy static struct clk_branch gcc_nssnoc_ce_apb_clk = { .halt_reg = 0x6830c, .clkr = { -@@ -4608,6 +4626,7 @@ static struct clk_regmap *gcc_ipq8074_cl +@@ -4602,6 +4620,7 @@ static struct clk_regmap *gcc_ipq8074_cl [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr, [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr, [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr, diff --git a/target/linux/ipq807x/patches-5.10/126-clk-ipq8074-Support-added-for-necessary-clocks-and-r.patch b/target/linux/ipq807x/patches-5.10/126-clk-ipq8074-Support-added-for-necessary-clocks-and-r.patch index fdd68d06519f5f..5f7238daed570c 100644 --- a/target/linux/ipq807x/patches-5.10/126-clk-ipq8074-Support-added-for-necessary-clocks-and-r.patch +++ b/target/linux/ipq807x/patches-5.10/126-clk-ipq8074-Support-added-for-necessary-clocks-and-r.patch @@ -37,7 +37,7 @@ Signed-off-by: Rajkumar Ayyasamy static struct clk_alpha_pll gpll0_main = { .offset = 0x21000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], -@@ -963,6 +979,12 @@ static const struct freq_tbl ftbl_pcie_a +@@ -957,6 +973,12 @@ static const struct freq_tbl ftbl_pcie_a { } }; @@ -50,7 +50,7 @@ Signed-off-by: Rajkumar Ayyasamy static struct clk_rcg2 pcie0_axi_clk_src = { .cmd_rcgr = 0x75054, .freq_tbl = ftbl_pcie_axi_clk_src, -@@ -2022,6 +2044,78 @@ static struct clk_rcg2 gp3_clk_src = { +@@ -2016,6 +2038,78 @@ static struct clk_rcg2 gp3_clk_src = { }, }; @@ -129,7 +129,7 @@ Signed-off-by: Rajkumar Ayyasamy static struct clk_branch gcc_blsp1_ahb_clk = { .halt_reg = 0x01008, .clkr = { -@@ -4353,13 +4447,7 @@ static struct clk_branch gcc_gp3_clk = { +@@ -4347,13 +4441,7 @@ static struct clk_branch gcc_gp3_clk = { }, }; @@ -144,7 +144,7 @@ Signed-off-by: Rajkumar Ayyasamy .cmd_rcgr = 0x75070, .freq_tbl = ftbl_pcie_rchng_clk_src, .hid_width = 5, -@@ -4435,6 +4523,114 @@ static const struct alpha_pll_config nss +@@ -4429,6 +4517,114 @@ static const struct alpha_pll_config nss .alpha_en_mask = BIT(24), }; @@ -259,7 +259,7 @@ Signed-off-by: Rajkumar Ayyasamy static struct clk_hw *gcc_ipq8074_hws[] = { &gpll0_out_main_div2.hw, &gpll6_out_main_div2.hw, -@@ -4443,6 +4639,7 @@ static struct clk_hw *gcc_ipq8074_hws[] +@@ -4437,6 +4633,7 @@ static struct clk_hw *gcc_ipq8074_hws[] &gcc_xo_div4_clk_src.hw, &nss_noc_clk_src.hw, &nss_ppe_cdiv_clk_src.hw, @@ -267,7 +267,7 @@ Signed-off-by: Rajkumar Ayyasamy }; static struct clk_regmap *gcc_ipq8074_clks[] = { -@@ -4674,6 +4871,15 @@ static struct clk_regmap *gcc_ipq8074_cl +@@ -4668,6 +4865,15 @@ static struct clk_regmap *gcc_ipq8074_cl [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr, [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr, [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, @@ -283,7 +283,7 @@ Signed-off-by: Rajkumar Ayyasamy }; static const struct qcom_reset_map gcc_ipq8074_resets[] = { -@@ -4810,6 +5016,20 @@ static const struct qcom_reset_map gcc_i +@@ -4804,6 +5010,20 @@ static const struct qcom_reset_map gcc_i [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 }, [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, [GCC_WCSSAON_RESET] = { 0x59010, 0 }, diff --git a/target/linux/ipq807x/patches-5.10/127-clk-qcom-ipq8074-Fix-gcc_snoc_bus_timeout_ahb_clk-of.patch b/target/linux/ipq807x/patches-5.10/127-clk-qcom-ipq8074-Fix-gcc_snoc_bus_timeout_ahb_clk-of.patch index b45580f7a3e874..2bf82f5da964ad 100644 --- a/target/linux/ipq807x/patches-5.10/127-clk-qcom-ipq8074-Fix-gcc_snoc_bus_timeout_ahb_clk-of.patch +++ b/target/linux/ipq807x/patches-5.10/127-clk-qcom-ipq8074-Fix-gcc_snoc_bus_timeout_ahb_clk-of.patch @@ -16,7 +16,7 @@ Signed-off-by: Selvam Sathappan Periakaruppan --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -4524,10 +4524,10 @@ static const struct alpha_pll_config nss +@@ -4518,10 +4518,10 @@ static const struct alpha_pll_config nss }; static struct clk_branch gcc_snoc_bus_timeout2_ahb_clk = { @@ -29,7 +29,7 @@ Signed-off-by: Selvam Sathappan Periakaruppan .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_snoc_bus_timeout2_ahb_clk", -@@ -4542,10 +4542,10 @@ static struct clk_branch gcc_snoc_bus_ti +@@ -4536,10 +4536,10 @@ static struct clk_branch gcc_snoc_bus_ti }; static struct clk_branch gcc_snoc_bus_timeout3_ahb_clk = { diff --git a/target/linux/ipq807x/patches-5.10/139-ipq8074-clk-apss-Added-APSS-clock-driver.patch b/target/linux/ipq807x/patches-5.10/139-ipq8074-clk-apss-Added-APSS-clock-driver.patch index 287c4cf57897e3..71c3124b91a2c9 100644 --- a/target/linux/ipq807x/patches-5.10/139-ipq8074-clk-apss-Added-APSS-clock-driver.patch +++ b/target/linux/ipq807x/patches-5.10/139-ipq8074-clk-apss-Added-APSS-clock-driver.patch @@ -21,7 +21,7 @@ Change-Id: I17ecad1f1731c88d8d91485d5d5f8a38b76f7104 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig -@@ -155,6 +155,13 @@ config IPQ_GCC_8074 +@@ -156,6 +156,13 @@ config IPQ_GCC_8074 i2c, USB, SD/eMMC, etc. Select this for the root clock of ipq8074. diff --git a/target/linux/ipq807x/patches-5.10/145-clk-qcom-ipq8074-disable-SW_COLLAPSE-for-USB-GDSCR-s.patch b/target/linux/ipq807x/patches-5.10/145-clk-qcom-ipq8074-disable-SW_COLLAPSE-for-USB-GDSCR-s.patch index 2e6d639a125264..7d0f822936c78b 100644 --- a/target/linux/ipq807x/patches-5.10/145-clk-qcom-ipq8074-disable-SW_COLLAPSE-for-USB-GDSCR-s.patch +++ b/target/linux/ipq807x/patches-5.10/145-clk-qcom-ipq8074-disable-SW_COLLAPSE-for-USB-GDSCR-s.patch @@ -15,7 +15,7 @@ Change-Id: I17beca334be79d738a35587860847aa0b1f96fa9 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -5067,6 +5067,11 @@ static int gcc_ipq8074_probe(struct plat +@@ -5061,6 +5061,11 @@ static int gcc_ipq8074_probe(struct plat /* SW Workaround for UBI32 Huayra PLL */ regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26)); diff --git a/target/linux/ipq807x/patches-5.10/146-clk-qcom-ipq8074-SW-workaround-for-UBI-PLL-lock.patch b/target/linux/ipq807x/patches-5.10/146-clk-qcom-ipq8074-SW-workaround-for-UBI-PLL-lock.patch index b7dc8b4727a455..1a929925e027aa 100644 --- a/target/linux/ipq807x/patches-5.10/146-clk-qcom-ipq8074-SW-workaround-for-UBI-PLL-lock.patch +++ b/target/linux/ipq807x/patches-5.10/146-clk-qcom-ipq8074-SW-workaround-for-UBI-PLL-lock.patch @@ -34,7 +34,7 @@ Signed-off-by: Abhishek Sahu --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -5072,6 +5072,9 @@ static int gcc_ipq8074_probe(struct plat +@@ -5066,6 +5066,9 @@ static int gcc_ipq8074_probe(struct plat /* Disable SW_COLLAPSE for USB1 GDSCR */ regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0); diff --git a/target/linux/ipq807x/patches-5.10/148-clk-ipq8074-fix-gcc_blsp1_ahb_clk-properties.patch b/target/linux/ipq807x/patches-5.10/148-clk-ipq8074-fix-gcc_blsp1_ahb_clk-properties.patch index 2c8887e332e62b..54999753f5ed74 100644 --- a/target/linux/ipq807x/patches-5.10/148-clk-ipq8074-fix-gcc_blsp1_ahb_clk-properties.patch +++ b/target/linux/ipq807x/patches-5.10/148-clk-ipq8074-fix-gcc_blsp1_ahb_clk-properties.patch @@ -26,7 +26,7 @@ Change-Id: I505cb560b31ad27a02c165fbe13bb33a2fc7d230 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -2118,9 +2118,10 @@ struct clk_rcg2 adss_pwm_clk_src = { +@@ -2112,9 +2112,10 @@ struct clk_rcg2 adss_pwm_clk_src = { static struct clk_branch gcc_blsp1_ahb_clk = { .halt_reg = 0x01008, diff --git a/target/linux/ipq807x/patches-5.10/600-qca-nss-ecm-support-CORE.patch b/target/linux/ipq807x/patches-5.10/600-qca-nss-ecm-support-CORE.patch index ebd1658f43f0a2..31ead21f111f88 100644 --- a/target/linux/ipq807x/patches-5.10/600-qca-nss-ecm-support-CORE.patch +++ b/target/linux/ipq807x/patches-5.10/600-qca-nss-ecm-support-CORE.patch @@ -78,7 +78,7 @@ #endif --- a/include/linux/if_vlan.h +++ b/include/linux/if_vlan.h -@@ -222,7 +222,28 @@ extern void vlan_vids_del_by_dev(struct +@@ -230,7 +230,28 @@ extern void vlan_vids_del_by_dev(struct extern bool vlan_uses_dev(const struct net_device *dev); @@ -109,7 +109,7 @@ __be16 vlan_proto, u16 vlan_id) --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h -@@ -2787,6 +2787,10 @@ enum netdev_cmd { +@@ -2786,6 +2786,10 @@ enum netdev_cmd { NETDEV_CVLAN_FILTER_DROP_INFO, NETDEV_SVLAN_FILTER_PUSH_INFO, NETDEV_SVLAN_FILTER_DROP_INFO, @@ -136,7 +136,7 @@ const struct dst_entry *dst = skb_dst(skb); --- a/include/net/neighbour.h +++ b/include/net/neighbour.h -@@ -574,4 +574,15 @@ static inline void neigh_update_is_route +@@ -567,4 +567,15 @@ static inline void neigh_update_is_route *notify = 1; } } @@ -401,7 +401,7 @@ /* * Determine initial path cost based on speed. * using recommendations from 802.1d standard -@@ -711,6 +717,8 @@ int br_add_if(struct net_bridge *br, str +@@ -712,6 +718,8 @@ int br_add_if(struct net_bridge *br, str kobject_uevent(&p->kobj, KOBJ_ADD); @@ -410,7 +410,7 @@ return 0; err7: -@@ -747,6 +755,8 @@ int br_del_if(struct net_bridge *br, str +@@ -748,6 +756,8 @@ int br_del_if(struct net_bridge *br, str if (!p || p->br != br) return -EINVAL; @@ -419,7 +419,7 @@ /* Since more than one interface can be attached to a bridge, * there still maybe an alternate path for netconsole to use; * therefore there is no reason for a NETDEV_RELEASE event. -@@ -812,3 +822,74 @@ bool br_port_flag_is_set(const struct ne +@@ -813,3 +823,74 @@ bool br_port_flag_is_set(const struct ne return p->flags & flag; } EXPORT_SYMBOL_GPL(br_port_flag_is_set); @@ -508,7 +508,7 @@ #endif --- a/net/core/neighbour.c +++ b/net/core/neighbour.c -@@ -1236,7 +1236,21 @@ static void neigh_update_hhs(struct neig +@@ -1209,7 +1209,21 @@ static void neigh_update_hhs(struct neig } } @@ -530,7 +530,7 @@ /* Generic update routine. -- lladdr is new lladdr or NULL, if it is not supplied. -@@ -1267,6 +1281,7 @@ static int __neigh_update(struct neighbo +@@ -1240,6 +1254,7 @@ static int __neigh_update(struct neighbo int notify = 0; struct net_device *dev; int update_isrouter = 0; @@ -538,7 +538,7 @@ trace_neigh_update(neigh, lladdr, new, flags, nlmsg_pid); -@@ -1281,6 +1296,8 @@ static int __neigh_update(struct neighbo +@@ -1254,6 +1269,8 @@ static int __neigh_update(struct neighbo new = old; goto out; } @@ -547,7 +547,7 @@ if (!(flags & NEIGH_UPDATE_F_ADMIN) && (old & (NUD_NOARP | NUD_PERMANENT))) goto out; -@@ -1318,6 +1335,11 @@ static int __neigh_update(struct neighbo +@@ -1291,6 +1308,11 @@ static int __neigh_update(struct neighbo - compare new & old - if they are different, check override flag */ @@ -559,7 +559,7 @@ if ((old & NUD_VALID) && !memcmp(lladdr, neigh->ha, dev->addr_len)) lladdr = neigh->ha; -@@ -1440,8 +1462,11 @@ out: +@@ -1413,8 +1435,11 @@ out: if (((new ^ old) & NUD_PERMANENT) || ext_learn_change) neigh_update_gc_list(neigh); @@ -594,7 +594,7 @@ return 0; out_remove_new_fa: -@@ -1724,6 +1730,9 @@ int fib_table_delete(struct net *net, st +@@ -1725,6 +1731,9 @@ int fib_table_delete(struct net *net, st if (fa_to_delete->fa_state & FA_S_ACCESSED) rt_cache_flush(cfg->fc_nlinfo.nl_net); @@ -604,7 +604,7 @@ fib_release_info(fa_to_delete->fa_info); alias_free_mem_rcu(fa_to_delete); return 0; -@@ -2360,6 +2369,20 @@ void __init fib_trie_init(void) +@@ -2365,6 +2374,20 @@ void __init fib_trie_init(void) 0, SLAB_PANIC, NULL); } @@ -627,7 +627,7 @@ struct fib_table *tb; --- a/include/net/addrconf.h +++ b/include/net/addrconf.h -@@ -506,4 +506,9 @@ int if6_proc_init(void); +@@ -514,4 +514,9 @@ int if6_proc_init(void); void if6_proc_exit(void); #endif @@ -639,7 +639,7 @@ #endif --- a/net/ipv6/addrconf.c +++ b/net/ipv6/addrconf.c -@@ -7269,3 +7269,35 @@ void addrconf_cleanup(void) +@@ -7283,3 +7283,35 @@ void addrconf_cleanup(void) destroy_workqueue(addrconf_wq); } @@ -677,7 +677,7 @@ + --- a/net/ipv6/ndisc.c +++ b/net/ipv6/ndisc.c -@@ -649,6 +649,7 @@ void ndisc_send_ns(struct net_device *de +@@ -650,6 +650,7 @@ void ndisc_send_ns(struct net_device *de ndisc_send_skb(skb, daddr, saddr); } diff --git a/target/linux/ipq807x/patches-5.10/602-qca-add-pppoe-offload-support.patch b/target/linux/ipq807x/patches-5.10/602-qca-add-pppoe-offload-support.patch index 9e62020ad66155..7582d2c7ca7c95 100644 --- a/target/linux/ipq807x/patches-5.10/602-qca-add-pppoe-offload-support.patch +++ b/target/linux/ipq807x/patches-5.10/602-qca-add-pppoe-offload-support.patch @@ -466,7 +466,7 @@ #endif /* !(__LINUX_IF_PPPOX_H) */ --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h -@@ -1651,6 +1651,24 @@ enum netdev_priv_flags { +@@ -1654,6 +1654,24 @@ enum netdev_priv_flags { IFF_NO_IP_ALIGN = 1<<31, }; @@ -491,7 +491,7 @@ #define IFF_802_1Q_VLAN IFF_802_1Q_VLAN #define IFF_EBRIDGE IFF_EBRIDGE #define IFF_BONDING IFF_BONDING -@@ -2031,6 +2049,7 @@ struct net_device { +@@ -2033,6 +2051,7 @@ struct net_device { unsigned int flags; unsigned int priv_flags; diff --git a/target/linux/ipq807x/patches-5.10/606-qca-nss-ecm-bonding-add-bond_get_id.patch b/target/linux/ipq807x/patches-5.10/606-qca-nss-ecm-bonding-add-bond_get_id.patch index 1d9e21abeaecf4..7c9ab09ec25273 100644 --- a/target/linux/ipq807x/patches-5.10/606-qca-nss-ecm-bonding-add-bond_get_id.patch +++ b/target/linux/ipq807x/patches-5.10/606-qca-nss-ecm-bonding-add-bond_get_id.patch @@ -2,16 +2,16 @@ +++ b/drivers/net/bonding/bond_main.c @@ -247,6 +247,7 @@ static const struct flow_dissector_key f }; - + static struct flow_dissector flow_keys_bonding __read_mostly; +static unsigned long bond_id_mask = 0xFFFFFFF0; - + /*-------------------------- Forward declarations ---------------------------*/ - + @@ -301,6 +302,20 @@ netdev_tx_t bond_dev_queue_xmit(struct b return dev_queue_xmit(skb); } - + +int bond_get_id(struct net_device *bond_dev) +{ + struct bonding *bond; @@ -27,9 +27,9 @@ +EXPORT_SYMBOL(bond_get_id); + /*---------------------------------- VLAN -----------------------------------*/ - + /* In the following 2 functions, bond_vlan_rx_add_vid and bond_vlan_rx_kill_vid, -@@ -4822,6 +4837,9 @@ static void bond_destructor(struct net_d +@@ -4876,6 +4891,9 @@ static void bond_destructor(struct net_d struct bonding *bond = netdev_priv(bond_dev); if (bond->wq) destroy_workqueue(bond->wq); @@ -37,31 +37,12 @@ + if (bond->id != (~0U)) + clear_bit(bond->id, &bond_id_mask); } - + void bond_setup(struct net_device *bond_dev) -@@ -4936,7 +4954,7 @@ static int bond_check_params(struct bond - int bond_mode = BOND_MODE_ROUNDROBIN; - int xmit_hashtype = BOND_XMIT_POLICY_LAYER2; - int lacp_fast = 0; -- int tlb_dynamic_lb; -+ int tlb_dynamic_lb; - - /* Convert string parameters. */ - if (mode) { -@@ -5275,7 +5293,7 @@ static int bond_check_params(struct bond - params->peer_notif_delay = 0; - params->use_carrier = use_carrier; - params->lacp_fast = lacp_fast; -- params->primary[0] = 0; -+ params->primary[0] = 0; - params->primary_reselect = primary_reselect_value; - params->fail_over_mac = fail_over_mac_value; - params->tx_queues = tx_queues; -@@ -5390,7 +5408,15 @@ int bond_create(struct net *net, const c +@@ -5448,6 +5466,14 @@ int bond_create(struct net *net, const c bond_work_init_all(bond); - + rtnl_unlock(); -- return 0; + + bond = netdev_priv(bond_dev); + bond->id = ~0U; @@ -70,21 +51,20 @@ + set_bit(bond->id, &bond_id_mask); + } + -+ return 0; + return 0; } - - static int __net_init bond_net_init(struct net *net) + --- a/include/net/bonding.h +++ b/include/net/bonding.h -@@ -256,6 +256,7 @@ struct bonding { +@@ -257,6 +257,7 @@ struct bonding { /* protecting ipsec_list */ spinlock_t ipsec_lock; #endif /* CONFIG_XFRM_OFFLOAD */ + u32 id; }; - + #define bond_slave_get_rcu(dev) \ -@@ -629,6 +629,7 @@ struct bond_net { +@@ -629,6 +630,7 @@ struct bond_net { int bond_arp_rcv(const struct sk_buff *skb, struct bonding *bond, struct slave *slave); netdev_tx_t bond_dev_queue_xmit(struct bonding *bond, struct sk_buff *skb, struct net_device *slave_dev); diff --git a/target/linux/ipq807x/patches-5.10/607-qca-nss-ecm-Add-bridge-join-and-leave-netdev-cmds.patch b/target/linux/ipq807x/patches-5.10/607-qca-nss-ecm-Add-bridge-join-and-leave-netdev-cmds.patch index e2a1285f5f2d24..69e5535283f02f 100644 --- a/target/linux/ipq807x/patches-5.10/607-qca-nss-ecm-Add-bridge-join-and-leave-netdev-cmds.patch +++ b/target/linux/ipq807x/patches-5.10/607-qca-nss-ecm-Add-bridge-join-and-leave-netdev-cmds.patch @@ -1,6 +1,6 @@ --- a/net/core/dev.c +++ b/net/core/dev.c -@@ -1685,7 +1685,7 @@ const char *netdev_cmd_to_name(enum netd +@@ -1802,7 +1802,7 @@ const char *netdev_cmd_to_name(enum netd N(UDP_TUNNEL_DROP_INFO) N(CHANGE_TX_QUEUE_LEN) N(CVLAN_FILTER_PUSH_INFO) N(CVLAN_FILTER_DROP_INFO) N(SVLAN_FILTER_PUSH_INFO) N(SVLAN_FILTER_DROP_INFO) diff --git a/target/linux/ipq807x/patches-5.10/990-clk-qcom-fix-wrong-RCG-clock-rate-for-high-parent-fr.patch b/target/linux/ipq807x/patches-5.10/990-clk-qcom-fix-wrong-RCG-clock-rate-for-high-parent-fr.patch deleted file mode 100644 index eb473410c7e9db..00000000000000 --- a/target/linux/ipq807x/patches-5.10/990-clk-qcom-fix-wrong-RCG-clock-rate-for-high-parent-fr.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 474740fac667ccf7a6b3c748d851e5ed364d59eb Mon Sep 17 00:00:00 2001 -From: Praveenkumar I -Date: Mon, 4 Sep 2017 15:00:10 +0530 -Subject: [PATCH 1/3] clk: qcom: fix wrong RCG clock rate for high parent freq - -If the parent clock rate is greater than unsigned long max -divided by 2 then the integer overflow is happening while -calculating the clock rate. Since RCG2 uses half integer -dividers, the clock rate is first being multiplied by 2 -followed by division and this multiplication leads to -overflow. - -Change-Id: I4e4f41b4a539446b962eb684761a3aad6f8a8977 -Signed-off-by: Abhishek Sahu -(cherry picked from commit 9cfedaf465eb18ef31e4d677cba5f3147fe6d430) -Signed-off-by: Praveenkumar I - -Change-Id: I69b78616f468bb7a9647c7994a8579b97c376d4e ---- - drivers/clk/qcom/clk-rcg2.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - ---- a/drivers/clk/qcom/clk-rcg2.c -+++ b/drivers/clk/qcom/clk-rcg2.c -@@ -145,18 +145,18 @@ static int clk_rcg2_set_parent(struct cl - * hid_div n - */ - static unsigned long --calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div) -+calc_rate(unsigned long parent_rate, u32 m, u32 n, u32 mode, u32 hid_div) - { -+ u64 rate = parent_rate; -+ - if (hid_div) { - rate *= 2; -- rate /= hid_div + 1; -+ do_div(rate, hid_div + 1); - } - - if (mode) { -- u64 tmp = rate; -- tmp *= m; -- do_div(tmp, n); -- rate = tmp; -+ rate *= m; -+ do_div(rate, n); - } - - return rate; diff --git a/target/linux/ipq807x/patches-5.10/991-clk-qcom-add-support-for-hw-controlled-RCG.patch b/target/linux/ipq807x/patches-5.10/991-clk-qcom-add-support-for-hw-controlled-RCG.patch index b7f61560807a54..6512b6f462faff 100644 --- a/target/linux/ipq807x/patches-5.10/991-clk-qcom-add-support-for-hw-controlled-RCG.patch +++ b/target/linux/ipq807x/patches-5.10/991-clk-qcom-add-support-for-hw-controlled-RCG.patch @@ -86,7 +86,7 @@ Change-Id: Ifb4175b02d89542baa1b758107c2ce86f7bf8599 } /* -@@ -311,12 +319,19 @@ static int __clk_rcg2_configure(struct c +@@ -305,12 +313,19 @@ static int __clk_rcg2_configure(struct c static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) { int ret; @@ -107,7 +107,7 @@ Change-Id: Ifb4175b02d89542baa1b758107c2ce86f7bf8599 } static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate, -@@ -796,7 +811,7 @@ static int clk_gfx3d_set_rate_and_parent +@@ -790,7 +805,7 @@ static int clk_gfx3d_set_rate_and_parent if (ret) return ret; @@ -116,7 +116,7 @@ Change-Id: Ifb4175b02d89542baa1b758107c2ce86f7bf8599 } static int clk_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate, -@@ -908,7 +923,7 @@ static int clk_rcg2_shared_enable(struct +@@ -902,7 +917,7 @@ static int clk_rcg2_shared_enable(struct if (ret) return ret; @@ -125,7 +125,7 @@ Change-Id: Ifb4175b02d89542baa1b758107c2ce86f7bf8599 if (ret) return ret; -@@ -939,7 +954,7 @@ static void clk_rcg2_shared_disable(stru +@@ -933,7 +948,7 @@ static void clk_rcg2_shared_disable(stru regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, rcg->safe_src_index << CFG_SRC_SEL_SHIFT); diff --git a/target/linux/ipq807x/patches-5.10/992-clk-qcom-ipq8074-add-hw-controlled-flag.patch b/target/linux/ipq807x/patches-5.10/992-clk-qcom-ipq8074-add-hw-controlled-flag.patch index 3ea835c8ce9872..2b11b7c01308b7 100644 --- a/target/linux/ipq807x/patches-5.10/992-clk-qcom-ipq8074-add-hw-controlled-flag.patch +++ b/target/linux/ipq807x/patches-5.10/992-clk-qcom-ipq8074-add-hw-controlled-flag.patch @@ -20,7 +20,7 @@ Change-Id: Ic5da1551bf46921890955312026b9175a42fe14e --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -643,6 +643,7 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_s +@@ -637,6 +637,7 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_s .freq_tbl = ftbl_pcnoc_bfdcd_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, @@ -28,7 +28,7 @@ Change-Id: Ic5da1551bf46921890955312026b9175a42fe14e .clkr.hw.init = &(struct clk_init_data){ .name = "pcnoc_bfdcd_clk_src", .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, -@@ -1317,6 +1318,7 @@ static struct clk_rcg2 system_noc_bfdcd_ +@@ -1311,6 +1312,7 @@ static struct clk_rcg2 system_noc_bfdcd_ .freq_tbl = ftbl_system_noc_bfdcd_clk_src, .hid_width = 5, .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map, diff --git a/target/linux/ipq807x/patches-5.15/0105-PCI-dwc-tegra-move-GEN3_RELATED-DBI-register-to-comm.patch b/target/linux/ipq807x/patches-5.15/0105-PCI-dwc-tegra-move-GEN3_RELATED-DBI-register-to-comm.patch index 0c606454984c5a..f81de791e2ee0b 100644 --- a/target/linux/ipq807x/patches-5.15/0105-PCI-dwc-tegra-move-GEN3_RELATED-DBI-register-to-comm.patch +++ b/target/linux/ipq807x/patches-5.15/0105-PCI-dwc-tegra-move-GEN3_RELATED-DBI-register-to-comm.patch @@ -30,7 +30,7 @@ Signed-off-by: Baruch Siach --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c -@@ -193,12 +193,6 @@ +@@ -194,12 +194,6 @@ #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK GENMASK(23, 8) #define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK GENMASK(3, 0) diff --git a/target/linux/ipq807x/patches-5.15/0117-clk-qcom-Add-WCSSAON-reset.patch b/target/linux/ipq807x/patches-5.15/0117-clk-qcom-Add-WCSSAON-reset.patch index 200e410ed9133c..00aeecd5fa96d9 100644 --- a/target/linux/ipq807x/patches-5.15/0117-clk-qcom-Add-WCSSAON-reset.patch +++ b/target/linux/ipq807x/patches-5.15/0117-clk-qcom-Add-WCSSAON-reset.patch @@ -15,7 +15,7 @@ Acked-by: Stephen Boyd --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -4790,6 +4790,7 @@ static const struct qcom_reset_map gcc_i +@@ -4784,6 +4784,7 @@ static const struct qcom_reset_map gcc_i [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 }, [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 }, [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, diff --git a/target/linux/ipq807x/patches-5.15/0132-clk-qcom-Add-IPQ8074-APSS-clock-controller.patch b/target/linux/ipq807x/patches-5.15/0132-clk-qcom-Add-IPQ8074-APSS-clock-controller.patch index a9ca767ccc40b3..519add036b9014 100644 --- a/target/linux/ipq807x/patches-5.15/0132-clk-qcom-Add-IPQ8074-APSS-clock-controller.patch +++ b/target/linux/ipq807x/patches-5.15/0132-clk-qcom-Add-IPQ8074-APSS-clock-controller.patch @@ -18,7 +18,7 @@ Signed-off-by: Robert Marko --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig -@@ -134,6 +134,16 @@ config IPQ_APSS_6018 +@@ -135,6 +135,16 @@ config IPQ_APSS_6018 Say Y if you want to support CPU frequency scaling on ipq based devices. diff --git a/target/linux/ipq807x/patches-5.15/0139-clk-qcom-ipq8074-add-missing-networking-resets.patch b/target/linux/ipq807x/patches-5.15/0139-clk-qcom-ipq8074-add-missing-networking-resets.patch index 1f0320a86927b3..c3939be263cbc2 100644 --- a/target/linux/ipq807x/patches-5.15/0139-clk-qcom-ipq8074-add-missing-networking-resets.patch +++ b/target/linux/ipq807x/patches-5.15/0139-clk-qcom-ipq8074-add-missing-networking-resets.patch @@ -17,7 +17,7 @@ Signed-off-by: Robert Marko --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -4791,6 +4791,20 @@ static const struct qcom_reset_map gcc_i +@@ -4785,6 +4785,20 @@ static const struct qcom_reset_map gcc_i [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 }, [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, [GCC_WCSSAON_RESET] = { 0x59010, 0 }, diff --git a/target/linux/ipq807x/patches-5.15/0141-clk-qcom-ipq8074-disable-USB-GDSC-s-SW_COLLAPSE.patch b/target/linux/ipq807x/patches-5.15/0141-clk-qcom-ipq8074-disable-USB-GDSC-s-SW_COLLAPSE.patch index 224531a8b99509..e2bd2a8fb7a285 100644 --- a/target/linux/ipq807x/patches-5.15/0141-clk-qcom-ipq8074-disable-USB-GDSC-s-SW_COLLAPSE.patch +++ b/target/linux/ipq807x/patches-5.15/0141-clk-qcom-ipq8074-disable-USB-GDSC-s-SW_COLLAPSE.patch @@ -16,7 +16,7 @@ Signed-off-by: Robert Marko --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -4842,6 +4842,11 @@ static int gcc_ipq8074_probe(struct plat +@@ -4836,6 +4836,11 @@ static int gcc_ipq8074_probe(struct plat /* SW Workaround for UBI32 Huayra PLL */ regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26)); diff --git a/target/linux/ipq807x/patches-5.15/0142-clk-qcom-ipq8074-SW-workaround-for-UBI32-PLL-lock.patch b/target/linux/ipq807x/patches-5.15/0142-clk-qcom-ipq8074-SW-workaround-for-UBI32-PLL-lock.patch index 8867a2b575b390..6e54c4a9ba9166 100644 --- a/target/linux/ipq807x/patches-5.15/0142-clk-qcom-ipq8074-SW-workaround-for-UBI32-PLL-lock.patch +++ b/target/linux/ipq807x/patches-5.15/0142-clk-qcom-ipq8074-SW-workaround-for-UBI32-PLL-lock.patch @@ -19,7 +19,7 @@ Signed-off-by: Robert Marko --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -4847,6 +4847,9 @@ static int gcc_ipq8074_probe(struct plat +@@ -4841,6 +4841,9 @@ static int gcc_ipq8074_probe(struct plat /* Disable SW_COLLAPSE for USB1 GDSCR */ regmap_update_bits(regmap, 0x3f078, BIT(0), 0x0); diff --git a/target/linux/ipq807x/patches-5.15/0145-clk-qcom-ipq8074-add-PPE-crypto-clock.patch b/target/linux/ipq807x/patches-5.15/0145-clk-qcom-ipq8074-add-PPE-crypto-clock.patch index 5e7099c771c42d..5cff4e6512289e 100644 --- a/target/linux/ipq807x/patches-5.15/0145-clk-qcom-ipq8074-add-PPE-crypto-clock.patch +++ b/target/linux/ipq807x/patches-5.15/0145-clk-qcom-ipq8074-add-PPE-crypto-clock.patch @@ -16,7 +16,7 @@ Signed-off-by: Robert Marko --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c -@@ -3183,6 +3183,24 @@ static struct clk_branch gcc_nss_ptp_ref +@@ -3177,6 +3177,24 @@ static struct clk_branch gcc_nss_ptp_ref }, }; @@ -41,7 +41,7 @@ Signed-off-by: Robert Marko static struct clk_branch gcc_nssnoc_ce_apb_clk = { .halt_reg = 0x6830c, .clkr = { -@@ -4655,6 +4673,7 @@ static struct clk_regmap *gcc_ipq8074_cl +@@ -4649,6 +4667,7 @@ static struct clk_regmap *gcc_ipq8074_cl [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr, [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr, [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, diff --git a/target/linux/ipq807x/patches-5.15/0600-5.15-qca-nss-ecm-support-CORE.patch b/target/linux/ipq807x/patches-5.15/0600-5.15-qca-nss-ecm-support-CORE.patch index cbdad8fa1edb55..05846cf53ab293 100644 --- a/target/linux/ipq807x/patches-5.15/0600-5.15-qca-nss-ecm-support-CORE.patch +++ b/target/linux/ipq807x/patches-5.15/0600-5.15-qca-nss-ecm-support-CORE.patch @@ -55,7 +55,7 @@ #endif --- a/include/linux/if_vlan.h +++ b/include/linux/if_vlan.h -@@ -222,7 +222,28 @@ extern void vlan_vids_del_by_dev(struct +@@ -230,7 +230,28 @@ extern void vlan_vids_del_by_dev(struct extern bool vlan_uses_dev(const struct net_device *dev); @@ -549,7 +549,7 @@ struct fib_table *tb; --- a/include/net/addrconf.h +++ b/include/net/addrconf.h -@@ -504,4 +504,9 @@ int if6_proc_init(void); +@@ -512,4 +512,9 @@ int if6_proc_init(void); void if6_proc_exit(void); #endif diff --git a/target/linux/ipq807x/patches-5.15/0606-5.15-qca-nss-ecm-bonding-add-bond_get_id.patch b/target/linux/ipq807x/patches-5.15/0606-5.15-qca-nss-ecm-bonding-add-bond_get_id.patch index 15580dfdf6beac..5480ae631653d6 100644 --- a/target/linux/ipq807x/patches-5.15/0606-5.15-qca-nss-ecm-bonding-add-bond_get_id.patch +++ b/target/linux/ipq807x/patches-5.15/0606-5.15-qca-nss-ecm-bonding-add-bond_get_id.patch @@ -10,7 +10,7 @@ static struct flow_dissector flow_keys_bonding __read_mostly; /*-------------------------- Forward declarations ---------------------------*/ -@@ -4109,6 +4112,23 @@ static int bond_get_lowest_level_rcu(str +@@ -4115,6 +4118,23 @@ static int bond_get_lowest_level_rcu(str } #endif @@ -34,7 +34,7 @@ static void bond_get_stats(struct net_device *bond_dev, struct rtnl_link_stats64 *stats) { -@@ -5441,6 +5461,10 @@ static void bond_destructor(struct net_d +@@ -5447,6 +5467,10 @@ static void bond_destructor(struct net_d if (bond->rr_tx_counter) free_percpu(bond->rr_tx_counter); @@ -45,7 +45,7 @@ } void bond_setup(struct net_device *bond_dev) -@@ -6014,7 +6038,14 @@ int bond_create(struct net *net, const c +@@ -6020,7 +6044,14 @@ int bond_create(struct net *net, const c bond_work_init_all(bond); diff --git a/target/linux/ipq95xx/Makefile b/target/linux/ipq95xx/Makefile new file mode 100644 index 00000000000000..875f7f954f29bf --- /dev/null +++ b/target/linux/ipq95xx/Makefile @@ -0,0 +1,18 @@ +include $(TOPDIR)/rules.mk + +ARCH:=aarch64 +BOARD:=ipq95xx +BOARDNAME:=Qualcomm Atheros IPQ95XX +FEATURES:=squashfs fpu ramdisk nand pcie +CPU_TYPE:=cortex-a73 +SUBTARGETS:=generic + +KERNELNAME:=Image dtbs +KERNEL_PATCHVER:=6.1 + +include $(INCLUDE_DIR)/target.mk + +DEFAULT_PACKAGES += \ + e2fsprogs uboot-envtools kmod-leds-gpio kmod-gpio-button-hotplug + +$(eval $(call BuildTarget)) diff --git a/target/linux/ipq95xx/base-files/etc/inittab b/target/linux/ipq95xx/base-files/etc/inittab new file mode 100644 index 00000000000000..167adf0348e5b4 --- /dev/null +++ b/target/linux/ipq95xx/base-files/etc/inittab @@ -0,0 +1,3 @@ +::sysinit:/etc/init.d/rcS S boot +::shutdown:/etc/init.d/rcS K shutdown +ttyMSM0::askfirst:/usr/libexec/login.sh diff --git a/target/linux/ipq95xx/config-6.1 b/target/linux/ipq95xx/config-6.1 new file mode 100644 index 00000000000000..ad18acbc33ed30 --- /dev/null +++ b/target/linux/ipq95xx/config-6.1 @@ -0,0 +1,1202 @@ +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y +CONFIG_GENERIC_IRQ_IPI=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +# CONFIG_IRQ_MSI_IOMMU is not set +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_HZ_FULL is not set +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +# CONFIG_ARCH_BITMAIN is not set +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_FORCE_MAX_ORDER=11 +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +# CONFIG_ARCH_IPQ40XX is not set +# CONFIG_ARCH_IPQ5332 is not set +# CONFIG_ARCH_IPQ6018 is not set +CONFIG_ARCH_KEEP_MEMBLOCK=y +# CONFIG_ARCH_MDM9615 is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +# CONFIG_ARCH_MILBEAUT is not set +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +# CONFIG_ARCH_MSM8909 is not set +# CONFIG_ARCH_MSM8916 is not set +# CONFIG_ARCH_MSM8960 is not set +# CONFIG_ARCH_MSM8974 is not set +# CONFIG_ARCH_MSM8X60 is not set +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +# CONFIG_ARCH_NXP is not set +CONFIG_ARCH_QCOM=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_ARM64=y +CONFIG_ARM64_4K_PAGES=y +CONFIG_ARM64_EPAN=y +# CONFIG_ARM_QCOM_CPUFREQ_HW is not set +# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set +# CONFIG_ARM64_CNP is not set +# CONFIG_ARM64_ERRATUM_1742098 is not set +# CONFIG_ARM64_ERRATUM_2051678 is not set +# CONFIG_ARM64_ERRATUM_2054223 is not set +# CONFIG_ARM64_ERRATUM_2067961 is not set +# CONFIG_ARM64_ERRATUM_2077057 is not set +# CONFIG_ARM64_ERRATUM_2441007 is not set +# CONFIG_ARM64_ERRATUM_2441009 is not set +# CONFIG_ARM64_ERRATUM_2658417 is not set +# CONFIG_ARM64_PMEM is not set +# CONFIG_ARM64_PSEUDO_NMI is not set +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_ARM64_TAGGED_ADDR_ABI=y +CONFIG_ARM_THUMB=y +CONFIG_ARM_PATCH_IDIV=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y +# CONFIG_ARM_QCOM_SPM_CPUIDLE is not set +# CONFIG_RELOCATABLE is not set +# CONFIG_RANDOMIZE_BASE is not set +# CONFIG_RANDOMIZE_MODULE_REGION_FULL is not set +# CONFIG_RANDOMIZE_KSTACK_OFFSET is not set +CONFIG_ARCH_NR_GPIO=0 +CONFIG_CMDLINE="" +# CONFIG_EFI is not set +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_SUSPEND_SKIP_SYNC is not set +# CONFIG_HIBERNATION is not set +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +# CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_USERSPACE_AUTOSLEEP is not set +# CONFIG_PM_WAKELOCKS is not set +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_CLK=y +CONFIG_PM_GENERIC_DOMAINS=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_PM_GENERIC_DOMAINS_SLEEP=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +# CONFIG_ARM_HIGHBANK_CPUIDLE is not set +CONFIG_ARM_PSCI=y +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_SMMU is not set +# CONFIG_ARM_SMMU_V3 is not set +# CONFIG_QCOM_IOMMU is not set +# CONFIG_VIRTIO_IOMMU is not set +CONFIG_ATA=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NVME=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_INLINE_ENCRYPTION=y +CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y +# CONFIG_VIRTIO_BLK is not set +CONFIG_BMP280=y +CONFIG_BMP280_I2C=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_BOUNCE=y +# CONFIG_BPF_KPROBE_OVERRIDE is not set +# CONFIG_BPFILTER is not set +CONFIG_BRIDGE_VLAN_FILTERING=y +# CONFIG_BT_HCIBTUSB_MTK is not set +# CONFIG_BT_MTKSDIO is not set +CONFIG_BUILD_BIN2C=y +# CONFIG_BUS_TOPOLOGY_ADHOC is not set +# CONFIG_CACHE_L2X0 is not set +# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set +# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CC_STACKPROTECTOR=y +# CONFIG_CC_STACKPROTECTOR_NONE is not set +CONFIG_CC_STACKPROTECTOR_REGULAR=y +CONFIG_CFG80211_HEADERS=y +# CONFIG_CHARGER_LT3651 is not set +# CONFIG_CHARGER_QCOM_SMBB is not set +# CONFIG_CHARGER_UCS1002 is not set +CONFIG_CLEANCACHE=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_OF=y +CONFIG_CLKSRC_PROBE=y +CONFIG_CLKSRC_QCOM=y +CONFIG_CLONE_BACKWARDS=y +# CONFIG_CMA is not set +# CONFIG_CMA_ALIGNMENT is not set +# CONFIG_CMA_AREAS is not set +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +# CONFIG_CMA_SIZE_MBYTES is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +# CONFIG_CMA_SIZE_SEL_MBYTES is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +CONFIG_CNSS2=y +CONFIG_CNSS2_QCA9574_SUPPORT=y +# CONFIG_CNSS2_CALIBRATION_SUPPORT is not set +# CONFIG_CNSS2_DEBUG is not set +CONFIG_CNSS2_GENL=y +# CONFIG_CNSS2_PCI_DRIVER is not set +# CONFIG_CNSS2_PM is not set +# CONFIG_CNSS2_RAMDUMP is not set +# CONFIG_CNSS2_SMMU is not set +CONFIG_CNSS_QCN9000=y +# CONFIG_SURFACE_PLATFORMS is not set +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_QCOM=y +# CONFIG_COMMON_CLK_XGENE is not set +# CONFIG_COMMON_CLK_SI5341 is not set +CONFIG_CONFIGFS_FS=y +CONFIG_COREDUMP=y +CONFIG_CORESIGHT=y +# CONFIG_CORESIGHT_BYTE_CNTR is not set +# CONFIG_CORESIGHT_CATU is not set +# CONFIG_CORESIGHT_CPU_DEBUG is not set +CONFIG_CORESIGHT_CSR=y +CONFIG_CORESIGHT_CTI=y +# CONFIG_CORESIGHT_CTI_INTEGRATION_REGS is not set +# CONFIG_CORESIGHT_TRBE is not set +# CONFIG_CORESIGHT_CTI_SAVE_DISABLE is not set +# CONFIG_CORESIGHT_DUMMY is not set +CONFIG_CORESIGHT_HWEVENT=y +CONFIG_CORESIGHT_LINKS_AND_SINKS=y +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y +# CONFIG_CORESIGHT_REMOTE_ETM is not set +# CONFIG_CORESIGHT_SINK_ETBV10 is not set +# CONFIG_CORESIGHT_SINK_TPIU is not set +# CONFIG_CORESIGHT_SOURCE_ETM3X is not set +CONFIG_CORESIGHT_SOURCE_ETM4X=y +CONFIG_CORESIGHT_STM=y +CONFIG_CORESIGHT_TPDA=y +CONFIG_CORESIGHT_TPDM=y +# CONFIG_CORESIGHT_TPDM_DEFAULT_ENABLE is not set +# CONFIG_COUNTER is not set +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +# CONFIG_SCHED_CLUSTER is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_HAS_ASID=y +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +# CONFIG_CPU_IDLE_GOV_TEO is not set +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +# CONFIG_CPU_SW_DOMAIN_PAN is not set +# CONFIG_CPU_THERMAL is not set +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_CRYPTO_ADIANTUM is not set +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_DISABLE_AES192_TEST is not set +CONFIG_CRYPTO_AES_586=y +# CONFIG_CRYPTO_ALL_CASES is not set +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set +# CONFIG_CRYPTO_DEV_HISI_ZIP is not set +# CONFIG_CRYPTO_DEV_OTA_CRYPTO is not set +CONFIG_CRYPTO_DEV_QCOM_ICE=y +# CONFIG_CRYPTO_DEV_QCOM_MSM_QCE is not set +# CONFIG_CRYPTO_DEV_QCOM_RNG is not set +CONFIG_CRYPTO_DISABLE_AHASH_LARGE_KEY_TEST=y +CONFIG_CRYPTO_DISABLE_AHASH_TYPE1_TESTS=y +CONFIG_CRYPTO_DISABLE_AHASH_TYPE2_TESTS=y +CONFIG_CRYPTO_DISABLE_AHASH_TYPE3_TESTS=y +CONFIG_CRYPTO_DISABLE_AUTH_SPLIT_TESTS=y +CONFIG_CRYPTO_DISABLE_HW_UNSUPPORTED_TESTS=y +CONFIG_CRYPTO_DISABLE_OUTOFPLACE_TESTS=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ECHAINIV=y +# CONFIG_CRYPTO_ECRDSA is not set +# CONFIG_CRYPTO_ESSIV is not set +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set +# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set +CONFIG_CRYPTO_MD5_PPC=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_NO_AES_XTS_ZERO_KEY_SUPPORT=y +CONFIG_CRYPTO_NO_AES_CTR_UNEVEN_DATA_LEN_SUPPORT=y +# CONFIG_CRYPTO_NO_ZERO_LEN_HASH is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_OFB=y +# CONFIG_CRYPTO_PCRYPT is not set +# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set +CONFIG_CRYPTO_RMD160=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA1_PPC=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_SM3_NEON is not set +# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set +# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set +# CONFIG_CRYPTO_STREEBOG is not set +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_CRYPTO_XTS=y +# CONFIG_CRYPTO_XXHASH is not set +CONFIG_CRYPTO_XZ=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_EFI is not set +CONFIG_DEBUG_GPIO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_MISC is not set +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_UART_8250 is not set +# CONFIG_DEBUG_USER is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEVMEM=y +# CONFIG_DIAGFWD_BRIDGE_CODE is not set +# CONFIG_DIAG_MHI is not set +CONFIG_DIAG_OVER_QRTR=y +# CONFIG_DIAG_OVER_USB is not set +CONFIG_DMADEVICES=y +# CONFIG_DMA_CMA is not set +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +# CONFIG_DMA_SOUND is not set +CONFIG_DMA_VIRTUAL_CHANNELS=y +# CONFIG_DMI is not set +# CONFIG_DMIID is not set +# CONFIG_DMI_SYSFS is not set +# CONFIG_DM_INIT is not set +# CONFIG_DP83640_PHY is not set +# CONFIG_DPS310 is not set +CONFIG_DTC=y +CONFIG_DT_IDLE_STATES=y +# CONFIG_DWMAC_GENERIC is not set +CONFIG_DYNAMIC_DEBUG=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EXT4_FS=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +# CONFIG_FW_CACHE is not set +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +# CONFIG_GENERIC_CPUFREQ_KRAIT is not set +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +# CONFIG_GEN_RTC is not set +# CONFIG_GLACIER is not set +# CONFIG_GLINK_DEBUG_FS is not set +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_GPIO_AMD_FCH is not set +# CONFIG_GPIO_CADENCE is not set +CONFIG_GPIO_DEVRES=y +# CONFIG_GPIO_GW_PLD is not set +# CONFIG_GPIO_LATCH is not set +# CONFIG_GPIO_NXP_74HC153 is not set +# CONFIG_GPIO_SAMA5D2_PIOBU is not set +CONFIG_GPIO_SYSFS=y +# CONFIG_GPIO_USB_DETECT is not set +# CONFIG_GSI is not set +# CONFIG_HABANA_AI is not set +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_ARM_ARCH_TIMER=y +CONFIG_HAVE_SMP=y +CONFIG_HIGHMEM=y +CONFIG_HIGHPTE=y +# CONFIG_HIST_TRIGGERS is not set +CONFIG_HOTPLUG_CPU=y +CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_QCOM=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MSM_LEGACY=y +CONFIG_HW_RANDOM_CN10K=y +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_HELPER_AUTO=y +# CONFIG_I2C_NVIDIA_GPU is not set +# CONFIG_I2C_QCOM_CCI is not set +CONFIG_I2C_QUP=y +# CONFIG_I3C is not set +# CONFIG_IGC is not set +CONFIG_IIO=y +# CONFIG_IIO_BUFFER is not set +# CONFIG_IIO_TRIGGER is not set +# CONFIG_ADMV8818 is not set +# CONFIG_ADMV1014 is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +# CONFIG_IKHEADERS is not set +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_RD_ZSTD is not set +# CONFIG_BOOT_CONFIG is not set +# CONFIG_INITRAMFS_PRESERVE_MTIME is not set +# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# CONFIG_INPUT_GPIO_VIBRA is not set +# CONFIG_INPUT_MSM_VIBRATOR is not set +# CONFIG_INPUT_PM8941_PWRKEY is not set +# CONFIG_INPUT_PM8XXX_VIBRATOR is not set +# CONFIG_INTERCONNECT is not set +CONFIG_IOMMU_HELPER=y +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set +# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set +# CONFIG_IOMMU_IO_PGTABLE_DART is not set +# CONFIG_OF_IOMMU is not set +# CONFIG_IOMMU_DMA is not set +# CONFIG_IOMMU_SUPPORT is not set +# CONFIG_APQ_GCC_8084 is not set +# CONFIG_APQ_MMCC_8084 is not set +# CONFIG_IPQ_APSS_PLL is not set +CONFIG_IPQ_APSS_6018=y +CONFIG_IPQ_DEBUG=y +# CONFIG_IPQ_GCC_4019 is not set +# CONFIG_IPQ_GCC_5018 is not set +# CONFIG_IPQ_GCC_5332 is not set +# CONFIG_IPQ_GCC_6018 is not set +# CONFIG_IPQ_GCC_806X is not set +# CONFIG_IPQ_GCC_8074 is not set +# CONFIG_IPQ_GCC_DEVSOC is not set +CONFIG_IPQ_GCC_9574=y +CONFIG_IPQ_NSSCC_9574=y +# CONFIG_IPQ_LCC_806X is not set +CONFIG_IPQ_REG_UPDATE=y +# CONFIG_IPQ_REMOTEPROC_ADSP is not set +CONFIG_IPQ_SUBSYSTEM_DUMP=y +CONFIG_IPQ_SUBSYSTEM_RAMDUMP=y +# CONFIG_IPQ_SUBSYSTEM_RESTART is not set +# CONFIG_IPQ_SUBSYSTEM_RESTART_TEST is not set +CONFIG_IPQ_TCSR=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +# CONFIG_KCOV is not set +CONFIG_KEYS=y +# CONFIG_KEYS_REQUEST_CACHE is not set +CONFIG_KPSS_XCC=y +# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set +# CONFIG_KRAITCC is not set +# CONFIG_KRAIT_CLOCKS is not set +# CONFIG_KRAIT_L2_ACCESSORS is not set +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_LEDS_IPQ=y +# CONFIG_LEDS_LM3532 is not set +# CONFIG_LEDS_PCA9956B is not set +CONFIG_LEDS_TLC591XX=y +# CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_LEDS_TRIGGER_PATTERN is not set +# CONFIG_LEDS_PWM_MULTICOLOR is not set +CONFIG_LIBFDT=y +CONFIG_LOCKUP_DETECTOR=y +# CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity" +# CONFIG_LTC1660 is not set +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MAILBOX=y +# CONFIG_MAILBOX_TEST is not set +# CONFIG_MAP_E_SUPPORT is not set +# CONFIG_MAX31856 is not set +# CONFIG_MAX44009 is not set +# CONFIG_MAX5432 is not set +# CONFIG_MB1232 is not set +# CONFIG_MCP3911 is not set +# CONFIG_MCP41010 is not set +CONFIG_MDIO=y +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BOARDINFO=y +# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set +CONFIG_MDIO_GPIO=y +CONFIG_MDIO_QCA=y +# CONFIG_MDM_GCC_9615 is not set +# CONFIG_MDM_LCC_9615 is not set +# CONFIG_MEMORY_HOTPLUG is not set +# CONFIG_MFD_LOCHNAGAR is not set +# CONFIG_MFD_MAX77650 is not set +CONFIG_MFD_QCOM_RPM=y +# CONFIG_MFD_SPMI_PMIC is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TQMX86 is not set +CONFIG_MHI_BUS=y +CONFIG_MHI_BUS_DEBUG=y +# CONFIG_MHI_BUS_RESERVED_DMA_POOL is not set +CONFIG_MHI_NETDEV=y +CONFIG_MHI_QTI=y +# CONFIG_MHI_SATELLITE is not set +CONFIG_MHI_UCI=y +CONFIG_MHI_WWAN_CTRL=y +CONFIG_MHI_BUS_PCI_GENERIC=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_ARMMMCI=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_CRYPTO=y +CONFIG_MMC_QCOM_DML=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_MMC_SDHCI_MSM_ICE=y +# CONFIG_MMC_SDHCI_OF_ARASAN is not set +# CONFIG_MMC_SDHCI_OF_ASPEED is not set +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +# CONFIG_MMC_STM32_SDMMC is not set +# CONFIG_MMC_TIFM_SD is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_MODULES_USE_ELF_REL=y +# CONFIG_MSM_GCC_8660 is not set +# CONFIG_MSM_GCC_8909 is not set +# CONFIG_MSM_GCC_8916 is not set +# CONFIG_MSM_GCC_8939 is not set +# CONFIG_MSM_GCC_8960 is not set +# CONFIG_MSM_GCC_8974 is not set +# CONFIG_MSM_GCC_8976 is not set +# CONFIG_MSM_GCC_8994 is not set +# CONFIG_MSM_GCC_8996 is not set +# CONFIG_MSM_GCC_8998 is not set +# CONFIG_MSM_GPUCC_8998 is not set +# CONFIG_MSM_IOMMU is not set +# CONFIG_MSM_LCC_8960 is not set +# CONFIG_MSM_MHI is not set +# CONFIG_MSM_MHI_DEBUG is not set +# CONFIG_MSM_MHI_DEV is not set +# CONFIG_MSM_MHI_UCI is not set +# CONFIG_MSM_MMCC_8960 is not set +# CONFIG_MSM_MMCC_8974 is not set +# CONFIG_MSM_MMCC_8996 is not set +# CONFIG_MSM_QMI_INTERFACE is not set +# CONFIG_MSM_RPM_GLINK is not set +CONFIG_MSM_RPM_LOG=y +CONFIG_MSM_RPM_RPMSG=y +# CONFIG_MSM_RPM_SMD is not set +# CONFIG_MSM_SECURE_BUFFER is not set +# CONFIG_MSM_SMEM is not set +# CONFIG_MSM_TEST_QMI_CLIENT is not set +# CONFIG_MSM_MMCC_8998 is not set +# CONFIG_QCM_GCC_2290 is not set +# CONFIG_QCM_DISPCC_2290 is not set +# CONFIG_MTD_SPLIT_BCM_WFI_FW is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_HYPERBUS is not set +CONFIG_MTD_M25P80=y +# CONFIG_MTD_NAND_ECC_SW_BCH is not set +# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set +CONFIG_MTD_NAND_QCOM=y +# CONFIG_MTD_NAND_QCOM_SERIAL is not set +# CONFIG_MTD_QCOMSMEM_PARTS is not set +CONFIG_MTD_RAW_NAND=y +# CONFIG_MTD_ROUTERBOOT_PARTS is not set +CONFIG_MTD_SPINAND_GIGADEVICE=y +CONFIG_MTD_SPINAND_MT29F=y +CONFIG_MTD_SPINAND_ONDIEECC=y +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_SPLIT_ELF_FW is not set +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_FIT_FW=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_MTD_UBI_FASTMAP is not set +CONFIG_MTD_UBI_GLUEBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEON=y +CONFIG_NET=y +# CONFIG_VIRTIO_NET is not set +# CONFIG_NET_DSA_MV88E6063 is not set +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_L3_MASTER_DEV=y +CONFIG_NET_PTP_CLASSIFY=y +# CONFIG_NET_SCH_TAPRIO is not set +CONFIG_NET_SWITCHDEV=y +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_PENSANDO is not set +# CONFIG_NF_CONNTRACK_DSCPREMARK_EXT is not set +# CONFIG_NF_IPV6_DUMMY_HEADER is not set +# CONFIG_NI_XGE_MANAGEMENT_ENET is not set +# CONFIG_NOA1305 is not set +CONFIG_NO_BOOTMEM=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=4 +# CONFIG_NULL_TTY is not set +# CONFIG_NUMA is not set +CONFIG_NUM_ALT_PARTITION=16 +CONFIG_NVME_HWMON=y +CONFIG_NVMEM=y +# CONFIG_NVMEM_SYSFS is not set +CONFIG_NVMEM_QCOM_QFPROM=y +# CONFIG_NVMEM_RMEM is not set +# CONFIG_NVMEM_U_BOOT_ENV is not set +# CONFIG_OCTEONTX2_AF is not set +# CONFIG_OCTEON_EP is not set +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_RESERVED_MEM=y +# CONFIG_OF_SLIMBUS is not set +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_PADATA=y +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PAGE_TABLE_CHECK is not set +CONFIG_PANIC_ON_OOPS=y +CONFIG_PANIC_ON_OOPS_VALUE=1 +CONFIG_PANIC_TIMEOUT=5 +CONFIG_PCI=y +# CONFIG_PCIEAER is not set +# CONFIG_PCIE_AL is not set +# CONFIG_PCIE_CADENCE_EP is not set +CONFIG_PCIE_DW=y +# CONFIG_PCIE_DW_PLAT is not set +# CONFIG_PCIE_PME is not set +CONFIG_PCIE_QCOM=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCS_XPCS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLINK=y +CONFIG_PHY_IPQ_UNIPHY_PCIE=y +CONFIG_PHYS_OFFSET=0x40000000 +# CONFIG_PHY_QCOM_APQ8064_SATA is not set +# CONFIG_PHY_QCOM_EDP is not set +# CONFIG_PHY_QCOM_IPQ4019_USB is not set +# CONFIG_PHY_QCOM_IPQ806X_SATA is not set +# CONFIG_PHY_QCOM_IPQ806X_USB is not set +# CONFIG_PHY_QCOM_PCIE2 is not set +CONFIG_PHY_QCOM_QMP=y +# CONFIG_PHY_QCOM_QUSB2 is not set +# CONFIG_PHY_QCOM_UFS is not set +# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set +# CONFIG_PHY_QCOM_USB_HS_28NM is not set +# CONFIG_PHY_QCOM_USB_SS is not set +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_APQ8064 is not set +# CONFIG_PINCTRL_APQ8084 is not set +# CONFIG_PINCTRL_DEVSOC is not set +# CONFIG_PINCTRL_IPQ4019 is not set +# CONFIG_PINCTRL_IPQ5018 is not set +# CONFIG_PINCTRL_IPQ5332 is not set +# CONFIG_PINCTRL_IPQ6018 is not set +# CONFIG_PINCTRL_IPQ8064 is not set +# CONFIG_PINCTRL_IPQ8074 is not set +CONFIG_PINCTRL_IPQ9574=y +# CONFIG_PINCTRL_MDM9615 is not set +CONFIG_PINCTRL_MSM=y +# CONFIG_PINCTRL_MSM8226 is not set +# CONFIG_PINCTRL_MSM8660 is not set +# CONFIG_PINCTRL_MSM8909 is not set +# CONFIG_PINCTRL_MSM8916 is not set +# CONFIG_PINCTRL_MSM8960 is not set +# CONFIG_PINCTRL_MSM8976 is not set +# CONFIG_PINCTRL_MSM8994 is not set +# CONFIG_PINCTRL_MSM8996 is not set +# CONFIG_PINCTRL_MSM8998 is not set +# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set +# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set +# CONFIG_PINCTRL_QCM2290 is not set +# CONFIG_PINCTRL_QCS404 is not set +# CONFIG_PINCTRL_SC7180 is not set +# CONFIG_PINCTRL_SC8280XP is not set +# CONFIG_PINCTRL_SDM660 is not set +# CONFIG_PINCTRL_SDM845 is not set +# CONFIG_PINCTRL_SDX65 is not set +# CONFIG_PINCTRL_SM8150 is not set +# CONFIG_PINCTRL_SM6350 is not set +# CONFIG_PINCTRL_SM6375 is not set +# CONFIG_PINCTRL_SM8250 is not set +# CONFIG_PINCTRL_SM8450 is not set +# CONFIG_PINCTRL_STMFX is not set +# CONFIG_PKCS7_TEST_KEY is not set +# CONFIG_PKCS7_MESSAGE_PARSER is not set +# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set +# CONFIG_PL330_DMA is not set +CONFIG_PM=y +# CONFIG_PM8916_WATCHDOG is not set +CONFIG_PM_CLK=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_PM_GENERIC_DOMAINS_SLEEP=y +CONFIG_PM_OPP=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_MSM=y +CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +# CONFIG_PREEMPT_DYNAMIC is not set +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_RCU=y +# CONFIG_COMPAT_ALIGNMENT_FIXUPS is not set +# CONFIG_PRINTK_CALLER is not set +CONFIG_PRINTK_TIME=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_STRIPPED is not set +# CONFIG_PSI is not set +CONFIG_PTP_1588_CLOCK=y +CONFIG_PUBLIC_KEY_ALGO_RSA=y +# CONFIG_PVPANIC is not set +CONFIG_PWM=y +CONFIG_PWM_IPQ=y +# CONFIG_PWM_PCA9685 is not set +CONFIG_PWM_SYSFS=y +# CONFIG_PWM_CLK is not set +# CONFIG_PWM_XILINX is not set +# CONFIG_PWRSEQ_EMMC is not set +CONFIG_PWRSEQ_IPQ=y +# CONFIG_PWRSEQ_SIMPLE is not set +CONFIG_QCA_MINIDUMP=y +# CONFIG_QCA_MINIDUMP_DEBUG is not set +# CONFIG_QCOM_A53PLL is not set +CONFIG_QCOM_ADM=y +# CONFIG_QCOM_AOSS_QMP is not set +CONFIG_QCOM_APCS_IPC=y +CONFIG_QCOM_APM=y +# CONFIG_QCOM_MPM is not set +# CONFIG_QCOM_IPCC is not set +# CONFIG_QCOM_APR is not set +CONFIG_QCOM_BAM_DMA=y +CONFIG_QCOM_CACHE_DUMP=y +CONFIG_QCOM_CACHE_DUMP_ON_PANIC=y +# CONFIG_QCOM_CPR is not set +# CONFIG_QCOM_OCMEM is not set +# CONFIG_QCOM_SPM is not set +# CONFIG_QCOM_STATS is not set +# CONFIG_QCOM_WCNSS_CTRL is not set +# CONFIG_QCOM_ICC_BWMON is not set +# CONFIG_QCOM_CLK_APCS_MSM8916 is not set +# CONFIG_QCOM_CLK_APCC_MSM8996 is not set +# CONFIG_QCOM_CLK_APCS_SDX55 is not set +# CONFIG_QCOM_CLK_RPM is not set +# CONFIG_QCOM_CLK_SMD_RPM is not set +# CONFIG_QCOM_COINCELL is not set +# CONFIG_QCOM_COMMAND_DB is not set +CONFIG_QCOM_DLOAD_MODE=y +CONFIG_QCOM_DLOAD_MODE_APPSBL=y +# CONFIG_QCOM_EBI2 is not set +# CONFIG_QCOM_FASTRPC is not set +CONFIG_QCOM_GDSC=y +# CONFIG_QCOM_GENI_SE is not set +CONFIG_QCOM_GLINK_SSR=y +# CONFIG_QCOM_GSBI is not set +# CONFIG_QCOM_HFPLL is not set +# CONFIG_QCOM_LLCC is not set +# CONFIG_QCOM_NON_SECURE_PIL is not set +CONFIG_QCOM_Q6V5_MPD=y +# CONFIG_QCOM_PDC is not set +# CONFIG_QCOM_PM is not set +# CONFIG_QCOM_Q6V5_ADSP is not set +# CONFIG_QCOM_Q6V5_MSS is not set +# CONFIG_QCOM_Q6V5_PAS is not set +# CONFIG_QCOM_Q6V5_WCSS is not set +CONFIG_QCOM_QFPROM=y +CONFIG_QCOM_QMI_HELPERS=y +CONFIG_QCOM_RESTART_REASON=y +# CONFIG_QCOM_RMTFS_MEM is not set +# CONFIG_QCOM_RPMH is not set +# CONFIG_QCOM_RPMPD is not set +CONFIG_QCOM_RPM_CLK=y +# CONFIG_QCOM_RTB is not set +CONFIG_QCOM_SCM=y +CONFIG_QCOM_SCM_32=y +CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT=y +# CONFIG_QCOM_SMD is not set +CONFIG_QCOM_SMD_RPM=y +CONFIG_QCOM_SMEM=y +CONFIG_QCOM_SMEM_STATE=y +CONFIG_QCOM_SMP2P=y +# CONFIG_QCOM_SMSM is not set +CONFIG_QCOM_SOC_NETSTANDBY=y +CONFIG_QCOM_SOCINFO=y +# CONFIG_QCOM_SPMI_ADC5 is not set +# CONFIG_QCOM_SPMI_TEMP_ALARM is not set +# CONFIG_QCOM_SPMI_VADC is not set +CONFIG_QCOM_SYSMON=y +CONFIG_QCOM_TSENS=y +CONFIG_QCOM_WDT=y +CONFIG_QCOM_DCC_V2=y +# CONFIG_QCS_GCC_404 is not set +# CONFIG_QCS_Q6SSTOP_404 is not set +# CONFIG_QCS_TURING_404 is not set +# CONFIG_HP_WATCHDOG is not set +CONFIG_RAS=y +CONFIG_RATIONAL=y +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +# CONFIG_RCU_EXPERT is not set +CONFIG_RCU_STALL_COMMON=y +# CONFIG_REED_SOLOMON_TEST is not set +CONFIG_REGMAP=y +CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_CPR3=y +CONFIG_REGULATOR_CPR3_NPU=y +CONFIG_REGULATOR_CPR4_APSS=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +# CONFIG_REGULATOR_IPQ40XX is not set +# CONFIG_REGULATOR_QCOM_RPM is not set +CONFIG_REGULATOR_QCOM_SMD_RPM=y +# CONFIG_REGULATOR_QCOM_SPMI is not set +CONFIG_REGULATOR_QTI_GPIO=y +CONFIG_REGULATOR_RPM_GLINK=y +# CONFIG_REGULATOR_RPM_SMD is not set +# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set +CONFIG_RELAY=y +CONFIG_REMOTEPROC=y +# CONFIG_REMOTEPROC_CDEV is not set +# CONFIG_RESET_ATTACK_MITIGATION is not set +CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_QCOM_AOSS is not set +# CONFIG_RESET_QCOM_PDC is not set +# CONFIG_QCOM_WCNSS_PIL is not set +CONFIG_QRTR=y +CONFIG_QRTR_MHI=y +CONFIG_QRTR_SMD=y +CONFIG_RFS_ACCEL=y +# CONFIG_RODATA_FULL_DEFAULT_ENABLED is not set +CONFIG_RPMSG=y +CONFIG_RPMSG_CHAR=y +# CONFIG_RPMSG_CTRL is not set +# CONFIG_RPMSG_NS is not set +CONFIG_RPMSG_QCOM_GLINK_RPM=y +CONFIG_RPMSG_QCOM_GLINK_SMEM=y +CONFIG_RPMSG_QCOM_SMD=y +# CONFIG_RPMSG_TTY is not set +# CONFIG_RPMSG_VIRTIO is not set +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_PM8XXX is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_SAMPLES=y +# CONFIG_SAMPLE_AUXDISPLAY is not set +# CONFIG_SAMPLE_CONFIGFS is not set +# CONFIG_SAMPLE_HW_BREAKPOINT is not set +# CONFIG_SAMPLE_KFIFO is not set +# CONFIG_SAMPLE_KOBJECT is not set +# CONFIG_SAMPLE_KPROBES is not set +# CONFIG_SAMPLE_KRETPROBES is not set +# CONFIG_SAMPLE_WATCHDOG is not set +# CONFIG_SAMPLE_CORESIGHT_SYSCFG is not set +CONFIG_SAMPLE_QMI_CLIENT=m +# CONFIG_SAMPLE_RPMSG_CLIENT is not set +# CONFIG_SAMPLE_TRACE_ARRAY is not set +# CONFIG_SAMPLE_TRACE_CUSTOM_EVENTS is not set +CONFIG_SAMPLE_TRACE_EVENTS=y +# CONFIG_SAMPLE_TRACE_PRINTK is not set +# CONFIG_SAMPLE_VFIO_MDEV_MDPY_FB is not set +# CONFIG_SATA_AHCI is not set +CONFIG_SCHED_HRTICK=y +# CONFIG_SCHED_INFO is not set +# CONFIG_SC_DISPCC_7180 is not set +# CONFIG_SC_MSS_7180 is not set +# CONFIG_SC_VIDEOCC_7180 is not set +# CONFIG_SC_CAMCC_7280 is not set +# CONFIG_SC_DISPCC_7280 is not set +# CONFIG_SC_GCC_7180 is not set +# CONFIG_SC_GCC_8280XP is not set +# CONFIG_SC_GPUCC_7180 is not set +# CONFIG_SC_LPASSCC_7280 is not set +# CONFIG_SC_LPASS_CORECC_7180 is not set +# CONFIG_SC_LPASS_CORECC_7280 is not set +CONFIG_UACCE=y +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_MYRS is not set +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SDM_CAMCC_845 is not set +# CONFIG_SDM_DISPCC_845 is not set +# CONFIG_SDM_GCC_660 is not set +# CONFIG_SDM_GCC_845 is not set +# CONFIG_SDM_GPUCC_845 is not set +# CONFIG_SDM_LPASSCC_845 is not set +# CONFIG_SDM_VIDEOCC_845 is not set +# CONFIG_SDX_GCC_65 is not set +# CONFIG_SEEMP_CORE is not set +# CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SENSORS_DRIVETEMP is not set +# CONFIG_SENSORS_OCC_P8_I2C is not set +# CONFIG_SENSORS_RM3100_I2C is not set +# CONFIG_SENSORS_RM3100_SPI is not set +# CONFIG_SERIAL_8250 is not set +# CONFIG_SERIAL_8250_CONSOLE is not set +# CONFIG_SERIAL_8250_DMA is not set +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y +# CONFIG_SERIAL_SIFIVE is not set +# CONFIG_SHADOW_CALL_STACK is not set +# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set +CONFIG_SKB_RECYCLER=y +CONFIG_SKB_RECYCLER_MULTI_CPU=y +# CONFIG_SKB_RECYCLER_PREALLOC is not set +# CONFIG_SLIMBUS is not set +# CONFIG_SLIMBUS_MSM_CTRL is not set +# CONFIG_SLIMBUS_MSM_NGD is not set +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +# CONFIG_SM_CAMCC_8450 is not set +# CONFIG_SM_GCC_8150 is not set +# CONFIG_SM_GCC_8250 is not set +# CONFIG_SM_GCC_8450 is not set +# CONFIG_SM_GPUCC_6350 is not set +# CONFIG_SM_GPUCC_8150 is not set +# CONFIG_SM_GPUCC_8250 is not set +# CONFIG_SM_GPUCC_8350 is not set +# CONFIG_SM_VIDEOCC_8150 is not set +# CONFIG_SM_VIDEOCC_8250 is not set +CONFIG_SOUND=y +# CONFIG_SND_SOC_APQ8016_SBC is not set +# CONFIG_SND_SOC_SC7180 is not set +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_IPQ=y +CONFIG_SND_SOC_IPQ9574_LPASS_PCM_RAW=y +CONFIG_SND_SOC_IPQ_LPASS=y +CONFIG_SND_SOC_QCOM=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +# CONFIG_SPI_MTK_QUADSPI is not set +# CONFIG_SPI_QCOM_QSPI is not set +CONFIG_SPI_QUP=y +CONFIG_SPI_SPIDEV=y +# CONFIG_SPI_VSC7385 is not set +# CONFIG_SPMI is not set +# CONFIG_SPMI_MSM_PMIC_ARB is not set +# CONFIG_SPMI_PMIC_CLKDIV is not set +CONFIG_SPS=y +# CONFIG_SPS30 is not set +# CONFIG_SPS_SUPPORT_BAMDMA is not set +CONFIG_SPS_SUPPORT_NDP_BAM=y +CONFIG_SRCU=y +# CONFIG_SRD_TRACE is not set +# CONFIG_STAGING is not set +# CONFIG_STM_PROTO_BASIC is not set +# CONFIG_STM_PROTO_SYS_T is not set +# CONFIG_STM_SOURCE_FTRACE is not set +# CONFIG_STM_SOURCE_HEARTBEAT is not set +# CONFIG_STOPWATCH is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +# CONFIG_SECONDARY_TRUSTED_KEYRING is not set +CONFIG_SUSPEND=y +# CONFIG_SWAP is not set +CONFIG_SWCONFIG=y +CONFIG_SWIOTLB=y +CONFIG_SWP_EMULATE=y +# CONFIG_SW_SYNC is not set +# CONFIG_SYNC is not set +CONFIG_INET_TABLE_PERTURB_ORDER=16 +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_TEST_BLACKHOLE_DEV is not set +# CONFIG_TEST_DYNAMIC_DEBUG is not set +# CONFIG_TEST_MEMCAT_P is not set +# CONFIG_TEST_MEMINIT is not set +# CONFIG_TEST_STACKINIT is not set +# CONFIG_TEST_STRSCPY is not set +# CONFIG_TEST_VMALLOC is not set +# CONFIG_TEST_XARRAY is not set +# CONFIG_TEST_MAPLE_TREE is not set +# CONFIG_NVME_MULTIPATH is not set +# CONFIG_ARM_MHU_V2 is not set +# CONFIG_HISI_PCIE_PMU is not set +# CONFIG_HNS3_PMU is not set +# CONFIG_HISI_PTT is not set +# CONFIG_ETM4X_IMPDEF_FEATURE is not set +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +# CONFIG_THUMB2_KERNEL is not set +# CONFIG_TICK_CPU_ACCOUNTING is not set +# CONFIG_TI_ADS124S08 is not set +# CONFIG_TI_ADS8344 is not set +# CONFIG_TI_CPSW_PHY_SEL is not set +# CONFIG_TI_DAC7311 is not set +# CONFIG_TI_DAC7612 is not set +CONFIG_TRACING_EVENTS_GPIO=y +# CONFIG_TRUSTED_FOUNDATIONS is not set +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_XATTR=y +CONFIG_UBIFS_FS_XZ=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_ZSTD is not set +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +# CONFIG_UNICODE is not set +CONFIG_UNINLINE_SPIN_UNLOCK=y +# CONFIG_UNMAP_KERNEL_AT_EL0 is not set +CONFIG_UNWINDER_ARM=y +# CONFIG_UNWINDER_FRAME_POINTER is not set +# CONFIG_USB_BAM is not set +CONFIG_USB_CONFIGFS=y +# CONFIG_USB_CONFIGFS_ACM is not set +# CONFIG_USB_CONFIGFS_ECM is not set +# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set +# CONFIG_USB_CONFIGFS_EEM is not set +# CONFIG_USB_CONFIGFS_F_DIAG is not set +# CONFIG_USB_CONFIGFS_F_FS is not set +# CONFIG_USB_CONFIGFS_F_HID is not set +# CONFIG_USB_CONFIGFS_F_LB_SS is not set +# CONFIG_USB_CONFIGFS_F_MIDI is not set +# CONFIG_USB_CONFIGFS_F_PRINTER is not set +# CONFIG_USB_CONFIGFS_F_QDSS is not set +# CONFIG_USB_CONFIGFS_F_UAC1 is not set +# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set +# CONFIG_USB_CONFIGFS_F_UAC2 is not set +# CONFIG_USB_CONFIGFS_MASS_STORAGE is not set +# CONFIG_USB_CONFIGFS_NCM is not set +# CONFIG_USB_CONFIGFS_OBEX is not set +# CONFIG_USB_CONFIGFS_RNDIS is not set +# CONFIG_USB_CONFIGFS_SERIAL is not set +# CONFIG_USB_CONN_GPIO is not set +# CONFIG_USB_DWC3_OF_SIMPLE is not set +# CONFIG_USB_EHCI_FSL is not set +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_NET_AQC111 is not set +# CONFIG_USB_OHCI_LITTLE_ENDIAN is not set +# CONFIG_USB_QCA_M31_PHY is not set +# CONFIG_USB_QCOM_8X16_PHY is not set +# CONFIG_USB_QCOM_QMP_PHY is not set +# CONFIG_USB_QCOM_QUSB_PHY is not set +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +# CONFIG_U_SERIAL_CONSOLE is not set +# CONFIG_VALIDATE_FS_PARSER is not set +# CONFIG_VCNL4035 is not set +CONFIG_VDSO=y +CONFIG_VECTORS_BASE=0xffff0000 +# CONFIG_VFIO is not set +CONFIG_VFP=y +CONFIG_VFPv3=y +# CONFIG_VMWARE_VMCI is not set +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +# CONFIG_WL_TI is not set +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_WWAN=y +# CONFIG_WWAN_DEBUGFS is not set +CONFIG_X509_CERTIFICATE_PARSER=y +# CONFIG_XILINX_SDFEC is not set +# CONFIG_XILINX_XADC is not set +CONFIG_XPS=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA32=y +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y +CONFIG_AQUANTIA_PHY=y +CONFIG_AT803X_PHY=y +CONFIG_MDIO_IPQ4019=y +CONFIG_QTI_TZ_LOG=y +CONFIG_QTI_LICENSE_MANAGER=y +# CONFIG_VIRT_WIFI is not set +# CONFIG_FIPS_SIGNATURE_SELFTEST is not set +# CONFIG_QTI_APSS_ACC is not set +# CONFIG_DEBUG_MEM_USAGE is not set +# CONFIG_SLAB_FREELIST_HARDENED is not set +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_ARM64_MODULE_PLTS is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +# CONFIG_SYMBOLIC_ERRNAME is not set +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set +# CONFIG_LEDS_CLASS_MULTICOLOR is not set +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set +# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set +# CONFIG_RANDOM_TRUST_CPU is not set +# CONFIG_ADVISE_SYSCALLS is not set +# CONFIG_AIO is not set +# CONFIG_ARM64_TAGGED_ADDR_ABI is not set +# CONFIG_BLK_DEV_THROTTLING is not set +# CONFIG_BPF_JIT is not set +# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set +# CONFIG_CGROUP_BPF is not set +# CONFIG_CGROUP_RDMA is not set +# CONFIG_CRC8 is not set +# CONFIG_DAX is not set +# CONFIG_EXT4_USE_FOR_EXT2 is not set +# CONFIG_FANOTIFY is not set +# CONFIG_FHANDLE is not set +# CONFIG_IO_URING is not set +# CONFIG_IP_PIMSM_V1 is not set +# CONFIG_IP_PIMSM_V2 is not set +# CONFIG_RAS is not set +# CONFIG_SECCOMP is not set +# CONFIG_SND_PROC_FS is not set +# CONFIG_OPTIMIZE_INLINING is not set diff --git a/target/linux/ipq95xx/generic/config-default b/target/linux/ipq95xx/generic/config-default new file mode 100644 index 00000000000000..a81cec0635a23a --- /dev/null +++ b/target/linux/ipq95xx/generic/config-default @@ -0,0 +1,70 @@ +# CONFIG_32BIT is not set +CONFIG_64BIT=y +# CONFIG_ACPI is not set +# CONFIG_ARCH_BCM_IPROC is not set +# CONFIG_ARCH_EXYNOS7 is not set +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y +# CONFIG_ARCH_LAYERSCAPE is not set +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +# CONFIG_ARCH_SEATTLE is not set +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +# CONFIG_ARCH_SPRD is not set +# CONFIG_ARCH_STRATIX10 is not set +# CONFIG_ARCH_THUNDER is not set +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +# CONFIG_ARCH_XGENE is not set +# CONFIG_ARCH_ZYNQMP is not set +CONFIG_ARM64=y +# CONFIG_ARM64_16K_PAGES is not set +CONFIG_ARM64_4K_PAGES=y +# CONFIG_ARM64_64K_PAGES is not set +# CONFIG_ARM64_CRYPTO is not set +# CONFIG_ARM64_ERRATUM_819472 is not set +# CONFIG_ARM64_ERRATUM_824069 is not set +# CONFIG_ARM64_ERRATUM_826319 is not set +# CONFIG_ARM64_ERRATUM_827319 is not set +# CONFIG_ARM64_ERRATUM_832075 is not set +# CONFIG_ARM64_ERRATUM_843419 is not set +# CONFIG_ARM64_ERRATUM_845719 is not set +CONFIG_ARM64_HW_AFDBM=y +# CONFIG_ARM64_LSE_ATOMICS is not set +CONFIG_ARM64_PAN=y +# CONFIG_ARM64_PTDUMP is not set +# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set +CONFIG_ARM64_VA_BITS=39 +CONFIG_ARM64_VA_BITS_39=y +# CONFIG_ARM64_VA_BITS_48 is not set +# CONFIG_ARMV8_DEPRECATED is not set +# CONFIG_CAVIUM_ERRATUM_22375 is not set +# CONFIG_CAVIUM_ERRATUM_23154 is not set +# CONFIG_CAVIUM_ERRATUM_27456 is not set +# CONFIG_COMMON_CLK_VERSATILE is not set +CONFIG_COMMON_CLK_XGENE=y +CONFIG_COMPAT=y +CONFIG_COMPAT_BINFMT_ELF=y +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set +# CONFIG_DEBUG_ALIGN_RODATA is not set +CONFIG_FRAME_WARN=2048 +# CONFIG_GPIO_XGENE is not set +# CONFIG_HUGETLBFS is not set +# CONFIG_I2C_CADENCE is not set +# CONFIG_KASAN is not set +# CONFIG_KVM is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_PCI_HISI is not set +CONFIG_PHYS_ADDR_T_64BIT=y +# CONFIG_PHY_XGENE is not set +# CONFIG_POWER_RESET_XGENE is not set +CONFIG_QCOM_SCM_64=y +# CONFIG_RTC_DRV_EFI is not set +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_VIRTUALIZATION=y diff --git a/target/linux/ipq95xx/generic/target.mk b/target/linux/ipq95xx/generic/target.mk new file mode 100644 index 00000000000000..9de98feff463aa --- /dev/null +++ b/target/linux/ipq95xx/generic/target.mk @@ -0,0 +1,8 @@ + +SUBTARGET:=generic +BOARDNAME:=QTI IPQ95xx(64bit) based boards +CPU_TYPE:=cortex-a73 + +define Target/Description + Build images for IPQ95xx 64 bit system. +endef diff --git a/target/linux/ipq95xx/image/Makefile b/target/linux/ipq95xx/image/Makefile new file mode 100644 index 00000000000000..3989e31139328e --- /dev/null +++ b/target/linux/ipq95xx/image/Makefile @@ -0,0 +1,35 @@ +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +define Device/Default + PROFILES := Default + DTS_DIR := $(LINUX_DIR)/arch/$(LINUX_KARCH)/boot/dts/$(if $(CONFIG_TARGET_ipq95xx_generic),qcom) + KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts) + KERNEL_LOADADDR := 0x40000000 + DEVICE_DTS = $$(SOC)-$(lastword $(subst _, ,$(1))) + DEVICE_DTS_CONFIG := config-1 + IMAGES := sysupgrade.bin + IMAGE/sysupgrade.bin = sysupgrade-tar | append-metadata + IMAGE/sysupgrade.bin/squashfs := +endef + +define Device/FitImage + KERNEL_SUFFIX := -fit-uImage.itb + KERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb + KERNEL_NAME := Image +endef + +define Device/FitImageLzma + KERNEL_SUFFIX := -fit-uImage.itb + KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb + KERNEL_NAME := Image +endef + +include generic.mk + +define Image/Build + $(call Image/Build/$(1),$(1)) + dd if=$(KDIR)/root$(2).$(1) of=$(BIN_DIR)/$(IMG_PREFIX)-$(1)-root$(3).img bs=2k conv=sync +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/ipq95xx/image/generic.mk b/target/linux/ipq95xx/image/generic.mk new file mode 100644 index 00000000000000..765ed06026ac72 --- /dev/null +++ b/target/linux/ipq95xx/image/generic.mk @@ -0,0 +1,14 @@ +define Device/qcom_rdp433 + $(call Device/FitImageLzma) + DEVICE_VENDOR := QTI + DEVICE_MODEL := RDP433 + DEVICE_VARIANT := AP-AL02-C4 + BOARD_NAME := ap-al02.1-c4 + BUILD_DTS_ipq9574-rdp433 := 1 + SOC := ipq9574 + KERNEL_INSTALL := 1 + KERNEL_SIZE := 6096k + IMAGE_SIZE := 25344k + IMAGE/sysupgrade.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-rootfs | pad-rootfs | append-metadata +endef +TARGET_DEVICES += qcom_rdp433 diff --git a/target/linux/ipq95xx/patches-6.1/0001-soc-qcom-smd-rpm-Add-IPQ9574-compatible.patch b/target/linux/ipq95xx/patches-6.1/0001-soc-qcom-smd-rpm-Add-IPQ9574-compatible.patch new file mode 100644 index 00000000000000..588876d6601880 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0001-soc-qcom-smd-rpm-Add-IPQ9574-compatible.patch @@ -0,0 +1,27 @@ +From d86de60f5e324034e1e917881ff0b46f2f9f00e7 Mon Sep 17 00:00:00 2001 +From: devi priya +Date: Fri, 13 Jan 2023 20:33:05 +0530 +Subject: [PATCH 01/41] soc: qcom: smd-rpm: Add IPQ9574 compatible + +Adding compatible string to support RPM communication over SMD for +IPQ9574 SoC + +Co-developed-by: Praveenkumar I +Signed-off-by: Praveenkumar I +Signed-off-by: devi priya +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230113150310.29709-2-quic_devipriy@quicinc.com +--- + drivers/soc/qcom/smd-rpm.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/soc/qcom/smd-rpm.c ++++ b/drivers/soc/qcom/smd-rpm.c +@@ -233,6 +233,7 @@ static void qcom_smd_rpm_remove(struct r + static const struct of_device_id qcom_smd_rpm_of_match[] = { + { .compatible = "qcom,rpm-apq8084" }, + { .compatible = "qcom,rpm-ipq6018" }, ++ { .compatible = "qcom,rpm-ipq9574" }, + { .compatible = "qcom,rpm-msm8226" }, + { .compatible = "qcom,rpm-msm8909" }, + { .compatible = "qcom,rpm-msm8916" }, diff --git a/target/linux/ipq95xx/patches-6.1/0002-clk-qcom-apss-ipq-pll-refactor-the-driver-to-accommo.patch b/target/linux/ipq95xx/patches-6.1/0002-clk-qcom-apss-ipq-pll-refactor-the-driver-to-accommo.patch new file mode 100644 index 00000000000000..ed74634c4c0b3e --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0002-clk-qcom-apss-ipq-pll-refactor-the-driver-to-accommo.patch @@ -0,0 +1,122 @@ +From 19cd9f8fc024ba70659411f00fd8c4f4a3814647 Mon Sep 17 00:00:00 2001 +From: Kathiravan T +Date: Fri, 17 Feb 2023 14:03:04 +0530 +Subject: [PATCH 02/41] clk: qcom: apss-ipq-pll: refactor the driver to + accommodate different PLL types + +APSS PLL found on the IPQ8074 and IPQ6018 are of type Huayra PLL. But, +IPQ5332 APSS PLL is of type Stromer Plus. To accommodate both these PLLs, +refactor the driver to take the clk_alpha_pll, alpha_pll_config via driver +data. + +Reviewed-by: Konrad Dybcio +Signed-off-by: Kathiravan T +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230217083308.12017-2-quic_kathirav@quicinc.com +--- + drivers/clk/qcom/apss-ipq-pll.c | 60 ++++++++++++++++++++++----------- + 1 file changed, 41 insertions(+), 19 deletions(-) + +--- a/drivers/clk/qcom/apss-ipq-pll.c ++++ b/drivers/clk/qcom/apss-ipq-pll.c +@@ -8,20 +8,27 @@ + + #include "clk-alpha-pll.h" + +-static const u8 ipq_pll_offsets[] = { +- [PLL_OFF_L_VAL] = 0x08, +- [PLL_OFF_ALPHA_VAL] = 0x10, +- [PLL_OFF_USER_CTL] = 0x18, +- [PLL_OFF_CONFIG_CTL] = 0x20, +- [PLL_OFF_CONFIG_CTL_U] = 0x24, +- [PLL_OFF_STATUS] = 0x28, +- [PLL_OFF_TEST_CTL] = 0x30, +- [PLL_OFF_TEST_CTL_U] = 0x34, ++/* ++ * Even though APSS PLL type is of existing one (like Huayra), its offsets ++ * are different from the one mentioned in the clk-alpha-pll.c, since the ++ * PLL is specific to APSS, so lets the define the same. ++ */ ++static const u8 ipq_pll_offsets[][PLL_OFF_MAX_REGS] = { ++ [CLK_ALPHA_PLL_TYPE_HUAYRA] = { ++ [PLL_OFF_L_VAL] = 0x08, ++ [PLL_OFF_ALPHA_VAL] = 0x10, ++ [PLL_OFF_USER_CTL] = 0x18, ++ [PLL_OFF_CONFIG_CTL] = 0x20, ++ [PLL_OFF_CONFIG_CTL_U] = 0x24, ++ [PLL_OFF_STATUS] = 0x28, ++ [PLL_OFF_TEST_CTL] = 0x30, ++ [PLL_OFF_TEST_CTL_U] = 0x34, ++ }, + }; + +-static struct clk_alpha_pll ipq_pll = { ++static struct clk_alpha_pll ipq_pll_huayra = { + .offset = 0x0, +- .regs = ipq_pll_offsets, ++ .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_HUAYRA], + .flags = SUPPORTS_DYNAMIC_UPDATE, + .clkr = { + .enable_reg = 0x0, +@@ -61,6 +68,21 @@ static const struct alpha_pll_config ipq + .test_ctl_hi_val = 0x4000, + }; + ++struct apss_pll_data { ++ struct clk_alpha_pll *pll; ++ const struct alpha_pll_config *pll_config; ++}; ++ ++static struct apss_pll_data ipq8074_pll_data = { ++ .pll = &ipq_pll_huayra, ++ .pll_config = &ipq8074_pll_config, ++}; ++ ++static struct apss_pll_data ipq6018_pll_data = { ++ .pll = &ipq_pll_huayra, ++ .pll_config = &ipq6018_pll_config, ++}; ++ + static const struct regmap_config ipq_pll_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, +@@ -71,7 +93,7 @@ static const struct regmap_config ipq_pl + + static int apss_ipq_pll_probe(struct platform_device *pdev) + { +- const struct alpha_pll_config *ipq_pll_config; ++ const struct apss_pll_data *data; + struct device *dev = &pdev->dev; + struct regmap *regmap; + void __iomem *base; +@@ -85,23 +107,23 @@ static int apss_ipq_pll_probe(struct pla + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + +- ipq_pll_config = of_device_get_match_data(&pdev->dev); +- if (!ipq_pll_config) ++ data = of_device_get_match_data(&pdev->dev); ++ if (!data) + return -ENODEV; + +- clk_alpha_pll_configure(&ipq_pll, regmap, ipq_pll_config); ++ clk_alpha_pll_configure(data->pll, regmap, data->pll_config); + +- ret = devm_clk_register_regmap(dev, &ipq_pll.clkr); ++ ret = devm_clk_register_regmap(dev, &data->pll->clkr); + if (ret) + return ret; + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, +- &ipq_pll.clkr.hw); ++ &data->pll->clkr.hw); + } + + static const struct of_device_id apss_ipq_pll_match_table[] = { +- { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_config }, +- { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_config }, ++ { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data }, ++ { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data }, + { } + }; + MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table); diff --git a/target/linux/ipq95xx/patches-6.1/0003-clk-qcom-clk-alpha-pll-Add-support-for-Stromer-PLLs.patch b/target/linux/ipq95xx/patches-6.1/0003-clk-qcom-clk-alpha-pll-Add-support-for-Stromer-PLLs.patch new file mode 100644 index 00000000000000..efbfad7d1d8309 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0003-clk-qcom-clk-alpha-pll-Add-support-for-Stromer-PLLs.patch @@ -0,0 +1,222 @@ +From 5bd9fcb9c152a9ed0c9bb22e403d4df359faad7b Mon Sep 17 00:00:00 2001 +From: Varadarajan Narayanan +Date: Tue, 7 Mar 2023 11:52:24 +0530 +Subject: [PATCH 03/41] clk: qcom: clk-alpha-pll: Add support for Stromer PLLs + +Add programming sequence support for managing the Stromer +PLLs. + +Reviewed-by: Stephen Boyd +Co-developed-by: Sricharan R +Signed-off-by: Sricharan R +Signed-off-by: Varadarajan Narayanan +Signed-off-by: Kathiravan T +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230307062232.4889-2-quic_kathirav@quicinc.com +--- + drivers/clk/qcom/clk-alpha-pll.c | 128 ++++++++++++++++++++++++++++++- + drivers/clk/qcom/clk-alpha-pll.h | 13 +++- + 2 files changed, 139 insertions(+), 2 deletions(-) + +--- a/drivers/clk/qcom/clk-alpha-pll.c ++++ b/drivers/clk/qcom/clk-alpha-pll.c +@@ -1,7 +1,7 @@ + // SPDX-License-Identifier: GPL-2.0 + /* + * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. +- * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. ++ * Copyright (c) 2021, 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + + #include +@@ -188,6 +188,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MA + [PLL_OFF_CONFIG_CTL] = 0x1C, + [PLL_OFF_STATUS] = 0x20, + }, ++ [CLK_ALPHA_PLL_TYPE_STROMER] = { ++ [PLL_OFF_L_VAL] = 0x08, ++ [PLL_OFF_ALPHA_VAL] = 0x10, ++ [PLL_OFF_ALPHA_VAL_U] = 0x14, ++ [PLL_OFF_USER_CTL] = 0x18, ++ [PLL_OFF_USER_CTL_U] = 0x1c, ++ [PLL_OFF_CONFIG_CTL] = 0x20, ++ [PLL_OFF_CONFIG_CTL_U] = 0xff, ++ [PLL_OFF_TEST_CTL] = 0x30, ++ [PLL_OFF_TEST_CTL_U] = 0x34, ++ [PLL_OFF_STATUS] = 0x28, ++ }, + }; + EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); + +@@ -199,6 +211,8 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); + #define ALPHA_BITWIDTH 32U + #define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH) + ++#define ALPHA_PLL_STATUS_REG_SHIFT 8 ++ + #define PLL_HUAYRA_M_WIDTH 8 + #define PLL_HUAYRA_M_SHIFT 8 + #define PLL_HUAYRA_M_MASK 0xff +@@ -2308,3 +2322,115 @@ const struct clk_ops clk_alpha_pll_rivia + .round_rate = clk_rivian_evo_pll_round_rate, + }; + EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops); ++ ++void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, ++ const struct alpha_pll_config *config) ++{ ++ u32 val, val_u, mask, mask_u; ++ ++ regmap_write(regmap, PLL_L_VAL(pll), config->l); ++ regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); ++ regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val); ++ ++ if (pll_has_64bit_config(pll)) ++ regmap_write(regmap, PLL_CONFIG_CTL_U(pll), ++ config->config_ctl_hi_val); ++ ++ if (pll_alpha_width(pll) > 32) ++ regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi); ++ ++ val = config->main_output_mask; ++ val |= config->aux_output_mask; ++ val |= config->aux2_output_mask; ++ val |= config->early_output_mask; ++ val |= config->pre_div_val; ++ val |= config->post_div_val; ++ val |= config->vco_val; ++ val |= config->alpha_en_mask; ++ val |= config->alpha_mode_mask; ++ ++ mask = config->main_output_mask; ++ mask |= config->aux_output_mask; ++ mask |= config->aux2_output_mask; ++ mask |= config->early_output_mask; ++ mask |= config->pre_div_mask; ++ mask |= config->post_div_mask; ++ mask |= config->vco_mask; ++ mask |= config->alpha_en_mask; ++ mask |= config->alpha_mode_mask; ++ ++ regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); ++ ++ /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */ ++ val_u = config->status_val << ALPHA_PLL_STATUS_REG_SHIFT; ++ val_u |= config->lock_det; ++ ++ mask_u = config->status_mask; ++ mask_u |= config->lock_det; ++ ++ regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u); ++ regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); ++ regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); ++ ++ if (pll->flags & SUPPORTS_FSM_MODE) ++ qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); ++} ++EXPORT_SYMBOL_GPL(clk_stromer_pll_configure); ++ ++static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ u32 l; ++ u64 a; ++ ++ req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, ++ &l, &a, ALPHA_REG_BITWIDTH); ++ ++ return 0; ++} ++ ++static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long prate) ++{ ++ struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); ++ int ret; ++ u32 l; ++ u64 a; ++ ++ rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH); ++ ++ regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); ++ regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); ++ regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), ++ a >> ALPHA_BITWIDTH); ++ ++ regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), ++ PLL_ALPHA_EN, PLL_ALPHA_EN); ++ ++ if (!clk_hw_is_enabled(hw)) ++ return 0; ++ ++ /* ++ * Stromer PLL supports Dynamic programming. ++ * It allows the PLL frequency to be changed on-the-fly without first ++ * execution of a shutdown procedure followed by a bring up procedure. ++ */ ++ regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, ++ PLL_UPDATE); ++ ++ ret = wait_for_pll_update(pll); ++ if (ret) ++ return ret; ++ ++ return wait_for_pll_enable_lock(pll); ++} ++ ++const struct clk_ops clk_alpha_pll_stromer_ops = { ++ .enable = clk_alpha_pll_enable, ++ .disable = clk_alpha_pll_disable, ++ .is_enabled = clk_alpha_pll_is_enabled, ++ .recalc_rate = clk_alpha_pll_recalc_rate, ++ .determine_rate = clk_alpha_pll_stromer_determine_rate, ++ .set_rate = clk_alpha_pll_stromer_set_rate, ++}; ++EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops); +--- a/drivers/clk/qcom/clk-alpha-pll.h ++++ b/drivers/clk/qcom/clk-alpha-pll.h +@@ -1,5 +1,9 @@ + /* SPDX-License-Identifier: GPL-2.0 */ +-/* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. */ ++/* ++ * Copyright (c) 2015, 2018, 2021 The Linux Foundation. All rights reserved. ++ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ + + #ifndef __QCOM_CLK_ALPHA_PLL_H__ + #define __QCOM_CLK_ALPHA_PLL_H__ +@@ -21,6 +25,7 @@ enum { + CLK_ALPHA_PLL_TYPE_RIVIAN_EVO, + CLK_ALPHA_PLL_TYPE_DEFAULT_EVO, + CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, ++ CLK_ALPHA_PLL_TYPE_STROMER, + CLK_ALPHA_PLL_TYPE_MAX, + }; + +@@ -128,6 +133,9 @@ struct alpha_pll_config { + u32 post_div_mask; + u32 vco_val; + u32 vco_mask; ++ u32 status_val; ++ u32 status_mask; ++ u32 lock_det; + }; + + extern const struct clk_ops clk_alpha_pll_ops; +@@ -136,6 +144,7 @@ extern const struct clk_ops clk_alpha_pl + extern const struct clk_ops clk_alpha_pll_postdiv_ops; + extern const struct clk_ops clk_alpha_pll_huayra_ops; + extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops; ++extern const struct clk_ops clk_alpha_pll_stromer_ops; + + extern const struct clk_ops clk_alpha_pll_fabia_ops; + extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops; +@@ -182,5 +191,7 @@ void clk_lucid_evo_pll_configure(struct + const struct alpha_pll_config *config); + void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config); ++void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, ++ const struct alpha_pll_config *config); + + #endif diff --git a/target/linux/ipq95xx/patches-6.1/0004-soc-qcom-socinfo-Add-IDs-for-IPQ9574-and-its-variant.patch b/target/linux/ipq95xx/patches-6.1/0004-soc-qcom-socinfo-Add-IDs-for-IPQ9574-and-its-variant.patch new file mode 100644 index 00000000000000..e44adb3cb95841 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0004-soc-qcom-socinfo-Add-IDs-for-IPQ9574-and-its-variant.patch @@ -0,0 +1,33 @@ +From d1429c2349b80274255a676404d15bb2e25fa4b9 Mon Sep 17 00:00:00 2001 +From: Varadarajan Narayanan +Date: Tue, 14 Mar 2023 11:43:34 +0530 +Subject: [PATCH 04/41] soc: qcom: socinfo: Add IDs for IPQ9574 and its + variants + +Add SOC ID for Qualcomm IPQ9574, IPQ9570, IPQ9554, IPQ9550, +IPQ9514 and IPQ9510 + +Signed-off-by: Varadarajan Narayanan +Reviewed-by: Krzysztof Kozlowski +Reviewed-by: Kathiravan T +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/1678774414-14414-3-git-send-email-quic_varada@quicinc.com +--- + drivers/soc/qcom/socinfo.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/soc/qcom/socinfo.c ++++ b/drivers/soc/qcom/socinfo.c +@@ -280,6 +280,12 @@ static const struct soc_id soc_id[] = { + { 487, "SC7280" }, + { 495, "SC7180P" }, + { 507, "SM6375" }, ++ { 510, "IPQ9514" }, ++ { 511, "IPQ9550" }, ++ { 512, "IPQ9554" }, ++ { 513, "IPQ9570" }, ++ { 514, "IPQ9574" }, ++ { 521, "IPQ9510" }, + }; + + static const char *socinfo_machine(struct device *dev, unsigned int id) diff --git a/target/linux/ipq95xx/patches-6.1/0005-arm64-dts-qcom-Add-ipq9574-SoC-and-AL02-board-suppor.patch b/target/linux/ipq95xx/patches-6.1/0005-arm64-dts-qcom-Add-ipq9574-SoC-and-AL02-board-suppor.patch new file mode 100644 index 00000000000000..ec922ee88bc662 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0005-arm64-dts-qcom-Add-ipq9574-SoC-and-AL02-board-suppor.patch @@ -0,0 +1,393 @@ +From 036302b2ff40f3922ce839b44c4c731cb52d8766 Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Thu, 16 Mar 2023 12:59:39 +0530 +Subject: [PATCH 05/41] arm64: dts: qcom: Add ipq9574 SoC and AL02 board + support + +Add initial device tree support for Qualcomm IPQ9574 SoC and AL02 board + +Co-developed-by: Anusha Rao +Signed-off-by: Anusha Rao +Co-developed-by: Poovendhan Selvaraj +Signed-off-by: Poovendhan Selvaraj +Signed-off-by: Devi Priya +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230316072940.29137-6-quic_devipriy@quicinc.com +--- + arch/arm64/boot/dts/qcom/Makefile | 1 + + arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 84 ++++++ + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 270 +++++++++++++++++++ + 3 files changed, 355 insertions(+) + create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts + create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi + +--- a/arch/arm64/boot/dts/qcom/Makefile ++++ b/arch/arm64/boot/dts/qcom/Makefile +@@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01- + dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb + dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb + dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb ++dtb-$(CONFIG_ARCH_QCOM) += ipq9574-al02-c7.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8916-huawei-g7.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts +@@ -0,0 +1,84 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * IPQ9574 AL02-C7 board device tree source ++ * ++ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. ++ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++/dts-v1/; ++ ++#include "ipq9574.dtsi" ++ ++/ { ++ model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7"; ++ compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574"; ++ ++ aliases { ++ serial0 = &blsp1_uart2; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++}; ++ ++&blsp1_uart2 { ++ pinctrl-0 = <&uart2_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&sdhc_1 { ++ pinctrl-0 = <&sdc_default_state>; ++ pinctrl-names = "default"; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ max-frequency = <384000000>; ++ bus-width = <8>; ++ status = "okay"; ++}; ++ ++&sleep_clk { ++ clock-frequency = <32000>; ++}; ++ ++&tlmm { ++ sdc_default_state: sdc-default-state { ++ clk-pins { ++ pins = "gpio5"; ++ function = "sdc_clk"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ ++ cmd-pins { ++ pins = "gpio4"; ++ function = "sdc_cmd"; ++ drive-strength = <8>; ++ bias-pull-up; ++ }; ++ ++ data-pins { ++ pins = "gpio0", "gpio1", "gpio2", ++ "gpio3", "gpio6", "gpio7", ++ "gpio8", "gpio9"; ++ function = "sdc_data"; ++ drive-strength = <8>; ++ bias-pull-up; ++ }; ++ ++ rclk-pins { ++ pins = "gpio10"; ++ function = "sdc_rclk"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ }; ++}; ++ ++&xo_board_clk { ++ clock-frequency = <24000000>; ++}; +--- /dev/null ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -0,0 +1,270 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * IPQ9574 SoC device tree source ++ * ++ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. ++ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++ ++/ { ++ interrupt-parent = <&intc>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ clocks { ++ bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk { ++ compatible = "fixed-clock"; ++ clock-frequency = <353000000>; ++ #clock-cells = <0>; ++ }; ++ ++ sleep_clk: sleep-clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ }; ++ ++ xo_board_clk: xo-board-clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ }; ++ }; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ CPU0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a73"; ++ reg = <0x0>; ++ enable-method = "psci"; ++ next-level-cache = <&L2_0>; ++ }; ++ ++ CPU1: cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a73"; ++ reg = <0x1>; ++ enable-method = "psci"; ++ next-level-cache = <&L2_0>; ++ }; ++ ++ CPU2: cpu@2 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a73"; ++ reg = <0x2>; ++ enable-method = "psci"; ++ next-level-cache = <&L2_0>; ++ }; ++ ++ CPU3: cpu@3 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a73"; ++ reg = <0x3>; ++ enable-method = "psci"; ++ next-level-cache = <&L2_0>; ++ }; ++ ++ L2_0: l2-cache { ++ compatible = "cache"; ++ cache-level = <2>; ++ }; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ /* We expect the bootloader to fill in the size */ ++ reg = <0x0 0x40000000 0x0 0x0>; ++ }; ++ ++ pmu { ++ compatible = "arm,cortex-a73-pmu"; ++ interrupts = ; ++ }; ++ ++ psci { ++ compatible = "arm,psci-1.0"; ++ method = "smc"; ++ }; ++ ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ tz_region: tz@4a600000 { ++ reg = <0x0 0x4a600000 0x0 0x400000>; ++ no-map; ++ }; ++ }; ++ ++ soc: soc@0 { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0 0 0xffffffff>; ++ ++ tlmm: pinctrl@1000000 { ++ compatible = "qcom,ipq9574-tlmm"; ++ reg = <0x01000000 0x300000>; ++ interrupts = ; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-ranges = <&tlmm 0 0 65>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ ++ uart2_pins: uart2-state { ++ pins = "gpio34", "gpio35"; ++ function = "blsp2_uart"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ }; ++ ++ gcc: clock-controller@1800000 { ++ compatible = "qcom,ipq9574-gcc"; ++ reg = <0x01800000 0x80000>; ++ clocks = <&xo_board_clk>, ++ <&sleep_clk>, ++ <&bias_pll_ubi_nc_clk>, ++ <0>, ++ <0>, ++ <0>, ++ <0>, ++ <0>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ #power-domain-cells = <1>; ++ }; ++ ++ sdhc_1: mmc@7804000 { ++ compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; ++ reg = <0x07804000 0x1000>, <0x07805000 0x1000>; ++ reg-names = "hc", "cqhci"; ++ ++ interrupts = , ++ ; ++ interrupt-names = "hc_irq", "pwr_irq"; ++ ++ clocks = <&gcc GCC_SDCC1_AHB_CLK>, ++ <&gcc GCC_SDCC1_APPS_CLK>, ++ <&xo_board_clk>; ++ clock-names = "iface", "core", "xo"; ++ non-removable; ++ status = "disabled"; ++ }; ++ ++ blsp1_uart2: serial@78b1000 { ++ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; ++ reg = <0x078b1000 0x200>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ status = "disabled"; ++ }; ++ ++ intc: interrupt-controller@b000000 { ++ compatible = "qcom,msm-qgic2"; ++ reg = <0x0b000000 0x1000>, /* GICD */ ++ <0x0b002000 0x1000>, /* GICC */ ++ <0x0b001000 0x1000>, /* GICH */ ++ <0x0b004000 0x1000>; /* GICV */ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ interrupts = ; ++ ranges = <0 0x0b00c000 0x3000>; ++ ++ v2m0: v2m@0 { ++ compatible = "arm,gic-v2m-frame"; ++ reg = <0x00000000 0xffd>; ++ msi-controller; ++ }; ++ ++ v2m1: v2m@1000 { ++ compatible = "arm,gic-v2m-frame"; ++ reg = <0x00001000 0xffd>; ++ msi-controller; ++ }; ++ ++ v2m2: v2m@2000 { ++ compatible = "arm,gic-v2m-frame"; ++ reg = <0x00002000 0xffd>; ++ msi-controller; ++ }; ++ }; ++ ++ timer@b120000 { ++ compatible = "arm,armv7-timer-mem"; ++ reg = <0x0b120000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ frame@b120000 { ++ reg = <0x0b121000 0x1000>, ++ <0x0b122000 0x1000>; ++ frame-number = <0>; ++ interrupts = , ++ ; ++ }; ++ ++ frame@b123000 { ++ reg = <0x0b123000 0x1000>; ++ frame-number = <1>; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ ++ frame@b124000 { ++ reg = <0x0b124000 0x1000>; ++ frame-number = <2>; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ ++ frame@b125000 { ++ reg = <0x0b125000 0x1000>; ++ frame-number = <3>; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ ++ frame@b126000 { ++ reg = <0x0b126000 0x1000>; ++ frame-number = <4>; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ ++ frame@b127000 { ++ reg = <0x0b127000 0x1000>; ++ frame-number = <5>; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ ++ frame@b128000 { ++ reg = <0x0b128000 0x1000>; ++ frame-number = <6>; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++}; diff --git a/target/linux/ipq95xx/patches-6.1/0006-arm64-defconfig-Enable-IPQ9574-SoC-base-configs.patch b/target/linux/ipq95xx/patches-6.1/0006-arm64-defconfig-Enable-IPQ9574-SoC-base-configs.patch new file mode 100644 index 00000000000000..bcec3db7f3c23d --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0006-arm64-defconfig-Enable-IPQ9574-SoC-base-configs.patch @@ -0,0 +1,33 @@ +From 10899f01cc0a72a2a06b2baa2261c5b898e4a26d Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Thu, 16 Mar 2023 12:59:40 +0530 +Subject: [PATCH 06/41] arm64: defconfig: Enable IPQ9574 SoC base configs + +Enables clk & pinctrl related configs for Qualcomm IPQ9574 SoC + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Devi Priya +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230316072940.29137-7-quic_devipriy@quicinc.com +--- + arch/arm64/configs/defconfig | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm64/configs/defconfig ++++ b/arch/arm64/configs/defconfig +@@ -537,6 +537,7 @@ CONFIG_PINCTRL_IMX93=y + CONFIG_PINCTRL_MSM=y + CONFIG_PINCTRL_IPQ8074=y + CONFIG_PINCTRL_IPQ6018=y ++CONFIG_PINCTRL_IPQ9574=y + CONFIG_PINCTRL_MSM8916=y + CONFIG_PINCTRL_MSM8994=y + CONFIG_PINCTRL_MSM8996=y +@@ -1068,6 +1069,7 @@ CONFIG_QCOM_CLK_SMD_RPM=y + CONFIG_QCOM_CLK_RPMH=y + CONFIG_IPQ_GCC_6018=y + CONFIG_IPQ_GCC_8074=y ++CONFIG_IPQ_GCC_9574=y + CONFIG_MSM_GCC_8916=y + CONFIG_MSM_GCC_8994=y + CONFIG_MSM_MMCC_8996=y diff --git a/target/linux/ipq95xx/patches-6.1/0007-clk-qcom-Add-Global-Clock-Controller-driver-for-IPQ9.patch b/target/linux/ipq95xx/patches-6.1/0007-clk-qcom-Add-Global-Clock-Controller-driver-for-IPQ9.patch new file mode 100644 index 00000000000000..ebd2dce8990410 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0007-clk-qcom-Add-Global-Clock-Controller-driver-for-IPQ9.patch @@ -0,0 +1,4298 @@ +From 443758ff3c5ab0445bc802cb4d4a318691de2917 Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Thu, 16 Mar 2023 12:59:36 +0530 +Subject: [PATCH 07/41] clk: qcom: Add Global Clock Controller driver for + IPQ9574 + +Add Global Clock Controller (GCC) driver for ipq9574 based devices + +Co-developed-by: Anusha Rao +Signed-off-by: Anusha Rao +Signed-off-by: Devi Priya +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230316072940.29137-3-quic_devipriy@quicinc.com +--- + drivers/clk/qcom/Kconfig | 8 + + drivers/clk/qcom/Makefile | 1 + + drivers/clk/qcom/gcc-ipq9574.c | 4248 ++++++++++++++++++++++++++++++++ + 3 files changed, 4257 insertions(+) + create mode 100644 drivers/clk/qcom/gcc-ipq9574.c + +--- a/drivers/clk/qcom/Kconfig ++++ b/drivers/clk/qcom/Kconfig +@@ -174,6 +174,14 @@ config IPQ_GCC_8074 + i2c, USB, SD/eMMC, etc. Select this for the root clock + of ipq8074. + ++config IPQ_GCC_9574 ++ tristate "IPQ9574 Global Clock Controller" ++ help ++ Support for global clock controller on ipq9574 devices. ++ Say Y if you want to use peripheral devices such as UART, SPI, ++ i2c, USB, SD/eMMC, etc. Select this for the root clock ++ of ipq9574. ++ + config MSM_GCC_8660 + tristate "MSM8660 Global Clock Controller" + help +--- a/drivers/clk/qcom/Makefile ++++ b/drivers/clk/qcom/Makefile +@@ -27,6 +27,7 @@ obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq401 + obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o + obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o + obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o ++obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o + obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o + obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o + obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o +--- /dev/null ++++ b/drivers/clk/qcom/gcc-ipq9574.c +@@ -0,0 +1,4248 @@ ++// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++/* ++ * Copyright (c) 2023 The Linux Foundation. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "clk-rcg.h" ++#include "clk-branch.h" ++#include "clk-alpha-pll.h" ++#include "clk-regmap-divider.h" ++#include "clk-regmap-mux.h" ++#include "clk-regmap-phy-mux.h" ++#include "reset.h" ++ ++/* Need to match the order of clocks in DT binding */ ++enum { ++ DT_XO, ++ DT_SLEEP_CLK, ++ DT_BIAS_PLL_UBI_NC_CLK, ++ DT_PCIE30_PHY0_PIPE_CLK, ++ DT_PCIE30_PHY1_PIPE_CLK, ++ DT_PCIE30_PHY2_PIPE_CLK, ++ DT_PCIE30_PHY3_PIPE_CLK, ++ DT_USB3PHY_0_CC_PIPE_CLK, ++}; ++ ++enum { ++ P_XO, ++ P_PCIE30_PHY0_PIPE, ++ P_PCIE30_PHY1_PIPE, ++ P_PCIE30_PHY2_PIPE, ++ P_PCIE30_PHY3_PIPE, ++ P_USB3PHY_0_PIPE, ++ P_GPLL0, ++ P_GPLL0_DIV2, ++ P_GPLL0_OUT_AUX, ++ P_GPLL2, ++ P_GPLL4, ++ P_PI_SLEEP, ++ P_BIAS_PLL_UBI_NC_CLK, ++}; ++ ++static const struct parent_map gcc_xo_map[] = { ++ { P_XO, 0 }, ++}; ++ ++static const struct clk_parent_data gcc_xo_data[] = { ++ { .index = DT_XO }, ++}; ++ ++static const struct clk_parent_data gcc_sleep_clk_data[] = { ++ { .index = DT_SLEEP_CLK }, ++}; ++ ++static struct clk_alpha_pll gpll0_main = { ++ .offset = 0x20000, ++ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], ++ .clkr = { ++ .enable_reg = 0x0b000, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gpll0_main", ++ .parent_data = gcc_xo_data, ++ .num_parents = ARRAY_SIZE(gcc_xo_data), ++ .ops = &clk_alpha_pll_ops, ++ }, ++ }, ++}; ++ ++static struct clk_fixed_factor gpll0_out_main_div2 = { ++ .mult = 1, ++ .div = 2, ++ .hw.init = &(struct clk_init_data) { ++ .name = "gpll0_out_main_div2", ++ .parent_hws = (const struct clk_hw *[]) { ++ &gpll0_main.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_fixed_factor_ops, ++ }, ++}; ++ ++static struct clk_alpha_pll_postdiv gpll0 = { ++ .offset = 0x20000, ++ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], ++ .width = 4, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "gpll0", ++ .parent_hws = (const struct clk_hw *[]) { ++ &gpll0_main.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_alpha_pll_postdiv_ro_ops, ++ }, ++}; ++ ++static struct clk_alpha_pll gpll4_main = { ++ .offset = 0x22000, ++ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], ++ .clkr = { ++ .enable_reg = 0x0b000, ++ .enable_mask = BIT(2), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gpll4_main", ++ .parent_data = gcc_xo_data, ++ .num_parents = ARRAY_SIZE(gcc_xo_data), ++ .ops = &clk_alpha_pll_ops, ++ }, ++ }, ++}; ++ ++static struct clk_alpha_pll_postdiv gpll4 = { ++ .offset = 0x22000, ++ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], ++ .width = 4, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "gpll4", ++ .parent_hws = (const struct clk_hw *[]) { ++ &gpll4_main.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_alpha_pll_postdiv_ro_ops, ++ }, ++}; ++ ++static struct clk_alpha_pll gpll2_main = { ++ .offset = 0x21000, ++ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], ++ .clkr = { ++ .enable_reg = 0x0b000, ++ .enable_mask = BIT(1), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gpll2_main", ++ .parent_data = gcc_xo_data, ++ .num_parents = ARRAY_SIZE(gcc_xo_data), ++ .ops = &clk_alpha_pll_ops, ++ }, ++ }, ++}; ++ ++static struct clk_alpha_pll_postdiv gpll2 = { ++ .offset = 0x21000, ++ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], ++ .width = 4, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "gpll2", ++ .parent_hws = (const struct clk_hw *[]) { ++ &gpll2_main.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_alpha_pll_postdiv_ro_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_sleep_clk_src = { ++ .halt_reg = 0x3400c, ++ .clkr = { ++ .enable_reg = 0x3400c, ++ .enable_mask = BIT(1), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_sleep_clk_src", ++ .parent_data = gcc_sleep_clk_data, ++ .num_parents = ARRAY_SIZE(gcc_sleep_clk_data), ++ .flags = CLK_IS_CRITICAL, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = { ++ { .index = DT_XO }, ++ { .hw = &gpll0.clkr.hw }, ++ { .hw = &gpll0_out_main_div2.hw }, ++}; ++ ++static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL0_DIV2, 4 }, ++}; ++ ++static const struct clk_parent_data gcc_xo_gpll0[] = { ++ { .index = DT_XO }, ++ { .hw = &gpll0.clkr.hw }, ++}; ++ ++static const struct parent_map gcc_xo_gpll0_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++}; ++ ++static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { ++ { .index = DT_XO }, ++ { .hw = &gpll0.clkr.hw }, ++ { .hw = &gpll4.clkr.hw }, ++}; ++ ++static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL4, 2 }, ++}; ++ ++static const struct clk_parent_data gcc_xo_gpll0_gpll0_div2_gpll0[] = { ++ { .index = DT_XO }, ++ { .hw = &gpll0.clkr.hw }, ++ { .hw = &gpll0_out_main_div2.hw }, ++ { .hw = &gpll0.clkr.hw }, ++}; ++ ++static const struct parent_map gcc_xo_gpll0_gpll0_div2_gpll0_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL0_DIV2, 4 }, ++ { P_GPLL0, 5 }, ++}; ++ ++static const struct clk_parent_data gcc_xo_gpll0_gpll0_sleep_clk[] = { ++ { .index = DT_XO }, ++ { .hw = &gpll0.clkr.hw }, ++ { .hw = &gpll0_out_main_div2.hw }, ++ { .index = DT_SLEEP_CLK }, ++}; ++ ++static const struct parent_map gcc_xo_gpll0_gpll0_sleep_clk_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL0_DIV2, 4 }, ++ { P_PI_SLEEP, 6 }, ++}; ++ ++static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = { ++ { .index = DT_XO }, ++ { .hw = &gpll0.clkr.hw }, ++ { .index = DT_SLEEP_CLK }, ++}; ++ ++static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 2 }, ++ { P_PI_SLEEP, 6 }, ++}; ++ ++static const struct clk_parent_data gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk[] = { ++ { .index = DT_XO }, ++ { .hw = &gpll0.clkr.hw }, ++ { .hw = &gpll4.clkr.hw }, ++ { .index = DT_BIAS_PLL_UBI_NC_CLK }, ++}; ++ ++static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL4, 2 }, ++ { P_BIAS_PLL_UBI_NC_CLK, 3 }, ++}; ++ ++static const struct clk_parent_data ++ gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk[] = { ++ { .index = DT_XO }, ++ { .hw = &gpll0.clkr.hw }, ++ { .hw = &gpll0.clkr.hw }, ++ { .index = DT_SLEEP_CLK }, ++}; ++ ++static const struct parent_map ++ gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL0_OUT_AUX, 2 }, ++ { P_PI_SLEEP, 6 }, ++}; ++ ++static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = { ++ { .index = DT_XO }, ++ { .hw = &gpll0.clkr.hw }, ++ { .hw = &gpll0_out_main_div2.hw }, ++}; ++ ++static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL0_DIV2, 4 }, ++}; ++ ++static const struct clk_parent_data ++ gcc_xo_gpll4_gpll0_gpll0_out_main_div2[] = { ++ { .index = DT_XO }, ++ { .hw = &gpll4.clkr.hw }, ++ { .hw = &gpll0.clkr.hw }, ++ { .hw = &gpll0_out_main_div2.hw }, ++}; ++ ++static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL4, 1 }, ++ { P_GPLL0, 3 }, ++ { P_GPLL0_DIV2, 4 }, ++}; ++ ++static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = { ++ { .index = DT_USB3PHY_0_CC_PIPE_CLK }, ++ { .index = DT_XO }, ++}; ++ ++static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = { ++ { P_USB3PHY_0_PIPE, 0 }, ++ { P_XO, 2 }, ++}; ++ ++static const struct clk_parent_data ++ gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = { ++ { .index = DT_XO }, ++ { .hw = &gpll0.clkr.hw }, ++ { .hw = &gpll2.clkr.hw }, ++ { .hw = &gpll0_out_main_div2.hw }, ++}; ++ ++static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL2, 2 }, ++ { P_GPLL0_DIV2, 4 }, ++}; ++ ++static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_div2[] = { ++ { .index = DT_XO}, ++ { .hw = &gpll0.clkr.hw }, ++ { .hw = &gpll4.clkr.hw }, ++ { .hw = &gpll0_out_main_div2.hw }, ++}; ++ ++static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_div2_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL4, 2 }, ++ { P_GPLL0_DIV2, 4 }, ++}; ++ ++static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_div2[] = { ++ { .index = DT_XO }, ++ { .hw = &gpll4.clkr.hw }, ++ { .hw = &gpll0.clkr.hw }, ++ { .hw = &gpll0_out_main_div2.hw }, ++}; ++ ++static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_div2_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL4, 1 }, ++ { P_GPLL0, 2 }, ++ { P_GPLL0_DIV2, 4 }, ++}; ++ ++static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = { ++ { .index = DT_XO }, ++ { .hw = &gpll0.clkr.hw }, ++ { .hw = &gpll2.clkr.hw }, ++}; ++ ++static const struct parent_map gcc_xo_gpll0_gpll2_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL2, 2 }, ++}; ++ ++static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_pi_sleep[] = { ++ { .index = DT_XO }, ++ { .hw = &gpll0.clkr.hw }, ++ { .hw = &gpll2.clkr.hw }, ++ { .hw = &gpll4.clkr.hw }, ++ { .index = DT_SLEEP_CLK }, ++}; ++ ++static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL2, 2 }, ++ { P_GPLL4, 3 }, ++ { P_PI_SLEEP, 6 }, ++}; ++ ++static const struct clk_parent_data gcc_xo_gpll0_gpll0_aux_gpll2[] = { ++ { .index = DT_XO }, ++ { .hw = &gpll0.clkr.hw }, ++ { .hw = &gpll0.clkr.hw }, ++ { .hw = &gpll2.clkr.hw }, ++}; ++ ++static const struct parent_map gcc_xo_gpll0_gpll0_aux_gpll2_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL0_OUT_AUX, 2 }, ++ { P_GPLL2, 3 }, ++}; ++ ++static const struct freq_tbl ftbl_apss_ahb_clk_src[] = { ++ F(24000000, P_XO, 1, 0, 0), ++ F(50000000, P_GPLL0, 16, 0, 0), ++ F(100000000, P_GPLL0, 8, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 apss_ahb_clk_src = { ++ .cmd_rcgr = 0x2400c, ++ .freq_tbl = ftbl_apss_ahb_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "apss_ahb_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_apss_axi_clk_src[] = { ++ F(533000000, P_GPLL0, 1.5, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 apss_axi_clk_src = { ++ .cmd_rcgr = 0x24004, ++ .freq_tbl = ftbl_apss_axi_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_div2_gpll0_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "apss_axi_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_div2_gpll0, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_div2_gpll0), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = { ++ F(9600000, P_XO, 2.5, 0, 0), ++ F(24000000, P_XO, 1, 0, 0), ++ F(50000000, P_GPLL0, 16, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { ++ .cmd_rcgr = 0x02018, ++ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "blsp1_qup1_i2c_apps_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = { ++ F(960000, P_XO, 10, 2, 5), ++ F(4800000, P_XO, 5, 0, 0), ++ F(9600000, P_XO, 2, 4, 5), ++ F(16000000, P_GPLL0, 10, 1, 5), ++ F(24000000, P_XO, 1, 0, 0), ++ F(25000000, P_GPLL0, 16, 1, 2), ++ F(50000000, P_GPLL0, 16, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { ++ .cmd_rcgr = 0x02004, ++ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, ++ .mnd_width = 8, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "blsp1_qup1_spi_apps_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { ++ .cmd_rcgr = 0x03018, ++ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "blsp1_qup2_i2c_apps_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { ++ .cmd_rcgr = 0x03004, ++ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, ++ .mnd_width = 8, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "blsp1_qup2_spi_apps_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { ++ .cmd_rcgr = 0x04018, ++ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "blsp1_qup3_i2c_apps_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { ++ .cmd_rcgr = 0x04004, ++ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, ++ .mnd_width = 8, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "blsp1_qup3_spi_apps_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { ++ .cmd_rcgr = 0x05018, ++ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "blsp1_qup4_i2c_apps_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { ++ .cmd_rcgr = 0x05004, ++ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, ++ .mnd_width = 8, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "blsp1_qup4_spi_apps_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { ++ .cmd_rcgr = 0x06018, ++ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "blsp1_qup5_i2c_apps_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { ++ .cmd_rcgr = 0x06004, ++ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, ++ .mnd_width = 8, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "blsp1_qup5_spi_apps_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { ++ .cmd_rcgr = 0x07018, ++ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "blsp1_qup6_i2c_apps_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { ++ .cmd_rcgr = 0x07004, ++ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, ++ .mnd_width = 8, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "blsp1_qup6_spi_apps_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = { ++ F(3686400, P_GPLL0_DIV2, 1, 144, 15625), ++ F(7372800, P_GPLL0_DIV2, 1, 288, 15625), ++ F(14745600, P_GPLL0_DIV2, 1, 576, 15625), ++ F(24000000, P_XO, 1, 0, 0), ++ F(25000000, P_GPLL0, 16, 1, 2), ++ F(32000000, P_GPLL0, 1, 1, 25), ++ F(40000000, P_GPLL0, 1, 1, 20), ++ F(46400000, P_GPLL0, 1, 29, 500), ++ F(48000000, P_GPLL0, 1, 3, 50), ++ F(51200000, P_GPLL0, 1, 8, 125), ++ F(56000000, P_GPLL0, 1, 7, 100), ++ F(58982400, P_GPLL0, 1, 1152, 15625), ++ F(60000000, P_GPLL0, 1, 3, 40), ++ F(64000000, P_GPLL0, 12.5, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 blsp1_uart1_apps_clk_src = { ++ .cmd_rcgr = 0x0202c, ++ .freq_tbl = ftbl_blsp1_uart_apps_clk_src, ++ .mnd_width = 16, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "blsp1_uart1_apps_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 blsp1_uart2_apps_clk_src = { ++ .cmd_rcgr = 0x0302c, ++ .freq_tbl = ftbl_blsp1_uart_apps_clk_src, ++ .mnd_width = 16, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "blsp1_uart2_apps_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 blsp1_uart3_apps_clk_src = { ++ .cmd_rcgr = 0x0402c, ++ .freq_tbl = ftbl_blsp1_uart_apps_clk_src, ++ .mnd_width = 16, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "blsp1_uart3_apps_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 blsp1_uart4_apps_clk_src = { ++ .cmd_rcgr = 0x0502c, ++ .freq_tbl = ftbl_blsp1_uart_apps_clk_src, ++ .mnd_width = 16, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "blsp1_uart4_apps_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 blsp1_uart5_apps_clk_src = { ++ .cmd_rcgr = 0x0602c, ++ .freq_tbl = ftbl_blsp1_uart_apps_clk_src, ++ .mnd_width = 16, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "blsp1_uart5_apps_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 blsp1_uart6_apps_clk_src = { ++ .cmd_rcgr = 0x0702c, ++ .freq_tbl = ftbl_blsp1_uart_apps_clk_src, ++ .mnd_width = 16, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "blsp1_uart6_apps_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_apss_ahb_clk = { ++ .halt_reg = 0x24018, ++ .halt_check = BRANCH_HALT_VOTED, ++ .clkr = { ++ .enable_reg = 0x0b004, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_apss_ahb_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &apss_ahb_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_apss_axi_clk = { ++ .halt_reg = 0x2401c, ++ .halt_check = BRANCH_HALT_VOTED, ++ .clkr = { ++ .enable_reg = 0x0b004, ++ .enable_mask = BIT(1), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_apss_axi_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &apss_axi_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { ++ .halt_reg = 0x2024, ++ .clkr = { ++ .enable_reg = 0x2024, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_blsp1_qup1_i2c_apps_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &blsp1_qup1_i2c_apps_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { ++ .halt_reg = 0x02020, ++ .clkr = { ++ .enable_reg = 0x02020, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_blsp1_qup1_spi_apps_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &blsp1_qup1_spi_apps_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { ++ .halt_reg = 0x03024, ++ .clkr = { ++ .enable_reg = 0x03024, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_blsp1_qup2_i2c_apps_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &blsp1_qup2_i2c_apps_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { ++ .halt_reg = 0x03020, ++ .clkr = { ++ .enable_reg = 0x03020, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_blsp1_qup2_spi_apps_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &blsp1_qup2_spi_apps_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { ++ .halt_reg = 0x04024, ++ .clkr = { ++ .enable_reg = 0x04024, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_blsp1_qup3_i2c_apps_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &blsp1_qup3_i2c_apps_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { ++ .halt_reg = 0x04020, ++ .clkr = { ++ .enable_reg = 0x04020, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_blsp1_qup3_spi_apps_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &blsp1_qup3_spi_apps_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { ++ .halt_reg = 0x05024, ++ .clkr = { ++ .enable_reg = 0x05024, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_blsp1_qup4_i2c_apps_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &blsp1_qup4_i2c_apps_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { ++ .halt_reg = 0x05020, ++ .clkr = { ++ .enable_reg = 0x05020, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_blsp1_qup4_spi_apps_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &blsp1_qup4_spi_apps_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { ++ .halt_reg = 0x06024, ++ .clkr = { ++ .enable_reg = 0x06024, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_blsp1_qup5_i2c_apps_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &blsp1_qup5_i2c_apps_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { ++ .halt_reg = 0x06020, ++ .clkr = { ++ .enable_reg = 0x06020, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_blsp1_qup5_spi_apps_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &blsp1_qup5_spi_apps_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { ++ .halt_reg = 0x07024, ++ .clkr = { ++ .enable_reg = 0x07024, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_blsp1_qup6_i2c_apps_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &blsp1_qup6_i2c_apps_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { ++ .halt_reg = 0x07020, ++ .clkr = { ++ .enable_reg = 0x07020, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_blsp1_qup6_spi_apps_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &blsp1_qup6_spi_apps_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_uart1_apps_clk = { ++ .halt_reg = 0x02040, ++ .clkr = { ++ .enable_reg = 0x02040, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_blsp1_uart1_apps_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &blsp1_uart1_apps_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_uart2_apps_clk = { ++ .halt_reg = 0x03040, ++ .clkr = { ++ .enable_reg = 0x03040, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_blsp1_uart2_apps_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &blsp1_uart2_apps_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_uart3_apps_clk = { ++ .halt_reg = 0x04054, ++ .clkr = { ++ .enable_reg = 0x04054, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_blsp1_uart3_apps_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &blsp1_uart3_apps_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_uart4_apps_clk = { ++ .halt_reg = 0x05040, ++ .clkr = { ++ .enable_reg = 0x05040, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_blsp1_uart4_apps_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &blsp1_uart4_apps_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_uart5_apps_clk = { ++ .halt_reg = 0x06040, ++ .clkr = { ++ .enable_reg = 0x06040, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_blsp1_uart5_apps_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &blsp1_uart5_apps_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_uart6_apps_clk = { ++ .halt_reg = 0x07040, ++ .clkr = { ++ .enable_reg = 0x07040, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_blsp1_uart6_apps_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &blsp1_uart6_apps_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_pcie0_axi_m_clk_src[] = { ++ F(240000000, P_GPLL4, 5, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 pcie0_axi_m_clk_src = { ++ .cmd_rcgr = 0x28018, ++ .freq_tbl = ftbl_pcie0_axi_m_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll4_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "pcie0_axi_m_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll4, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie0_axi_m_clk = { ++ .halt_reg = 0x28038, ++ .clkr = { ++ .enable_reg = 0x28038, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_pcie0_axi_m_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie0_axi_m_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_anoc_pcie0_1lane_m_clk = { ++ .halt_reg = 0x2e07c, ++ .clkr = { ++ .enable_reg = 0x2e07c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_anoc_pcie0_1lane_m_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie0_axi_m_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_rcg2 pcie1_axi_m_clk_src = { ++ .cmd_rcgr = 0x29018, ++ .freq_tbl = ftbl_pcie0_axi_m_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll4_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "pcie1_axi_m_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll4, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie1_axi_m_clk = { ++ .halt_reg = 0x29038, ++ .clkr = { ++ .enable_reg = 0x29038, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_pcie1_axi_m_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie1_axi_m_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_anoc_pcie1_1lane_m_clk = { ++ .halt_reg = 0x2e08c, ++ .clkr = { ++ .enable_reg = 0x2e08c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_anoc_pcie1_1lane_m_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie1_axi_m_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_pcie2_axi_m_clk_src[] = { ++ F(342857143, P_GPLL4, 3.5, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 pcie2_axi_m_clk_src = { ++ .cmd_rcgr = 0x2a018, ++ .freq_tbl = ftbl_pcie2_axi_m_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "pcie2_axi_m_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie2_axi_m_clk = { ++ .halt_reg = 0x2a038, ++ .clkr = { ++ .enable_reg = 0x2a038, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_pcie2_axi_m_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie2_axi_m_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_anoc_pcie2_2lane_m_clk = { ++ .halt_reg = 0x2e080, ++ .clkr = { ++ .enable_reg = 0x2e080, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_anoc_pcie2_2lane_m_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie2_axi_m_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_rcg2 pcie3_axi_m_clk_src = { ++ .cmd_rcgr = 0x2b018, ++ .freq_tbl = ftbl_pcie2_axi_m_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "pcie3_axi_m_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie3_axi_m_clk = { ++ .halt_reg = 0x2b038, ++ .clkr = { ++ .enable_reg = 0x2b038, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_pcie3_axi_m_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie3_axi_m_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_anoc_pcie3_2lane_m_clk = { ++ .halt_reg = 0x2e090, ++ .clkr = { ++ .enable_reg = 0x2e090, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_anoc_pcie3_2lane_m_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie3_axi_m_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_rcg2 pcie0_axi_s_clk_src = { ++ .cmd_rcgr = 0x28020, ++ .freq_tbl = ftbl_pcie0_axi_m_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll4_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "pcie0_axi_s_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll4, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie0_axi_s_clk = { ++ .halt_reg = 0x2803c, ++ .clkr = { ++ .enable_reg = 0x2803c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_pcie0_axi_s_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie0_axi_s_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie0_axi_s_bridge_clk = { ++ .halt_reg = 0x28040, ++ .clkr = { ++ .enable_reg = 0x28040, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_pcie0_axi_s_bridge_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie0_axi_s_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_snoc_pcie0_1lane_s_clk = { ++ .halt_reg = 0x2e048, ++ .clkr = { ++ .enable_reg = 0x2e048, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_snoc_pcie0_1lane_s_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie0_axi_s_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_rcg2 pcie1_axi_s_clk_src = { ++ .cmd_rcgr = 0x29020, ++ .freq_tbl = ftbl_pcie0_axi_m_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll4_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "pcie1_axi_s_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll4, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie1_axi_s_clk = { ++ .halt_reg = 0x2903c, ++ .clkr = { ++ .enable_reg = 0x2903c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_pcie1_axi_s_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie1_axi_s_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie1_axi_s_bridge_clk = { ++ .halt_reg = 0x29040, ++ .clkr = { ++ .enable_reg = 0x29040, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_pcie1_axi_s_bridge_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie1_axi_s_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_snoc_pcie1_1lane_s_clk = { ++ .halt_reg = 0x2e04c, ++ .clkr = { ++ .enable_reg = 0x2e04c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_snoc_pcie1_1lane_s_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie1_axi_s_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_rcg2 pcie2_axi_s_clk_src = { ++ .cmd_rcgr = 0x2a020, ++ .freq_tbl = ftbl_pcie0_axi_m_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll4_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "pcie2_axi_s_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll4, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie2_axi_s_clk = { ++ .halt_reg = 0x2a03c, ++ .clkr = { ++ .enable_reg = 0x2a03c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_pcie2_axi_s_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie2_axi_s_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie2_axi_s_bridge_clk = { ++ .halt_reg = 0x2a040, ++ .clkr = { ++ .enable_reg = 0x2a040, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_pcie2_axi_s_bridge_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie2_axi_s_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_snoc_pcie2_2lane_s_clk = { ++ .halt_reg = 0x2e050, ++ .clkr = { ++ .enable_reg = 0x2e050, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_snoc_pcie2_2lane_s_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie2_axi_s_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_rcg2 pcie3_axi_s_clk_src = { ++ .cmd_rcgr = 0x2b020, ++ .freq_tbl = ftbl_pcie0_axi_m_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll4_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "pcie3_axi_s_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll4, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie3_axi_s_clk = { ++ .halt_reg = 0x2b03c, ++ .clkr = { ++ .enable_reg = 0x2b03c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_pcie3_axi_s_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie3_axi_s_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie3_axi_s_bridge_clk = { ++ .halt_reg = 0x2b040, ++ .clkr = { ++ .enable_reg = 0x2b040, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_pcie3_axi_s_bridge_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie3_axi_s_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_snoc_pcie3_2lane_s_clk = { ++ .halt_reg = 0x2e054, ++ .clkr = { ++ .enable_reg = 0x2e054, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_snoc_pcie3_2lane_s_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie3_axi_s_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_regmap_phy_mux pcie0_pipe_clk_src = { ++ .reg = 0x28064, ++ .clkr = { ++ .hw.init = &(struct clk_init_data) { ++ .name = "pcie0_pipe_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .index = DT_PCIE30_PHY0_PIPE_CLK, ++ }, ++ .num_parents = 1, ++ .ops = &clk_regmap_phy_mux_ops, ++ }, ++ }, ++}; ++ ++static struct clk_regmap_phy_mux pcie1_pipe_clk_src = { ++ .reg = 0x29064, ++ .clkr = { ++ .hw.init = &(struct clk_init_data) { ++ .name = "pcie1_pipe_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .index = DT_PCIE30_PHY1_PIPE_CLK, ++ }, ++ .num_parents = 1, ++ .ops = &clk_regmap_phy_mux_ops, ++ }, ++ }, ++}; ++ ++static struct clk_regmap_phy_mux pcie2_pipe_clk_src = { ++ .reg = 0x2a064, ++ .clkr = { ++ .hw.init = &(struct clk_init_data) { ++ .name = "pcie2_pipe_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .index = DT_PCIE30_PHY2_PIPE_CLK, ++ }, ++ .num_parents = 1, ++ .ops = &clk_regmap_phy_mux_ops, ++ }, ++ }, ++}; ++ ++static struct clk_regmap_phy_mux pcie3_pipe_clk_src = { ++ .reg = 0x2b064, ++ .clkr = { ++ .hw.init = &(struct clk_init_data) { ++ .name = "pcie3_pipe_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .index = DT_PCIE30_PHY3_PIPE_CLK, ++ }, ++ .num_parents = 1, ++ .ops = &clk_regmap_phy_mux_ops, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = { ++ F(24000000, P_XO, 1, 0, 0), ++ F(100000000, P_GPLL0, 8, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 pcie0_rchng_clk_src = { ++ .cmd_rcgr = 0x28028, ++ .freq_tbl = ftbl_pcie_rchng_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "pcie0_rchng_clk_src", ++ .parent_data = gcc_xo_gpll0, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie0_rchng_clk = { ++ .halt_reg = 0x28028, ++ .clkr = { ++ .enable_reg = 0x28028, ++ .enable_mask = BIT(1), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_pcie0_rchng_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie0_rchng_clk_src.clkr.hw ++ ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_rcg2 pcie1_rchng_clk_src = { ++ .cmd_rcgr = 0x29028, ++ .freq_tbl = ftbl_pcie_rchng_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "pcie1_rchng_clk_src", ++ .parent_data = gcc_xo_gpll0, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie1_rchng_clk = { ++ .halt_reg = 0x29028, ++ .clkr = { ++ .enable_reg = 0x29028, ++ .enable_mask = BIT(1), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_pcie1_rchng_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie1_rchng_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_rcg2 pcie2_rchng_clk_src = { ++ .cmd_rcgr = 0x2a028, ++ .freq_tbl = ftbl_pcie_rchng_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "pcie2_rchng_clk_src", ++ .parent_data = gcc_xo_gpll0, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie2_rchng_clk = { ++ .halt_reg = 0x2a028, ++ .clkr = { ++ .enable_reg = 0x2a028, ++ .enable_mask = BIT(1), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_pcie2_rchng_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie2_rchng_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_rcg2 pcie3_rchng_clk_src = { ++ .cmd_rcgr = 0x2b028, ++ .freq_tbl = ftbl_pcie_rchng_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "pcie3_rchng_clk_src", ++ .parent_data = gcc_xo_gpll0, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie3_rchng_clk = { ++ .halt_reg = 0x2b028, ++ .clkr = { ++ .enable_reg = 0x2b028, ++ .enable_mask = BIT(1), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_pcie3_rchng_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie3_rchng_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_pcie_aux_clk_src[] = { ++ F(20000000, P_GPLL0, 10, 1, 4), ++ { } ++}; ++ ++static struct clk_rcg2 pcie_aux_clk_src = { ++ .cmd_rcgr = 0x28004, ++ .freq_tbl = ftbl_pcie_aux_clk_src, ++ .mnd_width = 16, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "pcie_aux_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie0_aux_clk = { ++ .halt_reg = 0x28034, ++ .clkr = { ++ .enable_reg = 0x28034, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_pcie0_aux_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie_aux_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie1_aux_clk = { ++ .halt_reg = 0x29034, ++ .clkr = { ++ .enable_reg = 0x29034, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_pcie1_aux_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie_aux_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie2_aux_clk = { ++ .halt_reg = 0x2a034, ++ .clkr = { ++ .enable_reg = 0x2a034, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_pcie2_aux_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie_aux_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie3_aux_clk = { ++ .halt_reg = 0x2b034, ++ .clkr = { ++ .enable_reg = 0x2b034, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_pcie3_aux_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcie_aux_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_usb_aux_clk_src[] = { ++ F(24000000, P_XO, 1, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 usb0_aux_clk_src = { ++ .cmd_rcgr = 0x2c018, ++ .freq_tbl = ftbl_usb_aux_clk_src, ++ .mnd_width = 16, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "usb0_aux_clk_src", ++ .parent_data = gcc_xo_gpll0_core_pi_sleep_clk, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_usb0_aux_clk = { ++ .halt_reg = 0x2c048, ++ .clkr = { ++ .enable_reg = 0x2c048, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_usb0_aux_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &usb0_aux_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_usb0_master_clk_src[] = { ++ F(100000000, P_GPLL0, 8, 0, 0), ++ F(200000000, P_GPLL0, 4, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 usb0_master_clk_src = { ++ .cmd_rcgr = 0x2c004, ++ .freq_tbl = ftbl_usb0_master_clk_src, ++ .mnd_width = 8, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "usb0_master_clk_src", ++ .parent_data = gcc_xo_gpll0_out_main_div2_gpll0, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_usb0_master_clk = { ++ .halt_reg = 0x2c044, ++ .clkr = { ++ .enable_reg = 0x2c044, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_usb0_master_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &usb0_master_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_snoc_usb_clk = { ++ .halt_reg = 0x2e058, ++ .clkr = { ++ .enable_reg = 0x2e058, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_snoc_usb_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &usb0_master_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_anoc_usb_axi_clk = { ++ .halt_reg = 0x2e084, ++ .clkr = { ++ .enable_reg = 0x2e084, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_anoc_usb_axi_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &usb0_master_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_usb0_mock_utmi_clk_src[] = { ++ F(24000000, P_XO, 1, 0, 0), ++ F(60000000, P_GPLL4, 10, 1, 2), ++ { } ++}; ++ ++static struct clk_rcg2 usb0_mock_utmi_clk_src = { ++ .cmd_rcgr = 0x2c02c, ++ .freq_tbl = ftbl_usb0_mock_utmi_clk_src, ++ .mnd_width = 8, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "usb0_mock_utmi_clk_src", ++ .parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_regmap_div usb0_mock_utmi_div_clk_src = { ++ .reg = 0x2c040, ++ .shift = 0, ++ .width = 2, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "usb0_mock_utmi_div_clk_src", ++ .parent_data = &(const struct clk_parent_data) { ++ .hw = &usb0_mock_utmi_clk_src.clkr.hw, ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_div_ro_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_usb0_mock_utmi_clk = { ++ .halt_reg = 0x2c04c, ++ .clkr = { ++ .enable_reg = 0x2c04c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_usb0_mock_utmi_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &usb0_mock_utmi_div_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_regmap_mux usb0_pipe_clk_src = { ++ .reg = 0x2C074, ++ .shift = 8, ++ .width = 2, ++ .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map, ++ .clkr = { ++ .hw.init = &(struct clk_init_data) { ++ .name = "usb0_pipe_clk_src", ++ .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo, ++ .num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo), ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_regmap_mux_closest_ops, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = { ++ F(144000, P_XO, 16, 12, 125), ++ F(400000, P_XO, 12, 1, 5), ++ F(24000000, P_GPLL2, 12, 1, 4), ++ F(48000000, P_GPLL2, 12, 1, 2), ++ F(96000000, P_GPLL2, 12, 0, 0), ++ F(177777778, P_GPLL0, 4.5, 0, 0), ++ F(192000000, P_GPLL2, 6, 0, 0), ++ F(384000000, P_GPLL2, 3, 0, 0), ++ F(400000000, P_GPLL0, 2, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 sdcc1_apps_clk_src = { ++ .cmd_rcgr = 0x33004, ++ .freq_tbl = ftbl_sdcc_apps_clk_src, ++ .mnd_width = 8, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "sdcc1_apps_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2), ++ .ops = &clk_rcg2_floor_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_sdcc1_apps_clk = { ++ .halt_reg = 0x3302c, ++ .clkr = { ++ .enable_reg = 0x3302c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_sdcc1_apps_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &sdcc1_apps_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = { ++ F(150000000, P_GPLL4, 8, 0, 0), ++ F(300000000, P_GPLL4, 4, 0, 0), ++}; ++ ++static struct clk_rcg2 sdcc1_ice_core_clk_src = { ++ .cmd_rcgr = 0x33018, ++ .freq_tbl = ftbl_sdcc_ice_core_clk_src, ++ .mnd_width = 8, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll4_gpll0_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "sdcc1_ice_core_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll4_gpll0_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_div2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_sdcc1_ice_core_clk = { ++ .halt_reg = 0x33030, ++ .clkr = { ++ .enable_reg = 0x33030, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_sdcc1_ice_core_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &sdcc1_ice_core_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = { ++ F(24000000, P_XO, 1, 0, 0), ++ F(50000000, P_GPLL0, 16, 0, 0), ++ F(80000000, P_GPLL0, 10, 0, 0), ++ F(100000000, P_GPLL0, 8, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 pcnoc_bfdcd_clk_src = { ++ .cmd_rcgr = 0x31004, ++ .freq_tbl = ftbl_pcnoc_bfdcd_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "pcnoc_bfdcd_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), ++ .flags = CLK_IS_CRITICAL, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_nsscfg_clk = { ++ .halt_reg = 0x1702c, ++ .clkr = { ++ .enable_reg = 0x1702c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_nsscfg_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_nssnoc_nsscc_clk = { ++ .halt_reg = 0x17030, ++ .clkr = { ++ .enable_reg = 0x17030, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_nssnoc_nsscc_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_nsscc_clk = { ++ .halt_reg = 0x17034, ++ .clkr = { ++ .enable_reg = 0x17034, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_nsscc_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_nssnoc_pcnoc_1_clk = { ++ .halt_reg = 0x17080, ++ .clkr = { ++ .enable_reg = 0x17080, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_nssnoc_pcnoc_1_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_dap_ahb_clk = { ++ .halt_reg = 0x2d064, ++ .clkr = { ++ .enable_reg = 0x2d064, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_qdss_dap_ahb_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_cfg_ahb_clk = { ++ .halt_reg = 0x2d068, ++ .clkr = { ++ .enable_reg = 0x2d068, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_qdss_cfg_ahb_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qpic_ahb_clk = { ++ .halt_reg = 0x32010, ++ .clkr = { ++ .enable_reg = 0x32010, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_qpic_ahb_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qpic_clk = { ++ .halt_reg = 0x32014, ++ .clkr = { ++ .enable_reg = 0x32014, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_qpic_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_ahb_clk = { ++ .halt_reg = 0x01004, ++ .halt_check = BRANCH_HALT_VOTED, ++ .clkr = { ++ .enable_reg = 0x0b004, ++ .enable_mask = BIT(4), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_blsp1_ahb_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_mdio_ahb_clk = { ++ .halt_reg = 0x17040, ++ .clkr = { ++ .enable_reg = 0x17040, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_mdio_ahb_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_prng_ahb_clk = { ++ .halt_reg = 0x13024, ++ .halt_check = BRANCH_HALT_VOTED, ++ .clkr = { ++ .enable_reg = 0x0b004, ++ .enable_mask = BIT(10), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_prng_ahb_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_uniphy0_ahb_clk = { ++ .halt_reg = 0x1704c, ++ .clkr = { ++ .enable_reg = 0x1704c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_uniphy0_ahb_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_uniphy1_ahb_clk = { ++ .halt_reg = 0x1705c, ++ .clkr = { ++ .enable_reg = 0x1705c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_uniphy1_ahb_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_uniphy2_ahb_clk = { ++ .halt_reg = 0x1706c, ++ .clkr = { ++ .enable_reg = 0x1706c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_uniphy2_ahb_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_cmn_12gpll_ahb_clk = { ++ .halt_reg = 0x3a004, ++ .clkr = { ++ .enable_reg = 0x3a004, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_cmn_12gpll_ahb_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_cmn_12gpll_apu_clk = { ++ .halt_reg = 0x3a00c, ++ .clkr = { ++ .enable_reg = 0x3a00c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_cmn_12gpll_apu_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie0_ahb_clk = { ++ .halt_reg = 0x28030, ++ .clkr = { ++ .enable_reg = 0x28030, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_pcie0_ahb_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie1_ahb_clk = { ++ .halt_reg = 0x29030, ++ .clkr = { ++ .enable_reg = 0x29030, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_pcie1_ahb_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie2_ahb_clk = { ++ .halt_reg = 0x2a030, ++ .clkr = { ++ .enable_reg = 0x2a030, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_pcie2_ahb_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie3_ahb_clk = { ++ .halt_reg = 0x2b030, ++ .clkr = { ++ .enable_reg = 0x2b030, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_pcie3_ahb_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = { ++ .halt_reg = 0x2c05c, ++ .clkr = { ++ .enable_reg = 0x2c05c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_usb0_phy_cfg_ahb_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_sdcc1_ahb_clk = { ++ .halt_reg = 0x33034, ++ .clkr = { ++ .enable_reg = 0x33034, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_sdcc1_ahb_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &pcnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = { ++ F(24000000, P_XO, 1, 0, 0), ++ F(133333333, P_GPLL0, 6, 0, 0), ++ F(200000000, P_GPLL0, 4, 0, 0), ++ F(342850000, P_GPLL4, 3.5, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 system_noc_bfdcd_clk_src = { ++ .cmd_rcgr = 0x2e004, ++ .freq_tbl = ftbl_system_noc_bfdcd_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll4_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "system_noc_bfdcd_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll4, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), ++ .flags = CLK_IS_CRITICAL, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_q6ss_boot_clk = { ++ .halt_reg = 0x25080, ++ .halt_check = BRANCH_HALT_SKIP, ++ .clkr = { ++ .enable_reg = 0x25080, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_q6ss_boot_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &system_noc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_nssnoc_snoc_clk = { ++ .halt_reg = 0x17028, ++ .clkr = { ++ .enable_reg = 0x17028, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_nssnoc_snoc_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &system_noc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_nssnoc_snoc_1_clk = { ++ .halt_reg = 0x1707c, ++ .clkr = { ++ .enable_reg = 0x1707c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_nssnoc_snoc_1_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &system_noc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_etr_usb_clk = { ++ .halt_reg = 0x2d060, ++ .clkr = { ++ .enable_reg = 0x2d060, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_qdss_etr_usb_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &system_noc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = { ++ F(24000000, P_XO, 1, 0, 0), ++ F(133333333, P_GPLL0, 6, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 wcss_ahb_clk_src = { ++ .cmd_rcgr = 0x25030, ++ .freq_tbl = ftbl_wcss_ahb_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "wcss_ahb_clk_src", ++ .parent_data = gcc_xo_gpll0, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_q6_ahb_clk = { ++ .halt_reg = 0x25014, ++ .clkr = { ++ .enable_reg = 0x25014, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_q6_ahb_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &wcss_ahb_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_q6_ahb_s_clk = { ++ .halt_reg = 0x25018, ++ .clkr = { ++ .enable_reg = 0x25018, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_q6_ahb_s_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &wcss_ahb_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_wcss_ecahb_clk = { ++ .halt_reg = 0x25058, ++ .clkr = { ++ .enable_reg = 0x25058, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_wcss_ecahb_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &wcss_ahb_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_wcss_acmt_clk = { ++ .halt_reg = 0x2505c, ++ .clkr = { ++ .enable_reg = 0x2505c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_wcss_acmt_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &wcss_ahb_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_sys_noc_wcss_ahb_clk = { ++ .halt_reg = 0x2e030, ++ .clkr = { ++ .enable_reg = 0x2e030, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_sys_noc_wcss_ahb_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &wcss_ahb_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_wcss_axi_m_clk_src[] = { ++ F(24000000, P_XO, 1, 0, 0), ++ F(133333333, P_GPLL0, 6, 0, 0), ++ F(266666667, P_GPLL0, 3, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 wcss_axi_m_clk_src = { ++ .cmd_rcgr = 0x25078, ++ .freq_tbl = ftbl_wcss_axi_m_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "wcss_axi_m_clk_src", ++ .parent_data = gcc_xo_gpll0, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_anoc_wcss_axi_m_clk = { ++ .halt_reg = 0x2e0a8, ++ .clkr = { ++ .enable_reg = 0x2e0a8, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_anoc_wcss_axi_m_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &wcss_axi_m_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_qdss_at_clk_src[] = { ++ F(240000000, P_GPLL4, 5, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 qdss_at_clk_src = { ++ .cmd_rcgr = 0x2d004, ++ .freq_tbl = ftbl_qdss_at_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "qdss_at_clk_src", ++ .parent_data = gcc_xo_gpll4_gpll0_gpll0_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_q6ss_atbm_clk = { ++ .halt_reg = 0x2501c, ++ .clkr = { ++ .enable_reg = 0x2501c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_q6ss_atbm_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_at_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = { ++ .halt_reg = 0x2503c, ++ .clkr = { ++ .enable_reg = 0x2503c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_wcss_dbg_ifc_atb_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_at_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_nssnoc_atb_clk = { ++ .halt_reg = 0x17014, ++ .clkr = { ++ .enable_reg = 0x17014, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_nssnoc_atb_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_at_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_at_clk = { ++ .halt_reg = 0x2d038, ++ .clkr = { ++ .enable_reg = 0x2d038, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_qdss_at_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_at_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_sys_noc_at_clk = { ++ .halt_reg = 0x2e038, ++ .clkr = { ++ .enable_reg = 0x2e038, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_sys_noc_at_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_at_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_pcnoc_at_clk = { ++ .halt_reg = 0x31024, ++ .clkr = { ++ .enable_reg = 0x31024, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_pcnoc_at_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_at_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_fixed_factor gcc_eud_at_div_clk_src = { ++ .mult = 1, ++ .div = 6, ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_eud_at_div_clk_src", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_at_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_fixed_factor_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_usb0_eud_at_clk = { ++ .halt_reg = 0x30004, ++ .clkr = { ++ .enable_reg = 0x30004, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_usb0_eud_at_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &gcc_eud_at_div_clk_src.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_eud_at_clk = { ++ .halt_reg = 0x2d06c, ++ .clkr = { ++ .enable_reg = 0x2d06c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_qdss_eud_at_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &gcc_eud_at_div_clk_src.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_qdss_stm_clk_src[] = { ++ F(24000000, P_XO, 1, 0, 0), ++ F(200000000, P_GPLL0, 4, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 qdss_stm_clk_src = { ++ .cmd_rcgr = 0x2d00c, ++ .freq_tbl = ftbl_qdss_stm_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "qdss_stm_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_stm_clk = { ++ .halt_reg = 0x2d03c, ++ .clkr = { ++ .enable_reg = 0x2d03c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_qdss_stm_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_stm_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = { ++ .halt_reg = 0x2e034, ++ .clkr = { ++ .enable_reg = 0x2e034, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_sys_noc_qdss_stm_axi_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_stm_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = { ++ F(300000000, P_GPLL4, 4, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 qdss_traceclkin_clk_src = { ++ .cmd_rcgr = 0x2d014, ++ .freq_tbl = ftbl_qdss_traceclkin_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "qdss_traceclkin_clk_src", ++ .parent_data = gcc_xo_gpll4_gpll0_gpll0_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_traceclkin_clk = { ++ .halt_reg = 0x2d040, ++ .clkr = { ++ .enable_reg = 0x2d040, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_qdss_traceclkin_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_traceclkin_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = { ++ F(600000000, P_GPLL4, 2, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 qdss_tsctr_clk_src = { ++ .cmd_rcgr = 0x2d01c, ++ .freq_tbl = ftbl_qdss_tsctr_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "qdss_tsctr_clk_src", ++ .parent_data = gcc_xo_gpll4_gpll0_gpll0_div2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_fixed_factor qdss_tsctr_div2_clk_src = { ++ .mult = 1, ++ .div = 2, ++ .hw.init = &(struct clk_init_data) { ++ .name = "qdss_tsctr_div2_clk_src", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_tsctr_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_fixed_factor_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_q6_tsctr_1to2_clk = { ++ .halt_reg = 0x25020, ++ .clkr = { ++ .enable_reg = 0x25020, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_q6_tsctr_1to2_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_tsctr_div2_clk_src.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = { ++ .halt_reg = 0x25040, ++ .clkr = { ++ .enable_reg = 0x25040, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_wcss_dbg_ifc_nts_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_tsctr_div2_clk_src.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_tsctr_div2_clk = { ++ .halt_reg = 0x2d044, ++ .clkr = { ++ .enable_reg = 0x2d044, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_qdss_tsctr_div2_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_tsctr_div2_clk_src.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_uniphy_sys_clk_src[] = { ++ F(24000000, P_XO, 1, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 uniphy_sys_clk_src = { ++ .cmd_rcgr = 0x17090, ++ .freq_tbl = ftbl_uniphy_sys_clk_src, ++ .mnd_width = 8, ++ .hid_width = 5, ++ .parent_map = gcc_xo_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "uniphy_sys_clk_src", ++ .parent_data = gcc_xo_data, ++ .num_parents = ARRAY_SIZE(gcc_xo_data), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 nss_ts_clk_src = { ++ .cmd_rcgr = 0x17088, ++ .freq_tbl = ftbl_uniphy_sys_clk_src, ++ .mnd_width = 8, ++ .hid_width = 5, ++ .parent_map = gcc_xo_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "nss_ts_clk_src", ++ .parent_data = gcc_xo_data, ++ .num_parents = ARRAY_SIZE(gcc_xo_data), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_ts_clk = { ++ .halt_reg = 0x2d078, ++ .clkr = { ++ .enable_reg = 0x2d078, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_qdss_ts_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &nss_ts_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_fixed_factor qdss_dap_sync_clk_src = { ++ .mult = 1, ++ .div = 4, ++ .hw.init = &(struct clk_init_data) { ++ .name = "qdss_dap_sync_clk_src", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_tsctr_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .ops = &clk_fixed_factor_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_tsctr_div4_clk = { ++ .halt_reg = 0x2d04c, ++ .clkr = { ++ .enable_reg = 0x2d04c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_qdss_tsctr_div4_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_dap_sync_clk_src.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_fixed_factor qdss_tsctr_div8_clk_src = { ++ .mult = 1, ++ .div = 8, ++ .hw.init = &(struct clk_init_data) { ++ .name = "qdss_tsctr_div8_clk_src", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_tsctr_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .ops = &clk_fixed_factor_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_nss_ts_clk = { ++ .halt_reg = 0x17018, ++ .clkr = { ++ .enable_reg = 0x17018, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_nss_ts_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &nss_ts_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_tsctr_div8_clk = { ++ .halt_reg = 0x2d050, ++ .clkr = { ++ .enable_reg = 0x2d050, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_qdss_tsctr_div8_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_tsctr_div8_clk_src.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_fixed_factor qdss_tsctr_div16_clk_src = { ++ .mult = 1, ++ .div = 16, ++ .hw.init = &(struct clk_init_data) { ++ .name = "qdss_tsctr_div16_clk_src", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_tsctr_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .ops = &clk_fixed_factor_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_tsctr_div16_clk = { ++ .halt_reg = 0x2d054, ++ .clkr = { ++ .enable_reg = 0x2d054, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_qdss_tsctr_div16_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_tsctr_div16_clk_src.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_q6ss_pclkdbg_clk = { ++ .halt_reg = 0x25024, ++ .clkr = { ++ .enable_reg = 0x25024, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_q6ss_pclkdbg_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_dap_sync_clk_src.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_q6ss_trig_clk = { ++ .halt_reg = 0x25068, ++ .clkr = { ++ .enable_reg = 0x25068, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_q6ss_trig_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_dap_sync_clk_src.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = { ++ .halt_reg = 0x25038, ++ .clkr = { ++ .enable_reg = 0x25038, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_wcss_dbg_ifc_apb_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_dap_sync_clk_src.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = { ++ .halt_reg = 0x25044, ++ .clkr = { ++ .enable_reg = 0x25044, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_wcss_dbg_ifc_dapbus_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_dap_sync_clk_src.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_dap_clk = { ++ .halt_reg = 0x2d058, ++ .clkr = { ++ .enable_reg = 0x2d058, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_qdss_dap_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_dap_sync_clk_src.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_apb2jtag_clk = { ++ .halt_reg = 0x2d05c, ++ .clkr = { ++ .enable_reg = 0x2d05c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_qdss_apb2jtag_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_dap_sync_clk_src.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_fixed_factor qdss_tsctr_div3_clk_src = { ++ .mult = 1, ++ .div = 3, ++ .hw.init = &(struct clk_init_data) { ++ .name = "qdss_tsctr_div3_clk_src", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_tsctr_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .ops = &clk_fixed_factor_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_tsctr_div3_clk = { ++ .halt_reg = 0x2d048, ++ .clkr = { ++ .enable_reg = 0x2d048, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_qdss_tsctr_div3_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &qdss_tsctr_div3_clk_src.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = { ++ F(24000000, P_XO, 1, 0, 0), ++ F(100000000, P_GPLL0, 8, 0, 0), ++ F(200000000, P_GPLL0, 4, 0, 0), ++ F(320000000, P_GPLL0, 2.5, 0, 0), ++ F(400000000, P_GPLL0, 2, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 qpic_io_macro_clk_src = { ++ .cmd_rcgr = 0x32004, ++ .freq_tbl = ftbl_qpic_io_macro_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "qpic_io_macro_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_qpic_io_macro_clk = { ++ .halt_reg = 0x3200c, ++ .clkr = { ++ .enable_reg = 0x3200c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_qpic_io_macro_clk", ++ .parent_hws = (const struct clk_hw *[]){ ++ &qpic_io_macro_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_q6_axi_clk_src[] = { ++ F(533333333, P_GPLL0, 1.5, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 q6_axi_clk_src = { ++ .cmd_rcgr = 0x25004, ++ .freq_tbl = ftbl_q6_axi_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "q6_axi_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll2_gpll4_pi_sleep, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_pi_sleep), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_q6_axim_clk = { ++ .halt_reg = 0x2500c, ++ .clkr = { ++ .enable_reg = 0x2500c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_q6_axim_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &q6_axi_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_wcss_q6_tbu_clk = { ++ .halt_reg = 0x12050, ++ .halt_check = BRANCH_HALT_DELAY, ++ .clkr = { ++ .enable_reg = 0xb00c, ++ .enable_mask = BIT(6), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_wcss_q6_tbu_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &q6_axi_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_mem_noc_q6_axi_clk = { ++ .halt_reg = 0x19010, ++ .clkr = { ++ .enable_reg = 0x19010, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_mem_noc_q6_axi_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &q6_axi_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_q6_axim2_clk_src[] = { ++ F(342857143, P_GPLL4, 3.5, 0, 0), ++ { } ++}; ++ ++static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL4, 2 }, ++ { P_BIAS_PLL_UBI_NC_CLK, 4 }, ++}; ++ ++static struct clk_rcg2 q6_axim2_clk_src = { ++ .cmd_rcgr = 0x25028, ++ .freq_tbl = ftbl_q6_axim2_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "q6_axim2_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_nssnoc_memnoc_bfdcd_clk_src[] = { ++ F(533333333, P_GPLL0, 1.5, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 nssnoc_memnoc_bfdcd_clk_src = { ++ .cmd_rcgr = 0x17004, ++ .freq_tbl = ftbl_nssnoc_memnoc_bfdcd_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_aux_gpll2_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "nssnoc_memnoc_bfdcd_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_aux_gpll2, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_gpll2), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_nssnoc_memnoc_clk = { ++ .halt_reg = 0x17024, ++ .clkr = { ++ .enable_reg = 0x17024, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_nssnoc_memnoc_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &nssnoc_memnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_nssnoc_mem_noc_1_clk = { ++ .halt_reg = 0x17084, ++ .clkr = { ++ .enable_reg = 0x17084, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_nssnoc_mem_noc_1_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &nssnoc_memnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_nss_tbu_clk = { ++ .halt_reg = 0x12040, ++ .clkr = { ++ .enable_reg = 0xb00c, ++ .enable_mask = BIT(4), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_nss_tbu_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &nssnoc_memnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_mem_noc_nssnoc_clk = { ++ .halt_reg = 0x19014, ++ .clkr = { ++ .enable_reg = 0x19014, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_mem_noc_nssnoc_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &nssnoc_memnoc_bfdcd_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_lpass_axim_clk_src[] = { ++ F(133333333, P_GPLL0, 6, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 lpass_axim_clk_src = { ++ .cmd_rcgr = 0x2700c, ++ .freq_tbl = ftbl_lpass_axim_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "lpass_axim_clk_src", ++ .parent_data = gcc_xo_gpll0, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 lpass_sway_clk_src = { ++ .cmd_rcgr = 0x27004, ++ .freq_tbl = ftbl_lpass_axim_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "lpass_sway_clk_src", ++ .parent_data = gcc_xo_gpll0, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_adss_pwm_clk_src[] = { ++ F(24000000, P_XO, 1, 0, 0), ++ F(100000000, P_GPLL0, 8, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 adss_pwm_clk_src = { ++ .cmd_rcgr = 0x1c004, ++ .freq_tbl = ftbl_adss_pwm_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "adss_pwm_clk_src", ++ .parent_data = gcc_xo_gpll0, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_adss_pwm_clk = { ++ .halt_reg = 0x1c00c, ++ .clkr = { ++ .enable_reg = 0x1c00c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_adss_pwm_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &adss_pwm_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_gp1_clk_src[] = { ++ F(24000000, P_XO, 1, 0, 0), ++ F(200000000, P_GPLL0, 4, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 gp1_clk_src = { ++ .cmd_rcgr = 0x8004, ++ .freq_tbl = ftbl_gp1_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "gp1_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_sleep_clk, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 gp2_clk_src = { ++ .cmd_rcgr = 0x9004, ++ .freq_tbl = ftbl_gp1_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "gp2_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_sleep_clk, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 gp3_clk_src = { ++ .cmd_rcgr = 0xa004, ++ .freq_tbl = ftbl_gp1_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map, ++ .clkr.hw.init = &(struct clk_init_data) { ++ .name = "gp3_clk_src", ++ .parent_data = gcc_xo_gpll0_gpll0_sleep_clk, ++ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk), ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_xo_clk_src = { ++ .halt_reg = 0x34004, ++ .clkr = { ++ .enable_reg = 0x34004, ++ .enable_mask = BIT(1), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_xo_clk_src", ++ .parent_data = gcc_xo_data, ++ .num_parents = ARRAY_SIZE(gcc_xo_data), ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_nssnoc_xo_dcd_clk = { ++ .halt_reg = 0x17074, ++ .clkr = { ++ .enable_reg = 0x17074, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_nssnoc_xo_dcd_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &gcc_xo_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_xo_clk = { ++ .halt_reg = 0x34018, ++ .clkr = { ++ .enable_reg = 0x34018, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_xo_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &gcc_xo_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_uniphy0_sys_clk = { ++ .halt_reg = 0x17048, ++ .clkr = { ++ .enable_reg = 0x17048, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_uniphy0_sys_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &uniphy_sys_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_uniphy1_sys_clk = { ++ .halt_reg = 0x17058, ++ .clkr = { ++ .enable_reg = 0x17058, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_uniphy1_sys_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &uniphy_sys_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_uniphy2_sys_clk = { ++ .halt_reg = 0x17068, ++ .clkr = { ++ .enable_reg = 0x17068, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_uniphy2_sys_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &uniphy_sys_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_cmn_12gpll_sys_clk = { ++ .halt_reg = 0x3a008, ++ .clkr = { ++ .enable_reg = 0x3a008, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_cmn_12gpll_sys_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &uniphy_sys_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_fixed_factor gcc_xo_div4_clk_src = { ++ .mult = 1, ++ .div = 4, ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_xo_div4_clk_src", ++ .parent_hws = (const struct clk_hw *[]) { ++ &gcc_xo_clk_src.clkr.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_fixed_factor_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_nssnoc_qosgen_ref_clk = { ++ .halt_reg = 0x1701c, ++ .clkr = { ++ .enable_reg = 0x1701c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_nssnoc_qosgen_ref_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &gcc_xo_div4_clk_src.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_nssnoc_timeout_ref_clk = { ++ .halt_reg = 0x17020, ++ .clkr = { ++ .enable_reg = 0x17020, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_nssnoc_timeout_ref_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &gcc_xo_div4_clk_src.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_xo_div4_clk = { ++ .halt_reg = 0x3401c, ++ .clkr = { ++ .enable_reg = 0x3401c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data) { ++ .name = "gcc_xo_div4_clk", ++ .parent_hws = (const struct clk_hw *[]) { ++ &gcc_xo_div4_clk_src.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_hw *gcc_ipq9574_hws[] = { ++ &gpll0_out_main_div2.hw, ++ &gcc_xo_div4_clk_src.hw, ++ &qdss_dap_sync_clk_src.hw, ++ &qdss_tsctr_div2_clk_src.hw, ++ &qdss_tsctr_div8_clk_src.hw, ++ &qdss_tsctr_div16_clk_src.hw, ++ &qdss_tsctr_div3_clk_src.hw, ++ &gcc_eud_at_div_clk_src.hw, ++}; ++ ++static struct clk_regmap *gcc_ipq9574_clks[] = { ++ [GPLL0_MAIN] = &gpll0_main.clkr, ++ [GPLL0] = &gpll0.clkr, ++ [GPLL4_MAIN] = &gpll4_main.clkr, ++ [GPLL4] = &gpll4.clkr, ++ [GPLL2_MAIN] = &gpll2_main.clkr, ++ [GPLL2] = &gpll2.clkr, ++ [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr, ++ [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr, ++ [APSS_AXI_CLK_SRC] = &apss_axi_clk_src.clkr, ++ [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, ++ [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, ++ [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, ++ [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, ++ [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, ++ [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, ++ [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, ++ [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, ++ [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, ++ [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, ++ [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, ++ [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, ++ [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, ++ [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, ++ [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, ++ [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, ++ [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, ++ [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, ++ [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr, ++ [GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr, ++ [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, ++ [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, ++ [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, ++ [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, ++ [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, ++ [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, ++ [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, ++ [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, ++ [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, ++ [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, ++ [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, ++ [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, ++ [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, ++ [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, ++ [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, ++ [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, ++ [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, ++ [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, ++ [PCIE0_AXI_M_CLK_SRC] = &pcie0_axi_m_clk_src.clkr, ++ [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr, ++ [PCIE1_AXI_M_CLK_SRC] = &pcie1_axi_m_clk_src.clkr, ++ [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr, ++ [PCIE2_AXI_M_CLK_SRC] = &pcie2_axi_m_clk_src.clkr, ++ [GCC_PCIE2_AXI_M_CLK] = &gcc_pcie2_axi_m_clk.clkr, ++ [PCIE3_AXI_M_CLK_SRC] = &pcie3_axi_m_clk_src.clkr, ++ [GCC_PCIE3_AXI_M_CLK] = &gcc_pcie3_axi_m_clk.clkr, ++ [PCIE0_AXI_S_CLK_SRC] = &pcie0_axi_s_clk_src.clkr, ++ [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, ++ [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr, ++ [PCIE1_AXI_S_CLK_SRC] = &pcie1_axi_s_clk_src.clkr, ++ [GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr, ++ [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr, ++ [PCIE2_AXI_S_CLK_SRC] = &pcie2_axi_s_clk_src.clkr, ++ [GCC_PCIE2_AXI_S_BRIDGE_CLK] = &gcc_pcie2_axi_s_bridge_clk.clkr, ++ [GCC_PCIE2_AXI_S_CLK] = &gcc_pcie2_axi_s_clk.clkr, ++ [PCIE3_AXI_S_CLK_SRC] = &pcie3_axi_s_clk_src.clkr, ++ [GCC_PCIE3_AXI_S_BRIDGE_CLK] = &gcc_pcie3_axi_s_bridge_clk.clkr, ++ [GCC_PCIE3_AXI_S_CLK] = &gcc_pcie3_axi_s_clk.clkr, ++ [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr, ++ [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr, ++ [PCIE2_PIPE_CLK_SRC] = &pcie2_pipe_clk_src.clkr, ++ [PCIE3_PIPE_CLK_SRC] = &pcie3_pipe_clk_src.clkr, ++ [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr, ++ [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr, ++ [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr, ++ [GCC_PCIE2_AUX_CLK] = &gcc_pcie2_aux_clk.clkr, ++ [GCC_PCIE3_AUX_CLK] = &gcc_pcie3_aux_clk.clkr, ++ [PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr, ++ [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr, ++ [PCIE1_RCHNG_CLK_SRC] = &pcie1_rchng_clk_src.clkr, ++ [GCC_PCIE1_RCHNG_CLK] = &gcc_pcie1_rchng_clk.clkr, ++ [PCIE2_RCHNG_CLK_SRC] = &pcie2_rchng_clk_src.clkr, ++ [GCC_PCIE2_RCHNG_CLK] = &gcc_pcie2_rchng_clk.clkr, ++ [PCIE3_RCHNG_CLK_SRC] = &pcie3_rchng_clk_src.clkr, ++ [GCC_PCIE3_RCHNG_CLK] = &gcc_pcie3_rchng_clk.clkr, ++ [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr, ++ [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr, ++ [GCC_PCIE2_AHB_CLK] = &gcc_pcie2_ahb_clk.clkr, ++ [GCC_PCIE3_AHB_CLK] = &gcc_pcie3_ahb_clk.clkr, ++ [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr, ++ [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr, ++ [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr, ++ [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr, ++ [GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr, ++ [GCC_ANOC_USB_AXI_CLK] = &gcc_anoc_usb_axi_clk.clkr, ++ [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr, ++ [USB0_MOCK_UTMI_DIV_CLK_SRC] = &usb0_mock_utmi_div_clk_src.clkr, ++ [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr, ++ [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr, ++ [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr, ++ [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, ++ [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, ++ [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr, ++ [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr, ++ [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, ++ [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr, ++ [GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr, ++ [GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr, ++ [GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr, ++ [GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr, ++ [GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr, ++ [GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr, ++ [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr, ++ [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr, ++ [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, ++ [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr, ++ [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, ++ [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr, ++ [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr, ++ [GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr, ++ [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr, ++ [GCC_CMN_12GPLL_APU_CLK] = &gcc_cmn_12gpll_apu_clk.clkr, ++ [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr, ++ [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr, ++ [GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr, ++ [GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr, ++ [WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr, ++ [GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr, ++ [GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr, ++ [GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr, ++ [GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr, ++ [GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr, ++ [WCSS_AXI_M_CLK_SRC] = &wcss_axi_m_clk_src.clkr, ++ [GCC_ANOC_WCSS_AXI_M_CLK] = &gcc_anoc_wcss_axi_m_clk.clkr, ++ [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr, ++ [GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr, ++ [GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr, ++ [GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr, ++ [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, ++ [GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr, ++ [GCC_PCNOC_AT_CLK] = &gcc_pcnoc_at_clk.clkr, ++ [GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr, ++ [GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr, ++ [QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr, ++ [GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr, ++ [GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr, ++ [QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr, ++ [GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr, ++ [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr, ++ [GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr, ++ [GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr, ++ [GCC_QDSS_TSCTR_DIV2_CLK] = &gcc_qdss_tsctr_div2_clk.clkr, ++ [GCC_QDSS_TS_CLK] = &gcc_qdss_ts_clk.clkr, ++ [GCC_QDSS_TSCTR_DIV4_CLK] = &gcc_qdss_tsctr_div4_clk.clkr, ++ [GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr, ++ [GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr, ++ [GCC_QDSS_TSCTR_DIV16_CLK] = &gcc_qdss_tsctr_div16_clk.clkr, ++ [GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr, ++ [GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr, ++ [GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr, ++ [GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr, ++ [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, ++ [GCC_QDSS_APB2JTAG_CLK] = &gcc_qdss_apb2jtag_clk.clkr, ++ [GCC_QDSS_TSCTR_DIV3_CLK] = &gcc_qdss_tsctr_div3_clk.clkr, ++ [QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr, ++ [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr, ++ [Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr, ++ [GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr, ++ [GCC_WCSS_Q6_TBU_CLK] = &gcc_wcss_q6_tbu_clk.clkr, ++ [GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr, ++ [Q6_AXIM2_CLK_SRC] = &q6_axim2_clk_src.clkr, ++ [NSSNOC_MEMNOC_BFDCD_CLK_SRC] = &nssnoc_memnoc_bfdcd_clk_src.clkr, ++ [GCC_NSSNOC_MEMNOC_CLK] = &gcc_nssnoc_memnoc_clk.clkr, ++ [GCC_NSSNOC_MEM_NOC_1_CLK] = &gcc_nssnoc_mem_noc_1_clk.clkr, ++ [GCC_NSS_TBU_CLK] = &gcc_nss_tbu_clk.clkr, ++ [GCC_MEM_NOC_NSSNOC_CLK] = &gcc_mem_noc_nssnoc_clk.clkr, ++ [LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr, ++ [LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr, ++ [ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr, ++ [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr, ++ [GP1_CLK_SRC] = &gp1_clk_src.clkr, ++ [GP2_CLK_SRC] = &gp2_clk_src.clkr, ++ [GP3_CLK_SRC] = &gp3_clk_src.clkr, ++ [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr, ++ [GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr, ++ [GCC_XO_CLK] = &gcc_xo_clk.clkr, ++ [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr, ++ [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr, ++ [GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr, ++ [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr, ++ [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr, ++ [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr, ++ [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr, ++ [GCC_Q6SS_BOOT_CLK] = &gcc_q6ss_boot_clk.clkr, ++ [UNIPHY_SYS_CLK_SRC] = &uniphy_sys_clk_src.clkr, ++ [NSS_TS_CLK_SRC] = &nss_ts_clk_src.clkr, ++ [GCC_ANOC_PCIE0_1LANE_M_CLK] = &gcc_anoc_pcie0_1lane_m_clk.clkr, ++ [GCC_ANOC_PCIE1_1LANE_M_CLK] = &gcc_anoc_pcie1_1lane_m_clk.clkr, ++ [GCC_ANOC_PCIE2_2LANE_M_CLK] = &gcc_anoc_pcie2_2lane_m_clk.clkr, ++ [GCC_ANOC_PCIE3_2LANE_M_CLK] = &gcc_anoc_pcie3_2lane_m_clk.clkr, ++ [GCC_SNOC_PCIE0_1LANE_S_CLK] = &gcc_snoc_pcie0_1lane_s_clk.clkr, ++ [GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr, ++ [GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr, ++ [GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr, ++}; ++ ++static const struct qcom_reset_map gcc_ipq9574_resets[] = { ++ [GCC_ADSS_BCR] = { 0x1c000, 0 }, ++ [GCC_ANOC0_TBU_BCR] = { 0x1203c, 0 }, ++ [GCC_ANOC1_TBU_BCR] = { 0x1204c, 0 }, ++ [GCC_ANOC_BCR] = { 0x2e074, 0 }, ++ [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000, 0 }, ++ [GCC_APSS_TCU_BCR] = { 0x12014, 0 }, ++ [GCC_BLSP1_BCR] = { 0x01000, 0 }, ++ [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 }, ++ [GCC_BLSP1_QUP2_BCR] = { 0x03000, 0 }, ++ [GCC_BLSP1_QUP3_BCR] = { 0x04000, 0 }, ++ [GCC_BLSP1_QUP4_BCR] = { 0x05000, 0 }, ++ [GCC_BLSP1_QUP5_BCR] = { 0x06000, 0 }, ++ [GCC_BLSP1_QUP6_BCR] = { 0x07000, 0 }, ++ [GCC_BLSP1_UART1_BCR] = { 0x02028, 0 }, ++ [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 }, ++ [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 }, ++ [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 }, ++ [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 }, ++ [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 }, ++ [GCC_BOOT_ROM_BCR] = { 0x13028, 0 }, ++ [GCC_CMN_BLK_BCR] = { 0x3a000, 0 }, ++ [GCC_CMN_BLK_AHB_ARES] = { 0x3a010, 0 }, ++ [GCC_CMN_BLK_SYS_ARES] = { 0x3a010, 1 }, ++ [GCC_CMN_BLK_APU_ARES] = { 0x3a010, 2 }, ++ [GCC_DCC_BCR] = { 0x35000, 0 }, ++ [GCC_DDRSS_BCR] = { 0x11000, 0 }, ++ [GCC_IMEM_BCR] = { 0x0e000, 0 }, ++ [GCC_LPASS_BCR] = { 0x27000, 0 }, ++ [GCC_MDIO_BCR] = { 0x1703c, 0 }, ++ [GCC_MPM_BCR] = { 0x37000, 0 }, ++ [GCC_MSG_RAM_BCR] = { 0x26000, 0 }, ++ [GCC_NSS_BCR] = { 0x17000, 0 }, ++ [GCC_NSS_TBU_BCR] = { 0x12044, 0 }, ++ [GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17038, 13 }, ++ [GCC_NSSNOC_PCNOC_1_ARES] = { 0x17038, 12 }, ++ [GCC_NSSNOC_SNOC_1_ARES] = { 0x17038, 11 }, ++ [GCC_NSSNOC_XO_DCD_ARES] = { 0x17038, 10 }, ++ [GCC_NSSNOC_TS_ARES] = { 0x17038, 9 }, ++ [GCC_NSSCC_ARES] = { 0x17038, 8 }, ++ [GCC_NSSNOC_NSSCC_ARES] = { 0x17038, 7 }, ++ [GCC_NSSNOC_ATB_ARES] = { 0x17038, 6 }, ++ [GCC_NSSNOC_MEMNOC_ARES] = { 0x17038, 5 }, ++ [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x17038, 4 }, ++ [GCC_NSSNOC_SNOC_ARES] = { 0x17038, 3 }, ++ [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17038, 2 }, ++ [GCC_NSS_CFG_ARES] = { 0x17038, 1 }, ++ [GCC_UBI0_DBG_ARES] = { 0x17038, 0 }, ++ [GCC_PCIE0PHY_PHY_BCR] = { 0x2805c, 0 }, ++ [GCC_PCIE0_AHB_ARES] = { 0x28058, 7 }, ++ [GCC_PCIE0_AUX_ARES] = { 0x28058, 6 }, ++ [GCC_PCIE0_AXI_M_ARES] = { 0x28058, 5 }, ++ [GCC_PCIE0_AXI_M_STICKY_ARES] = { 0x28058, 4 }, ++ [GCC_PCIE0_AXI_S_ARES] = { 0x28058, 3 }, ++ [GCC_PCIE0_AXI_S_STICKY_ARES] = { 0x28058, 2 }, ++ [GCC_PCIE0_CORE_STICKY_ARES] = { 0x28058, 1 }, ++ [GCC_PCIE0_PIPE_ARES] = { 0x28058, 0 }, ++ [GCC_PCIE1_AHB_ARES] = { 0x29058, 7 }, ++ [GCC_PCIE1_AUX_ARES] = { 0x29058, 6 }, ++ [GCC_PCIE1_AXI_M_ARES] = { 0x29058, 5 }, ++ [GCC_PCIE1_AXI_M_STICKY_ARES] = { 0x29058, 4 }, ++ [GCC_PCIE1_AXI_S_ARES] = { 0x29058, 3 }, ++ [GCC_PCIE1_AXI_S_STICKY_ARES] = { 0x29058, 2 }, ++ [GCC_PCIE1_CORE_STICKY_ARES] = { 0x29058, 1 }, ++ [GCC_PCIE1_PIPE_ARES] = { 0x29058, 0 }, ++ [GCC_PCIE2_AHB_ARES] = { 0x2a058, 7 }, ++ [GCC_PCIE2_AUX_ARES] = { 0x2a058, 6 }, ++ [GCC_PCIE2_AXI_M_ARES] = { 0x2a058, 5 }, ++ [GCC_PCIE2_AXI_M_STICKY_ARES] = { 0x2a058, 4 }, ++ [GCC_PCIE2_AXI_S_ARES] = { 0x2a058, 3 }, ++ [GCC_PCIE2_AXI_S_STICKY_ARES] = { 0x2a058, 2 }, ++ [GCC_PCIE2_CORE_STICKY_ARES] = { 0x2a058, 1 }, ++ [GCC_PCIE2_PIPE_ARES] = { 0x2a058, 0 }, ++ [GCC_PCIE3_AHB_ARES] = { 0x2b058, 7 }, ++ [GCC_PCIE3_AUX_ARES] = { 0x2b058, 6 }, ++ [GCC_PCIE3_AXI_M_ARES] = { 0x2b058, 5 }, ++ [GCC_PCIE3_AXI_M_STICKY_ARES] = { 0x2b058, 4 }, ++ [GCC_PCIE3_AXI_S_ARES] = { 0x2b058, 3 }, ++ [GCC_PCIE3_AXI_S_STICKY_ARES] = { 0x2b058, 2 }, ++ [GCC_PCIE3_CORE_STICKY_ARES] = { 0x2b058, 1 }, ++ [GCC_PCIE3_PIPE_ARES] = { 0x2b058, 0 }, ++ [GCC_PCIE0_BCR] = { 0x28000, 0 }, ++ [GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054, 0 }, ++ [GCC_PCIE0_PHY_BCR] = { 0x28060, 0 }, ++ [GCC_PCIE1_BCR] = { 0x29000, 0 }, ++ [GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054, 0 }, ++ [GCC_PCIE1_PHY_BCR] = { 0x29060, 0 }, ++ [GCC_PCIE1PHY_PHY_BCR] = { 0x2905c, 0 }, ++ [GCC_PCIE2_BCR] = { 0x2a000, 0 }, ++ [GCC_PCIE2_LINK_DOWN_BCR] = { 0x2a054, 0 }, ++ [GCC_PCIE2_PHY_BCR] = { 0x2a060, 0 }, ++ [GCC_PCIE2PHY_PHY_BCR] = { 0x2a05c, 0 }, ++ [GCC_PCIE3_BCR] = { 0x2b000, 0 }, ++ [GCC_PCIE3_LINK_DOWN_BCR] = { 0x2b054, 0 }, ++ [GCC_PCIE3PHY_PHY_BCR] = { 0x2b05c, 0 }, ++ [GCC_PCIE3_PHY_BCR] = { 0x2b060, 0 }, ++ [GCC_PCNOC_BCR] = { 0x31000, 0 }, ++ [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x31030, 0 }, ++ [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x31038, 0 }, ++ [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x31040, 0 }, ++ [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x31048, 0 }, ++ [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x31050, 0 }, ++ [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x31058, 0 }, ++ [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x31060, 0 }, ++ [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x31068, 0 }, ++ [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x31070, 0 }, ++ [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x31078, 0 }, ++ [GCC_PCNOC_TBU_BCR] = { 0x12034, 0 }, ++ [GCC_PRNG_BCR] = { 0x13020, 0 }, ++ [GCC_Q6SS_DBG_ARES] = { 0x2506c, 4 }, ++ [GCC_Q6_AHB_ARES] = { 0x2506c, 3 }, ++ [GCC_Q6_AHB_S_ARES] = { 0x2506c, 2 }, ++ [GCC_Q6_AXIM2_ARES] = { 0x2506c, 1 }, ++ [GCC_Q6_AXIM_ARES] = { 0x2506c, 0 }, ++ [GCC_QDSS_BCR] = { 0x2d000, 0 }, ++ [GCC_QPIC_BCR] = { 0x32000, 0 }, ++ [GCC_QPIC_AHB_ARES] = { 0x3201c, 1 }, ++ [GCC_QPIC_ARES] = { 0x3201c, 0 }, ++ [GCC_QUSB2_0_PHY_BCR] = { 0x2c068, 0 }, ++ [GCC_RBCPR_BCR] = { 0x39000, 0 }, ++ [GCC_RBCPR_MX_BCR] = { 0x39014, 0 }, ++ [GCC_SDCC_BCR] = { 0x33000, 0 }, ++ [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 }, ++ [GCC_SMMU_CFG_BCR] = { 0x1202c, 0 }, ++ [GCC_SNOC_BCR] = { 0x2e000, 0 }, ++ [GCC_SPDM_BCR] = { 0x36000, 0 }, ++ [GCC_TCSR_BCR] = { 0x3d000, 0 }, ++ [GCC_TLMM_BCR] = { 0x3e000, 0 }, ++ [GCC_TME_BCR] = { 0x10000, 0 }, ++ [GCC_UNIPHY0_BCR] = { 0x17044, 0 }, ++ [GCC_UNIPHY0_SYS_RESET] = { 0x17050, 0 }, ++ [GCC_UNIPHY0_AHB_RESET] = { 0x17050, 1 }, ++ [GCC_UNIPHY0_XPCS_RESET] = { 0x17050, 2 }, ++ [GCC_UNIPHY1_SYS_RESET] = { 0x17060, 0 }, ++ [GCC_UNIPHY1_AHB_RESET] = { 0x17060, 1 }, ++ [GCC_UNIPHY1_XPCS_RESET] = { 0x17060, 2 }, ++ [GCC_UNIPHY2_SYS_RESET] = { 0x17070, 0 }, ++ [GCC_UNIPHY2_AHB_RESET] = { 0x17070, 1 }, ++ [GCC_UNIPHY2_XPCS_RESET] = { 0x17070, 2 }, ++ [GCC_UNIPHY1_BCR] = { 0x17054, 0 }, ++ [GCC_UNIPHY2_BCR] = { 0x17064, 0 }, ++ [GCC_USB0_PHY_BCR] = { 0x2c06c, 0 }, ++ [GCC_USB3PHY_0_PHY_BCR] = { 0x2c070, 0 }, ++ [GCC_USB_BCR] = { 0x2c000, 0 }, ++ [GCC_USB_MISC_RESET] = { 0x2c064, 0 }, ++ [GCC_WCSSAON_RESET] = { 0x25074, 0 }, ++ [GCC_WCSS_ACMT_ARES] = { 0x25070, 5 }, ++ [GCC_WCSS_AHB_S_ARES] = { 0x25070, 4 }, ++ [GCC_WCSS_AXI_M_ARES] = { 0x25070, 3 }, ++ [GCC_WCSS_BCR] = { 0x18004, 0 }, ++ [GCC_WCSS_DBG_ARES] = { 0x25070, 2 }, ++ [GCC_WCSS_DBG_BDG_ARES] = { 0x25070, 1 }, ++ [GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 }, ++ [GCC_WCSS_Q6_BCR] = { 0x18000, 0 }, ++ [GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 }, ++}; ++ ++static const struct of_device_id gcc_ipq9574_match_table[] = { ++ { .compatible = "qcom,ipq9574-gcc" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, gcc_ipq9574_match_table); ++ ++static const struct regmap_config gcc_ipq9574_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = 0x7fffc, ++ .fast_io = true, ++}; ++ ++static const struct qcom_cc_desc gcc_ipq9574_desc = { ++ .config = &gcc_ipq9574_regmap_config, ++ .clks = gcc_ipq9574_clks, ++ .num_clks = ARRAY_SIZE(gcc_ipq9574_clks), ++ .resets = gcc_ipq9574_resets, ++ .num_resets = ARRAY_SIZE(gcc_ipq9574_resets), ++ .clk_hws = gcc_ipq9574_hws, ++ .num_clk_hws = ARRAY_SIZE(gcc_ipq9574_hws), ++}; ++ ++static int gcc_ipq9574_probe(struct platform_device *pdev) ++{ ++ return qcom_cc_probe(pdev, &gcc_ipq9574_desc); ++} ++ ++static struct platform_driver gcc_ipq9574_driver = { ++ .probe = gcc_ipq9574_probe, ++ .driver = { ++ .name = "qcom,gcc-ipq9574", ++ .of_match_table = gcc_ipq9574_match_table, ++ }, ++}; ++ ++static int __init gcc_ipq9574_init(void) ++{ ++ return platform_driver_register(&gcc_ipq9574_driver); ++} ++core_initcall(gcc_ipq9574_init); ++ ++static void __exit gcc_ipq9574_exit(void) ++{ ++ platform_driver_unregister(&gcc_ipq9574_driver); ++} ++module_exit(gcc_ipq9574_exit); ++ ++MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ9574 Driver"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/ipq95xx/patches-6.1/0008-dt-bindings-clock-Add-ipq9574-clock-and-reset-defini.patch b/target/linux/ipq95xx/patches-6.1/0008-dt-bindings-clock-Add-ipq9574-clock-and-reset-defini.patch new file mode 100644 index 00000000000000..61d2453b5e4bc1 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0008-dt-bindings-clock-Add-ipq9574-clock-and-reset-defini.patch @@ -0,0 +1,470 @@ +From 471b2c31ee9c3a0ab76f9ccb6a514cb9713afd80 Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Thu, 16 Mar 2023 12:59:35 +0530 +Subject: [PATCH 08/41] dt-bindings: clock: Add ipq9574 clock and reset + definitions + +Add clock and reset ID definitions for ipq9574 + +Reviewed-by: Krzysztof Kozlowski +Co-developed-by: Anusha Rao +Signed-off-by: Anusha Rao +Signed-off-by: Devi Priya +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230316072940.29137-2-quic_devipriy@quicinc.com +--- + .../bindings/clock/qcom,ipq9574-gcc.yaml | 61 +++++ + include/dt-bindings/clock/qcom,ipq9574-gcc.h | 213 ++++++++++++++++++ + include/dt-bindings/reset/qcom,ipq9574-gcc.h | 164 ++++++++++++++ + 3 files changed, 438 insertions(+) + create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml + create mode 100644 include/dt-bindings/clock/qcom,ipq9574-gcc.h + create mode 100644 include/dt-bindings/reset/qcom,ipq9574-gcc.h + +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml +@@ -0,0 +1,61 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/clock/qcom,ipq9574-gcc.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Qualcomm Global Clock & Reset Controller on IPQ9574 ++ ++maintainers: ++ - Anusha Rao ++ ++description: | ++ Qualcomm global clock control module provides the clocks, resets and power ++ domains on IPQ9574 ++ ++ See also:: ++ include/dt-bindings/clock/qcom,ipq9574-gcc.h ++ include/dt-bindings/reset/qcom,ipq9574-gcc.h ++ ++properties: ++ compatible: ++ const: qcom,ipq9574-gcc ++ ++ clocks: ++ items: ++ - description: Board XO source ++ - description: Sleep clock source ++ - description: Bias PLL ubi clock source ++ - description: PCIE30 PHY0 pipe clock source ++ - description: PCIE30 PHY1 pipe clock source ++ - description: PCIE30 PHY2 pipe clock source ++ - description: PCIE30 PHY3 pipe clock source ++ - description: USB3 PHY pipe clock source ++ ++required: ++ - compatible ++ - clocks ++ ++allOf: ++ - $ref: qcom,gcc.yaml# ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ clock-controller@1800000 { ++ compatible = "qcom,ipq9574-gcc"; ++ reg = <0x01800000 0x80000>; ++ clocks = <&xo_board_clk>, ++ <&sleep_clk>, ++ <&bias_pll_ubi_nc_clk>, ++ <&pcie30_phy0_pipe_clk>, ++ <&pcie30_phy1_pipe_clk>, ++ <&pcie30_phy2_pipe_clk>, ++ <&pcie30_phy3_pipe_clk>, ++ <&usb3phy_0_cc_pipe_clk>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ #power-domain-cells = <1>; ++ }; ++... +--- /dev/null ++++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h +@@ -0,0 +1,213 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ ++/* ++ * Copyright (c) 2018-2023 The Linux Foundation. All rights reserved. ++ */ ++ ++#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_9574_H ++#define _DT_BINDINGS_CLOCK_IPQ_GCC_9574_H ++ ++#define GPLL0_MAIN 0 ++#define GPLL0 1 ++#define GPLL2_MAIN 2 ++#define GPLL2 3 ++#define GPLL4_MAIN 4 ++#define GPLL4 5 ++#define GCC_SLEEP_CLK_SRC 6 ++#define APSS_AHB_CLK_SRC 7 ++#define APSS_AXI_CLK_SRC 8 ++#define BLSP1_QUP1_I2C_APPS_CLK_SRC 9 ++#define BLSP1_QUP1_SPI_APPS_CLK_SRC 10 ++#define BLSP1_QUP2_I2C_APPS_CLK_SRC 11 ++#define BLSP1_QUP2_SPI_APPS_CLK_SRC 12 ++#define BLSP1_QUP3_I2C_APPS_CLK_SRC 13 ++#define BLSP1_QUP3_SPI_APPS_CLK_SRC 14 ++#define BLSP1_QUP4_I2C_APPS_CLK_SRC 15 ++#define BLSP1_QUP4_SPI_APPS_CLK_SRC 16 ++#define BLSP1_QUP5_I2C_APPS_CLK_SRC 17 ++#define BLSP1_QUP5_SPI_APPS_CLK_SRC 18 ++#define BLSP1_QUP6_I2C_APPS_CLK_SRC 19 ++#define BLSP1_QUP6_SPI_APPS_CLK_SRC 20 ++#define BLSP1_UART1_APPS_CLK_SRC 21 ++#define BLSP1_UART2_APPS_CLK_SRC 22 ++#define BLSP1_UART3_APPS_CLK_SRC 23 ++#define BLSP1_UART4_APPS_CLK_SRC 24 ++#define BLSP1_UART5_APPS_CLK_SRC 25 ++#define BLSP1_UART6_APPS_CLK_SRC 26 ++#define GCC_APSS_AHB_CLK 27 ++#define GCC_APSS_AXI_CLK 28 ++#define GCC_BLSP1_QUP1_I2C_APPS_CLK 29 ++#define GCC_BLSP1_QUP1_SPI_APPS_CLK 30 ++#define GCC_BLSP1_QUP2_I2C_APPS_CLK 31 ++#define GCC_BLSP1_QUP2_SPI_APPS_CLK 32 ++#define GCC_BLSP1_QUP3_I2C_APPS_CLK 33 ++#define GCC_BLSP1_QUP3_SPI_APPS_CLK 34 ++#define GCC_BLSP1_QUP4_I2C_APPS_CLK 35 ++#define GCC_BLSP1_QUP4_SPI_APPS_CLK 36 ++#define GCC_BLSP1_QUP5_I2C_APPS_CLK 37 ++#define GCC_BLSP1_QUP5_SPI_APPS_CLK 38 ++#define GCC_BLSP1_QUP6_I2C_APPS_CLK 39 ++#define GCC_BLSP1_QUP6_SPI_APPS_CLK 40 ++#define GCC_BLSP1_UART1_APPS_CLK 41 ++#define GCC_BLSP1_UART2_APPS_CLK 42 ++#define GCC_BLSP1_UART3_APPS_CLK 43 ++#define GCC_BLSP1_UART4_APPS_CLK 44 ++#define GCC_BLSP1_UART5_APPS_CLK 45 ++#define GCC_BLSP1_UART6_APPS_CLK 46 ++#define PCIE0_AXI_M_CLK_SRC 47 ++#define GCC_PCIE0_AXI_M_CLK 48 ++#define PCIE1_AXI_M_CLK_SRC 49 ++#define GCC_PCIE1_AXI_M_CLK 50 ++#define PCIE2_AXI_M_CLK_SRC 51 ++#define GCC_PCIE2_AXI_M_CLK 52 ++#define PCIE3_AXI_M_CLK_SRC 53 ++#define GCC_PCIE3_AXI_M_CLK 54 ++#define PCIE0_AXI_S_CLK_SRC 55 ++#define GCC_PCIE0_AXI_S_BRIDGE_CLK 56 ++#define GCC_PCIE0_AXI_S_CLK 57 ++#define PCIE1_AXI_S_CLK_SRC 58 ++#define GCC_PCIE1_AXI_S_BRIDGE_CLK 59 ++#define GCC_PCIE1_AXI_S_CLK 60 ++#define PCIE2_AXI_S_CLK_SRC 61 ++#define GCC_PCIE2_AXI_S_BRIDGE_CLK 62 ++#define GCC_PCIE2_AXI_S_CLK 63 ++#define PCIE3_AXI_S_CLK_SRC 64 ++#define GCC_PCIE3_AXI_S_BRIDGE_CLK 65 ++#define GCC_PCIE3_AXI_S_CLK 66 ++#define PCIE0_PIPE_CLK_SRC 67 ++#define PCIE1_PIPE_CLK_SRC 68 ++#define PCIE2_PIPE_CLK_SRC 69 ++#define PCIE3_PIPE_CLK_SRC 70 ++#define PCIE_AUX_CLK_SRC 71 ++#define GCC_PCIE0_AUX_CLK 72 ++#define GCC_PCIE1_AUX_CLK 73 ++#define GCC_PCIE2_AUX_CLK 74 ++#define GCC_PCIE3_AUX_CLK 75 ++#define PCIE0_RCHNG_CLK_SRC 76 ++#define GCC_PCIE0_RCHNG_CLK 77 ++#define PCIE1_RCHNG_CLK_SRC 78 ++#define GCC_PCIE1_RCHNG_CLK 79 ++#define PCIE2_RCHNG_CLK_SRC 80 ++#define GCC_PCIE2_RCHNG_CLK 81 ++#define PCIE3_RCHNG_CLK_SRC 82 ++#define GCC_PCIE3_RCHNG_CLK 83 ++#define GCC_PCIE0_AHB_CLK 84 ++#define GCC_PCIE1_AHB_CLK 85 ++#define GCC_PCIE2_AHB_CLK 86 ++#define GCC_PCIE3_AHB_CLK 87 ++#define USB0_AUX_CLK_SRC 88 ++#define GCC_USB0_AUX_CLK 89 ++#define USB0_MASTER_CLK_SRC 90 ++#define GCC_USB0_MASTER_CLK 91 ++#define GCC_SNOC_USB_CLK 92 ++#define GCC_ANOC_USB_AXI_CLK 93 ++#define USB0_MOCK_UTMI_CLK_SRC 94 ++#define USB0_MOCK_UTMI_DIV_CLK_SRC 95 ++#define GCC_USB0_MOCK_UTMI_CLK 96 ++#define USB0_PIPE_CLK_SRC 97 ++#define GCC_USB0_PHY_CFG_AHB_CLK 98 ++#define SDCC1_APPS_CLK_SRC 99 ++#define GCC_SDCC1_APPS_CLK 100 ++#define SDCC1_ICE_CORE_CLK_SRC 101 ++#define GCC_SDCC1_ICE_CORE_CLK 102 ++#define GCC_SDCC1_AHB_CLK 103 ++#define PCNOC_BFDCD_CLK_SRC 104 ++#define GCC_NSSCFG_CLK 105 ++#define GCC_NSSNOC_NSSCC_CLK 106 ++#define GCC_NSSCC_CLK 107 ++#define GCC_NSSNOC_PCNOC_1_CLK 108 ++#define GCC_QDSS_DAP_AHB_CLK 109 ++#define GCC_QDSS_CFG_AHB_CLK 110 ++#define GCC_QPIC_AHB_CLK 111 ++#define GCC_QPIC_CLK 112 ++#define GCC_BLSP1_AHB_CLK 113 ++#define GCC_MDIO_AHB_CLK 114 ++#define GCC_PRNG_AHB_CLK 115 ++#define GCC_UNIPHY0_AHB_CLK 116 ++#define GCC_UNIPHY1_AHB_CLK 117 ++#define GCC_UNIPHY2_AHB_CLK 118 ++#define GCC_CMN_12GPLL_AHB_CLK 119 ++#define GCC_CMN_12GPLL_APU_CLK 120 ++#define SYSTEM_NOC_BFDCD_CLK_SRC 121 ++#define GCC_NSSNOC_SNOC_CLK 122 ++#define GCC_NSSNOC_SNOC_1_CLK 123 ++#define GCC_QDSS_ETR_USB_CLK 124 ++#define WCSS_AHB_CLK_SRC 125 ++#define GCC_Q6_AHB_CLK 126 ++#define GCC_Q6_AHB_S_CLK 127 ++#define GCC_WCSS_ECAHB_CLK 128 ++#define GCC_WCSS_ACMT_CLK 129 ++#define GCC_SYS_NOC_WCSS_AHB_CLK 130 ++#define WCSS_AXI_M_CLK_SRC 131 ++#define GCC_ANOC_WCSS_AXI_M_CLK 132 ++#define QDSS_AT_CLK_SRC 133 ++#define GCC_Q6SS_ATBM_CLK 134 ++#define GCC_WCSS_DBG_IFC_ATB_CLK 135 ++#define GCC_NSSNOC_ATB_CLK 136 ++#define GCC_QDSS_AT_CLK 137 ++#define GCC_SYS_NOC_AT_CLK 138 ++#define GCC_PCNOC_AT_CLK 139 ++#define GCC_USB0_EUD_AT_CLK 140 ++#define GCC_QDSS_EUD_AT_CLK 141 ++#define QDSS_STM_CLK_SRC 142 ++#define GCC_QDSS_STM_CLK 143 ++#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 144 ++#define QDSS_TRACECLKIN_CLK_SRC 145 ++#define GCC_QDSS_TRACECLKIN_CLK 146 ++#define QDSS_TSCTR_CLK_SRC 147 ++#define GCC_Q6_TSCTR_1TO2_CLK 148 ++#define GCC_WCSS_DBG_IFC_NTS_CLK 149 ++#define GCC_QDSS_TSCTR_DIV2_CLK 150 ++#define GCC_QDSS_TS_CLK 151 ++#define GCC_QDSS_TSCTR_DIV4_CLK 152 ++#define GCC_NSS_TS_CLK 153 ++#define GCC_QDSS_TSCTR_DIV8_CLK 154 ++#define GCC_QDSS_TSCTR_DIV16_CLK 155 ++#define GCC_Q6SS_PCLKDBG_CLK 156 ++#define GCC_Q6SS_TRIG_CLK 157 ++#define GCC_WCSS_DBG_IFC_APB_CLK 158 ++#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 159 ++#define GCC_QDSS_DAP_CLK 160 ++#define GCC_QDSS_APB2JTAG_CLK 161 ++#define GCC_QDSS_TSCTR_DIV3_CLK 162 ++#define QPIC_IO_MACRO_CLK_SRC 163 ++#define GCC_QPIC_IO_MACRO_CLK 164 ++#define Q6_AXI_CLK_SRC 165 ++#define GCC_Q6_AXIM_CLK 166 ++#define GCC_WCSS_Q6_TBU_CLK 167 ++#define GCC_MEM_NOC_Q6_AXI_CLK 168 ++#define Q6_AXIM2_CLK_SRC 169 ++#define NSSNOC_MEMNOC_BFDCD_CLK_SRC 170 ++#define GCC_NSSNOC_MEMNOC_CLK 171 ++#define GCC_NSSNOC_MEM_NOC_1_CLK 172 ++#define GCC_NSS_TBU_CLK 173 ++#define GCC_MEM_NOC_NSSNOC_CLK 174 ++#define LPASS_AXIM_CLK_SRC 175 ++#define LPASS_SWAY_CLK_SRC 176 ++#define ADSS_PWM_CLK_SRC 177 ++#define GCC_ADSS_PWM_CLK 178 ++#define GP1_CLK_SRC 179 ++#define GP2_CLK_SRC 180 ++#define GP3_CLK_SRC 181 ++#define DDRSS_SMS_SLOW_CLK_SRC 182 ++#define GCC_XO_CLK_SRC 183 ++#define GCC_XO_CLK 184 ++#define GCC_NSSNOC_QOSGEN_REF_CLK 185 ++#define GCC_NSSNOC_TIMEOUT_REF_CLK 186 ++#define GCC_XO_DIV4_CLK 187 ++#define GCC_UNIPHY0_SYS_CLK 188 ++#define GCC_UNIPHY1_SYS_CLK 189 ++#define GCC_UNIPHY2_SYS_CLK 190 ++#define GCC_CMN_12GPLL_SYS_CLK 191 ++#define GCC_NSSNOC_XO_DCD_CLK 192 ++#define GCC_Q6SS_BOOT_CLK 193 ++#define UNIPHY_SYS_CLK_SRC 194 ++#define NSS_TS_CLK_SRC 195 ++#define GCC_ANOC_PCIE0_1LANE_M_CLK 196 ++#define GCC_ANOC_PCIE1_1LANE_M_CLK 197 ++#define GCC_ANOC_PCIE2_2LANE_M_CLK 198 ++#define GCC_ANOC_PCIE3_2LANE_M_CLK 199 ++#define GCC_SNOC_PCIE0_1LANE_S_CLK 200 ++#define GCC_SNOC_PCIE1_1LANE_S_CLK 201 ++#define GCC_SNOC_PCIE2_2LANE_S_CLK 202 ++#define GCC_SNOC_PCIE3_2LANE_S_CLK 203 ++#endif +--- /dev/null ++++ b/include/dt-bindings/reset/qcom,ipq9574-gcc.h +@@ -0,0 +1,164 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ ++/* ++ * Copyright (c) 2018-2023, The Linux Foundation. All rights reserved. ++ */ ++ ++#ifndef _DT_BINDINGS_RESET_IPQ_GCC_9574_H ++#define _DT_BINDINGS_RESET_IPQ_GCC_9574_H ++ ++#define GCC_ADSS_BCR 0 ++#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 1 ++#define GCC_BLSP1_BCR 2 ++#define GCC_BLSP1_QUP1_BCR 3 ++#define GCC_BLSP1_QUP2_BCR 4 ++#define GCC_BLSP1_QUP3_BCR 5 ++#define GCC_BLSP1_QUP4_BCR 6 ++#define GCC_BLSP1_QUP5_BCR 7 ++#define GCC_BLSP1_QUP6_BCR 8 ++#define GCC_BLSP1_UART1_BCR 9 ++#define GCC_BLSP1_UART2_BCR 10 ++#define GCC_BLSP1_UART3_BCR 11 ++#define GCC_BLSP1_UART4_BCR 12 ++#define GCC_BLSP1_UART5_BCR 13 ++#define GCC_BLSP1_UART6_BCR 14 ++#define GCC_BOOT_ROM_BCR 15 ++#define GCC_MDIO_BCR 16 ++#define GCC_NSS_BCR 17 ++#define GCC_NSS_TBU_BCR 18 ++#define GCC_PCIE0_BCR 19 ++#define GCC_PCIE0_LINK_DOWN_BCR 20 ++#define GCC_PCIE0_PHY_BCR 21 ++#define GCC_PCIE0PHY_PHY_BCR 22 ++#define GCC_PCIE1_BCR 23 ++#define GCC_PCIE1_LINK_DOWN_BCR 24 ++#define GCC_PCIE1_PHY_BCR 25 ++#define GCC_PCIE1PHY_PHY_BCR 26 ++#define GCC_PCIE2_BCR 27 ++#define GCC_PCIE2_LINK_DOWN_BCR 28 ++#define GCC_PCIE2_PHY_BCR 29 ++#define GCC_PCIE2PHY_PHY_BCR 30 ++#define GCC_PCIE3_BCR 31 ++#define GCC_PCIE3_LINK_DOWN_BCR 32 ++#define GCC_PCIE3_PHY_BCR 33 ++#define GCC_PCIE3PHY_PHY_BCR 34 ++#define GCC_PRNG_BCR 35 ++#define GCC_QUSB2_0_PHY_BCR 36 ++#define GCC_SDCC_BCR 37 ++#define GCC_TLMM_BCR 38 ++#define GCC_UNIPHY0_BCR 39 ++#define GCC_UNIPHY1_BCR 40 ++#define GCC_UNIPHY2_BCR 41 ++#define GCC_USB0_PHY_BCR 42 ++#define GCC_USB3PHY_0_PHY_BCR 43 ++#define GCC_USB_BCR 44 ++#define GCC_ANOC0_TBU_BCR 45 ++#define GCC_ANOC1_TBU_BCR 46 ++#define GCC_ANOC_BCR 47 ++#define GCC_APSS_TCU_BCR 48 ++#define GCC_CMN_BLK_BCR 49 ++#define GCC_CMN_BLK_AHB_ARES 50 ++#define GCC_CMN_BLK_SYS_ARES 51 ++#define GCC_CMN_BLK_APU_ARES 52 ++#define GCC_DCC_BCR 53 ++#define GCC_DDRSS_BCR 54 ++#define GCC_IMEM_BCR 55 ++#define GCC_LPASS_BCR 56 ++#define GCC_MPM_BCR 57 ++#define GCC_MSG_RAM_BCR 58 ++#define GCC_NSSNOC_MEMNOC_1_ARES 59 ++#define GCC_NSSNOC_PCNOC_1_ARES 60 ++#define GCC_NSSNOC_SNOC_1_ARES 61 ++#define GCC_NSSNOC_XO_DCD_ARES 62 ++#define GCC_NSSNOC_TS_ARES 63 ++#define GCC_NSSCC_ARES 64 ++#define GCC_NSSNOC_NSSCC_ARES 65 ++#define GCC_NSSNOC_ATB_ARES 66 ++#define GCC_NSSNOC_MEMNOC_ARES 67 ++#define GCC_NSSNOC_QOSGEN_REF_ARES 68 ++#define GCC_NSSNOC_SNOC_ARES 69 ++#define GCC_NSSNOC_TIMEOUT_REF_ARES 70 ++#define GCC_NSS_CFG_ARES 71 ++#define GCC_UBI0_DBG_ARES 72 ++#define GCC_PCIE0_AHB_ARES 73 ++#define GCC_PCIE0_AUX_ARES 74 ++#define GCC_PCIE0_AXI_M_ARES 75 ++#define GCC_PCIE0_AXI_M_STICKY_ARES 76 ++#define GCC_PCIE0_AXI_S_ARES 77 ++#define GCC_PCIE0_AXI_S_STICKY_ARES 78 ++#define GCC_PCIE0_CORE_STICKY_ARES 79 ++#define GCC_PCIE0_PIPE_ARES 80 ++#define GCC_PCIE1_AHB_ARES 81 ++#define GCC_PCIE1_AUX_ARES 82 ++#define GCC_PCIE1_AXI_M_ARES 83 ++#define GCC_PCIE1_AXI_M_STICKY_ARES 84 ++#define GCC_PCIE1_AXI_S_ARES 85 ++#define GCC_PCIE1_AXI_S_STICKY_ARES 86 ++#define GCC_PCIE1_CORE_STICKY_ARES 87 ++#define GCC_PCIE1_PIPE_ARES 88 ++#define GCC_PCIE2_AHB_ARES 89 ++#define GCC_PCIE2_AUX_ARES 90 ++#define GCC_PCIE2_AXI_M_ARES 91 ++#define GCC_PCIE2_AXI_M_STICKY_ARES 92 ++#define GCC_PCIE2_AXI_S_ARES 93 ++#define GCC_PCIE2_AXI_S_STICKY_ARES 94 ++#define GCC_PCIE2_CORE_STICKY_ARES 95 ++#define GCC_PCIE2_PIPE_ARES 96 ++#define GCC_PCIE3_AHB_ARES 97 ++#define GCC_PCIE3_AUX_ARES 98 ++#define GCC_PCIE3_AXI_M_ARES 99 ++#define GCC_PCIE3_AXI_M_STICKY_ARES 100 ++#define GCC_PCIE3_AXI_S_ARES 101 ++#define GCC_PCIE3_AXI_S_STICKY_ARES 102 ++#define GCC_PCIE3_CORE_STICKY_ARES 103 ++#define GCC_PCIE3_PIPE_ARES 104 ++#define GCC_PCNOC_BCR 105 ++#define GCC_PCNOC_BUS_TIMEOUT0_BCR 106 ++#define GCC_PCNOC_BUS_TIMEOUT1_BCR 107 ++#define GCC_PCNOC_BUS_TIMEOUT2_BCR 108 ++#define GCC_PCNOC_BUS_TIMEOUT3_BCR 109 ++#define GCC_PCNOC_BUS_TIMEOUT4_BCR 110 ++#define GCC_PCNOC_BUS_TIMEOUT5_BCR 111 ++#define GCC_PCNOC_BUS_TIMEOUT6_BCR 112 ++#define GCC_PCNOC_BUS_TIMEOUT7_BCR 113 ++#define GCC_PCNOC_BUS_TIMEOUT8_BCR 114 ++#define GCC_PCNOC_BUS_TIMEOUT9_BCR 115 ++#define GCC_PCNOC_TBU_BCR 116 ++#define GCC_Q6SS_DBG_ARES 117 ++#define GCC_Q6_AHB_ARES 118 ++#define GCC_Q6_AHB_S_ARES 119 ++#define GCC_Q6_AXIM2_ARES 120 ++#define GCC_Q6_AXIM_ARES 121 ++#define GCC_QDSS_BCR 122 ++#define GCC_QPIC_BCR 123 ++#define GCC_QPIC_AHB_ARES 124 ++#define GCC_QPIC_ARES 125 ++#define GCC_RBCPR_BCR 126 ++#define GCC_RBCPR_MX_BCR 127 ++#define GCC_SEC_CTRL_BCR 128 ++#define GCC_SMMU_CFG_BCR 129 ++#define GCC_SNOC_BCR 130 ++#define GCC_SPDM_BCR 131 ++#define GCC_TME_BCR 132 ++#define GCC_UNIPHY0_SYS_RESET 133 ++#define GCC_UNIPHY0_AHB_RESET 134 ++#define GCC_UNIPHY0_XPCS_RESET 135 ++#define GCC_UNIPHY1_SYS_RESET 136 ++#define GCC_UNIPHY1_AHB_RESET 137 ++#define GCC_UNIPHY1_XPCS_RESET 138 ++#define GCC_UNIPHY2_SYS_RESET 139 ++#define GCC_UNIPHY2_AHB_RESET 140 ++#define GCC_UNIPHY2_XPCS_RESET 141 ++#define GCC_USB_MISC_RESET 142 ++#define GCC_WCSSAON_RESET 143 ++#define GCC_WCSS_ACMT_ARES 144 ++#define GCC_WCSS_AHB_S_ARES 145 ++#define GCC_WCSS_AXI_M_ARES 146 ++#define GCC_WCSS_BCR 147 ++#define GCC_WCSS_DBG_ARES 148 ++#define GCC_WCSS_DBG_BDG_ARES 149 ++#define GCC_WCSS_ECAHB_ARES 150 ++#define GCC_WCSS_Q6_BCR 151 ++#define GCC_WCSS_Q6_TBU_BCR 152 ++#define GCC_TCSR_BCR 153 ++ ++#endif diff --git a/target/linux/ipq95xx/patches-6.1/0009-pinctrl-qcom-Add-IPQ9574-pinctrl-driver.patch b/target/linux/ipq95xx/patches-6.1/0009-pinctrl-qcom-Add-IPQ9574-pinctrl-driver.patch new file mode 100644 index 00000000000000..b4461ebbb17c2f --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0009-pinctrl-qcom-Add-IPQ9574-pinctrl-driver.patch @@ -0,0 +1,879 @@ +From 1d437190764f774f61f1ab389b4c074e0f69bbb1 Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Thu, 16 Mar 2023 12:59:38 +0530 +Subject: [PATCH 09/41] pinctrl: qcom: Add IPQ9574 pinctrl driver + +Add pinctrl definitions for the TLMM of IPQ9574 + +Reviewed-by: Krzysztof Kozlowski +Co-developed-by: Anusha Rao +Signed-off-by: Anusha Rao +Signed-off-by: Devi Priya +Link: https://lore.kernel.org/r/20230316072940.29137-5-quic_devipriy@quicinc.com +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/qcom/Kconfig | 11 + + drivers/pinctrl/qcom/Makefile | 1 + + drivers/pinctrl/qcom/pinctrl-ipq9574.c | 826 +++++++++++++++++++++++++ + 3 files changed, 838 insertions(+) + create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq9574.c + +--- a/drivers/pinctrl/qcom/Kconfig ++++ b/drivers/pinctrl/qcom/Kconfig +@@ -70,6 +70,17 @@ config PINCTRL_IPQ6018 + Qualcomm Technologies Inc. IPQ6018 platform. Select this for + IPQ6018. + ++config PINCTRL_IPQ9574 ++ tristate "Qualcomm Technologies, Inc. IPQ9574 pin controller driver" ++ depends on OF || COMPILE_TEST ++ depends on ARM64 || COMPILE_TEST ++ depends on PINCTRL_MSM ++ help ++ This is the pinctrl, pinmux, pinconf and gpiolib driver for ++ the Qualcomm Technologies Inc. TLMM block found on the ++ Qualcomm Technologies Inc. IPQ9574 platform. Select this for ++ IPQ9574. ++ + config PINCTRL_MSM8226 + tristate "Qualcomm 8226 pin controller driver" + depends on OF +--- a/drivers/pinctrl/qcom/Makefile ++++ b/drivers/pinctrl/qcom/Makefile +@@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl + obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o + obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o + obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o ++obj-$(CONFIG_PINCTRL_IPQ9574) += pinctrl-ipq9574.o + obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o + obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o + obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o +--- /dev/null ++++ b/drivers/pinctrl/qcom/pinctrl-ipq9574.c +@@ -0,0 +1,826 @@ ++// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++/* ++ * Copyright (c) 2023 The Linux Foundation. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "pinctrl-msm.h" ++ ++#define FUNCTION(fname) \ ++ [msm_mux_##fname] = { \ ++ .name = #fname, \ ++ .groups = fname##_groups, \ ++ .ngroups = ARRAY_SIZE(fname##_groups), \ ++ } ++ ++#define REG_SIZE 0x1000 ++#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ ++ { \ ++ .name = "gpio" #id, \ ++ .pins = gpio##id##_pins, \ ++ .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ ++ .funcs = (int[]){ \ ++ msm_mux_gpio, /* gpio mode */ \ ++ msm_mux_##f1, \ ++ msm_mux_##f2, \ ++ msm_mux_##f3, \ ++ msm_mux_##f4, \ ++ msm_mux_##f5, \ ++ msm_mux_##f6, \ ++ msm_mux_##f7, \ ++ msm_mux_##f8, \ ++ msm_mux_##f9 \ ++ }, \ ++ .nfuncs = 10, \ ++ .ctl_reg = REG_SIZE * id, \ ++ .io_reg = 0x4 + REG_SIZE * id, \ ++ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ ++ .intr_status_reg = 0xc + REG_SIZE * id, \ ++ .intr_target_reg = 0x8 + REG_SIZE * id, \ ++ .mux_bit = 2, \ ++ .pull_bit = 0, \ ++ .drv_bit = 6, \ ++ .oe_bit = 9, \ ++ .in_bit = 0, \ ++ .out_bit = 1, \ ++ .intr_enable_bit = 0, \ ++ .intr_status_bit = 0, \ ++ .intr_target_bit = 5, \ ++ .intr_target_kpss_val = 3, \ ++ .intr_raw_status_bit = 4, \ ++ .intr_polarity_bit = 1, \ ++ .intr_detection_bit = 2, \ ++ .intr_detection_width = 2, \ ++ } ++ ++static const struct pinctrl_pin_desc ipq9574_pins[] = { ++ PINCTRL_PIN(0, "GPIO_0"), ++ PINCTRL_PIN(1, "GPIO_1"), ++ PINCTRL_PIN(2, "GPIO_2"), ++ PINCTRL_PIN(3, "GPIO_3"), ++ PINCTRL_PIN(4, "GPIO_4"), ++ PINCTRL_PIN(5, "GPIO_5"), ++ PINCTRL_PIN(6, "GPIO_6"), ++ PINCTRL_PIN(7, "GPIO_7"), ++ PINCTRL_PIN(8, "GPIO_8"), ++ PINCTRL_PIN(9, "GPIO_9"), ++ PINCTRL_PIN(10, "GPIO_10"), ++ PINCTRL_PIN(11, "GPIO_11"), ++ PINCTRL_PIN(12, "GPIO_12"), ++ PINCTRL_PIN(13, "GPIO_13"), ++ PINCTRL_PIN(14, "GPIO_14"), ++ PINCTRL_PIN(15, "GPIO_15"), ++ PINCTRL_PIN(16, "GPIO_16"), ++ PINCTRL_PIN(17, "GPIO_17"), ++ PINCTRL_PIN(18, "GPIO_18"), ++ PINCTRL_PIN(19, "GPIO_19"), ++ PINCTRL_PIN(20, "GPIO_20"), ++ PINCTRL_PIN(21, "GPIO_21"), ++ PINCTRL_PIN(22, "GPIO_22"), ++ PINCTRL_PIN(23, "GPIO_23"), ++ PINCTRL_PIN(24, "GPIO_24"), ++ PINCTRL_PIN(25, "GPIO_25"), ++ PINCTRL_PIN(26, "GPIO_26"), ++ PINCTRL_PIN(27, "GPIO_27"), ++ PINCTRL_PIN(28, "GPIO_28"), ++ PINCTRL_PIN(29, "GPIO_29"), ++ PINCTRL_PIN(30, "GPIO_30"), ++ PINCTRL_PIN(31, "GPIO_31"), ++ PINCTRL_PIN(32, "GPIO_32"), ++ PINCTRL_PIN(33, "GPIO_33"), ++ PINCTRL_PIN(34, "GPIO_34"), ++ PINCTRL_PIN(35, "GPIO_35"), ++ PINCTRL_PIN(36, "GPIO_36"), ++ PINCTRL_PIN(37, "GPIO_37"), ++ PINCTRL_PIN(38, "GPIO_38"), ++ PINCTRL_PIN(39, "GPIO_39"), ++ PINCTRL_PIN(40, "GPIO_40"), ++ PINCTRL_PIN(41, "GPIO_41"), ++ PINCTRL_PIN(42, "GPIO_42"), ++ PINCTRL_PIN(43, "GPIO_43"), ++ PINCTRL_PIN(44, "GPIO_44"), ++ PINCTRL_PIN(45, "GPIO_45"), ++ PINCTRL_PIN(46, "GPIO_46"), ++ PINCTRL_PIN(47, "GPIO_47"), ++ PINCTRL_PIN(48, "GPIO_48"), ++ PINCTRL_PIN(49, "GPIO_49"), ++ PINCTRL_PIN(50, "GPIO_50"), ++ PINCTRL_PIN(51, "GPIO_51"), ++ PINCTRL_PIN(52, "GPIO_52"), ++ PINCTRL_PIN(53, "GPIO_53"), ++ PINCTRL_PIN(54, "GPIO_54"), ++ PINCTRL_PIN(55, "GPIO_55"), ++ PINCTRL_PIN(56, "GPIO_56"), ++ PINCTRL_PIN(57, "GPIO_57"), ++ PINCTRL_PIN(58, "GPIO_58"), ++ PINCTRL_PIN(59, "GPIO_59"), ++ PINCTRL_PIN(60, "GPIO_60"), ++ PINCTRL_PIN(61, "GPIO_61"), ++ PINCTRL_PIN(62, "GPIO_62"), ++ PINCTRL_PIN(63, "GPIO_63"), ++ PINCTRL_PIN(64, "GPIO_64"), ++}; ++ ++#define DECLARE_MSM_GPIO_PINS(pin) \ ++ static const unsigned int gpio##pin##_pins[] = { pin } ++DECLARE_MSM_GPIO_PINS(0); ++DECLARE_MSM_GPIO_PINS(1); ++DECLARE_MSM_GPIO_PINS(2); ++DECLARE_MSM_GPIO_PINS(3); ++DECLARE_MSM_GPIO_PINS(4); ++DECLARE_MSM_GPIO_PINS(5); ++DECLARE_MSM_GPIO_PINS(6); ++DECLARE_MSM_GPIO_PINS(7); ++DECLARE_MSM_GPIO_PINS(8); ++DECLARE_MSM_GPIO_PINS(9); ++DECLARE_MSM_GPIO_PINS(10); ++DECLARE_MSM_GPIO_PINS(11); ++DECLARE_MSM_GPIO_PINS(12); ++DECLARE_MSM_GPIO_PINS(13); ++DECLARE_MSM_GPIO_PINS(14); ++DECLARE_MSM_GPIO_PINS(15); ++DECLARE_MSM_GPIO_PINS(16); ++DECLARE_MSM_GPIO_PINS(17); ++DECLARE_MSM_GPIO_PINS(18); ++DECLARE_MSM_GPIO_PINS(19); ++DECLARE_MSM_GPIO_PINS(20); ++DECLARE_MSM_GPIO_PINS(21); ++DECLARE_MSM_GPIO_PINS(22); ++DECLARE_MSM_GPIO_PINS(23); ++DECLARE_MSM_GPIO_PINS(24); ++DECLARE_MSM_GPIO_PINS(25); ++DECLARE_MSM_GPIO_PINS(26); ++DECLARE_MSM_GPIO_PINS(27); ++DECLARE_MSM_GPIO_PINS(28); ++DECLARE_MSM_GPIO_PINS(29); ++DECLARE_MSM_GPIO_PINS(30); ++DECLARE_MSM_GPIO_PINS(31); ++DECLARE_MSM_GPIO_PINS(32); ++DECLARE_MSM_GPIO_PINS(33); ++DECLARE_MSM_GPIO_PINS(34); ++DECLARE_MSM_GPIO_PINS(35); ++DECLARE_MSM_GPIO_PINS(36); ++DECLARE_MSM_GPIO_PINS(37); ++DECLARE_MSM_GPIO_PINS(38); ++DECLARE_MSM_GPIO_PINS(39); ++DECLARE_MSM_GPIO_PINS(40); ++DECLARE_MSM_GPIO_PINS(41); ++DECLARE_MSM_GPIO_PINS(42); ++DECLARE_MSM_GPIO_PINS(43); ++DECLARE_MSM_GPIO_PINS(44); ++DECLARE_MSM_GPIO_PINS(45); ++DECLARE_MSM_GPIO_PINS(46); ++DECLARE_MSM_GPIO_PINS(47); ++DECLARE_MSM_GPIO_PINS(48); ++DECLARE_MSM_GPIO_PINS(49); ++DECLARE_MSM_GPIO_PINS(50); ++DECLARE_MSM_GPIO_PINS(51); ++DECLARE_MSM_GPIO_PINS(52); ++DECLARE_MSM_GPIO_PINS(53); ++DECLARE_MSM_GPIO_PINS(54); ++DECLARE_MSM_GPIO_PINS(55); ++DECLARE_MSM_GPIO_PINS(56); ++DECLARE_MSM_GPIO_PINS(57); ++DECLARE_MSM_GPIO_PINS(58); ++DECLARE_MSM_GPIO_PINS(59); ++DECLARE_MSM_GPIO_PINS(60); ++DECLARE_MSM_GPIO_PINS(61); ++DECLARE_MSM_GPIO_PINS(62); ++DECLARE_MSM_GPIO_PINS(63); ++DECLARE_MSM_GPIO_PINS(64); ++ ++enum ipq9574_functions { ++ msm_mux_atest_char, ++ msm_mux_atest_char0, ++ msm_mux_atest_char1, ++ msm_mux_atest_char2, ++ msm_mux_atest_char3, ++ msm_mux_audio_pdm0, ++ msm_mux_audio_pdm1, ++ msm_mux_audio_pri, ++ msm_mux_audio_sec, ++ msm_mux_blsp0_spi, ++ msm_mux_blsp0_uart, ++ msm_mux_blsp1_i2c, ++ msm_mux_blsp1_spi, ++ msm_mux_blsp1_uart, ++ msm_mux_blsp2_i2c, ++ msm_mux_blsp2_spi, ++ msm_mux_blsp2_uart, ++ msm_mux_blsp3_i2c, ++ msm_mux_blsp3_spi, ++ msm_mux_blsp3_uart, ++ msm_mux_blsp4_i2c, ++ msm_mux_blsp4_spi, ++ msm_mux_blsp4_uart, ++ msm_mux_blsp5_i2c, ++ msm_mux_blsp5_uart, ++ msm_mux_cri_trng0, ++ msm_mux_cri_trng1, ++ msm_mux_cri_trng2, ++ msm_mux_cri_trng3, ++ msm_mux_cxc0, ++ msm_mux_cxc1, ++ msm_mux_dbg_out, ++ msm_mux_dwc_ddrphy, ++ msm_mux_gcc_plltest, ++ msm_mux_gcc_tlmm, ++ msm_mux_gpio, ++ msm_mux_mac, ++ msm_mux_mdc, ++ msm_mux_mdio, ++ msm_mux_pcie0_clk, ++ msm_mux_pcie0_wake, ++ msm_mux_pcie1_clk, ++ msm_mux_pcie1_wake, ++ msm_mux_pcie2_clk, ++ msm_mux_pcie2_wake, ++ msm_mux_pcie3_clk, ++ msm_mux_pcie3_wake, ++ msm_mux_prng_rosc0, ++ msm_mux_prng_rosc1, ++ msm_mux_prng_rosc2, ++ msm_mux_prng_rosc3, ++ msm_mux_pta, ++ msm_mux_pwm, ++ msm_mux_qdss_cti_trig_in_a0, ++ msm_mux_qdss_cti_trig_in_a1, ++ msm_mux_qdss_cti_trig_in_b0, ++ msm_mux_qdss_cti_trig_in_b1, ++ msm_mux_qdss_cti_trig_out_a0, ++ msm_mux_qdss_cti_trig_out_a1, ++ msm_mux_qdss_cti_trig_out_b0, ++ msm_mux_qdss_cti_trig_out_b1, ++ msm_mux_qdss_traceclk_a, ++ msm_mux_qdss_traceclk_b, ++ msm_mux_qdss_tracectl_a, ++ msm_mux_qdss_tracectl_b, ++ msm_mux_qdss_tracedata_a, ++ msm_mux_qdss_tracedata_b, ++ msm_mux_qspi_data, ++ msm_mux_qspi_clk, ++ msm_mux_qspi_cs, ++ msm_mux_rx0, ++ msm_mux_rx1, ++ msm_mux_sdc_data, ++ msm_mux_sdc_clk, ++ msm_mux_sdc_cmd, ++ msm_mux_sdc_rclk, ++ msm_mux_tsens_max, ++ msm_mux_wci20, ++ msm_mux_wci21, ++ msm_mux_wsa_swrm, ++ msm_mux__, ++}; ++ ++static const char * const gpio_groups[] = { ++ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", ++ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", ++ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", ++ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", ++ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", ++ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", ++ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", ++ "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", ++ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", ++ "gpio64", ++}; ++ ++static const char * const sdc_data_groups[] = { ++ "gpio0", ++ "gpio1", ++ "gpio2", ++ "gpio3", ++ "gpio6", ++ "gpio7", ++ "gpio8", ++ "gpio9", ++}; ++ ++static const char * const qspi_data_groups[] = { ++ "gpio0", ++ "gpio1", ++ "gpio2", ++ "gpio3", ++}; ++ ++static const char * const qdss_traceclk_b_groups[] = { ++ "gpio0", ++}; ++ ++static const char * const qdss_tracectl_b_groups[] = { ++ "gpio1", ++}; ++ ++static const char * const qdss_tracedata_b_groups[] = { ++ "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio9", ++ "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", ++ "gpio17", ++}; ++ ++static const char * const sdc_cmd_groups[] = { ++ "gpio4", ++}; ++ ++static const char * const qspi_cs_groups[] = { ++ "gpio4", ++}; ++ ++static const char * const sdc_clk_groups[] = { ++ "gpio5", ++}; ++ ++static const char * const qspi_clk_groups[] = { ++ "gpio5", ++}; ++ ++static const char * const sdc_rclk_groups[] = { ++ "gpio10", ++}; ++ ++static const char * const blsp0_spi_groups[] = { ++ "gpio11", "gpio12", "gpio13", "gpio14", ++}; ++ ++static const char * const blsp0_uart_groups[] = { ++ "gpio11", "gpio12", "gpio13", "gpio14", ++}; ++ ++static const char * const blsp3_spi_groups[] = { ++ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", ++}; ++ ++static const char * const blsp3_i2c_groups[] = { ++ "gpio15", "gpio16", ++}; ++ ++static const char * const blsp3_uart_groups[] = { ++ "gpio15", "gpio16", "gpio17", "gpio18", ++}; ++ ++static const char * const dbg_out_groups[] = { ++ "gpio17", ++}; ++ ++static const char * const cri_trng0_groups[] = { ++ "gpio20", "gpio38", ++}; ++ ++static const char * const cri_trng1_groups[] = { ++ "gpio21", "gpio34", ++}; ++ ++static const char * const pcie0_clk_groups[] = { ++ "gpio22", ++}; ++ ++static const char * const pta_groups[] = { ++ "gpio22", "gpio23", "gpio24", "gpio54", "gpio55", "gpio56", "gpio61", ++ "gpio62", "gpio63", ++}; ++ ++static const char * const wci21_groups[] = { ++ "gpio23", "gpio24", ++}; ++ ++static const char * const cxc0_groups[] = { ++ "gpio23", "gpio24", ++}; ++ ++static const char * const pcie0_wake_groups[] = { ++ "gpio24", ++}; ++ ++static const char * const qdss_cti_trig_out_b0_groups[] = { ++ "gpio24", ++}; ++ ++static const char * const pcie1_clk_groups[] = { ++ "gpio25", ++}; ++ ++static const char * const qdss_cti_trig_in_b0_groups[] = { ++ "gpio25", ++}; ++ ++static const char * const atest_char0_groups[] = { ++ "gpio26", ++}; ++ ++static const char * const qdss_cti_trig_out_b1_groups[] = { ++ "gpio26", ++}; ++ ++static const char * const pcie1_wake_groups[] = { ++ "gpio27", ++}; ++ ++static const char * const atest_char1_groups[] = { ++ "gpio27", ++}; ++ ++static const char * const qdss_cti_trig_in_b1_groups[] = { ++ "gpio27", ++}; ++ ++static const char * const pcie2_clk_groups[] = { ++ "gpio28", ++}; ++ ++static const char * const atest_char2_groups[] = { ++ "gpio28", ++}; ++ ++static const char * const atest_char3_groups[] = { ++ "gpio29", ++}; ++ ++static const char * const pcie2_wake_groups[] = { ++ "gpio30", ++}; ++ ++static const char * const pwm_groups[] = { ++ "gpio30", "gpio31", "gpio32", "gpio33", "gpio44", "gpio45", "gpio46", ++ "gpio47", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", ++ "gpio56", "gpio57", "gpio58", "gpio59", "gpio60", ++}; ++ ++static const char * const atest_char_groups[] = { ++ "gpio30", ++}; ++ ++static const char * const pcie3_clk_groups[] = { ++ "gpio31", ++}; ++ ++static const char * const qdss_cti_trig_in_a1_groups[] = { ++ "gpio31", ++}; ++ ++static const char * const qdss_cti_trig_out_a1_groups[] = { ++ "gpio32", ++}; ++ ++static const char * const pcie3_wake_groups[] = { ++ "gpio33", ++}; ++ ++static const char * const qdss_cti_trig_in_a0_groups[] = { ++ "gpio33", ++}; ++ ++static const char * const blsp2_uart_groups[] = { ++ "gpio34", "gpio35", ++}; ++ ++static const char * const blsp2_i2c_groups[] = { ++ "gpio34", "gpio35", ++}; ++ ++static const char * const blsp2_spi_groups[] = { ++ "gpio34", "gpio35", "gpio36", "gpio37", ++}; ++ ++static const char * const blsp1_uart_groups[] = { ++ "gpio34", "gpio35", "gpio36", "gpio37", ++}; ++ ++static const char * const qdss_cti_trig_out_a0_groups[] = { ++ "gpio34", ++}; ++ ++static const char * const cri_trng2_groups[] = { ++ "gpio35", ++}; ++ ++static const char * const blsp1_i2c_groups[] = { ++ "gpio36", "gpio37", ++}; ++ ++static const char * const cri_trng3_groups[] = { ++ "gpio36", ++}; ++ ++static const char * const dwc_ddrphy_groups[] = { ++ "gpio37", ++}; ++ ++static const char * const mdc_groups[] = { ++ "gpio38", ++}; ++ ++static const char * const mdio_groups[] = { ++ "gpio39", ++}; ++ ++static const char * const audio_pri_groups[] = { ++ "gpio40", "gpio41", "gpio42", "gpio43", "gpio61", "gpio61", ++}; ++ ++static const char * const audio_pdm0_groups[] = { ++ "gpio40", "gpio41", "gpio42", "gpio43", ++}; ++ ++static const char * const qdss_traceclk_a_groups[] = { ++ "gpio43", ++}; ++ ++static const char * const audio_sec_groups[] = { ++ "gpio44", "gpio45", "gpio46", "gpio47", "gpio62", "gpio62", ++}; ++ ++static const char * const wsa_swrm_groups[] = { ++ "gpio44", "gpio45", ++}; ++ ++static const char * const qdss_tracectl_a_groups[] = { ++ "gpio44", ++}; ++ ++static const char * const qdss_tracedata_a_groups[] = { ++ "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51", ++ "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", ++ "gpio59", "gpio60", ++}; ++ ++static const char * const rx1_groups[] = { ++ "gpio46", ++}; ++ ++static const char * const mac_groups[] = { ++ "gpio46", "gpio47", "gpio57", "gpio58", ++}; ++ ++static const char * const blsp5_i2c_groups[] = { ++ "gpio48", "gpio49", ++}; ++ ++static const char * const blsp5_uart_groups[] = { ++ "gpio48", "gpio49", ++}; ++ ++static const char * const blsp4_uart_groups[] = { ++ "gpio50", "gpio51", "gpio52", "gpio53", ++}; ++ ++static const char * const blsp4_i2c_groups[] = { ++ "gpio50", "gpio51", ++}; ++ ++static const char * const blsp4_spi_groups[] = { ++ "gpio50", "gpio51", "gpio52", "gpio53", ++}; ++ ++static const char * const wci20_groups[] = { ++ "gpio57", "gpio58", ++}; ++ ++static const char * const cxc1_groups[] = { ++ "gpio57", "gpio58", ++}; ++ ++static const char * const rx0_groups[] = { ++ "gpio59", ++}; ++ ++static const char * const prng_rosc0_groups[] = { ++ "gpio60", ++}; ++ ++static const char * const gcc_plltest_groups[] = { ++ "gpio60", "gpio62", ++}; ++ ++static const char * const blsp1_spi_groups[] = { ++ "gpio61", "gpio62", "gpio63", "gpio64", ++}; ++ ++static const char * const audio_pdm1_groups[] = { ++ "gpio61", "gpio62", "gpio63", "gpio64", ++}; ++ ++static const char * const prng_rosc1_groups[] = { ++ "gpio61", ++}; ++ ++static const char * const gcc_tlmm_groups[] = { ++ "gpio61", ++}; ++ ++static const char * const prng_rosc2_groups[] = { ++ "gpio62", ++}; ++ ++static const char * const prng_rosc3_groups[] = { ++ "gpio63", ++}; ++ ++static const char * const tsens_max_groups[] = { ++ "gpio64", ++}; ++ ++static const struct msm_function ipq9574_functions[] = { ++ FUNCTION(atest_char), ++ FUNCTION(atest_char0), ++ FUNCTION(atest_char1), ++ FUNCTION(atest_char2), ++ FUNCTION(atest_char3), ++ FUNCTION(audio_pdm0), ++ FUNCTION(audio_pdm1), ++ FUNCTION(audio_pri), ++ FUNCTION(audio_sec), ++ FUNCTION(blsp0_spi), ++ FUNCTION(blsp0_uart), ++ FUNCTION(blsp1_i2c), ++ FUNCTION(blsp1_spi), ++ FUNCTION(blsp1_uart), ++ FUNCTION(blsp2_i2c), ++ FUNCTION(blsp2_spi), ++ FUNCTION(blsp2_uart), ++ FUNCTION(blsp3_i2c), ++ FUNCTION(blsp3_spi), ++ FUNCTION(blsp3_uart), ++ FUNCTION(blsp4_i2c), ++ FUNCTION(blsp4_spi), ++ FUNCTION(blsp4_uart), ++ FUNCTION(blsp5_i2c), ++ FUNCTION(blsp5_uart), ++ FUNCTION(cri_trng0), ++ FUNCTION(cri_trng1), ++ FUNCTION(cri_trng2), ++ FUNCTION(cri_trng3), ++ FUNCTION(cxc0), ++ FUNCTION(cxc1), ++ FUNCTION(dbg_out), ++ FUNCTION(dwc_ddrphy), ++ FUNCTION(gcc_plltest), ++ FUNCTION(gcc_tlmm), ++ FUNCTION(gpio), ++ FUNCTION(mac), ++ FUNCTION(mdc), ++ FUNCTION(mdio), ++ FUNCTION(pcie0_clk), ++ FUNCTION(pcie0_wake), ++ FUNCTION(pcie1_clk), ++ FUNCTION(pcie1_wake), ++ FUNCTION(pcie2_clk), ++ FUNCTION(pcie2_wake), ++ FUNCTION(pcie3_clk), ++ FUNCTION(pcie3_wake), ++ FUNCTION(prng_rosc0), ++ FUNCTION(prng_rosc1), ++ FUNCTION(prng_rosc2), ++ FUNCTION(prng_rosc3), ++ FUNCTION(pta), ++ FUNCTION(pwm), ++ FUNCTION(qdss_cti_trig_in_a0), ++ FUNCTION(qdss_cti_trig_in_a1), ++ FUNCTION(qdss_cti_trig_in_b0), ++ FUNCTION(qdss_cti_trig_in_b1), ++ FUNCTION(qdss_cti_trig_out_a0), ++ FUNCTION(qdss_cti_trig_out_a1), ++ FUNCTION(qdss_cti_trig_out_b0), ++ FUNCTION(qdss_cti_trig_out_b1), ++ FUNCTION(qdss_traceclk_a), ++ FUNCTION(qdss_traceclk_b), ++ FUNCTION(qdss_tracectl_a), ++ FUNCTION(qdss_tracectl_b), ++ FUNCTION(qdss_tracedata_a), ++ FUNCTION(qdss_tracedata_b), ++ FUNCTION(qspi_data), ++ FUNCTION(qspi_clk), ++ FUNCTION(qspi_cs), ++ FUNCTION(rx0), ++ FUNCTION(rx1), ++ FUNCTION(sdc_data), ++ FUNCTION(sdc_clk), ++ FUNCTION(sdc_cmd), ++ FUNCTION(sdc_rclk), ++ FUNCTION(tsens_max), ++ FUNCTION(wci20), ++ FUNCTION(wci21), ++ FUNCTION(wsa_swrm), ++}; ++ ++static const struct msm_pingroup ipq9574_groups[] = { ++ PINGROUP(0, sdc_data, qspi_data, qdss_traceclk_b, _, _, _, _, _, _), ++ PINGROUP(1, sdc_data, qspi_data, qdss_tracectl_b, _, _, _, _, _, _), ++ PINGROUP(2, sdc_data, qspi_data, qdss_tracedata_b, _, _, _, _, _, _), ++ PINGROUP(3, sdc_data, qspi_data, qdss_tracedata_b, _, _, _, _, _, _), ++ PINGROUP(4, sdc_cmd, qspi_cs, qdss_tracedata_b, _, _, _, _, _, _), ++ PINGROUP(5, sdc_clk, qspi_clk, qdss_tracedata_b, _, _, _, _, _, _), ++ PINGROUP(6, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _), ++ PINGROUP(7, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _), ++ PINGROUP(8, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _), ++ PINGROUP(9, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _), ++ PINGROUP(10, sdc_rclk, qdss_tracedata_b, _, _, _, _, _, _, _), ++ PINGROUP(11, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _, _, _), ++ PINGROUP(12, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _, _, _), ++ PINGROUP(13, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _, _, _), ++ PINGROUP(14, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _, _, _), ++ PINGROUP(15, blsp3_spi, blsp3_i2c, blsp3_uart, qdss_tracedata_b, _, _, _, _, _), ++ PINGROUP(16, blsp3_spi, blsp3_i2c, blsp3_uart, qdss_tracedata_b, _, _, _, _, _), ++ PINGROUP(17, blsp3_spi, blsp3_uart, dbg_out, qdss_tracedata_b, _, _, _, _, _), ++ PINGROUP(18, blsp3_spi, blsp3_uart, _, _, _, _, _, _, _), ++ PINGROUP(19, blsp3_spi, _, _, _, _, _, _, _, _), ++ PINGROUP(20, blsp3_spi, _, cri_trng0, _, _, _, _, _, _), ++ PINGROUP(21, blsp3_spi, _, cri_trng1, _, _, _, _, _, _), ++ PINGROUP(22, pcie0_clk, _, pta, _, _, _, _, _, _), ++ PINGROUP(23, _, pta, wci21, cxc0, _, _, _, _, _), ++ PINGROUP(24, pcie0_wake, _, pta, wci21, cxc0, _, qdss_cti_trig_out_b0, _, _), ++ PINGROUP(25, pcie1_clk, _, _, qdss_cti_trig_in_b0, _, _, _, _, _), ++ PINGROUP(26, _, atest_char0, _, qdss_cti_trig_out_b1, _, _, _, _, _), ++ PINGROUP(27, pcie1_wake, _, atest_char1, qdss_cti_trig_in_b1, _, _, _, _, _), ++ PINGROUP(28, pcie2_clk, atest_char2, _, _, _, _, _, _, _), ++ PINGROUP(29, atest_char3, _, _, _, _, _, _, _, _), ++ PINGROUP(30, pcie2_wake, pwm, atest_char, _, _, _, _, _, _), ++ PINGROUP(31, pcie3_clk, pwm, _, qdss_cti_trig_in_a1, _, _, _, _, _), ++ PINGROUP(32, pwm, _, qdss_cti_trig_out_a1, _, _, _, _, _, _), ++ PINGROUP(33, pcie3_wake, pwm, _, qdss_cti_trig_in_a0, _, _, _, _, _), ++ PINGROUP(34, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, _, cri_trng1, qdss_cti_trig_out_a0, _, _), ++ PINGROUP(35, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, _, cri_trng2, _, _, _), ++ PINGROUP(36, blsp1_uart, blsp1_i2c, blsp2_spi, _, cri_trng3, _, _, _, _), ++ PINGROUP(37, blsp1_uart, blsp1_i2c, blsp2_spi, _, dwc_ddrphy, _, _, _, _), ++ PINGROUP(38, mdc, _, cri_trng0, _, _, _, _, _, _), ++ PINGROUP(39, mdio, _, _, _, _, _, _, _, _), ++ PINGROUP(40, audio_pri, audio_pdm0, _, _, _, _, _, _, _), ++ PINGROUP(41, audio_pri, audio_pdm0, _, _, _, _, _, _, _), ++ PINGROUP(42, audio_pri, audio_pdm0, _, _, _, _, _, _, _), ++ PINGROUP(43, audio_pri, audio_pdm0, _, qdss_traceclk_a, _, _, _, _, _), ++ PINGROUP(44, pwm, audio_sec, wsa_swrm, _, qdss_tracectl_a, _, _, _, _), ++ PINGROUP(45, pwm, audio_sec, wsa_swrm, _, qdss_tracedata_a, _, _, _, _), ++ PINGROUP(46, pwm, audio_sec, rx1, mac, _, qdss_tracedata_a, _, _, _), ++ PINGROUP(47, pwm, audio_sec, mac, _, qdss_tracedata_a, _, _, _, _), ++ PINGROUP(48, blsp5_i2c, blsp5_uart, _, qdss_tracedata_a, _, _, _, _, _), ++ PINGROUP(49, blsp5_i2c, blsp5_uart, _, qdss_tracedata_a, _, _, _, _, _), ++ PINGROUP(50, blsp4_uart, blsp4_i2c, blsp4_spi, pwm, qdss_tracedata_a, _, _, _, _), ++ PINGROUP(51, blsp4_uart, blsp4_i2c, blsp4_spi, pwm, qdss_tracedata_a, _, _, _, _), ++ PINGROUP(52, blsp4_uart, blsp4_spi, pwm, qdss_tracedata_a, _, _, _, _, _), ++ PINGROUP(53, blsp4_uart, blsp4_spi, pwm, qdss_tracedata_a, _, _, _, _, _), ++ PINGROUP(54, pta, pwm, qdss_tracedata_a, _, _, _, _, _, _), ++ PINGROUP(55, pta, pwm, qdss_tracedata_a, _, _, _, _, _, _), ++ PINGROUP(56, pta, pwm, qdss_tracedata_a, _, _, _, _, _, _), ++ PINGROUP(57, wci20, cxc1, mac, pwm, qdss_tracedata_a, _, _, _, _), ++ PINGROUP(58, wci20, cxc1, mac, pwm, qdss_tracedata_a, _, _, _, _), ++ PINGROUP(59, rx0, pwm, qdss_tracedata_a, _, _, _, _, _, _), ++ PINGROUP(60, pwm, prng_rosc0, qdss_tracedata_a, _, gcc_plltest, _, _, _, _), ++ PINGROUP(61, blsp1_spi, audio_pri, audio_pdm1, audio_pri, pta, prng_rosc1, gcc_tlmm, _, _), ++ PINGROUP(62, blsp1_spi, audio_sec, audio_pdm1, audio_sec, pta, prng_rosc2, gcc_plltest, _, _), ++ PINGROUP(63, blsp1_spi, audio_pdm1, pta, prng_rosc3, _, _, _, _, _), ++ PINGROUP(64, blsp1_spi, audio_pdm1, tsens_max, _, _, _, _, _, _), ++}; ++ ++/* Reserving GPIO59 for controlling the QFPROM LDO regulator */ ++static const int ipq9574_reserved_gpios[] = { ++ 59, -1 ++}; ++ ++static const struct msm_pinctrl_soc_data ipq9574_pinctrl = { ++ .pins = ipq9574_pins, ++ .npins = ARRAY_SIZE(ipq9574_pins), ++ .functions = ipq9574_functions, ++ .nfunctions = ARRAY_SIZE(ipq9574_functions), ++ .groups = ipq9574_groups, ++ .ngroups = ARRAY_SIZE(ipq9574_groups), ++ .reserved_gpios = ipq9574_reserved_gpios, ++ .ngpios = 65, ++}; ++ ++static int ipq9574_pinctrl_probe(struct platform_device *pdev) ++{ ++ return msm_pinctrl_probe(pdev, &ipq9574_pinctrl); ++} ++ ++static const struct of_device_id ipq9574_pinctrl_of_match[] = { ++ { .compatible = "qcom,ipq9574-tlmm", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, ipq9574_pinctrl_of_match); ++ ++static struct platform_driver ipq9574_pinctrl_driver = { ++ .driver = { ++ .name = "ipq9574-tlmm", ++ .of_match_table = ipq9574_pinctrl_of_match, ++ }, ++ .probe = ipq9574_pinctrl_probe, ++ .remove = msm_pinctrl_remove, ++}; ++ ++static int __init ipq9574_pinctrl_init(void) ++{ ++ return platform_driver_register(&ipq9574_pinctrl_driver); ++} ++arch_initcall(ipq9574_pinctrl_init); ++ ++static void __exit ipq9574_pinctrl_exit(void) ++{ ++ platform_driver_unregister(&ipq9574_pinctrl_driver); ++} ++module_exit(ipq9574_pinctrl_exit); ++ ++MODULE_DESCRIPTION("QTI IPQ9574 TLMM driver"); ++MODULE_LICENSE("GPL"); diff --git a/target/linux/ipq95xx/patches-6.1/0010-arm64-dts-qcom-ipq9574-Add-support-for-APSS-clock-co.patch b/target/linux/ipq95xx/patches-6.1/0010-arm64-dts-qcom-ipq9574-Add-support-for-APSS-clock-co.patch new file mode 100644 index 00000000000000..3dd5c98d2a0a65 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0010-arm64-dts-qcom-ipq9574-Add-support-for-APSS-clock-co.patch @@ -0,0 +1,43 @@ +From 7fd33c757ae079f5fcba4ab1de145392247462d0 Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Thu, 6 Apr 2023 11:43:13 +0530 +Subject: [PATCH 10/41] arm64: dts: qcom: ipq9574: Add support for APSS clock + controller + +Add the APCS & A73 PLL nodes to support CPU frequency scaling. + +Signed-off-by: Devi Priya +Reviewed-by: Konrad Dybcio +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230406061314.10916-5-quic_devipriy@quicinc.com +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -201,6 +201,24 @@ + }; + }; + ++ apcs_glb: mailbox@b111000 { ++ compatible = "qcom,ipq9574-apcs-apps-global", ++ "qcom,ipq6018-apcs-apps-global"; ++ reg = <0x0b111000 0x1000>; ++ #clock-cells = <1>; ++ clocks = <&a73pll>, <&xo_board_clk>; ++ clock-names = "pll", "xo"; ++ #mbox-cells = <1>; ++ }; ++ ++ a73pll: clock@b116000 { ++ compatible = "qcom,ipq9574-a73pll"; ++ reg = <0x0b116000 0x40>; ++ #clock-cells = <0>; ++ clocks = <&xo_board_clk>; ++ clock-names = "xo"; ++ }; ++ + timer@b120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; diff --git a/target/linux/ipq95xx/patches-6.1/0011-clk-qcom-apss-ipq-pll-Add-support-for-IPQ9574.patch b/target/linux/ipq95xx/patches-6.1/0011-clk-qcom-apss-ipq-pll-Add-support-for-IPQ9574.patch new file mode 100644 index 00000000000000..9c5bdb73f633b0 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0011-clk-qcom-apss-ipq-pll-Add-support-for-IPQ9574.patch @@ -0,0 +1,61 @@ +From f2e33970f45a9ce5c94da83980d1e95e21a565fe Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Thu, 6 Apr 2023 11:43:11 +0530 +Subject: [PATCH 11/41] clk: qcom: apss-ipq-pll: Add support for IPQ9574 + +Add the compatible and configuration values for A73 Huayra PLL found +on IPQ9574. + +Co-developed-by: Praveenkumar I +Signed-off-by: Praveenkumar I +Signed-off-by: Devi Priya +Acked-by: Stephen Boyd +Reviewed-by: Konrad Dybcio +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230406061314.10916-3-quic_devipriy@quicinc.com +--- + drivers/clk/qcom/apss-ipq-pll.c | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +--- a/drivers/clk/qcom/apss-ipq-pll.c ++++ b/drivers/clk/qcom/apss-ipq-pll.c +@@ -68,6 +68,18 @@ static const struct alpha_pll_config ipq + .test_ctl_hi_val = 0x4000, + }; + ++static const struct alpha_pll_config ipq9574_pll_config = { ++ .l = 0x3b, ++ .config_ctl_val = 0x200d4828, ++ .config_ctl_hi_val = 0x6, ++ .early_output_mask = BIT(3), ++ .aux2_output_mask = BIT(2), ++ .aux_output_mask = BIT(1), ++ .main_output_mask = BIT(0), ++ .test_ctl_val = 0x0, ++ .test_ctl_hi_val = 0x4000, ++}; ++ + struct apss_pll_data { + struct clk_alpha_pll *pll; + const struct alpha_pll_config *pll_config; +@@ -83,6 +95,12 @@ static struct apss_pll_data ipq6018_pll_ + .pll_config = &ipq6018_pll_config, + }; + ++static struct apss_pll_data ipq9574_pll_data = { ++ .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA, ++ .pll = &ipq_pll_huayra, ++ .pll_config = &ipq9574_pll_config, ++}; ++ + static const struct regmap_config ipq_pll_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, +@@ -124,6 +142,7 @@ static int apss_ipq_pll_probe(struct pla + static const struct of_device_id apss_ipq_pll_match_table[] = { + { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data }, + { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data }, ++ { .compatible = "qcom,ipq9574-a73pll", .data = &ipq9574_pll_data }, + { } + }; + MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table); diff --git a/target/linux/ipq95xx/patches-6.1/0012-regulator-qcom_smd-Add-MP5496-S1-regulator.patch b/target/linux/ipq95xx/patches-6.1/0012-regulator-qcom_smd-Add-MP5496-S1-regulator.patch new file mode 100644 index 00000000000000..fd7b046099d3ee --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0012-regulator-qcom_smd-Add-MP5496-S1-regulator.patch @@ -0,0 +1,38 @@ +From 10b07ee264b5cc807939be4cbc60a3abad3ddf03 Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Fri, 7 Apr 2023 21:27:24 +0530 +Subject: [PATCH 12/41] regulator: qcom_smd: Add MP5496 S1 regulator + +Adding support for MP5496 S1 regulator on IPQ9574 SoC. + +Co-developed-by: Praveenkumar I +Signed-off-by: Praveenkumar I +Signed-off-by: Devi Priya +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20230407155727.20615-3-quic_devipriy@quicinc.com +Signed-off-by: Mark Brown +--- + drivers/regulator/qcom_smd-regulator.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/regulator/qcom_smd-regulator.c ++++ b/drivers/regulator/qcom_smd-regulator.c +@@ -731,7 +731,7 @@ static const struct regulator_desc pms40 + .ops = &rpm_smps_ldo_ops, + }; + +-static const struct regulator_desc mp5496_smpa2 = { ++static const struct regulator_desc mp5496_smps = { + .linear_ranges = (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(600000, 0, 127, 12500), + }, +@@ -776,7 +776,8 @@ struct rpm_regulator_data { + }; + + static const struct rpm_regulator_data rpm_mp5496_regulators[] = { +- { "s2", QCOM_SMD_RPM_SMPA, 2, &mp5496_smpa2, "s2" }, ++ { "s1", QCOM_SMD_RPM_SMPA, 1, &mp5496_smps, "s1" }, ++ { "s2", QCOM_SMD_RPM_SMPA, 2, &mp5496_smps, "s2" }, + { "l2", QCOM_SMD_RPM_LDOA, 2, &mp5496_ldoa2, "l2" }, + {} + }; diff --git a/target/linux/ipq95xx/patches-6.1/0013-arm64-dts-qcom-ipq9574-rename-al02-c7-dts-to-rdp433.patch b/target/linux/ipq95xx/patches-6.1/0013-arm64-dts-qcom-ipq9574-rename-al02-c7-dts-to-rdp433.patch new file mode 100644 index 00000000000000..cc1d654b03753c --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0013-arm64-dts-qcom-ipq9574-rename-al02-c7-dts-to-rdp433.patch @@ -0,0 +1,203 @@ +From 89978464908147356b67ee57dd07482dc7ffe332 Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Tue, 25 Apr 2023 14:10:10 +0530 +Subject: [PATCH 13/41] arm64: dts: qcom: ipq9574: rename al02-c7 dts to rdp433 + +Rename the dts after Reference Design Platform(RDP) to adopt +standard naming convention. + +Acked-by: Konrad Dybcio +Signed-off-by: Devi Priya +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230425084010.15581-7-quic_devipriy@quicinc.com +--- + arch/arm64/boot/dts/qcom/Makefile | 2 +- + .../boot/dts/qcom/{ipq9574-al02-c7.dts => ipq9574-rdp433.dts} | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + rename arch/arm64/boot/dts/qcom/{ipq9574-al02-c7.dts => ipq9574-rdp433.dts} (97%) + +--- a/arch/arm64/boot/dts/qcom/Makefile ++++ b/arch/arm64/boot/dts/qcom/Makefile +@@ -7,7 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01- + dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb + dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb + dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb +-dtb-$(CONFIG_ARCH_QCOM) += ipq9574-al02-c7.dtb ++dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8916-huawei-g7.dtb +--- a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts ++++ /dev/null +@@ -1,84 +0,0 @@ +-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +-/* +- * IPQ9574 AL02-C7 board device tree source +- * +- * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. +- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. +- */ +- +-/dts-v1/; +- +-#include "ipq9574.dtsi" +- +-/ { +- model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7"; +- compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574"; +- +- aliases { +- serial0 = &blsp1_uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&blsp1_uart2 { +- pinctrl-0 = <&uart2_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&sdhc_1 { +- pinctrl-0 = <&sdc_default_state>; +- pinctrl-names = "default"; +- mmc-ddr-1_8v; +- mmc-hs200-1_8v; +- mmc-hs400-1_8v; +- mmc-hs400-enhanced-strobe; +- max-frequency = <384000000>; +- bus-width = <8>; +- status = "okay"; +-}; +- +-&sleep_clk { +- clock-frequency = <32000>; +-}; +- +-&tlmm { +- sdc_default_state: sdc-default-state { +- clk-pins { +- pins = "gpio5"; +- function = "sdc_clk"; +- drive-strength = <8>; +- bias-disable; +- }; +- +- cmd-pins { +- pins = "gpio4"; +- function = "sdc_cmd"; +- drive-strength = <8>; +- bias-pull-up; +- }; +- +- data-pins { +- pins = "gpio0", "gpio1", "gpio2", +- "gpio3", "gpio6", "gpio7", +- "gpio8", "gpio9"; +- function = "sdc_data"; +- drive-strength = <8>; +- bias-pull-up; +- }; +- +- rclk-pins { +- pins = "gpio10"; +- function = "sdc_rclk"; +- drive-strength = <8>; +- bias-pull-down; +- }; +- }; +-}; +- +-&xo_board_clk { +- clock-frequency = <24000000>; +-}; +--- /dev/null ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +@@ -0,0 +1,84 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * IPQ9574 RDP433 board device tree source ++ * ++ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. ++ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++/dts-v1/; ++ ++#include "ipq9574.dtsi" ++ ++/ { ++ model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7"; ++ compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574"; ++ ++ aliases { ++ serial0 = &blsp1_uart2; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++}; ++ ++&blsp1_uart2 { ++ pinctrl-0 = <&uart2_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&sdhc_1 { ++ pinctrl-0 = <&sdc_default_state>; ++ pinctrl-names = "default"; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ max-frequency = <384000000>; ++ bus-width = <8>; ++ status = "okay"; ++}; ++ ++&sleep_clk { ++ clock-frequency = <32000>; ++}; ++ ++&tlmm { ++ sdc_default_state: sdc-default-state { ++ clk-pins { ++ pins = "gpio5"; ++ function = "sdc_clk"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ ++ cmd-pins { ++ pins = "gpio4"; ++ function = "sdc_cmd"; ++ drive-strength = <8>; ++ bias-pull-up; ++ }; ++ ++ data-pins { ++ pins = "gpio0", "gpio1", "gpio2", ++ "gpio3", "gpio6", "gpio7", ++ "gpio8", "gpio9"; ++ function = "sdc_data"; ++ drive-strength = <8>; ++ bias-pull-up; ++ }; ++ ++ rclk-pins { ++ pins = "gpio10"; ++ function = "sdc_rclk"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ }; ++}; ++ ++&xo_board_clk { ++ clock-frequency = <24000000>; ++}; diff --git a/target/linux/ipq95xx/patches-6.1/0014-arm64-dts-qcom-ipq9574-Drop-bias_pll_ubi_nc_clk-inpu.patch b/target/linux/ipq95xx/patches-6.1/0014-arm64-dts-qcom-ipq9574-Drop-bias_pll_ubi_nc_clk-inpu.patch new file mode 100644 index 00000000000000..bda5121cfed6ca --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0014-arm64-dts-qcom-ipq9574-Drop-bias_pll_ubi_nc_clk-inpu.patch @@ -0,0 +1,39 @@ +From 20576d5e55831df510ed60f53d83c6e0618c2343 Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Tue, 25 Apr 2023 14:10:09 +0530 +Subject: [PATCH 14/41] arm64: dts: qcom: ipq9574: Drop bias_pll_ubi_nc_clk + input + +Drop unused bias_pll_ubi_nc_clk input to the clock controller. + +Signed-off-by: Devi Priya +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230425084010.15581-6-quic_devipriy@quicinc.com +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 8 +------- + 1 file changed, 1 insertion(+), 7 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -16,12 +16,6 @@ + #size-cells = <2>; + + clocks { +- bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk { +- compatible = "fixed-clock"; +- clock-frequency = <353000000>; +- #clock-cells = <0>; +- }; +- + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; +@@ -131,7 +125,7 @@ + reg = <0x01800000 0x80000>; + clocks = <&xo_board_clk>, + <&sleep_clk>, +- <&bias_pll_ubi_nc_clk>, ++ <0>, + <0>, + <0>, + <0>, diff --git a/target/linux/ipq95xx/patches-6.1/0015-arm64-dts-qcom-ipq9574-Update-the-size-of-GICC-GICV-.patch b/target/linux/ipq95xx/patches-6.1/0015-arm64-dts-qcom-ipq9574-Update-the-size-of-GICC-GICV-.patch new file mode 100644 index 00000000000000..302c6a5eb10f6a --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0015-arm64-dts-qcom-ipq9574-Update-the-size-of-GICC-GICV-.patch @@ -0,0 +1,37 @@ +From d7a20702b072333cc36cc78eb715295d65159196 Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Tue, 25 Apr 2023 14:10:05 +0530 +Subject: [PATCH 15/41] arm64: dts: qcom: ipq9574: Update the size of GICC & + GICV regions + +Update the size of GICC and GICV regions to 8kB as the GICC_DIR & GICV_DIR +registers lie in the second 4kB region. Also, add target CPU encoding. + +Fixes: 97cb36ff52a1 ("arm64: dts: qcom: Add ipq9574 SoC and AL02 board support") +Signed-off-by: Devi Priya +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230425084010.15581-2-quic_devipriy@quicinc.com +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -166,14 +166,14 @@ + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + reg = <0x0b000000 0x1000>, /* GICD */ +- <0x0b002000 0x1000>, /* GICC */ ++ <0x0b002000 0x2000>, /* GICC */ + <0x0b001000 0x1000>, /* GICH */ +- <0x0b004000 0x1000>; /* GICV */ ++ <0x0b004000 0x2000>; /* GICV */ + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <3>; +- interrupts = ; ++ interrupts = ; + ranges = <0 0x0b00c000 0x3000>; + + v2m0: v2m@0 { diff --git a/target/linux/ipq95xx/patches-6.1/0016-arm64-dts-qcom-ipq9574-add-support-for-RDP418-varian.patch b/target/linux/ipq95xx/patches-6.1/0016-arm64-dts-qcom-ipq9574-add-support-for-RDP418-varian.patch new file mode 100644 index 00000000000000..564e89b0d41e28 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0016-arm64-dts-qcom-ipq9574-add-support-for-RDP418-varian.patch @@ -0,0 +1,158 @@ +From e218ade7d728582bce795f6cce6fff39c4107dd5 Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Wed, 10 May 2023 16:13:59 +0530 +Subject: [PATCH 16/41] arm64: dts: qcom: ipq9574: add support for RDP418 + variant + +Add the initial device tree support for the Reference Design Platform (RDP) +418 based on IPQ9574 family of SoCs. This patch adds support for Console +UART, SPI NOR, eMMC and SMPA1 regulator node. + +Co-developed-by: Anusha Rao +Signed-off-by: Anusha Rao +Signed-off-by: Devi Priya +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230510104359.16678-3-quic_devipriy@quicinc.com +--- + arch/arm64/boot/dts/qcom/Makefile | 1 + + arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts | 124 ++++++++++++++++++++ + 2 files changed, 125 insertions(+) + create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts + +--- a/arch/arm64/boot/dts/qcom/Makefile ++++ b/arch/arm64/boot/dts/qcom/Makefile +@@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01- + dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb + dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb + dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb ++dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp418.dtb + dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts +@@ -0,0 +1,124 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * IPQ9574 RDP418 board device tree source ++ * ++ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. ++ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++/dts-v1/; ++ ++#include "ipq9574.dtsi" ++ ++/ { ++ model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C2"; ++ compatible = "qcom,ipq9574-ap-al02-c2", "qcom,ipq9574"; ++ ++ aliases { ++ serial0 = &blsp1_uart2; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++}; ++ ++&blsp1_spi0 { ++ pinctrl-0 = <&spi_0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "micron,n25q128a11", "jedec,spi-nor"; ++ reg = <0>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ spi-max-frequency = <50000000>; ++ }; ++}; ++ ++&blsp1_uart2 { ++ pinctrl-0 = <&uart2_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&rpm_requests { ++ regulators { ++ compatible = "qcom,rpm-mp5496-regulators"; ++ ++ ipq9574_s1: s1 { ++ /* ++ * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. ++ * During regulator registration, kernel not knowing the initial voltage, ++ * considers it as zero and brings up the regulators with minimum supported voltage. ++ * Update the regulator-min-microvolt with SVS voltage of 725mV so that ++ * the regulators are brought up with 725mV which is sufficient for all the ++ * corner parts to operate at 800MHz ++ */ ++ regulator-min-microvolt = <725000>; ++ regulator-max-microvolt = <1075000>; ++ }; ++ }; ++}; ++ ++&sdhc_1 { ++ pinctrl-0 = <&sdc_default_state>; ++ pinctrl-names = "default"; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ max-frequency = <384000000>; ++ bus-width = <8>; ++ status = "okay"; ++}; ++ ++&sleep_clk { ++ clock-frequency = <32000>; ++}; ++ ++&tlmm { ++ sdc_default_state: sdc-default-state { ++ clk-pins { ++ pins = "gpio5"; ++ function = "sdc_clk"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ ++ cmd-pins { ++ pins = "gpio4"; ++ function = "sdc_cmd"; ++ drive-strength = <8>; ++ bias-pull-up; ++ }; ++ ++ data-pins { ++ pins = "gpio0", "gpio1", "gpio2", ++ "gpio3", "gpio6", "gpio7", ++ "gpio8", "gpio9"; ++ function = "sdc_data"; ++ drive-strength = <8>; ++ bias-pull-up; ++ }; ++ ++ rclk-pins { ++ pins = "gpio10"; ++ function = "sdc_rclk"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ }; ++ ++ spi_0_pins: spi-0-state { ++ pins = "gpio11", "gpio12", "gpio13", "gpio14"; ++ function = "blsp0_spi"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++}; ++ ++&xo_board_clk { ++ clock-frequency = <24000000>; ++}; diff --git a/target/linux/ipq95xx/patches-6.1/0017-arm64-dts-qcom-ipq9574-Add-SMEM-support.patch b/target/linux/ipq95xx/patches-6.1/0017-arm64-dts-qcom-ipq9574-Add-SMEM-support.patch new file mode 100644 index 00000000000000..e357482f37fa8c --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0017-arm64-dts-qcom-ipq9574-Add-SMEM-support.patch @@ -0,0 +1,43 @@ +From dcd3cd850131c36cc52ccee74e509d6cf194af2b Mon Sep 17 00:00:00 2001 +From: Poovendhan Selvaraj +Date: Thu, 11 May 2023 13:28:14 +0530 +Subject: [PATCH 17/41] arm64: dts: qcom: ipq9574: Add SMEM support + +Add the required nodes to support SMEM + +Signed-off-by: Poovendhan Selvaraj +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230511075814.2370-3-quic_poovendh@quicinc.com +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -94,6 +94,13 @@ + reg = <0x0 0x4a600000 0x0 0x400000>; + no-map; + }; ++ ++ smem@4aa00000 { ++ compatible = "qcom,smem"; ++ reg = <0x0 0x4aa00000 0x0 0x00100000>; ++ hwlocks = <&tcsr_mutex 0>; ++ no-map; ++ }; + }; + + soc: soc@0 { +@@ -136,6 +143,12 @@ + #power-domain-cells = <1>; + }; + ++ tcsr_mutex: hwlock@1905000 { ++ compatible = "qcom,tcsr-mutex"; ++ reg = <0x01905000 0x20000>; ++ #hwlock-cells = <1>; ++ }; ++ + sdhc_1: mmc@7804000 { + compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x07804000 0x1000>, <0x07805000 0x1000>; diff --git a/target/linux/ipq95xx/patches-6.1/0018-arm64-dts-qcom-ipq9574-add-support-for-RDP449-varian.patch b/target/linux/ipq95xx/patches-6.1/0018-arm64-dts-qcom-ipq9574-add-support-for-RDP449-varian.patch new file mode 100644 index 00000000000000..59c88969c428d7 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0018-arm64-dts-qcom-ipq9574-add-support-for-RDP449-varian.patch @@ -0,0 +1,113 @@ +From 013dab443b763648d450931df3f73a6c783c8197 Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Tue, 16 May 2023 19:20:13 +0530 +Subject: [PATCH 18/41] arm64: dts: qcom: ipq9574: add support for RDP449 + variant + +Add the initial device tree support for the Reference Design Platform (RDP) +449 based on IPQ9574 family of SoCs. This patch adds support for Console +UART, SPI NOR and SMPA1 regulator node. + +Signed-off-by: Devi Priya +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230516135013.3547-3-quic_devipriy@quicinc.com +--- + arch/arm64/boot/dts/qcom/Makefile | 1 + + arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts | 80 +++++++++++++++++++++ + 2 files changed, 81 insertions(+) + create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts + +--- a/arch/arm64/boot/dts/qcom/Makefile ++++ b/arch/arm64/boot/dts/qcom/Makefile +@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10- + dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb + dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp418.dtb + dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb ++dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8916-huawei-g7.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts +@@ -0,0 +1,80 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * IPQ9574 RDP449 board device tree source ++ * ++ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. ++ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++/dts-v1/; ++ ++#include "ipq9574.dtsi" ++ ++/ { ++ model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C6"; ++ compatible = "qcom,ipq9574-ap-al02-c6", "qcom,ipq9574"; ++ ++ aliases { ++ serial0 = &blsp1_uart2; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++}; ++ ++&blsp1_spi0 { ++ pinctrl-0 = <&spi_0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "micron,n25q128a11", "jedec,spi-nor"; ++ reg = <0>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ spi-max-frequency = <50000000>; ++ }; ++}; ++ ++&blsp1_uart2 { ++ pinctrl-0 = <&uart2_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&rpm_requests { ++ regulators { ++ compatible = "qcom,rpm-mp5496-regulators"; ++ ++ ipq9574_s1: s1 { ++ /* ++ * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. ++ * During regulator registration, kernel not knowing the initial voltage, ++ * considers it as zero and brings up the regulators with minimum supported voltage. ++ * Update the regulator-min-microvolt with SVS voltage of 725mV so that ++ * the regulators are brought up with 725mV which is sufficient for all the ++ * corner parts to operate at 800MHz ++ */ ++ regulator-min-microvolt = <725000>; ++ regulator-max-microvolt = <1075000>; ++ }; ++ }; ++}; ++ ++&sleep_clk { ++ clock-frequency = <32000>; ++}; ++ ++&tlmm { ++ spi_0_pins: spi-0-state { ++ pins = "gpio11", "gpio12", "gpio13", "gpio14"; ++ function = "blsp0_spi"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++}; ++ ++&xo_board_clk { ++ clock-frequency = <24000000>; ++}; diff --git a/target/linux/ipq95xx/patches-6.1/0019-arm64-dts-qcom-ipq9574-Add-cpufreq-support.patch b/target/linux/ipq95xx/patches-6.1/0019-arm64-dts-qcom-ipq9574-Add-cpufreq-support.patch new file mode 100644 index 00000000000000..54ea709d548dd5 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0019-arm64-dts-qcom-ipq9574-Add-cpufreq-support.patch @@ -0,0 +1,122 @@ +From 13ad51cfa78defdafd717ed89785c7bab8330a7b Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Wed, 17 May 2023 22:55:27 +0530 +Subject: [PATCH 19/41] arm64: dts: qcom: ipq9574: Add cpufreq support + +Add cpu freq nodes in the device tree to bump cpu frequency above 800MHz. + +Reviewed-by: Konrad Dybcio +Co-developed-by: Praveenkumar I +Signed-off-by: Praveenkumar I +Signed-off-by: Devi Priya +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230517172527.1968-4-quic_devipriy@quicinc.com +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 60 ++++++++++++++++++++++++++- + 1 file changed, 59 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -6,8 +6,9 @@ + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +-#include ++#include + #include ++#include + #include + + / { +@@ -37,6 +38,10 @@ + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; ++ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; ++ clock-names = "cpu"; ++ operating-points-v2 = <&cpu_opp_table>; ++ cpu-supply = <&ipq9574_s1>; + }; + + CPU1: cpu@1 { +@@ -45,6 +50,10 @@ + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; ++ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; ++ clock-names = "cpu"; ++ operating-points-v2 = <&cpu_opp_table>; ++ cpu-supply = <&ipq9574_s1>; + }; + + CPU2: cpu@2 { +@@ -53,6 +62,10 @@ + reg = <0x2>; + enable-method = "psci"; + next-level-cache = <&L2_0>; ++ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; ++ clock-names = "cpu"; ++ operating-points-v2 = <&cpu_opp_table>; ++ cpu-supply = <&ipq9574_s1>; + }; + + CPU3: cpu@3 { +@@ -61,6 +74,10 @@ + reg = <0x3>; + enable-method = "psci"; + next-level-cache = <&L2_0>; ++ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; ++ clock-names = "cpu"; ++ operating-points-v2 = <&cpu_opp_table>; ++ cpu-supply = <&ipq9574_s1>; + }; + + L2_0: l2-cache { +@@ -75,6 +92,47 @@ + reg = <0x0 0x40000000 0x0 0x0>; + }; + ++ cpu_opp_table: opp-table-cpu { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp-936000000 { ++ opp-hz = /bits/ 64 <936000000>; ++ opp-microvolt = <725000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-1104000000 { ++ opp-hz = /bits/ 64 <1104000000>; ++ opp-microvolt = <787500>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-1416000000 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <862500>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-1488000000 { ++ opp-hz = /bits/ 64 <1488000000>; ++ opp-microvolt = <925000>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-1800000000 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <987500>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-2208000000 { ++ opp-hz = /bits/ 64 <2208000000>; ++ opp-microvolt = <1062500>; ++ clock-latency-ns = <200000>; ++ }; ++ }; ++ + pmu { + compatible = "arm,cortex-a73-pmu"; + interrupts = ; diff --git a/target/linux/ipq95xx/patches-6.1/0020-arm64-dts-qcom-ipq9574-Add-SMPA1-regulator-node.patch b/target/linux/ipq95xx/patches-6.1/0020-arm64-dts-qcom-ipq9574-Add-SMPA1-regulator-node.patch new file mode 100644 index 00000000000000..71e3278cd76de0 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0020-arm64-dts-qcom-ipq9574-Add-SMPA1-regulator-node.patch @@ -0,0 +1,45 @@ +From d02b30b6e397d2ab09a703bb873fe722406ab06a Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Wed, 17 May 2023 22:55:26 +0530 +Subject: [PATCH 20/41] arm64: dts: qcom: ipq9574: Add SMPA1 regulator node + +Add support for SMPA1 regulator node in IPQ9574. + +Reviewed-by: Konrad Dybcio +Co-developed-by: Praveenkumar I +Signed-off-by: Praveenkumar I +Signed-off-by: Devi Priya +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230517172527.1968-3-quic_devipriy@quicinc.com +--- + arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +@@ -29,6 +29,25 @@ + status = "okay"; + }; + ++&rpm_requests { ++ regulators { ++ compatible = "qcom,rpm-mp5496-regulators"; ++ ++ ipq9574_s1: s1 { ++ /* ++ * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. ++ * During regulator registration, kernel not knowing the initial voltage, ++ * considers it as zero and brings up the regulators with minimum supported voltage. ++ * Update the regulator-min-microvolt with SVS voltage of 725mV so that ++ * the regulators are brought up with 725mV which is sufficient for all the ++ * corner parts to operate at 800MHz ++ */ ++ regulator-min-microvolt = <725000>; ++ regulator-max-microvolt = <1075000>; ++ }; ++ }; ++}; ++ + &sdhc_1 { + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; diff --git a/target/linux/ipq95xx/patches-6.1/0021-arm64-dts-qcom-ipq9574-Add-RPM-related-nodes.patch b/target/linux/ipq95xx/patches-6.1/0021-arm64-dts-qcom-ipq9574-Add-RPM-related-nodes.patch new file mode 100644 index 00000000000000..fb89c28cb850fc --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0021-arm64-dts-qcom-ipq9574-Add-RPM-related-nodes.patch @@ -0,0 +1,50 @@ +From 3ef03d409e8cb97d6659fa7b130b14f1726ea8bb Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Wed, 17 May 2023 22:55:25 +0530 +Subject: [PATCH 21/41] arm64: dts: qcom: ipq9574: Add RPM related nodes + +Add RPM Glink & RPM message RAM nodes to support frequency scaling +on IPQ9574. + +Reviewed-by: Konrad Dybcio +Co-developed-by: Praveenkumar I +Signed-off-by: Praveenkumar I +Signed-off-by: Devi Priya +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230517172527.1968-2-quic_devipriy@quicinc.com +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -161,12 +161,29 @@ + }; + }; + ++ rpm-glink { ++ compatible = "qcom,glink-rpm"; ++ interrupts = ; ++ qcom,rpm-msg-ram = <&rpm_msg_ram>; ++ mboxes = <&apcs_glb 0>; ++ ++ rpm_requests: rpm-requests { ++ compatible = "qcom,rpm-ipq9574"; ++ qcom,glink-channels = "rpm_requests"; ++ }; ++ }; ++ + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + ++ rpm_msg_ram: sram@60000 { ++ compatible = "qcom,rpm-msg-ram"; ++ reg = <0x00060000 0x6000>; ++ }; ++ + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq9574-tlmm"; + reg = <0x01000000 0x300000>; diff --git a/target/linux/ipq95xx/patches-6.1/0022-arm64-dts-qcom-ipq9574-add-few-device-nodes.patch b/target/linux/ipq95xx/patches-6.1/0022-arm64-dts-qcom-ipq9574-add-few-device-nodes.patch new file mode 100644 index 00000000000000..0f779485093368 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0022-arm64-dts-qcom-ipq9574-add-few-device-nodes.patch @@ -0,0 +1,247 @@ +From 0a8b1ac041c37115b7d09afeb203ed8900225cd1 Mon Sep 17 00:00:00 2001 +From: Kathiravan T +Date: Wed, 17 May 2023 12:58:06 +0530 +Subject: [PATCH 22/41] arm64: dts: qcom: ipq9574: add few device nodes + +Add QUP(SPI / I2C) peripheral, PRNG, WDOG and the remaining UART nodes. +While at it, enable the SPI NOR in RDP433 board. + +Signed-off-by: Kathiravan T +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230517072806.13170-1-quic_kathirav@quicinc.com +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 202 ++++++++++++++++++++++++++ + 1 file changed, 202 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -184,6 +184,13 @@ + reg = <0x00060000 0x6000>; + }; + ++ rng: rng@e3000 { ++ compatible = "qcom,prng-ee"; ++ reg = <0x000e3000 0x1000>; ++ clocks = <&gcc GCC_PRNG_AHB_CLK>; ++ clock-names = "core"; ++ }; ++ + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq9574-tlmm"; + reg = <0x01000000 0x300000>; +@@ -241,6 +248,36 @@ + status = "disabled"; + }; + ++ blsp_dma: dma-controller@7884000 { ++ compatible = "qcom,bam-v1.7.0"; ++ reg = <0x07884000 0x2b000>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "bam_clk"; ++ #dma-cells = <1>; ++ qcom,ee = <0>; ++ }; ++ ++ blsp1_uart0: serial@78af000 { ++ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; ++ reg = <0x078af000 0x200>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ status = "disabled"; ++ }; ++ ++ blsp1_uart1: serial@78b0000 { ++ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; ++ reg = <0x078b0000 0x200>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ status = "disabled"; ++ }; ++ + blsp1_uart2: serial@78b1000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b1000 0x200>; +@@ -251,6 +288,163 @@ + status = "disabled"; + }; + ++ blsp1_uart3: serial@78b2000 { ++ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; ++ reg = <0x078b2000 0x200>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ status = "disabled"; ++ }; ++ ++ blsp1_uart4: serial@78b3000 { ++ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; ++ reg = <0x078b3000 0x200>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ status = "disabled"; ++ }; ++ ++ blsp1_uart5: serial@78b4000 { ++ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; ++ reg = <0x078b4000 0x200>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ status = "disabled"; ++ }; ++ ++ blsp1_spi0: spi@78b5000 { ++ compatible = "qcom,spi-qup-v2.2.1"; ++ reg = <0x078b5000 0x600>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ dmas = <&blsp_dma 12>, <&blsp_dma 13>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ ++ blsp1_i2c1: i2c@78b6000 { ++ compatible = "qcom,i2c-qup-v2.2.1"; ++ reg = <0x078b6000 0x600>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ dmas = <&blsp_dma 14>, <&blsp_dma 15>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ ++ blsp1_spi1: spi@78b6000 { ++ compatible = "qcom,spi-qup-v2.2.1"; ++ reg = <0x078b6000 0x600>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ dmas = <&blsp_dma 14>, <&blsp_dma 15>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ ++ blsp1_i2c2: i2c@78b7000 { ++ compatible = "qcom,i2c-qup-v2.2.1"; ++ reg = <0x078b7000 0x600>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ dmas = <&blsp_dma 16>, <&blsp_dma 17>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ ++ blsp1_spi2: spi@78b7000 { ++ compatible = "qcom,spi-qup-v2.2.1"; ++ reg = <0x078b7000 0x600>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ dmas = <&blsp_dma 16>, <&blsp_dma 17>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ ++ blsp1_i2c3: i2c@78b8000 { ++ compatible = "qcom,i2c-qup-v2.2.1"; ++ reg = <0x078b8000 0x600>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ dmas = <&blsp_dma 18>, <&blsp_dma 19>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ ++ blsp1_spi3: spi@78b8000 { ++ compatible = "qcom,spi-qup-v2.2.1"; ++ reg = <0x078b8000 0x600>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = ; ++ spi-max-frequency = <50000000>; ++ clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ dmas = <&blsp_dma 18>, <&blsp_dma 19>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ ++ blsp1_i2c4: i2c@78b9000 { ++ compatible = "qcom,i2c-qup-v2.2.1"; ++ reg = <0x078b9000 0x600>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ dmas = <&blsp_dma 20>, <&blsp_dma 21>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ ++ blsp1_spi4: spi@78b9000 { ++ compatible = "qcom,spi-qup-v2.2.1"; ++ reg = <0x078b9000 0x600>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ dmas = <&blsp_dma 20>, <&blsp_dma 21>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + reg = <0x0b000000 0x1000>, /* GICD */ +@@ -301,6 +495,14 @@ + clock-names = "xo"; + }; + ++ watchdog: watchdog@b017000 { ++ compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt"; ++ reg = <0x0b017000 0x1000>; ++ interrupts = ; ++ clocks = <&sleep_clk>; ++ timeout-sec = <30>; ++ }; ++ + timer@b120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; diff --git a/target/linux/ipq95xx/patches-6.1/0023-arm64-dts-qcom-add-few-more-reserved-memory-region.patch b/target/linux/ipq95xx/patches-6.1/0023-arm64-dts-qcom-add-few-more-reserved-memory-region.patch new file mode 100644 index 00000000000000..c429ef0b4667c8 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0023-arm64-dts-qcom-add-few-more-reserved-memory-region.patch @@ -0,0 +1,60 @@ +From d8dc9c70bb55769ebcf17ed9b1ff085c7fb09bff Mon Sep 17 00:00:00 2001 +From: Vignesh Viswanathan +Date: Fri, 26 May 2023 16:36:53 +0530 +Subject: [PATCH 23/41] arm64: dts: qcom: add few more reserved memory region + +In IPQ SoCs, bootloader will collect the system RAM contents upon crash +for the post morterm analysis. If we don't reserve the memory region used +by bootloader, obviously linux will consume it and upon next boot on +crash, bootloader will be loaded in the same region, which will lead to +loose some of the data, sometimes we may miss out critical information. +So lets reserve the region used by the bootloader. + +Similarly SBL copies some data into the reserved region and it will be +used in the crash scenario. So reserve 1MB for SBL as well. + +While at it, drop the size padding in the reserved memory region, +wherever applicable. + +Signed-off-by: Vignesh Viswanathan +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230526110653.27777-4-quic_viswanat@quicinc.com +--- + arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 +++++++++++++--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++-- + 2 files changed, 25 insertions(+), 5 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi +@@ -150,18 +150,28 @@ + no-map; + }; + ++ bootloader@4a100000 { ++ reg = <0x0 0x4a100000 0x0 0x400000>; ++ no-map; ++ }; ++ ++ sbl@4a500000 { ++ reg = <0x0 0x4a500000 0x0 0x100000>; ++ no-map; ++ }; ++ + tz: memory@4a600000 { +- reg = <0x0 0x4a600000 0x0 0x00400000>; ++ reg = <0x0 0x4a600000 0x0 0x400000>; + no-map; + }; + + smem_region: memory@4aa00000 { +- reg = <0x0 0x4aa00000 0x0 0x00100000>; ++ reg = <0x0 0x4aa00000 0x0 0x100000>; + no-map; + }; + + q6_region: memory@4ab00000 { +- reg = <0x0 0x4ab00000 0x0 0x05500000>; ++ reg = <0x0 0x4ab00000 0x0 0x5500000>; + no-map; + }; + }; diff --git a/target/linux/ipq95xx/patches-6.1/0024-arm64-dts-qcom-ipq9574-add-QFPROM-node.patch b/target/linux/ipq95xx/patches-6.1/0024-arm64-dts-qcom-ipq9574-add-QFPROM-node.patch new file mode 100644 index 00000000000000..6ad52b4982c30a --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0024-arm64-dts-qcom-ipq9574-add-QFPROM-node.patch @@ -0,0 +1,33 @@ +From 040e839870bb864a62a1e769fdfbbc5de64a724d Mon Sep 17 00:00:00 2001 +From: Kathiravan T +Date: Fri, 26 May 2023 18:23:05 +0530 +Subject: [PATCH 24/41] arm64: dts: qcom: ipq9574: add QFPROM node + +IPQ9574 has efuse region to determine the various HW quirks. Lets +add the initial support and the individual fuses will be added as they +are required. + +Reviewed-by: Konrad Dybcio +Signed-off-by: Kathiravan T +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230526125305.19626-5-quic_kathirav@quicinc.com +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -191,6 +191,13 @@ + clock-names = "core"; + }; + ++ qfprom: efuse@a4000 { ++ compatible = "qcom,ipq9574-qfprom", "qcom,qfprom"; ++ reg = <0x000a4000 0x5a1>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ }; ++ + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq9574-tlmm"; + reg = <0x01000000 0x300000>; diff --git a/target/linux/ipq95xx/patches-6.1/0025-arm64-dts-qcom-ipq9574-add-support-for-RDP453-varian.patch b/target/linux/ipq95xx/patches-6.1/0025-arm64-dts-qcom-ipq9574-add-support-for-RDP453-varian.patch new file mode 100644 index 00000000000000..57eb656cbd0be9 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0025-arm64-dts-qcom-ipq9574-add-support-for-RDP453-varian.patch @@ -0,0 +1,112 @@ +From cc88e897a8fe19d2a611a51321577c11a7997e68 Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Fri, 26 May 2023 21:01:52 +0530 +Subject: [PATCH 25/41] arm64: dts: qcom: ipq9574: add support for RDP453 + variant + +Add the initial device tree support for the Reference Design Platform (RDP) +453 based on IPQ9574 family of SoCs. This patch adds support for Console +UART, SPI NOR and SMPA1 regulator node. + +Signed-off-by: Devi Priya +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230526153152.777-3-quic_devipriy@quicinc.com +--- + arch/arm64/boot/dts/qcom/Makefile | 1 + + arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts | 80 +++++++++++++++++++++ + 2 files changed, 81 insertions(+) + create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts + +--- a/arch/arm64/boot/dts/qcom/Makefile ++++ b/arch/arm64/boot/dts/qcom/Makefile +@@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10- + dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp418.dtb + dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb + dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb ++dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8916-huawei-g7.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts +@@ -0,0 +1,80 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * IPQ9574 RDP453 board device tree source ++ * ++ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. ++ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++/dts-v1/; ++ ++#include "ipq9574.dtsi" ++ ++/ { ++ model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C8"; ++ compatible = "qcom,ipq9574-ap-al02-c8", "qcom,ipq9574"; ++ ++ aliases { ++ serial0 = &blsp1_uart2; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++}; ++ ++&blsp1_spi0 { ++ pinctrl-0 = <&spi_0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "micron,n25q128a11", "jedec,spi-nor"; ++ reg = <0>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ spi-max-frequency = <50000000>; ++ }; ++}; ++ ++&blsp1_uart2 { ++ pinctrl-0 = <&uart2_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&rpm_requests { ++ regulators { ++ compatible = "qcom,rpm-mp5496-regulators"; ++ ++ ipq9574_s1: s1 { ++ /* ++ * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. ++ * During regulator registration, kernel not knowing the initial voltage, ++ * considers it as zero and brings up the regulators with minimum supported voltage. ++ * Update the regulator-min-microvolt with SVS voltage of 725mV so that ++ * the regulators are brought up with 725mV which is sufficient for all the ++ * corner parts to operate at 800MHz ++ */ ++ regulator-min-microvolt = <725000>; ++ regulator-max-microvolt = <1075000>; ++ }; ++ }; ++}; ++ ++&sleep_clk { ++ clock-frequency = <32000>; ++}; ++ ++&tlmm { ++ spi_0_pins: spi-0-state { ++ pins = "gpio11", "gpio12", "gpio13", "gpio14"; ++ function = "blsp0_spi"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++}; ++ ++&xo_board_clk { ++ clock-frequency = <24000000>; ++}; diff --git a/target/linux/ipq95xx/patches-6.1/0026-arm64-dts-qcom-ipq9574-add-support-for-RDP454-varian.patch b/target/linux/ipq95xx/patches-6.1/0026-arm64-dts-qcom-ipq9574-add-support-for-RDP454-varian.patch new file mode 100644 index 00000000000000..fa8e886bd0830c --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0026-arm64-dts-qcom-ipq9574-add-support-for-RDP454-varian.patch @@ -0,0 +1,112 @@ +From acd0e1607b9d113fe2240a571358d8bbdb6f2504 Mon Sep 17 00:00:00 2001 +From: Poovendhan Selvaraj +Date: Wed, 31 May 2023 08:56:48 +0530 +Subject: [PATCH 26/41] arm64: dts: qcom: ipq9574: add support for RDP454 + variant + +Add the initial device tree support for the Reference Design Platform (RDP) +454 based on IPQ9574 family of SoCs. This patch adds support for Console +UART, SPI NOR and SMPA1 regulator node. + +Signed-off-by: Poovendhan Selvaraj +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230531032648.23816-3-quic_poovendh@quicinc.com +--- + arch/arm64/boot/dts/qcom/Makefile | 1 + + arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts | 80 +++++++++++++++++++++ + 2 files changed, 81 insertions(+) + create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts + +--- a/arch/arm64/boot/dts/qcom/Makefile ++++ b/arch/arm64/boot/dts/qcom/Makefile +@@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp41 + dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb + dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb + dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb ++dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb + dtb-$(CONFIG_ARCH_QCOM) += msm8916-huawei-g7.dtb +--- /dev/null ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts +@@ -0,0 +1,80 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * IPQ9574 RDP454 board device tree source ++ * ++ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. ++ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++/dts-v1/; ++ ++#include "ipq9574.dtsi" ++ ++/ { ++ model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C9"; ++ compatible = "qcom,ipq9574-ap-al02-c9", "qcom,ipq9574"; ++ ++ aliases { ++ serial0 = &blsp1_uart2; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++}; ++ ++&blsp1_spi0 { ++ pinctrl-0 = <&spi_0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "micron,n25q128a11", "jedec,spi-nor"; ++ reg = <0>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ spi-max-frequency = <50000000>; ++ }; ++}; ++ ++&blsp1_uart2 { ++ pinctrl-0 = <&uart2_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&rpm_requests { ++ regulators { ++ compatible = "qcom,rpm-mp5496-regulators"; ++ ++ ipq9574_s1: s1 { ++ /* ++ * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. ++ * During regulator registration, kernel not knowing the initial voltage, ++ * considers it as zero and brings up the regulators with minimum supported voltage. ++ * Update the regulator-min-microvolt with SVS voltage of 725mV so that ++ * the regulators are brought up with 725mV which is sufficient for all the ++ * corner parts to operate at 800MHz ++ */ ++ regulator-min-microvolt = <725000>; ++ regulator-max-microvolt = <1075000>; ++ }; ++ }; ++}; ++ ++&sleep_clk { ++ clock-frequency = <32000>; ++}; ++ ++&tlmm { ++ spi_0_pins: spi-0-state { ++ pins = "gpio11", "gpio12", "gpio13", "gpio14"; ++ function = "blsp0_spi"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++}; ++ ++&xo_board_clk { ++ clock-frequency = <24000000>; ++}; diff --git a/target/linux/ipq95xx/patches-6.1/0027-arm64-dts-qcom-ipq9574-add-few-more-reserved-memory-.patch b/target/linux/ipq95xx/patches-6.1/0027-arm64-dts-qcom-ipq9574-add-few-more-reserved-memory-.patch new file mode 100644 index 00000000000000..f30d3e47d2fe88 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0027-arm64-dts-qcom-ipq9574-add-few-more-reserved-memory-.patch @@ -0,0 +1,55 @@ +From cf53f8937fa9241f6d873a469c04d509e3062539 Mon Sep 17 00:00:00 2001 +From: Anusha Rao +Date: Fri, 2 Jun 2023 14:14:31 +0530 +Subject: [PATCH 27/41] arm64: dts: qcom: ipq9574: add few more reserved memory + region + +In IPQ SoCs, bootloader will collect the system RAM contents upon crash +for post-morterm analysis. If we don't reserve the memory region used +by bootloader, obviously linux will consume it and upon next boot on +crash, bootloader will be loaded in the same region, which will lead to +loss of some data, sometimes we may miss out critical information. +So lets reserve the region used by the bootloader. + +Similarly SBL copies some data into the reserved region and it will be +used in the crash scenario. So reserve 1MB for SBL as well. + +While at it, drop the size padding in the reserved memory region, +wherever applicable + +Signed-off-by: Anusha Rao +Reviewed-by: Kathiravan T +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230602084431.19134-1-quic_anusha@quicinc.com +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 12 +++++++++++- + 1 file changed, 11 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -148,6 +148,16 @@ + #size-cells = <2>; + ranges; + ++ bootloader@4a100000 { ++ reg = <0x0 0x4a100000 0x0 0x400000>; ++ no-map; ++ }; ++ ++ sbl@4a500000 { ++ reg = <0x0 0x4a500000 0x0 0x100000>; ++ no-map; ++ }; ++ + tz_region: tz@4a600000 { + reg = <0x0 0x4a600000 0x0 0x400000>; + no-map; +@@ -155,7 +165,7 @@ + + smem@4aa00000 { + compatible = "qcom,smem"; +- reg = <0x0 0x4aa00000 0x0 0x00100000>; ++ reg = <0x0 0x4aa00000 0x0 0x100000>; + hwlocks = <&tcsr_mutex 0>; + no-map; + }; diff --git a/target/linux/ipq95xx/patches-6.1/0028-arm64-dts-qcom-ipq9574-Use-assigned-clock-rates-for-.patch b/target/linux/ipq95xx/patches-6.1/0028-arm64-dts-qcom-ipq9574-Use-assigned-clock-rates-for-.patch new file mode 100644 index 00000000000000..943b55960375d0 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0028-arm64-dts-qcom-ipq9574-Use-assigned-clock-rates-for-.patch @@ -0,0 +1,54 @@ +From 366d78e84d2a737d75d72b2fb201aacac3a86696 Mon Sep 17 00:00:00 2001 +From: Devi Priya +Date: Thu, 15 Jun 2023 14:18:41 +0530 +Subject: [PATCH 28/41] arm64: dts: qcom: ipq9574: Use assigned-clock-rates for + QUP I2C core clks + +Use assigned-clock-rates property for configuring the QUP I2C core clocks +to operate at nominal frequency. + +Signed-off-by: Devi Priya +Link: https://lore.kernel.org/r/20230615084841.12375-1-quic_devipriy@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -358,6 +358,8 @@ + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; ++ assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; ++ assigned-clock-rates = <50000000>; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; + status = "disabled"; +@@ -386,6 +388,8 @@ + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; ++ assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; ++ assigned-clock-rates = <50000000>; + dmas = <&blsp_dma 16>, <&blsp_dma 17>; + dma-names = "tx", "rx"; + status = "disabled"; +@@ -414,6 +418,8 @@ + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; ++ assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; ++ assigned-clock-rates = <50000000>; + dmas = <&blsp_dma 18>, <&blsp_dma 19>; + dma-names = "tx", "rx"; + status = "disabled"; +@@ -443,6 +449,8 @@ + clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; ++ assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; ++ assigned-clock-rates = <50000000>; + dmas = <&blsp_dma 20>, <&blsp_dma 21>; + dma-names = "tx", "rx"; + status = "disabled"; diff --git a/target/linux/ipq95xx/patches-6.1/0029-arm64-dts-qcom-ipq9574-Fix-hwlock-index-for-SMEM.patch b/target/linux/ipq95xx/patches-6.1/0029-arm64-dts-qcom-ipq9574-Fix-hwlock-index-for-SMEM.patch new file mode 100644 index 00000000000000..77140650ef9030 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0029-arm64-dts-qcom-ipq9574-Fix-hwlock-index-for-SMEM.patch @@ -0,0 +1,31 @@ +From 4de55890566a8ca941af940c1ada4826c069969e Mon Sep 17 00:00:00 2001 +From: Vignesh Viswanathan +Date: Mon, 4 Sep 2023 22:55:15 +0530 +Subject: [PATCH 29/41] arm64: dts: qcom: ipq9574: Fix hwlock index for SMEM + +SMEM uses lock index 3 of the TCSR Mutex hwlock for allocations +in SMEM region shared by the Host and FW. + +Fix the SMEM hwlock index to 3 for IPQ9574. + +Cc: stable@vger.kernel.org +Fixes: 46384ac7a618 ("arm64: dts: qcom: ipq9574: Add SMEM support") +Signed-off-by: Vignesh Viswanathan +Acked-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20230904172516.479866-5-quic_viswanat@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -166,7 +166,7 @@ + smem@4aa00000 { + compatible = "qcom,smem"; + reg = <0x0 0x4aa00000 0x0 0x100000>; +- hwlocks = <&tcsr_mutex 0>; ++ hwlocks = <&tcsr_mutex 3>; + no-map; + }; + }; diff --git a/target/linux/ipq95xx/patches-6.1/0030-arm64-dts-qcom-ipq9574-include-the-GPLL0-as-clock-pr.patch b/target/linux/ipq95xx/patches-6.1/0030-arm64-dts-qcom-ipq9574-include-the-GPLL0-as-clock-pr.patch new file mode 100644 index 00000000000000..bbdb49b9de39d7 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0030-arm64-dts-qcom-ipq9574-include-the-GPLL0-as-clock-pr.patch @@ -0,0 +1,35 @@ +From ceeec9e4dbd9561b9483b3ad8648e66eba3c8016 Mon Sep 17 00:00:00 2001 +From: Kathiravan Thirumoorthy +Date: Thu, 14 Sep 2023 12:30:00 +0530 +Subject: [PATCH 30/41] arm64: dts: qcom: ipq9574: include the GPLL0 as clock + provider for mailbox + +While the kernel is booting up, APSS clock / CPU clock will be running +at 800MHz with GPLL0 as source. Once the cpufreq driver is available, +APSS PLL will be configured to the rate based on the opp table and the +source also will be changed to APSS_PLL_EARLY. So allow the mailbox to +consume the GPLL0, with this inclusion, CPU Freq correctly reports that +CPU is running at 800MHz rather than 24MHz. + +Signed-off-by: Kathiravan Thirumoorthy +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-10-c8ceb1a37680@quicinc.com +[bjorn: Updated commit message, as requested by Kathiravan] +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -507,8 +507,8 @@ + "qcom,ipq6018-apcs-apps-global"; + reg = <0x0b111000 0x1000>; + #clock-cells = <1>; +- clocks = <&a73pll>, <&xo_board_clk>; +- clock-names = "pll", "xo"; ++ clocks = <&a73pll>, <&xo_board_clk>, <&gcc GPLL0>; ++ clock-names = "pll", "xo", "gpll0"; + #mbox-cells = <1>; + }; + diff --git a/target/linux/ipq95xx/patches-6.1/0031-clk-qcom-apss-ipq6018-add-the-GPLL0-clock-also-as-cl.patch b/target/linux/ipq95xx/patches-6.1/0031-clk-qcom-apss-ipq6018-add-the-GPLL0-clock-also-as-cl.patch new file mode 100644 index 00000000000000..767cb797177637 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0031-clk-qcom-apss-ipq6018-add-the-GPLL0-clock-also-as-cl.patch @@ -0,0 +1,45 @@ +From 618e80e9a977954c06fd6fa5d65b6f712562bdaf Mon Sep 17 00:00:00 2001 +From: Kathiravan Thirumoorthy +Date: Thu, 14 Sep 2023 12:29:57 +0530 +Subject: [PATCH 31/41] clk: qcom: apss-ipq6018: add the GPLL0 clock also as + clock provider + +While the kernel is booting up, APSS PLL will be running at 800MHz with +GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be +configured and select the rate based on the opp table and the source will +be changed to APSS_PLL_EARLY. + +Without this patch, CPU Freq driver reports that CPU is running at 24MHz +instead of the 800MHz. + +Reviewed-by: Konrad Dybcio +Tested-by: Robert Marko +Signed-off-by: Kathiravan Thirumoorthy +Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-7-c8ceb1a37680@quicinc.com +Signed-off-by: Bjorn Andersson +--- + drivers/clk/qcom/apss-ipq6018.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/clk/qcom/apss-ipq6018.c ++++ b/drivers/clk/qcom/apss-ipq6018.c +@@ -20,16 +20,19 @@ + + enum { + P_XO, ++ P_GPLL0, + P_APSS_PLL_EARLY, + }; + + static const struct clk_parent_data parents_apcs_alias0_clk_src[] = { + { .fw_name = "xo" }, ++ { .fw_name = "gpll0" }, + { .fw_name = "pll" }, + }; + + static const struct parent_map parents_apcs_alias0_clk_src_map[] = { + { P_XO, 0 }, ++ { P_GPLL0, 4 }, + { P_APSS_PLL_EARLY, 5 }, + }; + diff --git a/target/linux/ipq95xx/patches-6.1/0032-clk-qcom-ipq9574-drop-the-CLK_SET_RATE_PARENT-flag-f.patch b/target/linux/ipq95xx/patches-6.1/0032-clk-qcom-ipq9574-drop-the-CLK_SET_RATE_PARENT-flag-f.patch new file mode 100644 index 00000000000000..d07a21f5b9224b --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0032-clk-qcom-ipq9574-drop-the-CLK_SET_RATE_PARENT-flag-f.patch @@ -0,0 +1,57 @@ +From f0869d5304a548b18bd0402ed2ebe6e6fa66ec04 Mon Sep 17 00:00:00 2001 +From: Kathiravan Thirumoorthy +Date: Thu, 14 Sep 2023 12:29:54 +0530 +Subject: [PATCH 32/41] clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag + from GPLL clocks + +GPLL clock rates are fixed and shouldn't be scaled based on the request +from dependent clocks. Doing so will result in the unexpected behaviour. +So drop the CLK_SET_RATE_PARENT flag from the GPLL clocks. + +---- +Changes in V2: + - No changes + +Fixes: d75b82cff488 ("clk: qcom: Add Global Clock Controller driver for IPQ9574") +Signed-off-by: Kathiravan Thirumoorthy +Reviewed-by: Konrad Dybcio +Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-4-c8ceb1a37680@quicinc.com +Signed-off-by: Bjorn Andersson +--- + drivers/clk/qcom/gcc-ipq9574.c | 4 ---- + 1 file changed, 4 deletions(-) + +--- a/drivers/clk/qcom/gcc-ipq9574.c ++++ b/drivers/clk/qcom/gcc-ipq9574.c +@@ -87,7 +87,6 @@ static struct clk_fixed_factor gpll0_out + &gpll0_main.clkr.hw + }, + .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_fixed_factor_ops, + }, + }; +@@ -102,7 +101,6 @@ static struct clk_alpha_pll_postdiv gpll + &gpll0_main.clkr.hw + }, + .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_ro_ops, + }, + }; +@@ -132,7 +130,6 @@ static struct clk_alpha_pll_postdiv gpll + &gpll4_main.clkr.hw + }, + .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_ro_ops, + }, + }; +@@ -162,7 +159,6 @@ static struct clk_alpha_pll_postdiv gpll + &gpll2_main.clkr.hw + }, + .num_parents = 1, +- .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_ro_ops, + }, + }; diff --git a/target/linux/ipq95xx/patches-6.1/0033-firmware-qcom_scm-use-64-bit-calling-convention-only.patch b/target/linux/ipq95xx/patches-6.1/0033-firmware-qcom_scm-use-64-bit-calling-convention-only.patch new file mode 100644 index 00000000000000..fc54c2db071d3d --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0033-firmware-qcom_scm-use-64-bit-calling-convention-only.patch @@ -0,0 +1,48 @@ +From e9449be0c59beb0de16b7719ae5d9555a1a1ada7 Mon Sep 17 00:00:00 2001 +From: Kathiravan Thirumoorthy +Date: Mon, 25 Sep 2023 13:59:22 +0530 +Subject: [PATCH 33/41] firmware: qcom_scm: use 64-bit calling convention only + when client is 64-bit + +Per the "SMC calling convention specification", the 64-bit calling +convention can only be used when the client is 64-bit. Whereas the +32-bit calling convention can be used by either a 32-bit or a 64-bit +client. + +Currently during SCM probe, irrespective of the client, 64-bit calling +convention is made, which is incorrect and may lead to the undefined +behaviour when the client is 32-bit. Let's fix it. + +Cc: stable@vger.kernel.org +Fixes: 9a434cee773a ("firmware: qcom_scm: Dynamically support SMCCC and legacy conventions") +Reviewed-By: Elliot Berman +Signed-off-by: Kathiravan Thirumoorthy +Link: https://lore.kernel.org/r/20230925-scm-v3-1-8790dff6a749@quicinc.com +Signed-off-by: Bjorn Andersson +--- + drivers/firmware/qcom_scm.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/drivers/firmware/qcom_scm.c ++++ b/drivers/firmware/qcom_scm.c +@@ -171,6 +171,12 @@ static enum qcom_scm_convention __get_co + */ + #if IS_ENABLED(CONFIG_ARM64) + /* ++ * Per the "SMC calling convention specification", the 64-bit calling ++ * convention can only be used when the client is 64-bit, otherwise ++ * system will encounter the undefined behaviour. ++ */ ++#if IS_ENABLED(CONFIG_ARM64) ++ /* + * Device isn't required as there is only one argument - no device + * needed to dma_map_single to secure world + */ +@@ -286,6 +292,7 @@ static bool __qcom_scm_is_call_available + pr_err("Unknown SMC convention being used\n"); + return false; + } ++#endif + + ret = qcom_scm_call(dev, &desc, &res); + diff --git a/target/linux/ipq95xx/patches-6.1/0034-arm64-dts-qcom-ipq9574-Add-common-RDP-dtsi-file.patch b/target/linux/ipq95xx/patches-6.1/0034-arm64-dts-qcom-ipq9574-Add-common-RDP-dtsi-file.patch new file mode 100644 index 00000000000000..139d4d663b04b9 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0034-arm64-dts-qcom-ipq9574-Add-common-RDP-dtsi-file.patch @@ -0,0 +1,503 @@ +From 0f868f286529001ee37334815f4962b8a2f283dd Mon Sep 17 00:00:00 2001 +From: Anusha Rao +Date: Wed, 27 Sep 2023 12:13:18 +0530 +Subject: [PATCH 34/41] arm64: dts: qcom: ipq9574: Add common RDP dtsi file + +Add a dtsi file to include interfaces that are common +across RDPs. + +Signed-off-by: Anusha Rao +Signed-off-by: Kathiravan Thirumoorthy +Link: https://lore.kernel.org/r/20230927-common-rdp-v3-1-3d07b3ff6d42@quicinc.com +Signed-off-by: Bjorn Andersson +--- + .../boot/dts/qcom/ipq9574-rdp-common.dtsi | 102 ++++++++++++++++++ + arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts | 63 +---------- + arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 38 +------ + arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts | 65 +---------- + arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts | 65 +---------- + arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts | 66 +----------- + 6 files changed, 107 insertions(+), 292 deletions(-) + create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi + +--- /dev/null ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +@@ -0,0 +1,102 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * IPQ9574 RDP board common device tree source ++ * ++ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. ++ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. ++ */ ++ ++/dts-v1/; ++ ++#include "ipq9574.dtsi" ++ ++/ { ++ aliases { ++ serial0 = &blsp1_uart2; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ regulator_fixed_3p3: s3300 { ++ compatible = "regulator-fixed"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-name = "fixed_3p3"; ++ }; ++ ++ regulator_fixed_0p925: s0925 { ++ compatible = "regulator-fixed"; ++ regulator-min-microvolt = <925000>; ++ regulator-max-microvolt = <925000>; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-name = "fixed_0p925"; ++ }; ++}; ++ ++&blsp1_spi0 { ++ pinctrl-0 = <&spi_0_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "micron,n25q128a11", "jedec,spi-nor"; ++ reg = <0>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ spi-max-frequency = <50000000>; ++ }; ++}; ++ ++&blsp1_uart2 { ++ pinctrl-0 = <&uart2_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&rpm_requests { ++ regulators { ++ compatible = "qcom,rpm-mp5496-regulators"; ++ ++ ipq9574_s1: s1 { ++ /* ++ * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. ++ * During regulator registration, kernel not knowing the initial voltage, ++ * considers it as zero and brings up the regulators with minimum supported voltage. ++ * Update the regulator-min-microvolt with SVS voltage of 725mV so that ++ * the regulators are brought up with 725mV which is sufficient for all the ++ * corner parts to operate at 800MHz ++ */ ++ regulator-min-microvolt = <725000>; ++ regulator-max-microvolt = <1075000>; ++ }; ++ ++ mp5496_l2: l2 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ }; ++}; ++ ++&sleep_clk { ++ clock-frequency = <32000>; ++}; ++ ++&tlmm { ++ spi_0_pins: spi-0-state { ++ pins = "gpio11", "gpio12", "gpio13", "gpio14"; ++ function = "blsp0_spi"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++}; ++ ++&xo_board_clk { ++ clock-frequency = <24000000>; ++}; +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp418.dts +@@ -8,58 +8,12 @@ + + /dts-v1/; + +-#include "ipq9574.dtsi" ++#include "ipq9574-rdp-common.dtsi" + + / { + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C2"; + compatible = "qcom,ipq9574-ap-al02-c2", "qcom,ipq9574"; + +- aliases { +- serial0 = &blsp1_uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&blsp1_spi0 { +- pinctrl-0 = <&spi_0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- flash@0 { +- compatible = "micron,n25q128a11", "jedec,spi-nor"; +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <50000000>; +- }; +-}; +- +-&blsp1_uart2 { +- pinctrl-0 = <&uart2_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&rpm_requests { +- regulators { +- compatible = "qcom,rpm-mp5496-regulators"; +- +- ipq9574_s1: s1 { +- /* +- * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. +- * During regulator registration, kernel not knowing the initial voltage, +- * considers it as zero and brings up the regulators with minimum supported voltage. +- * Update the regulator-min-microvolt with SVS voltage of 725mV so that +- * the regulators are brought up with 725mV which is sufficient for all the +- * corner parts to operate at 800MHz +- */ +- regulator-min-microvolt = <725000>; +- regulator-max-microvolt = <1075000>; +- }; +- }; + }; + + &sdhc_1 { +@@ -74,10 +28,6 @@ + status = "okay"; + }; + +-&sleep_clk { +- clock-frequency = <32000>; +-}; +- + &tlmm { + sdc_default_state: sdc-default-state { + clk-pins { +@@ -110,15 +60,4 @@ + bias-pull-down; + }; + }; +- +- spi_0_pins: spi-0-state { +- pins = "gpio11", "gpio12", "gpio13", "gpio14"; +- function = "blsp0_spi"; +- drive-strength = <8>; +- bias-disable; +- }; +-}; +- +-&xo_board_clk { +- clock-frequency = <24000000>; + }; +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +@@ -8,44 +8,12 @@ + + /dts-v1/; + +-#include "ipq9574.dtsi" ++#include "ipq9574-rdp-common.dtsi" + + / { + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7"; + compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574"; + +- aliases { +- serial0 = &blsp1_uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&blsp1_uart2 { +- pinctrl-0 = <&uart2_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&rpm_requests { +- regulators { +- compatible = "qcom,rpm-mp5496-regulators"; +- +- ipq9574_s1: s1 { +- /* +- * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. +- * During regulator registration, kernel not knowing the initial voltage, +- * considers it as zero and brings up the regulators with minimum supported voltage. +- * Update the regulator-min-microvolt with SVS voltage of 725mV so that +- * the regulators are brought up with 725mV which is sufficient for all the +- * corner parts to operate at 800MHz +- */ +- regulator-min-microvolt = <725000>; +- regulator-max-microvolt = <1075000>; +- }; +- }; + }; + + &sdhc_1 { +@@ -97,7 +65,3 @@ + }; + }; + }; +- +-&xo_board_clk { +- clock-frequency = <24000000>; +-}; +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp449.dts +@@ -8,73 +8,10 @@ + + /dts-v1/; + +-#include "ipq9574.dtsi" ++#include "ipq9574-rdp-common.dtsi" + + / { + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C6"; + compatible = "qcom,ipq9574-ap-al02-c6", "qcom,ipq9574"; + +- aliases { +- serial0 = &blsp1_uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&blsp1_spi0 { +- pinctrl-0 = <&spi_0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- flash@0 { +- compatible = "micron,n25q128a11", "jedec,spi-nor"; +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <50000000>; +- }; +-}; +- +-&blsp1_uart2 { +- pinctrl-0 = <&uart2_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&rpm_requests { +- regulators { +- compatible = "qcom,rpm-mp5496-regulators"; +- +- ipq9574_s1: s1 { +- /* +- * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. +- * During regulator registration, kernel not knowing the initial voltage, +- * considers it as zero and brings up the regulators with minimum supported voltage. +- * Update the regulator-min-microvolt with SVS voltage of 725mV so that +- * the regulators are brought up with 725mV which is sufficient for all the +- * corner parts to operate at 800MHz +- */ +- regulator-min-microvolt = <725000>; +- regulator-max-microvolt = <1075000>; +- }; +- }; +-}; +- +-&sleep_clk { +- clock-frequency = <32000>; +-}; +- +-&tlmm { +- spi_0_pins: spi-0-state { +- pins = "gpio11", "gpio12", "gpio13", "gpio14"; +- function = "blsp0_spi"; +- drive-strength = <8>; +- bias-disable; +- }; +-}; +- +-&xo_board_clk { +- clock-frequency = <24000000>; + }; +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp453.dts +@@ -8,73 +8,10 @@ + + /dts-v1/; + +-#include "ipq9574.dtsi" ++#include "ipq9574-rdp-common.dtsi" + + / { + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C8"; + compatible = "qcom,ipq9574-ap-al02-c8", "qcom,ipq9574"; + +- aliases { +- serial0 = &blsp1_uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&blsp1_spi0 { +- pinctrl-0 = <&spi_0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- flash@0 { +- compatible = "micron,n25q128a11", "jedec,spi-nor"; +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <50000000>; +- }; +-}; +- +-&blsp1_uart2 { +- pinctrl-0 = <&uart2_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&rpm_requests { +- regulators { +- compatible = "qcom,rpm-mp5496-regulators"; +- +- ipq9574_s1: s1 { +- /* +- * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. +- * During regulator registration, kernel not knowing the initial voltage, +- * considers it as zero and brings up the regulators with minimum supported voltage. +- * Update the regulator-min-microvolt with SVS voltage of 725mV so that +- * the regulators are brought up with 725mV which is sufficient for all the +- * corner parts to operate at 800MHz +- */ +- regulator-min-microvolt = <725000>; +- regulator-max-microvolt = <1075000>; +- }; +- }; +-}; +- +-&sleep_clk { +- clock-frequency = <32000>; +-}; +- +-&tlmm { +- spi_0_pins: spi-0-state { +- pins = "gpio11", "gpio12", "gpio13", "gpio14"; +- function = "blsp0_spi"; +- drive-strength = <8>; +- bias-disable; +- }; +-}; +- +-&xo_board_clk { +- clock-frequency = <24000000>; + }; +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts +@@ -8,73 +8,9 @@ + + /dts-v1/; + +-#include "ipq9574.dtsi" ++#include "ipq9574-rdp-common.dtsi" + + / { + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C9"; + compatible = "qcom,ipq9574-ap-al02-c9", "qcom,ipq9574"; +- +- aliases { +- serial0 = &blsp1_uart2; +- }; +- +- chosen { +- stdout-path = "serial0:115200n8"; +- }; +-}; +- +-&blsp1_spi0 { +- pinctrl-0 = <&spi_0_pins>; +- pinctrl-names = "default"; +- status = "okay"; +- +- flash@0 { +- compatible = "micron,n25q128a11", "jedec,spi-nor"; +- reg = <0>; +- #address-cells = <1>; +- #size-cells = <1>; +- spi-max-frequency = <50000000>; +- }; +-}; +- +-&blsp1_uart2 { +- pinctrl-0 = <&uart2_pins>; +- pinctrl-names = "default"; +- status = "okay"; +-}; +- +-&rpm_requests { +- regulators { +- compatible = "qcom,rpm-mp5496-regulators"; +- +- ipq9574_s1: s1 { +- /* +- * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders. +- * During regulator registration, kernel not knowing the initial voltage, +- * considers it as zero and brings up the regulators with minimum supported voltage. +- * Update the regulator-min-microvolt with SVS voltage of 725mV so that +- * the regulators are brought up with 725mV which is sufficient for all the +- * corner parts to operate at 800MHz +- */ +- regulator-min-microvolt = <725000>; +- regulator-max-microvolt = <1075000>; +- }; +- }; +-}; +- +-&sleep_clk { +- clock-frequency = <32000>; +-}; +- +-&tlmm { +- spi_0_pins: spi-0-state { +- pins = "gpio11", "gpio12", "gpio13", "gpio14"; +- function = "blsp0_spi"; +- drive-strength = <8>; +- bias-disable; +- }; +-}; +- +-&xo_board_clk { +- clock-frequency = <24000000>; + }; diff --git a/target/linux/ipq95xx/patches-6.1/0035-arm64-dts-qcom-ipq9574-populate-the-opp-table-based-.patch b/target/linux/ipq95xx/patches-6.1/0035-arm64-dts-qcom-ipq9574-populate-the-opp-table-based-.patch new file mode 100644 index 00000000000000..a5419d2d0cf7a5 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0035-arm64-dts-qcom-ipq9574-populate-the-opp-table-based-.patch @@ -0,0 +1,105 @@ +From f1001470268206073905a37fdba06355eb43d32c Mon Sep 17 00:00:00 2001 +From: Varadarajan Narayanan +Date: Fri, 20 Oct 2023 11:49:39 +0530 +Subject: [PATCH 35/41] arm64: dts: qcom: ipq9574: populate the opp table based + on the eFuse + +IPQ95xx SoCs have different OPPs available for the CPU based on +SoC variant. This can be determined from an eFuse register +present in the silicon. + +Add support to read the eFuse and populate the OPPs based on it. + +Frequency 1.2GHz 1.8GHz 1.5GHz No opp-supported-hw + Limit +------------------------------------------------------------ +936000000 1 1 1 1 0xf +1104000000 1 1 1 1 0xf +1200000000 1 1 1 1 0xf +1416000000 0 1 1 1 0x7 +1488000000 0 1 1 1 0x7 +1800000000 0 1 0 1 0x5 +2208000000 0 0 0 1 0x1 +----------------------------------------------------------- + +Reviewed-by: Konrad Dybcio +Signed-off-by: Kathiravan T +Signed-off-by: Varadarajan Narayanan +Link: https://lore.kernel.org/r/14ab08b7cfd904433ca6065fac798d4f221c9d95.1697781921.git.quic_varada@quicinc.com +Signed-off-by: Bjorn Andersson +--- + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 21 ++++++++++++++++++++- + 1 file changed, 20 insertions(+), 1 deletion(-) + +--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi +@@ -93,42 +93,56 @@ + }; + + cpu_opp_table: opp-table-cpu { +- compatible = "operating-points-v2"; ++ compatible = "operating-points-v2-kryo-cpu"; + opp-shared; ++ nvmem-cells = <&cpu_speed_bin>; + + opp-936000000 { + opp-hz = /bits/ 64 <936000000>; + opp-microvolt = <725000>; ++ opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <787500>; ++ opp-supported-hw = <0xf>; ++ clock-latency-ns = <200000>; ++ }; ++ ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <862500>; ++ opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + }; + + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <862500>; ++ opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + + opp-1488000000 { + opp-hz = /bits/ 64 <1488000000>; + opp-microvolt = <925000>; ++ opp-supported-hw = <0x7>; + clock-latency-ns = <200000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <987500>; ++ opp-supported-hw = <0x5>; + clock-latency-ns = <200000>; + }; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <1062500>; ++ opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + }; + }; +@@ -206,6 +220,11 @@ + reg = <0x000a4000 0x5a1>; + #address-cells = <1>; + #size-cells = <1>; ++ ++ cpu_speed_bin: cpu-speed-bin@15 { ++ reg = <0x15 0x2>; ++ bits = <7 2>; ++ }; + }; + + tlmm: pinctrl@1000000 { diff --git a/target/linux/ipq95xx/patches-6.1/0036-clk-qcom-clk-alpha-pll-introduce-stromer-plus-ops.patch b/target/linux/ipq95xx/patches-6.1/0036-clk-qcom-clk-alpha-pll-introduce-stromer-plus-ops.patch new file mode 100644 index 00000000000000..34213c41378d19 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0036-clk-qcom-clk-alpha-pll-introduce-stromer-plus-ops.patch @@ -0,0 +1,99 @@ +From 539a79c58042c7902bfff6453a589d5dc2e0230c Mon Sep 17 00:00:00 2001 +From: Varadarajan Narayanan +Date: Fri, 20 Oct 2023 11:49:32 +0530 +Subject: [PATCH 36/41] clk: qcom: clk-alpha-pll: introduce stromer plus ops + +Stromer plus APSS PLL does not support dynamic frequency scaling. +To switch between frequencies, we have to shut down the PLL, +configure the L and ALPHA values and turn on again. So introduce the +separate set of ops for Stromer Plus PLL. + +Reviewed-by: Dmitry Baryshkov +Signed-off-by: Kathiravan T +Signed-off-by: Varadarajan Narayanan +Link: https://lore.kernel.org/r/2affa6c63ff0c4342230623a7d4eef02ec7c02d4.1697781921.git.quic_varada@quicinc.com +Signed-off-by: Bjorn Andersson +--- + drivers/clk/qcom/clk-alpha-pll.c | 63 ++++++++++++++++++++++++++++++++ + drivers/clk/qcom/clk-alpha-pll.h | 1 + + 2 files changed, 64 insertions(+) + +--- a/drivers/clk/qcom/clk-alpha-pll.c ++++ b/drivers/clk/qcom/clk-alpha-pll.c +@@ -2434,3 +2434,66 @@ const struct clk_ops clk_alpha_pll_strom + .set_rate = clk_alpha_pll_stromer_set_rate, + }; + EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops); ++ ++static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw, ++ unsigned long rate, ++ unsigned long prate) ++{ ++ struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); ++ u32 l, alpha_width = pll_alpha_width(pll); ++ int ret, pll_mode; ++ u64 a; ++ ++ rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); ++ ++ ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode); ++ if (ret) ++ return ret; ++ ++ regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0); ++ ++ /* Delay of 2 output clock ticks required until output is disabled */ ++ udelay(1); ++ ++ regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); ++ ++ if (alpha_width > ALPHA_BITWIDTH) ++ a <<= alpha_width - ALPHA_BITWIDTH; ++ ++ regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); ++ regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), ++ a >> ALPHA_BITWIDTH); ++ ++ regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL); ++ ++ /* Wait five micro seconds or more */ ++ udelay(5); ++ regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, ++ PLL_RESET_N); ++ ++ /* The lock time should be less than 50 micro seconds worst case */ ++ usleep_range(50, 60); ++ ++ ret = wait_for_pll_enable_lock(pll); ++ if (ret) { ++ pr_err("Wait for PLL enable lock failed [%s] %d\n", ++ clk_hw_get_name(hw), ret); ++ return ret; ++ } ++ ++ if (pll_mode & PLL_OUTCTRL) ++ regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, ++ PLL_OUTCTRL); ++ ++ return 0; ++} ++ ++const struct clk_ops clk_alpha_pll_stromer_plus_ops = { ++ .prepare = clk_alpha_pll_enable, ++ .unprepare = clk_alpha_pll_disable, ++ .is_enabled = clk_alpha_pll_is_enabled, ++ .recalc_rate = clk_alpha_pll_recalc_rate, ++ .determine_rate = clk_alpha_pll_stromer_determine_rate, ++ .set_rate = clk_alpha_pll_stromer_plus_set_rate, ++}; ++EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_plus_ops); +--- a/drivers/clk/qcom/clk-alpha-pll.h ++++ b/drivers/clk/qcom/clk-alpha-pll.h +@@ -145,6 +145,7 @@ extern const struct clk_ops clk_alpha_pl + extern const struct clk_ops clk_alpha_pll_huayra_ops; + extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops; + extern const struct clk_ops clk_alpha_pll_stromer_ops; ++extern const struct clk_ops clk_alpha_pll_stromer_plus_ops; + + extern const struct clk_ops clk_alpha_pll_fabia_ops; + extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops; diff --git a/target/linux/ipq95xx/patches-6.1/0037-cpufreq-qcom-nvmem-Introduce-cpufreq-for-ipq95xx.patch b/target/linux/ipq95xx/patches-6.1/0037-cpufreq-qcom-nvmem-Introduce-cpufreq-for-ipq95xx.patch new file mode 100644 index 00000000000000..e07815592d65a3 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0037-cpufreq-qcom-nvmem-Introduce-cpufreq-for-ipq95xx.patch @@ -0,0 +1,65 @@ +From 80838ab7ebd416cbac38c1cd30a76d61641f7ee1 Mon Sep 17 00:00:00 2001 +From: Varadarajan Narayanan +Date: Tue, 31 Oct 2023 12:41:39 +0530 +Subject: [PATCH 37/41] cpufreq: qcom-nvmem: Introduce cpufreq for ipq95xx + +IPQ95xx SoCs have different OPPs available for the CPU based on +the SoC variant. This can be determined from an eFuse register +present in the silicon. + +Added support for ipq95xx on nvmem driver which helps to +determine OPPs at runtime based on the eFuse register which +has the CPU frequency limits. opp-supported-hw dt binding +can be used to indicate the available OPPs for each limit. + +Reviewed-by: Dmitry Baryshkov +Signed-off-by: Praveenkumar I +Signed-off-by: Kathiravan T +Signed-off-by: Varadarajan Narayanan +[ Viresh: Fixed subject ] +Signed-off-by: Viresh Kumar +--- + drivers/cpufreq/cpufreq-dt-platdev.c | 1 + + drivers/cpufreq/qcom-cpufreq-nvmem.c | 5 +++++ + include/dt-bindings/arm/qcom,ids.h | 6 ++++++ + 3 files changed, 12 insertions(+) + +--- a/drivers/cpufreq/cpufreq-dt-platdev.c ++++ b/drivers/cpufreq/cpufreq-dt-platdev.c +@@ -164,6 +164,7 @@ static const struct of_device_id blockli + { .compatible = "ti,omap3", }, + + { .compatible = "qcom,ipq8064", }, ++ { .compatible = "qcom,ipq9574", }, + { .compatible = "qcom,apq8064", }, + { .compatible = "qcom,msm8974", }, + { .compatible = "qcom,msm8960", }, +--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c ++++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c +@@ -149,6 +149,11 @@ static int qcom_cpufreq_kryo_name_versio + switch (msm_id) { + case QCOM_ID_MSM8996: + case QCOM_ID_APQ8096: ++ case QCOM_ID_IPQ9514: ++ case QCOM_ID_IPQ9550: ++ case QCOM_ID_IPQ9554: ++ case QCOM_ID_IPQ9570: ++ case QCOM_ID_IPQ9574: + drv->versions = 1 << (unsigned int)(*speedbin); + break; + case QCOM_ID_MSM8996SG: +--- a/include/dt-bindings/arm/qcom,ids.h ++++ b/include/dt-bindings/arm/qcom,ids.h +@@ -140,6 +140,12 @@ + #define QCOM_ID_SC7280 487 + #define QCOM_ID_SC7180P 495 + #define QCOM_ID_SM6375 507 ++#define QCOM_ID_IPQ9514 510 ++#define QCOM_ID_IPQ9550 511 ++#define QCOM_ID_IPQ9554 512 ++#define QCOM_ID_IPQ9570 513 ++#define QCOM_ID_IPQ9574 514 ++#define QCOM_ID_IPQ9510 521 + + /* + * The board type and revision information, used by Qualcomm bootloaders and diff --git a/target/linux/ipq95xx/patches-6.1/0038-arm64-dts-qcom-ipq9574-Enable-WPS-buttons.patch b/target/linux/ipq95xx/patches-6.1/0038-arm64-dts-qcom-ipq9574-Enable-WPS-buttons.patch new file mode 100644 index 00000000000000..fe33b589d9d9a8 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0038-arm64-dts-qcom-ipq9574-Enable-WPS-buttons.patch @@ -0,0 +1,61 @@ +From ff1925f7070d4cc3c5772565672632854444317e Mon Sep 17 00:00:00 2001 +From: Anusha Rao +Date: Wed, 27 Sep 2023 12:13:19 +0530 +Subject: [PATCH 38/41] arm64: dts: qcom: ipq9574: Enable WPS buttons + +Add support for wps buttons on GPIO 37. + +Reviewed-by: Konrad Dybcio +Signed-off-by: Anusha Rao +Signed-off-by: Kathiravan Thirumoorthy +Link: https://lore.kernel.org/r/20230927-common-rdp-v3-2-3d07b3ff6d42@quicinc.com +Signed-off-by: Bjorn Andersson +--- + .../boot/dts/qcom/ipq9574-rdp-common.dtsi | 22 +++++++++++++++++++ + 1 file changed, 22 insertions(+) + +--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi +@@ -8,6 +8,8 @@ + + /dts-v1/; + ++#include ++#include + #include "ipq9574.dtsi" + + / { +@@ -36,6 +38,19 @@ + regulator-always-on; + regulator-name = "fixed_0p925"; + }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-0 = <&gpio_keys_default>; ++ pinctrl-names = "default"; ++ ++ button-wps { ++ label = "wps"; ++ linux,code = ; ++ gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; ++ debounce-interval = <60>; ++ }; ++ }; + }; + + &blsp1_spi0 { +@@ -95,6 +110,13 @@ + drive-strength = <8>; + bias-disable; + }; ++ ++ gpio_keys_default: gpio-keys-default-state { ++ pins = "gpio37"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-up; ++ }; + }; + + &xo_board_clk { diff --git a/target/linux/ipq95xx/patches-6.1/0039-clk-qcom-apss-ipq-pll-add-support-for-IPQ5332.patch b/target/linux/ipq95xx/patches-6.1/0039-clk-qcom-apss-ipq-pll-add-support-for-IPQ5332.patch new file mode 100644 index 00000000000000..6dba5446531841 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0039-clk-qcom-apss-ipq-pll-add-support-for-IPQ5332.patch @@ -0,0 +1,126 @@ +From 7b20271bc8c2982ab1e7bcfcf896ca5320b16a6f Mon Sep 17 00:00:00 2001 +From: Kathiravan T +Date: Fri, 17 Feb 2023 14:03:06 +0530 +Subject: [PATCH 39/41] clk: qcom: apss-ipq-pll: add support for IPQ5332 + +IPQ5332 APSS PLL is of type Stromer Plus. Add support for the same. + +To configure the stromer plus PLL separate API +(clock_stromer_pll_configure) to be used. To achieve this, introduce the +new member pll_type in device data structure and call the appropriate +function based on this. + +Reviewed-by: Konrad Dybcio +Signed-off-by: Kathiravan T +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230217083308.12017-4-quic_kathirav@quicinc.com +--- + drivers/clk/qcom/apss-ipq-pll.c | 59 ++++++++++++++++++++++++++++++++- + 1 file changed, 58 insertions(+), 1 deletion(-) + +--- a/drivers/clk/qcom/apss-ipq-pll.c ++++ b/drivers/clk/qcom/apss-ipq-pll.c +@@ -24,6 +24,18 @@ static const u8 ipq_pll_offsets[][PLL_OF + [PLL_OFF_TEST_CTL] = 0x30, + [PLL_OFF_TEST_CTL_U] = 0x34, + }, ++ ++ [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = { ++ [PLL_OFF_L_VAL] = 0x08, ++ [PLL_OFF_ALPHA_VAL] = 0x10, ++ [PLL_OFF_ALPHA_VAL_U] = 0x14, ++ [PLL_OFF_USER_CTL] = 0x18, ++ [PLL_OFF_USER_CTL_U] = 0x1c, ++ [PLL_OFF_CONFIG_CTL] = 0x20, ++ [PLL_OFF_STATUS] = 0x28, ++ [PLL_OFF_TEST_CTL] = 0x30, ++ [PLL_OFF_TEST_CTL_U] = 0x34, ++ }, + }; + + static struct clk_alpha_pll ipq_pll_huayra = { +@@ -44,6 +56,38 @@ static struct clk_alpha_pll ipq_pll_huay + }, + }; + ++static struct clk_alpha_pll ipq_pll_stromer_plus = { ++ .offset = 0x0, ++ .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], ++ .flags = SUPPORTS_DYNAMIC_UPDATE, ++ .clkr = { ++ .enable_reg = 0x0, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "a53pll", ++ .parent_data = &(const struct clk_parent_data) { ++ .fw_name = "xo", ++ }, ++ .num_parents = 1, ++ .ops = &clk_alpha_pll_stromer_ops, ++ }, ++ }, ++}; ++ ++static const struct alpha_pll_config ipq5332_pll_config = { ++ .l = 0x3e, ++ .config_ctl_val = 0x4001075b, ++ .config_ctl_hi_val = 0x304, ++ .main_output_mask = BIT(0), ++ .aux_output_mask = BIT(1), ++ .early_output_mask = BIT(3), ++ .alpha_en_mask = BIT(24), ++ .status_val = 0x3, ++ .status_mask = GENMASK(10, 8), ++ .lock_det = BIT(2), ++ .test_ctl_hi_val = 0x00400003, ++}; ++ + static const struct alpha_pll_config ipq6018_pll_config = { + .l = 0x37, + .config_ctl_val = 0x240d4828, +@@ -81,16 +125,25 @@ static const struct alpha_pll_config ipq + }; + + struct apss_pll_data { ++ int pll_type; + struct clk_alpha_pll *pll; + const struct alpha_pll_config *pll_config; + }; + ++static struct apss_pll_data ipq5332_pll_data = { ++ .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS, ++ .pll = &ipq_pll_stromer_plus, ++ .pll_config = &ipq5332_pll_config, ++}; ++ + static struct apss_pll_data ipq8074_pll_data = { ++ .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA, + .pll = &ipq_pll_huayra, + .pll_config = &ipq8074_pll_config, + }; + + static struct apss_pll_data ipq6018_pll_data = { ++ .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA, + .pll = &ipq_pll_huayra, + .pll_config = &ipq6018_pll_config, + }; +@@ -129,7 +182,10 @@ static int apss_ipq_pll_probe(struct pla + if (!data) + return -ENODEV; + +- clk_alpha_pll_configure(data->pll, regmap, data->pll_config); ++ if (data->pll_type == CLK_ALPHA_PLL_TYPE_HUAYRA) ++ clk_alpha_pll_configure(data->pll, regmap, data->pll_config); ++ else if (data->pll_type == CLK_ALPHA_PLL_TYPE_STROMER_PLUS) ++ clk_stromer_pll_configure(data->pll, regmap, data->pll_config); + + ret = devm_clk_register_regmap(dev, &data->pll->clkr); + if (ret) +@@ -140,6 +196,7 @@ static int apss_ipq_pll_probe(struct pla + } + + static const struct of_device_id apss_ipq_pll_match_table[] = { ++ { .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data }, + { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data }, + { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data }, + { .compatible = "qcom,ipq9574-a73pll", .data = &ipq9574_pll_data }, diff --git a/target/linux/ipq95xx/patches-6.1/0040-clk-qcom-apss-ipq-pll-Use-stromer-plus-ops-for-strom.patch b/target/linux/ipq95xx/patches-6.1/0040-clk-qcom-apss-ipq-pll-Use-stromer-plus-ops-for-strom.patch new file mode 100644 index 00000000000000..c405376cbc0e93 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0040-clk-qcom-apss-ipq-pll-Use-stromer-plus-ops-for-strom.patch @@ -0,0 +1,34 @@ +From 998d251c67072059c80a5747d19e8c34a154a213 Mon Sep 17 00:00:00 2001 +From: Varadarajan Narayanan +Date: Fri, 20 Oct 2023 11:49:33 +0530 +Subject: [PATCH 40/41] clk: qcom: apss-ipq-pll: Use stromer plus ops for + stromer plus pll + +The set rate and determine rate operations are different between +Stromer and Stromer Plus PLLs. Since the programming sequence is +different, the PLLs dont get configured properly and random, +inexplicable crash/freeze is seen. Hence, use stromer plus ops +for ipq_pll_stromer_plus. + +Reviewed-by: Dmitry Baryshkov +Acked-by: Stephen Boyd +Fixes: c7ef7fbb1ccf ("clk: qcom: apss-ipq-pll: add support for IPQ5332") +Signed-off-by: Kathiravan T +Signed-off-by: Varadarajan Narayanan +Link: https://lore.kernel.org/r/c86ecaa23dc4f39650bcf4a3bd54a617a932e4fd.1697781921.git.quic_varada@quicinc.com +Signed-off-by: Bjorn Andersson +--- + drivers/clk/qcom/apss-ipq-pll.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/qcom/apss-ipq-pll.c ++++ b/drivers/clk/qcom/apss-ipq-pll.c +@@ -69,7 +69,7 @@ static struct clk_alpha_pll ipq_pll_stro + .fw_name = "xo", + }, + .num_parents = 1, +- .ops = &clk_alpha_pll_stromer_ops, ++ .ops = &clk_alpha_pll_stromer_plus_ops, + }, + }, + }; diff --git a/target/linux/ipq95xx/patches-6.1/0041-clk-qcom-Add-STROMER-PLUS-PLL-type-for-IPQ5332.patch b/target/linux/ipq95xx/patches-6.1/0041-clk-qcom-Add-STROMER-PLUS-PLL-type-for-IPQ5332.patch new file mode 100644 index 00000000000000..a4674a71906208 --- /dev/null +++ b/target/linux/ipq95xx/patches-6.1/0041-clk-qcom-Add-STROMER-PLUS-PLL-type-for-IPQ5332.patch @@ -0,0 +1,48 @@ +From d10112948b0ff58b749f6f89a963185a190ce885 Mon Sep 17 00:00:00 2001 +From: Kathiravan T +Date: Tue, 7 Mar 2023 11:52:25 +0530 +Subject: [PATCH 41/41] clk: qcom: Add STROMER PLUS PLL type for IPQ5332 + +Add the support for stromer plus pll, which is found on the IPQ5332 +SoCs. Programming sequence is same as the stromer pll, so we can re-use +the same. + +Reviewed-by: Stephen Boyd +Signed-off-by: Kathiravan T +Signed-off-by: Bjorn Andersson +Link: https://lore.kernel.org/r/20230307062232.4889-3-quic_kathirav@quicinc.com +--- + drivers/clk/qcom/clk-alpha-pll.c | 11 +++++++++++ + drivers/clk/qcom/clk-alpha-pll.h | 1 + + 2 files changed, 12 insertions(+) + +--- a/drivers/clk/qcom/clk-alpha-pll.c ++++ b/drivers/clk/qcom/clk-alpha-pll.c +@@ -200,6 +200,17 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MA + [PLL_OFF_TEST_CTL_U] = 0x34, + [PLL_OFF_STATUS] = 0x28, + }, ++ [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = { ++ [PLL_OFF_L_VAL] = 0x04, ++ [PLL_OFF_USER_CTL] = 0x08, ++ [PLL_OFF_USER_CTL_U] = 0x0c, ++ [PLL_OFF_CONFIG_CTL] = 0x10, ++ [PLL_OFF_TEST_CTL] = 0x14, ++ [PLL_OFF_TEST_CTL_U] = 0x18, ++ [PLL_OFF_STATUS] = 0x1c, ++ [PLL_OFF_ALPHA_VAL] = 0x24, ++ [PLL_OFF_ALPHA_VAL_U] = 0x28, ++ }, + }; + EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); + +--- a/drivers/clk/qcom/clk-alpha-pll.h ++++ b/drivers/clk/qcom/clk-alpha-pll.h +@@ -26,6 +26,7 @@ enum { + CLK_ALPHA_PLL_TYPE_DEFAULT_EVO, + CLK_ALPHA_PLL_TYPE_BRAMMO_EVO, + CLK_ALPHA_PLL_TYPE_STROMER, ++ CLK_ALPHA_PLL_TYPE_STROMER_PLUS, + CLK_ALPHA_PLL_TYPE_MAX, + }; + diff --git a/target/linux/lantiq/patches-5.10/0001-MIPS-lantiq-add-pcie-driver.patch b/target/linux/lantiq/patches-5.10/0001-MIPS-lantiq-add-pcie-driver.patch index 9068be5d4a1066..ba07ddb1657637 100644 --- a/target/linux/lantiq/patches-5.10/0001-MIPS-lantiq-add-pcie-driver.patch +++ b/target/linux/lantiq/patches-5.10/0001-MIPS-lantiq-add-pcie-driver.patch @@ -5492,7 +5492,7 @@ Signed-off-by: John Crispin unsigned long type); --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h -@@ -1079,6 +1079,12 @@ +@@ -1080,6 +1080,12 @@ #define PCI_DEVICE_ID_SGI_IOC3 0x0003 #define PCI_DEVICE_ID_SGI_LITHIUM 0x1002 diff --git a/target/linux/lantiq/patches-5.10/0152-lantiq-VPE.patch b/target/linux/lantiq/patches-5.10/0152-lantiq-VPE.patch index 1aa0fdf1bcfc45..7d09e2df1a12b4 100644 --- a/target/linux/lantiq/patches-5.10/0152-lantiq-VPE.patch +++ b/target/linux/lantiq/patches-5.10/0152-lantiq-VPE.patch @@ -1,6 +1,6 @@ --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -2438,6 +2438,12 @@ config MIPS_VPE_LOADER +@@ -2441,6 +2441,12 @@ config MIPS_VPE_LOADER Includes a loader for loading an elf relocatable object onto another VPE and running it. diff --git a/target/linux/lantiq/patches-5.4/0030-GPIO-add-named-gpio-exports.patch b/target/linux/lantiq/patches-5.4/0030-GPIO-add-named-gpio-exports.patch index 81eed04e6fab9a..1bd5d84405b579 100644 --- a/target/linux/lantiq/patches-5.4/0030-GPIO-add-named-gpio-exports.patch +++ b/target/linux/lantiq/patches-5.4/0030-GPIO-add-named-gpio-exports.patch @@ -136,7 +136,7 @@ Signed-off-by: John Crispin { --- a/drivers/gpio/gpiolib-sysfs.c +++ b/drivers/gpio/gpiolib-sysfs.c -@@ -571,7 +571,7 @@ static struct class gpio_class = { +@@ -574,7 +574,7 @@ static struct class gpio_class = { * * Returns zero on success, else an error. */ @@ -145,7 +145,7 @@ Signed-off-by: John Crispin { struct gpio_chip *chip; struct gpio_device *gdev; -@@ -633,6 +633,8 @@ int gpiod_export(struct gpio_desc *desc, +@@ -636,6 +636,8 @@ int gpiod_export(struct gpio_desc *desc, offset = gpio_chip_hwgpio(desc); if (chip->names && chip->names[offset]) ioname = chip->names[offset]; @@ -154,7 +154,7 @@ Signed-off-by: John Crispin dev = device_create_with_groups(&gpio_class, &gdev->dev, MKDEV(0, 0), data, gpio_groups, -@@ -654,6 +656,12 @@ err_unlock: +@@ -657,6 +659,12 @@ err_unlock: gpiod_dbg(desc, "%s: status %d\n", __func__, status); return status; } diff --git a/target/linux/layerscape/patches-5.10/701-staging-add-fsl_ppfe-driver.patch b/target/linux/layerscape/patches-5.10/701-staging-add-fsl_ppfe-driver.patch index 71c86e55fd9a7d..6198fd8a4898ac 100644 --- a/target/linux/layerscape/patches-5.10/701-staging-add-fsl_ppfe-driver.patch +++ b/target/linux/layerscape/patches-5.10/701-staging-add-fsl_ppfe-driver.patch @@ -1090,7 +1090,7 @@ Date: Wed Sep 30 17:20:19 2020 +0530 +}; --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -7068,6 +7068,14 @@ F: drivers/ptp/ptp_qoriq.c +@@ -7061,6 +7061,14 @@ F: drivers/ptp/ptp_qoriq.c F: drivers/ptp/ptp_qoriq_debugfs.c F: include/linux/fsl/ptp_qoriq.h diff --git a/target/linux/mediatek/dts/mt7981b-fzs-5gcpe-p3.dts b/target/linux/mediatek/dts/mt7981b-fzs-5gcpe-p3.dts new file mode 100644 index 00000000000000..d1813a7fcdadaa --- /dev/null +++ b/target/linux/mediatek/dts/mt7981b-fzs-5gcpe-p3.dts @@ -0,0 +1,268 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include +#include + +#include "mt7981.dtsi" + +/ { + model = "FZS 5GCPE P3"; + compatible = "fzs,5gcpe-p3", "mediatek,mt7981"; + + aliases { + serial0 = &uart0; + led-boot = &led_wifi; + led-upgrade = &led_wifi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0 0x40000000 0 0x10000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "wps"; + linux,code = ; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_wifi: wifi { + label = "green:wifi"; + gpios = <&pio 15 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy1tpt"; + }; + + 4g { + label = "green:4g"; + gpios = <&pio 34 GPIO_ACTIVE_LOW>; + }; + + 5g { + label = "green:5g"; + gpios = <&pio 35 GPIO_ACTIVE_LOW>; + }; + }; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + nvmem-cells = <&macaddr_factory_2a>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; +}; + +&mdio_bus { + switch: switch@0 { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "okay"; + + spi_nand@0 { + compatible = "spi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + + spi-max-frequency = <52000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "BL2"; + reg = <0x000000 0x0100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x100000 0x0080000>; + }; + + factory: partition@180000 { + label = "Factory"; + reg = <0x180000 0x0200000>; + read-only; + }; + + partition@380000 { + label = "FIP"; + reg = <0x380000 0x0200000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x7000000>; + }; + }; + }; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "wan"; + nvmem-cells = <&macaddr_factory_24>; + nvmem-cell-names = "mac-address"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + }; + + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1_1"; + }; + }; + + uart2_pins: uart2-pins { + mux { + function = "uart"; + groups = "uart2_1"; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&xhci { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + status = "okay"; + + mediatek,mtd-eeprom = <&factory 0x0>; +}; + +&factory { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_24: macaddr@24 { + reg = <0x24 0x6>; + }; + + macaddr_factory_2a: macaddr@2a { + reg = <0x2a 0x6>; + }; +}; diff --git a/target/linux/mediatek/dts/mt7986a-jdcloud-re-cs-05.dts b/target/linux/mediatek/dts/mt7986a-jdcloud-re-cs-05.dts new file mode 100644 index 00000000000000..00b4c79c6bf8f1 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-jdcloud-re-cs-05.dts @@ -0,0 +1,281 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include +#include + +#include "mt7986a.dtsi" + +/ { + model = "JDCloud RE-CS-05"; + compatible = "jdcloud,re-cs-05", "mediatek,mt7986a"; + + aliases { + serial0 = &uart0; + led-boot = &led_status_green; + led-failsafe = &led_status_red; + led-running = &led_status_blue; + led-upgrade = &led_status_red; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "console=ttyS0,115200n8 root=PARTLABEL=rootfs rootwait"; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "wps"; + linux,code = ; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status_blue: blue { + label = "blue:status"; + gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + }; + + led_status_red: red { + label = "red:status"; + gpios = <&pio 11 GPIO_ACTIVE_HIGH>; + }; + + led_status_green: green { + label = "green:status"; + gpios = <&pio 12 GPIO_ACTIVE_LOW>; + }; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&crypto { + status = "okay"; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-handle = <&phy6>; + phy-mode = "2500base-x"; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&mdio { + phy6: ethernet-phy@6 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <6>; + reset-assert-us = <100000>; + reset-deassert-us = <100000>; + reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>; + realtek,aldps-enable; + }; + + switch: switch@0 { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@4 { + reg = <4>; + label = "lan4"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + cap-mmc-highspeed; + hs400-ds-delay = <0x14014>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + non-removable; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + status = "okay"; +}; + +&pio { + mmc0_pins_default: mmc0-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + + wf_2g_5g_pins: wf_2g_5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wmac { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wf_2g_5g_pins>; +}; diff --git a/target/linux/mediatek/dts/mt7986a-ruijie-rg-x60-pro.dts b/target/linux/mediatek/dts/mt7986a-ruijie-rg-x60-pro.dts new file mode 100644 index 00000000000000..c486d9d553deb3 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-ruijie-rg-x60-pro.dts @@ -0,0 +1,264 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +#include +#include +#include + +#include "mt7986a.dtsi" + +/ { + compatible = "ruijie,rg-x60-pro", "mediatek,mt7986a"; + model = "Ruijie RG-X60 Pro"; + + aliases { + serial0 = &uart0; + led-boot = &led_system; + led-failsafe = &led_alarm; + led-running = &led_system; + led-upgrade = &led_alarm; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlycon=uart8250,mmio32,0x11002000"; + }; + + memory { + reg = <0 0x40000000 0 0x20000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-0 { + label = "reset"; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + button-1 { + label = "mesh"; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds-gpio { + compatible = "gpio-leds"; + + led_system: led-0 { + label = "white:status"; + gpios = <&pio 22 GPIO_ACTIVE_LOW>; + }; + + led_alarm: led-1 { + label = "purple:status"; + gpios = <&pio 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-handle = <&phy7>; + phy-mode = "2500base-x"; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&mdio { + switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; + }; + + phy7: phy@7 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <7>; + reset-assert-us = <100000>; + reset-deassert-us = <100000>; + reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>; + realtek,aldps-enable; + }; +}; + +&pio { + spi_flash_pins: spi-flash-pins-33-to-38 { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <8>; + mediatek,pull-down-adv = <0>; /* bias-disable */ + }; + }; + + wf_2g_5g_pins: wf_2g_5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + + spi-max-frequency = <20000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "BL2"; + reg = <0x000000 0x100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x100000 0x80000>; + read-only; + }; + + factory: partition@180000 { + label = "Factory"; + reg = <0x180000 0x200000>; + read-only; + }; + + partition@380000 { + label = "FIP"; + reg = <0x380000 0x200000>; + read-only; + }; + + partition@580000 { + label = "product_info"; + reg = <0x580000 0x80000>; + read-only; + }; + + partition@600000 { + label = "kdump"; + reg = <0x600000 0x80000>; + read-only; + }; + + partition@680000 { + label = "ubi"; + reg = <0x680000 0x3f00000>; + }; + }; + }; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&wmac { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wf_2g_5g_pins>; + + mediatek,mtd-eeprom = <&factory 0x0>; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts new file mode 100644 index 00000000000000..98dbf8d6913ff1 --- /dev/null +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include "mt7988a-rfb-spim-nand.dtsi" +#include + +/ { + model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB"; + compatible = "mediatek,mt7988a-dsa-10g-spim-snand", + "mediatek,mt7988a-rfb-snand", + "mediatek,mt7988"; + + chosen { + bootargs = "console=ttyS0,115200n1 loglevel=8 \ + earlycon=uart8250,mmio32,0x11000000 \ + pci=pcie_bus_perf"; + }; + + memory { + reg = <0 0x40000000 0 0x40000000>; + }; +}; + +ð { + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "internal"; + + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "internal"; + phy-connection-type = "internal"; + phy = <&phy15>; + }; + + gmac2: mac@2 { + compatible = "mediatek,eth-mac"; + reg = <2>; + phy-mode = "10gbase-kr"; + phy-connection-type = "10gbase-kr"; + phy = <&phy8>; + }; + + mdio0: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + /* external Aquantia AQR113C */ + phy0: ethernet-phy@0 { + reg = <0>; + compatible = "ethernet-phy-ieee802.3-c45"; + reset-gpios = <&pio 72 1>; + reset-assert-us = <100000>; + reset-deassert-us = <221000>; + }; + + /* external Aquantia AQR113C */ + phy8: ethernet-phy@8 { + reg = <8>; + compatible = "ethernet-phy-ieee802.3-c45"; + reset-gpios = <&pio 71 1>; + reset-assert-us = <100000>; + reset-deassert-us = <221000>; + }; + + /* external Maxlinear GPY211C */ + phy5: ethernet-phy@5 { + reg = <5>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "2500base-x"; + }; + + /* external Maxlinear GPY211C */ + phy13: ethernet-phy@13 { + reg = <13>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "2500base-x"; + }; + + /* internal 2.5G PHY */ + phy15: ethernet-phy@15 { + reg = <15>; + pinctrl-names = "i2p5gbe-led"; + pinctrl-0 = <&i2p5gbe_led0_pins>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "internal"; + }; + }; +}; + +&switch { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + phy-mode = "internal"; + phy-handle = <&gsw_phy0>; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-mode = "internal"; + phy-handle = <&gsw_phy1>; + }; + + port@2 { + reg = <2>; + label = "lan2"; + phy-mode = "internal"; + phy-handle = <&gsw_phy2>; + }; + + port@3 { + reg = <3>; + label = "lan3"; + phy-mode = "internal"; + phy-handle = <&gsw_phy3>; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "internal"; + + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + gsw_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id03a2.9481"; + reg = <0>; + phy-mode = "internal"; + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe0_led0_pins>; + nvmem-cells = <&phy_calibration_p0>; + nvmem-cell-names = "phy-cal-data"; + }; + + gsw_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id03a2.9481"; + reg = <1>; + phy-mode = "internal"; + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe1_led0_pins>; + nvmem-cells = <&phy_calibration_p1>; + nvmem-cell-names = "phy-cal-data"; + }; + + gsw_phy2: ethernet-phy@2 { + compatible = "ethernet-phy-id03a2.9481"; + reg = <2>; + phy-mode = "internal"; + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe2_led0_pins>; + nvmem-cells = <&phy_calibration_p2>; + nvmem-cell-names = "phy-cal-data"; + }; + + gsw_phy3: ethernet-phy@3 { + compatible = "ethernet-phy-id03a2.9481"; + reg = <3>; + phy-mode = "internal"; + pinctrl-names = "gbe-led"; + pinctrl-0 = <&gbe3_led0_pins>; + nvmem-cells = <&phy_calibration_p3>; + nvmem-cell-names = "phy-cal-data"; + }; + }; +}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtsi new file mode 100644 index 00000000000000..e4c05712509ee4 --- /dev/null +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtsi @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include "mt7988a-rfb.dtsi" + +&pio { + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_flash_pins>; + status = "okay"; + + spi_nand: spi_nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + }; + +}; + +&spi_nand { + mediatek,nmbm; + mediatek,bmt-max-ratio = <1>; + mediatek,bmt-max-reserved-blocks = <64>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "BL2"; + reg = <0x00000 0x0100000>; + read-only; + }; + + partition@100000 { + label = "u-boot-env"; + reg = <0x0100000 0x0080000>; + }; + + factory: partition@180000 { + label = "Factory"; + reg = <0x180000 0x0400000>; + }; + + partition@580000 { + label = "FIP"; + reg = <0x580000 0x0200000>; + }; + + partition@780000 { + label = "ubi"; + reg = <0x780000 0x7080000>; + }; + }; +}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dtsi new file mode 100644 index 00000000000000..423b3860c6c64e --- /dev/null +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dtsi @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + * Author: Sam.Shih + */ + +/dts-v1/; +#include "mt7988a.dtsi" +#include + +&cpu0 { + proc-supply = <&rt5190_buck3>; +}; + +&cpu1 { + proc-supply = <&rt5190_buck3>; +}; + +&cpu2 { + proc-supply = <&rt5190_buck3>; +}; + +&cpu3 { + proc-supply = <&rt5190_buck3>; +}; + +&cci { + proc-supply = <&rt5190_buck3>; +}; + +ð { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + rt5190a_64: rt5190a@64 { + compatible = "richtek,rt5190a"; + reg = <0x64>; + /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ + vin2-supply = <&rt5190_buck1>; + vin3-supply = <&rt5190_buck1>; + vin4-supply = <&rt5190_buck1>; + + regulators { + rt5190_buck1: buck1 { + regulator-name = "rt5190a-buck1"; + regulator-min-microvolt = <5090000>; + regulator-max-microvolt = <5090000>; + regulator-allowed-modes = + ; + regulator-boot-on; + regulator-always-on; + }; + buck2 { + regulator-name = "vcore"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + rt5190_buck3: buck3 { + regulator-name = "vproc"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + }; + buck4 { + regulator-name = "rt5190a-buck4"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-allowed-modes = + ; + regulator-boot-on; + regulator-always-on; + }; + ldo { + regulator-name = "rt5190a-ldo"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "okay"; +}; + +&pcie2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_pins>; + status = "disabled"; +}; + +&pcie3 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_pins>; + status = "okay"; +}; + +&ssusb0 { + status = "okay"; +}; + +&ssusb1 { + status = "okay"; +}; + +&tphy { + status = "okay"; +}; + +&pio { + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; + groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", + "pcie_wake_n0_0"; + }; + }; + + pcie1_pins: pcie1-pins { + mux { + function = "pcie"; + groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", + "pcie_wake_n1_0"; + }; + }; + + pcie2_pins: pcie2-pins { + mux { + function = "pcie"; + groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", + "pcie_wake_n2_0"; + }; + }; + + pcie3_pins: pcie3-pins { + mux { + function = "pcie"; + groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", + "pcie_wake_n3_0"; + }; + }; +}; + +&spi0 { + status = "disabled"; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&xphy { + status = "okay"; +}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi new file mode 100644 index 00000000000000..13ad39500d1b93 --- /dev/null +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -0,0 +1,853 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Sam.Shih + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible = "mediatek,mt7988"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + clk40m: oscillator@0 { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + clock-output-names = "clkxtal"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + enable-method = "psci"; + reg = <0x0>; + clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + mediatek,cci = <&cci>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + enable-method = "psci"; + reg = <0x1>; + clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + mediatek,cci = <&cci>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + enable-method = "psci"; + reg = <0x2>; + clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + mediatek,cci = <&cci>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + enable-method = "psci"; + reg = <0x3>; + clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; + mediatek,cci = <&cci>; + }; + + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + opp00 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <850000>; + }; + opp01 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <850000>; + }; + opp02 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <850000>; + }; + opp03 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <900000>; + }; + }; + }; + + cci: cci { + compatible = "mediatek,mt7988-cci", + "mediatek,mt8183-cci"; + clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, + <&topckgen CLK_TOP_XTAL>; + clock-names = "cci", "intermediate"; + operating-points-v2 = <&cci_opp>; + }; + + cci_opp: opp_table_cci { + compatible = "operating-points-v2"; + opp-shared; + opp00 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <850000>; + }; + opp01 { + opp-hz = /bits/ 64 <660000000>; + opp-microvolt = <850000>; + }; + opp02 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <850000>; + }; + opp03 { + opp-hz = /bits/ 64 <1080000000>; + opp-microvolt = <900000>; + }; + }; + + pmu { + compatible = "arm,cortex-a73-pmu"; + interrupt-parent = <&gic>; + interrupt = ; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x30000>; + no-map; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c080000 0 0x200000>, /* GICR */ + <0 0x0c400000 0 0x2000>, /* GICC */ + <0 0x0c410000 0 0x1000>, /* GICH */ + <0 0x0c420000 0 0x2000>; /* GICV */ + + interrupts = ; + }; + + phyfw: phy-firmware@f000000 { + compatible = "mediatek,2p5gphy-fw"; + reg = <0 0x0f000000 0 0x8000>, + <0 0x0f100000 0 0x20000>, + <0 0x0f0f0000 0 0x200>; + }; + + infracfg: infracfg@10001000 { + compatible = "mediatek,mt7988-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + topckgen: topckgen@1001b000 { + compatible = "mediatek,mt7988-topckgen", "syscon"; + reg = <0 0x1001b000 0 0x1000>; + #clock-cells = <1>; + }; + + watchdog: watchdog@1001c000 { + compatible = "mediatek,mt7988-wdt", + "mediatek,mt6589-wdt", + "syscon"; + reg = <0 0x1001c000 0 0x1000>; + interrupts = ; + #reset-cells = <1>; + }; + + apmixedsys: apmixedsys@1001e000 { + compatible = "mediatek,mt7988-apmixedsys"; + reg = <0 0x1001e000 0 0x1000>; + #clock-cells = <1>; + }; + + pio: pinctrl@1001f000 { + compatible = "mediatek,mt7988-pinctrl"; + reg = <0 0x1001f000 0 0x1000>, + <0 0x11c10000 0 0x1000>, + <0 0x11d00000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11e00000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio_base", "iocfg_tr_base", + "iocfg_br_base", "iocfg_rb_base", + "iocfg_lb_base", "iocfg_tl_base", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 83>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + + mdio0_pins: mdio0-pins { + mux { + function = "eth"; + groups = "mdc_mdio0"; + }; + + conf { + groups = "mdc_mdio0"; + drive-strength = ; + }; + }; + + i2c0_pins: i2c0-pins-g0 { + mux { + function = "i2c"; + groups = "i2c0_1"; + }; + }; + + i2c1_pins: i2c1-pins-g0 { + mux { + function = "i2c"; + groups = "i2c1_0"; + }; + }; + + i2c2_pins: i2c2-pins-g0 { + mux { + function = "i2c"; + groups = "i2c2_1"; + }; + }; + + gbe0_led0_pins: gbe0-pins { + mux { + function = "led"; + groups = "gbe0_led0"; + }; + }; + + gbe1_led0_pins: gbe1-pins { + mux { + function = "led"; + groups = "gbe1_led0"; + }; + }; + + gbe2_led0_pins: gbe2-pins { + mux { + function = "led"; + groups = "gbe2_led0"; + }; + }; + + gbe3_led0_pins: gbe3-pins { + mux { + function = "led"; + groups = "gbe3_led0"; + }; + }; + + i2p5gbe_led0_pins: 2p5gbe-pins { + mux { + function = "led"; + groups = "2p5gbe_led0"; + }; + }; + }; + + boottrap: boottrap@1001f6f0 { + compatible = "mediatek,boottrap"; + reg = <0 0x1001f6f0 0 0x4>; + }; + + sgmiisys0: syscon@10060000 { + compatible = "mediatek,mt7988-sgmiisys", + "mediatek,mt7988-sgmiisys_0", + "syscon"; + reg = <0 0x10060000 0 0x1000>; + #clock-cells = <1>; + }; + + sgmiisys1: syscon@10070000 { + compatible = "mediatek,mt7988-sgmiisys", + "mediatek,mt7988-sgmiisys_1", + "syscon"; + reg = <0 0x10070000 0 0x1000>; + #clock-cells = <1>; + }; + + usxgmiisys0: usxgmiisys@10080000 { + compatible = "mediatek,mt7988-usxgmiisys", + "mediatek,mt7988-usxgmiisys_0", + "syscon"; + reg = <0 0x10080000 0 0x1000>; + #clock-cells = <1>; + }; + + usxgmiisys1: usxgmiisys@10081000 { + compatible = "mediatek,mt7988-usxgmiisys", + "mediatek,mt7988-usxgmiisys_1", + "syscon"; + reg = <0 0x10081000 0 0x1000>; + #clock-cells = <1>; + }; + + xfi_pextp0: xfi_pextp@11f20000 { + compatible = "mediatek,mt7988-xfi_pextp", + "mediatek,mt7988-xfi_pextp_0", + "syscon"; + reg = <0 0x11f20000 0 0x10000>; + #clock-cells = <1>; + }; + + xfi_pextp1: xfi_pextp@11f30000 { + compatible = "mediatek,mt7988-xfi_pextp", + "mediatek,mt7988-xfi_pextp_1", + "syscon"; + reg = <0 0x11f30000 0 0x10000>; + #clock-cells = <1>; + }; + + xfi_pll: xfi_pll@11f40000 { + compatible = "mediatek,mt7988-xfi_pll", "syscon"; + reg = <0 0x11f40000 0 0x1000>; + #clock-cells = <1>; + }; + + mcusys: mcusys@100e0000 { + compatible = "mediatek,mt7988-mcusys", "syscon"; + reg = <0 0x100e0000 0 0x1000>; + #clock-cells = <1>; + }; + + uart0: serial@11000000 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11000000 0 0x100>; + interrupts = ; + /* + * 8250-mtk driver don't control "baud" clock since commit + * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks + * still need to be passed to the driver to prevent probe fail + */ + clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_52M_UART0_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_MUX_UART0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, + <&topckgen CLK_TOP_UART_SEL>; + status = "disabled"; + }; + + i2c0: i2c@11003000 { + compatible = "mediatek,mt7988-i2c", + "mediatek,mt7981-i2c"; + reg = <0 0x11003000 0 0x1000>, + <0 0x10217080 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_INFRA_I2C_BCK>, + <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11004000 { + compatible = "mediatek,mt7988-i2c", + "mediatek,mt7981-i2c"; + reg = <0 0x11004000 0 0x1000>, + <0 0x10217100 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_INFRA_I2C_BCK>, + <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11005000 { + compatible = "mediatek,mt7988-i2c", + "mediatek,mt7981-i2c"; + reg = <0 0x11005000 0 0x1000>, + <0 0x10217180 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_INFRA_I2C_BCK>, + <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@11007000 { + compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm"; + reg = <0 0x11007000 0 0x100>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MPLL_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_104M_SPI0>, + <&infracfg CLK_INFRA_66M_SPI0_HCK>; + clock-names = "parent-clk", "sel-clk", "spi-clk", + "spi-hclk"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + pcie2: pcie@11280000 { + compatible = "mediatek,mt7988-pcie", + "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x11280000 0 0x2000>; + reg-names = "pcie-mac"; + linux,pci-domain = <3>; + interrupts = ; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0x00 0x20000000 0x00 + 0x20000000 0x00 0x00200000>, + <0x82000000 0x00 0x20200000 0x00 + 0x20200000 0x00 0x07e00000>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P2>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m"; + status = "disabled"; + + phys = <&xphyu3port0 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc2 0>, + <0 0 0 2 &pcie_intc2 1>, + <0 0 0 3 &pcie_intc2 2>, + <0 0 0 4 &pcie_intc2 3>; + pcie_intc2: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie3: pcie@11290000 { + compatible = "mediatek,mt7988-pcie", + "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x11290000 0 0x2000>; + reg-names = "pcie-mac"; + linux,pci-domain = <2>; + interrupts = ; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0x00 0x28000000 0x00 + 0x28000000 0x00 0x00200000>, + <0x82000000 0x00 0x28200000 0x00 + 0x28200000 0x00 0x07e00000>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P3>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m"; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc3 0>, + <0 0 0 2 &pcie_intc3 1>, + <0 0 0 3 &pcie_intc3 2>, + <0 0 0 4 &pcie_intc3 3>; + pcie_intc3: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie0: pcie@11300000 { + compatible = "mediatek,mt7988-pcie", + "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x11300000 0 0x2000>; + reg-names = "pcie-mac"; + linux,pci-domain = <0>; + interrupts = ; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0x00 0x30000000 0x00 + 0x30000000 0x00 0x00200000>, + <0x82000000 0x00 0x30200000 0x00 + 0x30200000 0x00 0x07e00000>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P0>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m"; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie1: pcie@11310000 { + compatible = "mediatek,mt7988-pcie", + "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x11310000 0 0x2000>; + reg-names = "pcie-mac"; + linux,pci-domain = <1>; + interrupts = ; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0x00 0x38000000 0x00 + 0x38000000 0x00 0x00200000>, + <0x82000000 0x00 0x38200000 0x00 + 0x38200000 0x00 0x07e00000>; + clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, + <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, + <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, + <&infracfg CLK_INFRA_133M_PCIE_CK_P1>; + clock-names = "pl_250m", "tl_26m", "peri_26m", + "top_133m"; + status = "disabled"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + ssusb0: usb@11190000 { + compatible = "mediatek,mt7988-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11190000 0 0x2e00>, + <0 0x11193e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&xphyu2port0 PHY_TYPE_USB2>, + <&xphyu3port0 PHY_TYPE_USB3>; + clocks = <&infracfg CLK_INFRA_USB_SYS>, + <&infracfg CLK_INFRA_USB_XHCI>, + <&infracfg CLK_INFRA_USB_REF>, + <&infracfg CLK_INFRA_66M_USB_HCK>, + <&infracfg CLK_INFRA_133M_USB_HCK>; + clock-names = "sys_ck", + "xhci_ck", + "ref_ck", + "mcu_ck", + "dma_ck"; + #address-cells = <2>; + #size-cells = <2>; + mediatek,p0_speed_fixup; + status = "disabled"; + }; + + ssusb1: usb@11200000 { + compatible = "mediatek,mt7988-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x2e00>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&tphyu2port0 PHY_TYPE_USB2>, + <&tphyu3port0 PHY_TYPE_USB3>; + clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>, + <&infracfg CLK_INFRA_USB_XHCI_CK_P1>, + <&infracfg CLK_INFRA_USB_CK_P1>, + <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>, + <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>; + clock-names = "sys_ck", + "xhci_ck", + "ref_ck", + "mcu_ck", + "dma_ck"; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + }; + + tphy: tphy@11c50000 { + compatible = "mediatek,mt7988", + "mediatek,generic-tphy-v2"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + tphyu2port0: usb-phy@11c50000 { + reg = <0 0x11c50000 0 0x700>; + clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>; + clock-names = "ref"; + #phy-cells = <1>; + }; + tphyu3port0: usb-phy@11c50700 { + reg = <0 0x11c50700 0 0x900>; + clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>; + clock-names = "ref"; + #phy-cells = <1>; + mediatek,usb3-pll-ssc-delta; + mediatek,usb3-pll-ssc-delta1; + }; + }; + + topmisc: topmisc@11d10000 { + compatible = "mediatek,mt7988-topmisc", "syscon", + "mediatek,mt7988-power-controller"; + reg = <0 0x11d10000 0 0x10000>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + xphy: xphy@11e10000 { + compatible = "mediatek,mt7988", + "mediatek,xsphy"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + xphyu2port0: usb-phy@11e10000 { + reg = <0 0x11e10000 0 0x400>; + clocks = <&infracfg CLK_INFRA_USB_UTMI>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + xphyu3port0: usb-phy@11e13000 { + reg = <0 0x11e13400 0 0x500>; + clocks = <&infracfg CLK_INFRA_USB_PIPE>; + clock-names = "ref"; + #phy-cells = <1>; + mediatek,syscon-type = <&topmisc 0x218 0>; + }; + }; + + efuse: efuse@11f50000 { + compatible = "mediatek,efuse"; + reg = <0 0x11f50000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + lvts_calibration: calib@918 { + reg = <0x918 0x28>; + }; + phy_calibration_p0: calib@940 { + reg = <0x940 0x10>; + }; + phy_calibration_p1: calib@954 { + reg = <0x954 0x10>; + }; + phy_calibration_p2: calib@968 { + reg = <0x968 0x10>; + }; + phy_calibration_p3: calib@97c { + reg = <0x97c 0x10>; + }; + cpufreq_calibration: calib@278 { + reg = <0x278 0x1>; + }; + }; + + ethsys: syscon@15000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt7988-ethsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + switch: switch@15020000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt7988-switch"; + reg = <0 0x15020000 0 0x8000>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + resets = <ðrst 0>; + }; + + ethwarp: syscon@15031000 { + compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd"; + reg = <0 0x15031000 0 0x1000>; + #clock-cells = <1>; + + ethrst: reset-controller { + compatible = "ti,syscon-reset"; + #reset-cells = <1>; + ti,reset-bits = < + 0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE) + >; + }; + }; + + eth: ethernet@15100000 { + compatible = "mediatek,mt7988-eth"; + reg = <0 0x15100000 0 0x80000>, + <0 0x15400000 0 0x380000>; + interrupts = , + , + , + ; + clocks = <ðsys CLK_ETHDMA_XGP1_EN>, + <ðsys CLK_ETHDMA_XGP2_EN>, + <ðsys CLK_ETHDMA_XGP3_EN>, + <ðsys CLK_ETHDMA_FE_EN>, + <ðsys CLK_ETHDMA_GP2_EN>, + <ðsys CLK_ETHDMA_GP1_EN>, + <ðsys CLK_ETHDMA_GP3_EN>, + <ðsys CLK_ETHDMA_ESW_EN>, + <ðsys CLK_ETHDMA_CRYPT0_EN>, + <&sgmiisys0 CLK_SGM0_TX_EN>, + <&sgmiisys0 CLK_SGM0_RX_EN>, + <&sgmiisys1 CLK_SGM1_TX_EN>, + <&sgmiisys1 CLK_SGM1_RX_EN>, + <ðwarp CLK_ETHWARP_WOCPU2_EN>, + <ðwarp CLK_ETHWARP_WOCPU1_EN>, + <ðwarp CLK_ETHWARP_WOCPU0_EN>, + <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, + <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, + <&topckgen CLK_TOP_SGM_0_SEL>, + <&topckgen CLK_TOP_SGM_1_SEL>, + <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>, + <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>, + <&topckgen CLK_TOP_ETH_GMII_SEL>, + <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>, + <&topckgen CLK_TOP_ETH_SYS_200M_SEL>, + <&topckgen CLK_TOP_ETH_SYS_SEL>, + <&topckgen CLK_TOP_ETH_XGMII_SEL>, + <&topckgen CLK_TOP_ETH_MII_SEL>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_500M_SEL>, + <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>, + <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>, + <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>, + <&topckgen CLK_TOP_NETSYS_WARP_SEL>; + clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1", + "gp3", "esw", "crypto", "sgmii_tx250m", + "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m", + "ethwarp_wocpu2", "ethwarp_wocpu1", + "ethwarp_wocpu0", "top_usxgmii0_sel", + "top_usxgmii1_sel", "top_sgm0_sel", + "top_sgm1_sel", "top_xfi_phy0_xtal_sel", + "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel", + "top_eth_refck_50m_sel", "top_eth_sys_200m_sel", + "top_eth_sys_sel", "top_eth_xgmii_sel", + "top_eth_mii_sel", "top_netsys_sel", + "top_netsys_500m_sel", "top_netsys_pao_2x_sel", + "top_netsys_sync_250m_sel", + "top_netsys_ppefb_250m_sel", + "top_netsys_warp_sel"; + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_NETSYS_GSW_SEL>, + <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, + <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, + <&topckgen CLK_TOP_SGM_0_SEL>, + <&topckgen CLK_TOP_SGM_1_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, + <&topckgen CLK_TOP_NET1PLL_D4>, + <&topckgen CLK_TOP_NET1PLL_D8_D4>, + <&topckgen CLK_TOP_NET1PLL_D8_D4>, + <&apmixedsys CLK_APMIXED_SGMPLL>, + <&apmixedsys CLK_APMIXED_SGMPLL>; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; + mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>; + mediatek,xfi_pextp = <&xfi_pextp0>, <&xfi_pextp1>; + mediatek,xfi_pll = <&xfi_pll>; + mediatek,infracfg = <&topmisc>; + mediatek,toprgu = <&watchdog>; + #reset-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; +}; diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-apmixed.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-apmixed.c new file mode 100644 index 00000000000000..587b70767eb21e --- /dev/null +++ b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-apmixed.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 MediaTek Inc. + * Author: Sam Shih + * Author: Xiufeng Li + */ + +#include +#include +#include +#include +#include +#include "clk-mtk.h" +#include "clk-gate.h" +#include "clk-mux.h" +#include + +#define MT7988_PLL_FMAX (2500UL * MHZ) +#define MT7988_PCW_CHG_SHIFT 2 + +#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \ + _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ + _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, \ + _div_table) \ + { \ + .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, .flags = _flags, \ + .rst_bar_mask = BIT(_rst_bar_mask), .fmax = MT7988_PLL_FMAX, \ + .pcwbits = _pcwbits, .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, .tuner_reg = _tuner_reg, \ + .tuner_en_reg = _tuner_en_reg, .tuner_en_bit = _tuner_en_bit, \ + .pcw_reg = _pcw_reg, .pcw_shift = _pcw_shift, \ + .pcw_chg_reg = _pcw_chg_reg, \ + .pcw_chg_shift = MT7988_PCW_CHG_SHIFT, \ + .div_table = _div_table, .parent_name = "clkxtal", \ + } + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \ + _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ + _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg) \ + PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \ + _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ + _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, NULL) + +static const struct mtk_pll_data plls[] = { + PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, + 0, 32, 0x0104, 4, 0, 0, 0, 0x0108, 0, 0x0104), + PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR, + 23, 32, 0x0114, 4, 0, 0, 0, 0x0118, 0, 0x0114), + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, + HAVE_RST_BAR, 23, 32, 0x0124, 4, 0, 0, 0, 0x0128, 0, 0x0124), + PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, + 0x0134, 4, 0x0704, 0x0700, 1, 0x0138, 0, 0x0134), + PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001, + HAVE_RST_BAR, 23, 32, 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144), + PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001, + (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0154, 4, 0, 0, 0, 0x0158, 0, + 0x0154), + PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0, + 0, 32, 0x0164, 4, 0, 0, 0, 0x0168, 0, 0x0164), + PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32, + 0x0174, 4, 0, 0, 0, 0x0178, 0, 0x0174), + PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001, + (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0204, 4, 0, 0, 0, 0x0208, 0, + 0x0204), + PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001, + HAVE_RST_BAR, 23, 32, 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214), + PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001, + HAVE_RST_BAR, 23, 32, 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304), + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0, + 32, 0x0314, 4, 0, 0, 0, 0x0318, 0, 0x0314), +}; + +static const struct of_device_id of_match_clk_mt7988_apmixed[] = { + { + .compatible = "mediatek,mt7988-apmixedsys", + }, + {} +}; + +static int clk_mt7988_apmixed_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); + if (!clk_data) + return -ENOMEM; + + mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) { + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + goto free_apmixed_data; + } + return r; + +free_apmixed_data: + mtk_free_clk_data(clk_data); + return r; +} + +static struct platform_driver clk_mt7988_apmixed_drv = { + .probe = clk_mt7988_apmixed_probe, + .driver = { + .name = "clk-mt7988-apmixed", + .of_match_table = of_match_clk_mt7988_apmixed, + }, +}; +builtin_platform_driver(clk_mt7988_apmixed_drv); diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-eth.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-eth.c new file mode 100644 index 00000000000000..341d0f73fd3080 --- /dev/null +++ b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-eth.c @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 MediaTek Inc. + * Author: Sam Shih + * Author: Xiufeng Li + */ + +#include +#include +#include +#include +#include +#include "clk-mtk.h" +#include "clk-gate.h" +#include + +static const struct mtk_gate_regs ethdma_cg_regs = { + .set_ofs = 0x30, + .clr_ofs = 0x30, + .sta_ofs = 0x30, +}; + +#define GATE_ETHDMA(_id, _name, _parent, _shift) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = ðdma_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr_inv, \ + } + +static const struct mtk_gate ethdma_clks[] = { + GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0), + GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1), + GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2), + GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6), + GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7), + GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8), + GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10), + GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16), + GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel", + 29), +}; + +static int clk_mt7988_ethsys_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + void __iomem *base; + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s(): ioremap failed\n", __func__); + return -ENOMEM; + } + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(ethdma_clks)); + + if (!clk_data) + return -ENOMEM; + + mtk_clk_register_gates(node, ethdma_clks, ARRAY_SIZE(ethdma_clks), + clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) { + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + goto free_data; + } + return r; + +free_data: + mtk_free_clk_data(clk_data); + return r; +} + +static const struct mtk_gate_regs sgmii0_cg_regs = { + .set_ofs = 0xe4, + .clr_ofs = 0xe4, + .sta_ofs = 0xe4, +}; + +#define GATE_SGMII0(_id, _name, _parent, _shift) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = &sgmii0_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr_inv, \ + } + +static const struct mtk_gate sgmii0_clks[] = { + GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2), + GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3), +}; + +static int clk_mt7988_sgmii0_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + void __iomem *base; + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s(): ioremap failed\n", __func__); + return -ENOMEM; + } + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks)); + + if (!clk_data) + return -ENOMEM; + + mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks), + clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) { + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + goto free_data; + } + return r; + +free_data: + mtk_free_clk_data(clk_data); + return r; +} + +static const struct mtk_gate_regs sgmii1_cg_regs = { + .set_ofs = 0xe4, + .clr_ofs = 0xe4, + .sta_ofs = 0xe4, +}; + +#define GATE_SGMII1(_id, _name, _parent, _shift) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = &sgmii1_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr_inv, \ + } + +static const struct mtk_gate sgmii1_clks[] = { + GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2), + GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3), +}; + +static int clk_mt7988_sgmii1_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + void __iomem *base; + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s(): ioremap failed\n", __func__); + return -ENOMEM; + } + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks)); + + if (!clk_data) + return -ENOMEM; + + mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks), + clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) { + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + goto free_data; + } + return r; + +free_data: + mtk_free_clk_data(clk_data); + return r; +} + +static const struct mtk_gate_regs ethwarp_cg_regs = { + .set_ofs = 0x14, + .clr_ofs = 0x14, + .sta_ofs = 0x14, +}; + +#define GATE_ETHWARP(_id, _name, _parent, _shift) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = ðwarp_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_no_setclr_inv, \ + } + +static const struct mtk_gate ethwarp_clks[] = { + GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en", + "netsys_mcu_sel", 13), + GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en", + "netsys_mcu_sel", 14), + GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en", + "netsys_mcu_sel", 15), +}; + +static int clk_mt7988_ethwarp_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + void __iomem *base; + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s(): ioremap failed\n", __func__); + return -ENOMEM; + } + + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(ethwarp_clks)); + + if (!clk_data) + return -ENOMEM; + + mtk_clk_register_gates(node, ethwarp_clks, ARRAY_SIZE(ethwarp_clks), + clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) { + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + goto free_data; + } + return r; + +free_data: + mtk_free_clk_data(clk_data); + return r; +} + +static const struct of_device_id of_match_clk_mt7988_ethsys[] = { + { + .compatible = "mediatek,mt7988-ethsys", + }, + {} +}; + +static struct platform_driver clk_mt7988_ethsys_drv = { + .probe = clk_mt7988_ethsys_probe, + .driver = { + .name = "clk-mt7988-ethsys", + .of_match_table = of_match_clk_mt7988_ethsys, + }, +}; +builtin_platform_driver(clk_mt7988_ethsys_drv); + +static const struct of_device_id of_match_clk_mt7988_sgmii0[] = { + { + .compatible = "mediatek,mt7988-sgmiisys_0", + }, + {} +}; + +static struct platform_driver clk_mt7988_sgmii0_drv = { + .probe = clk_mt7988_sgmii0_probe, + .driver = { + .name = "clk-mt7988-sgmiisys_0", + .of_match_table = of_match_clk_mt7988_sgmii0, + }, +}; +builtin_platform_driver(clk_mt7988_sgmii0_drv); + +static const struct of_device_id of_match_clk_mt7988_sgmii1[] = { + { + .compatible = "mediatek,mt7988-sgmiisys_1", + }, + {} +}; + +static struct platform_driver clk_mt7988_sgmii1_drv = { + .probe = clk_mt7988_sgmii1_probe, + .driver = { + .name = "clk-mt7988-sgmiisys_1", + .of_match_table = of_match_clk_mt7988_sgmii1, + }, +}; +builtin_platform_driver(clk_mt7988_sgmii1_drv); + +static const struct of_device_id of_match_clk_mt7988_ethwarp[] = { + { + .compatible = "mediatek,mt7988-ethwarp", + }, + {} +}; + +static struct platform_driver clk_mt7988_ethwarp_drv = { + .probe = clk_mt7988_ethwarp_probe, + .driver = { + .name = "clk-mt7988-ethwarp", + .of_match_table = of_match_clk_mt7988_ethwarp, + }, +}; +builtin_platform_driver(clk_mt7988_ethwarp_drv); \ No newline at end of file diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-infracfg.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-infracfg.c new file mode 100644 index 00000000000000..77e25383b6e3c1 --- /dev/null +++ b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-infracfg.c @@ -0,0 +1,399 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 MediaTek Inc. + * Author: Sam Shih + * Author: Xiufeng Li + */ + +#include +#include +#include +#include +#include +#include "clk-mtk.h" +#include "clk-gate.h" +#include "clk-mux.h" +#include + +static DEFINE_SPINLOCK(mt7988_clk_lock); + +static const char *const infra_mux_uart0_parents[] __initconst = { + "csw_infra_f26m_sel", "uart_sel" +}; + +static const char *const infra_mux_uart1_parents[] __initconst = { + "csw_infra_f26m_sel", "uart_sel" +}; + +static const char *const infra_mux_uart2_parents[] __initconst = { + "csw_infra_f26m_sel", "uart_sel" +}; + +static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel", + "spi_sel" }; + +static const char *const infra_mux_spi1_parents[] __initconst = { + "i2c_sel", "spim_mst_sel" +}; + +static const char *const infra_pwm_bck_parents[] __initconst = { + "top_rtc_32p7k", "csw_infra_f26m_sel", "sysaxi_sel", "pwm_sel" +}; + +static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = { + "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", + "pextp_tl_sel" +}; + +static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = { + "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", + "pextp_tl_p1_sel" +}; + +static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = { + "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", + "pextp_tl_p2_sel" +}; + +static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = { + "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", + "pextp_tl_p3_sel" +}; + +static const struct mtk_mux infra_muxes[] = { + /* MODULE_CLK_SEL_0 */ + MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel", + infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, + 0, 1, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel", + infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, + 1, 1, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel", + infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, + 2, 1, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", + infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 4, + 1, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", + infra_mux_spi1_parents, 0x0018, 0x0010, 0x0014, 5, + 1, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", + infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 6, + 1, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", + infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 14, + 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", + infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 16, + 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", + infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 18, + 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", + infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 20, + 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", + infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 22, + 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", + infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 24, + 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", + infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 26, + 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", + infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 28, + 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", + infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 30, + 2, -1, -1, -1), + /* MODULE_CLK_SEL_1 */ + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, + "infra_pcie_gfmux_tl_o_p0_sel", + infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, + 0x0020, 0x0024, 0, 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, + "infra_pcie_gfmux_tl_o_p1_sel", + infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, + 0x0020, 0x0024, 2, 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, + "infra_pcie_gfmux_tl_o_p2_sel", + infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028, + 0x0020, 0x0024, 4, 2, -1, -1, -1), + MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, + "infra_pcie_gfmux_tl_o_p3_sel", + infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028, + 0x0020, 0x0024, 6, 2, -1, -1, -1), +}; + +static const struct mtk_gate_regs infra0_cg_regs = { + .set_ofs = 0x10, + .clr_ofs = 0x14, + .sta_ofs = 0x18, +}; + +static const struct mtk_gate_regs infra1_cg_regs = { + .set_ofs = 0x40, + .clr_ofs = 0x44, + .sta_ofs = 0x48, +}; + +static const struct mtk_gate_regs infra2_cg_regs = { + .set_ofs = 0x50, + .clr_ofs = 0x54, + .sta_ofs = 0x58, +}; + +static const struct mtk_gate_regs infra3_cg_regs = { + .set_ofs = 0x60, + .clr_ofs = 0x64, + .sta_ofs = 0x68, +}; + +#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = &infra0_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \ + } + +#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = &infra1_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \ + } + +#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = &infra2_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \ + } + +#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags) \ + { \ + .id = _id, .name = _name, .parent_name = _parent, \ + .regs = &infra3_cg_regs, .shift = _shift, \ + .ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \ + } + +#define GATE_INFRA0(_id, _name, _parent, _shift) \ + GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0) + +#define GATE_INFRA1(_id, _name, _parent, _shift) \ + GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0) + +#define GATE_INFRA2(_id, _name, _parent, _shift) \ + GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0) + +#define GATE_INFRA3(_id, _name, _parent, _shift) \ + GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0) + +static const struct mtk_gate infra_clks[] = { + /* INFRA0 */ + GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0, + "infra_pcie_peri_ck_26m_ck_p0", "csw_infra_f26m_sel", 7), + GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, + "infra_pcie_peri_ck_26m_ck_p1", "csw_infra_f26m_sel", 8), + GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, + "infra_pcie_peri_ck_26m_ck_p2", "csw_infra_f26m_sel", 9), + GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, + "infra_pcie_peri_ck_26m_ck_p3", "csw_infra_f26m_sel", 10), + /* INFRA1 */ + GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", + "sysaxi_sel", 0), + GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", + "sysaxi_sel", 1), + GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", + "infra_pwm_sel", 2), + GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1", + "infra_pwm_ck1_sel", 3), + GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2", + "infra_pwm_ck2_sel", 4), + GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3", + "infra_pwm_ck3_sel", 5), + GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4", + "infra_pwm_ck4_sel", 6), + GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5", + "infra_pwm_ck5_sel", 7), + GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6", + "infra_pwm_ck6_sel", 8), + GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7", + "infra_pwm_ck7_sel", 9), + GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8", + "infra_pwm_ck8_sel", 10), + GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", + "sysaxi_sel", 12), + GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", + "sysaxi_sel", 13), + GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m", + "csw_infra_f26m_sel", 14), + GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15), + GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16), + GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18), + GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", + "csw_infra_f26m_sel", 19, CLK_IS_CRITICAL), + // JTAG + GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", + "sysaxi_sel", 20, CLK_IS_CRITICAL), + GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", + "sysaxi_sel", 21), + GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", + "sysaxi_sel", 29), + GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", + "csw_infra_f26m_sel", 30), + /* INFRA2 */ + GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", + "csw_infra_f26m_sel", 0), + GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1), + GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", + "infra_mux_uart0_sel", 3), + GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", + "infra_mux_uart1_sel", 4), + GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", + "infra_mux_uart2_sel", 5), + GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9), + GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10), + GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", + "sysaxi_sel", 11, CLK_IS_CRITICAL), + GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", + "infra_mux_spi0_sel", 12, CLK_IS_CRITICAL), + GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", + "infra_mux_spi1_sel", 13), + GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", + "infra_mux_spi2_sel", 14), + GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", + "sysaxi_sel", 15, CLK_IS_CRITICAL), + GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", + "sysaxi_sel", 16), + GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", + "sysaxi_sel", 17), + GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", + "sysaxi_sel", 18), + GATE_INFRA2(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", 19), + GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", + "csw_infra_f26m_sel", 20), + GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck", + 21), + GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel", + 22), + GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel", + 23), + GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", + "sysaxi_sel", 24), + GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", + "sysaxi_sel", 25), + GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", + "sysaxi_sel", 26), + GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27), + GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1, + "infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29), + GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1, + "infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31), + /* INFRA3 */ + GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel", + 0), + GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", + "sysaxi_sel", 1), + GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel", + 2), + GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", + "sysaxi_sel", 3), + GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4), + GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", + "usb_sys_p1_sel", 5), + GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6), + GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7), + GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", + "usb_frmcnt_sel", 8, CLK_IS_CRITICAL), + GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", + "usb_frmcnt_p1_sel", 9, CLK_IS_CRITICAL), + GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10), + GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", + "usb_phy_sel", 11), + GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12), + GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", + "top_xtal", 13), + GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14), + GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", + "usb_xhci_p1_sel", 15), + GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0", + "infra_pcie_gfmux_tl_o_p0_sel", 20), + GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1", + "infra_pcie_gfmux_tl_o_p1_sel", 21), + GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2", + "infra_pcie_gfmux_tl_o_p2_sel", 22), + GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3", + "infra_pcie_gfmux_tl_o_p3_sel", 23), + GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", + "top_xtal", 24), + GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", + "top_xtal", 25), + GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", + "top_xtal", 26), + GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", + "top_xtal", 27), + GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", + "sysaxi_sel", 28), + GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", + "sysaxi_sel", 29), + GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2", + "sysaxi_sel", 30), + GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", + "sysaxi_sel", 31), +}; + +static int clk_mt7988_infracfg_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + void __iomem *base; + int nr = ARRAY_SIZE(infra_muxes) + ARRAY_SIZE(infra_clks); + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s(): ioremap failed\n", __func__); + return -ENOMEM; + } + + clk_data = mtk_alloc_clk_data(nr); + + if (!clk_data) + return -ENOMEM; + + mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node, + &mt7988_clk_lock, clk_data); + + mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), + clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + if (r) { + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + goto free_infracfg_data; + } + return r; + +free_infracfg_data: + mtk_free_clk_data(clk_data); + return r; +} + +static const struct of_device_id of_match_clk_mt7988_infracfg[] = { + { + .compatible = "mediatek,mt7988-infracfg", + }, + {} +}; + +static struct platform_driver clk_mt7988_infracfg_drv = { + .probe = clk_mt7988_infracfg_probe, + .driver = { + .name = "clk-mt7988-infracfg", + .of_match_table = of_match_clk_mt7988_infracfg, + }, +}; +builtin_platform_driver(clk_mt7988_infracfg_drv); diff --git a/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-topckgen.c b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-topckgen.c new file mode 100644 index 00000000000000..917302b6df682a --- /dev/null +++ b/target/linux/mediatek/files-5.15/drivers/clk/mediatek/clk-mt7988-topckgen.c @@ -0,0 +1,522 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 MediaTek Inc. + * Author: Sam Shih + * Author: Xiufeng Li + */ + +#include +#include +#include +#include +#include +#include "clk-mtk.h" +#include "clk-gate.h" +#include "clk-mux.h" +#include + +static DEFINE_SPINLOCK(mt7988_clk_lock); + +static const struct mtk_fixed_clk top_fixed_clks[] = { + FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000), +}; + +static const struct mtk_fixed_factor top_divs[] = { + FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2), + FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250), + FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220), + FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2), + FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2), + FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4), + FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8), + FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16), + FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), + FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15), + FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4), + FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12), + FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8), + FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), + FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4), + FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5), + FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10), + FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20), + FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8), + FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16), + FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32), + FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64), + FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128), + FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2), + FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4), + FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16), + FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32), + FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6), + FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8), +}; + +static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2", + "mmpll_d2" }; + +static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5", + "net1pll_d5_d2" }; + +static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll", + "mmpll" }; + +static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4", + "net1pll_d5" }; + +static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" }; + +static const char *const netsys_mcu_parents[] = { "top_xtal", "net2pll", + "mmpll", "net1pll_d4", + "net1pll_d5", "mpll" }; + +static const char *const eip197_parents[] = { "top_xtal", "netsyspll", + "net2pll", "mmpll", + "net1pll_d4", "net1pll_d5" }; + +static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" }; + +static const char *const uart_parents[] = { "top_xtal", "mpll_d8", + "mpll_d8_d2" }; + +static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2", + "mmpll_d4" }; + +static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll", + "mmpll_d2", "mpll_d2", + "mmpll_d4", "net1pll_d8_d2" }; + +static const char *const spi_parents[] = { "top_xtal", "mpll_d2", + "mmpll_d4", "net1pll_d8_d2", + "net2pll_d6", "net1pll_d5_d4", + "mpll_d4", "net1pll_d8_d4" }; + +static const char *const nfi1x_parents[] = { "top_xtal", "mmpll_d4", + "net1pll_d8_d2", "net2pll_d6", + "mpll_d4", "mmpll_d8", + "net1pll_d8_d4", "mpll_d8" }; + +static const char *const spinfi_parents[] = { "top_xtal_d2", "top_xtal", + "net1pll_d5_d4", "mpll_d4", + "mmpll_d8", "net1pll_d8_d4", + "mmpll_d6_d2", "mpll_d8" }; + +static const char *const pwm_parents[] = { "top_xtal", "net1pll_d8_d2", + "net1pll_d5_d4", "mpll_d4", + "mpll_d8_d2", "top_rtc_32k" }; + +static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4", + "mpll_d4", "net1pll_d8_d4" }; + +static const char *const pcie_mbist_250m_parents[] = { "top_xtal", + "net1pll_d5_d2" }; + +static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6", + "mmpll_d8", "mpll_d8_d2", + "top_rtc_32k" }; + +static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" }; + +static const char *const aud_parents[] = { "top_xtal", "apll2" }; + +static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" }; + +static const char *const aud_l_parents[] = { "top_xtal", "apll2", + "mpll_d8_d2" }; + +static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" }; + +static const char *const usxgmii_sbus_0_parents[] = { "top_xtal", + "net1pll_d8_d4" }; + +static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" }; + +static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" }; + +static const char *const eth_refck_50m_parents[] = { "top_xtal", + "net2pll_d4_d4" }; + +static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" }; + +static const char *const eth_xgmii_parents[] = { "top_xtal_d2", + "net1pll_d8_d8", + "net1pll_d8_d16" }; + +static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5", + "net2pll_d2" }; + +static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" }; + +static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2", + "wedmcupll" }; + +static const char *const da_xtp_glb_p0_parents[] = { "top_xtal", + "net2pll_d8" }; + +static const char *const mcusys_backup_625m_parents[] = { "top_xtal", + "net1pll_d4" }; + +static const char *const macsec_parents[] = { "top_xtal", "sgmpll", + "net1pll_d8" }; + +static const char *const netsys_tops_400m_parents[] = { "top_xtal", + "net2pll_d2" }; + +static const char *const eth_mii_parents[] = { "top_xtal_d2", + "net2pll_d4_d8" }; + +static const struct mtk_mux top_muxes[] = { + /* CLK_CFG_0 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, + 0x000, 0x004, 0x008, 0, 2, 7, 0x1c0, 0), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", + netsys_500m_parents, 0x000, 0x004, 0x008, 8, 2, + 15, 0x1C0, 1), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", + netsys_2x_parents, 0x000, 0x004, 0x008, 16, 2, 23, + 0x1C0, 2), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", + netsys_gsw_parents, 0x000, 0x004, 0x008, 24, 2, + 31, 0x1C0, 3), + /* CLK_CFG_1 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", + eth_gmii_parents, 0x010, 0x014, 0x018, 0, 1, 7, + 0x1C0, 4), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", + netsys_mcu_parents, 0x010, 0x014, 0x018, 8, 3, 15, + 0x1C0, 5), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel", + netsys_mcu_parents, 0x010, 0x014, 0x018, 16, 3, + 23, 0x1C0, 6), + MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, + 0x010, 0x014, 0x018, 24, 3, 31, 0x1c0, 7), + /* CLK_CFG_2 */ + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", + axi_infra_parents, 0x020, 0x024, 0x028, 0, + 1, 7, 0x1C0, 8, CLK_IS_CRITICAL), + MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020, + 0x024, 0x028, 8, 2, 15, 0x1c0, 9), + MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", + emmc_250m_parents, 0x020, 0x024, 0x028, 16, 2, 23, + 0x1C0, 10), + MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", + emmc_400m_parents, 0x020, 0x024, 0x028, 24, 3, 31, + 0x1C0, 11), + /* CLK_CFG_3 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030, + 0x034, 0x038, 0, 3, 7, 0x1c0, 12), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, + 0x030, 0x034, 0x038, 8, 3, 15, 0x1c0, 13), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, + 0x030, 0x034, 0x038, 16, 3, 23, 0x1c0, 14), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, + 0x030, 0x034, 0x038, 24, 3, 31, 0x1c0, 15), + /* CLK_CFG_4 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040, + 0x044, 0x048, 0, 3, 7, 0x1c0, 16), + MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040, + 0x044, 0x048, 8, 2, 15, 0x1c0, 17), + MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL, + "pcie_mbist_250m_sel", pcie_mbist_250m_parents, + 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18), + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel", + pextp_tl_ck_parents, 0x040, 0x044, 0x048, 24, 3, + 31, 0x1C0, 19), + /* CLK_CFG_5 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel", + pextp_tl_ck_parents, 0x050, 0x054, 0x058, 0, 3, 7, + 0x1C0, 20), + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel", + pextp_tl_ck_parents, 0x050, 0x054, 0x058, 8, 3, + 15, 0x1C0, 21), + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel", + pextp_tl_ck_parents, 0x050, 0x054, 0x058, 16, 3, + 23, 0x1C0, 22), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel", + eth_gmii_parents, 0x050, 0x054, 0x058, 24, 1, 31, + 0x1C0, 23), + /* CLK_CFG_6 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", + eth_gmii_parents, 0x060, 0x064, 0x068, 0, 1, 7, + 0x1C0, 24), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel", + eth_gmii_parents, 0x060, 0x064, 0x068, 8, 1, 15, + 0x1C0, 25), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", + eth_gmii_parents, 0x060, 0x064, 0x068, 16, 1, 23, + 0x1C0, 26), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", + usb_frmcnt_parents, 0x060, 0x064, 0x068, 24, 1, + 31, 0x1C0, 27), + /* CLK_CFG_7 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel", + usb_frmcnt_parents, 0x070, 0x074, 0x078, 0, 1, 7, + 0x1C0, 28), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070, + 0x074, 0x078, 8, 1, 15, 0x1c0, 29), + MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, + 0x070, 0x074, 0x078, 16, 1, 23, 0x1c0, 30), + MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, + 0x070, 0x074, 0x078, 24, 2, 31, 0x1c4, 0), + /* CLK_CFG_8 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, + 0x080, 0x084, 0x088, 0, 1, 7, 0x1c4, 1), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, + 0x080, 0x084, 0x088, 8, 1, 15, 0x1c4, 2), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", + sspxtp_parents, 0x080, 0x084, 0x088, 16, 1, 23, + 0x1c4, 3), + MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel", + usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24, + 1, 31, 0x1C4, 4), + /* CLK_CFG_9 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel", + usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1, + 7, 0x1C4, 5), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, + 0x090, 0x094, 0x098, 8, 1, 15, 0x1c4, 6), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", + usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, + 16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL), + MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, + 0x090, 0x094, 0x098, 24, 1, 31, 0x1c4, 8), + /* CLK_CFG_10 */ + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", + usxgmii_sbus_0_parents, 0x0a0, 0x0a4, 0x0a8, + 0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL), + MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", + sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15, + 0x1C4, 10), + MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", + sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 16, 1, 23, + 0x1C4, 11), + /* CLK_CFG_11 */ + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", + axi_infra_parents, 0x0a0, 0x0a4, 0x0a8, 24, + 1, 31, 0x1C4, 12, CLK_IS_CRITICAL), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", + sysapb_parents, 0x0b0, 0x0b4, 0x0b8, 0, 1, + 7, 0x1c4, 13, CLK_IS_CRITICAL), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", + eth_refck_50m_parents, 0x0b0, 0x0b4, 0x0b8, 8, 1, + 15, 0x1C4, 14), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", + eth_sys_200m_parents, 0x0b0, 0x0b4, 0x0b8, 16, 1, + 23, 0x1C4, 15), + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", + pcie_mbist_250m_parents, 0x0b0, 0x0b4, 0x0b8, 24, + 1, 31, 0x1C4, 16), + /* CLK_CFG_12 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", + eth_xgmii_parents, 0x0c0, 0x0c4, 0x0c8, 0, 2, 7, + 0x1C4, 17), + MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel", + bus_tops_parents, 0x0c0, 0x0c4, 0x0c8, 8, 2, 15, + 0x1C4, 18), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel", + npu_tops_parents, 0x0c0, 0x0c4, 0x0c8, 16, 1, 23, + 0x1C4, 19), + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", + sspxtp_parents, 0x0c0, 0x0c4, 0x0c8, 24, 1, + 31, 0x1C4, 20, CLK_IS_CRITICAL), + /* CLK_CFG_13 */ + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", + dramc_md32_parents, 0x0d0, 0x0d4, 0x0d8, 0, + 2, 7, 0x1C4, 21, CLK_IS_CRITICAL), + MUX_GATE_CLR_SET_UPD_FLAGS( + CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents, + 0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL), + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", + sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 16, 1, 23, + 0x1C4, 23), + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", + sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 24, 1, 31, + 0x1C4, 24), + /* CLK_CFG_14 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", + sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7, + 0x1C4, 25), + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", + sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15, + 0x1C4, 26), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", + da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 16, 1, + 23, 0x1C4, 27), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", + da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 24, 1, + 31, 0x1C4, 28), + /* CLK_CFG_15 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel", + da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 0, 1, + 7, 0x1C4, 29), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel", + da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 8, 1, + 15, 0x1C4, 30), + MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0, + 0x0f4, 0x0f8, 16, 1, 23, 0x1c8, 0), + MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0, + 0x0f4, 0x0f8, 24, 1, 31, 0x1C8, 1), + /* CLK_CFG_16 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, + 0x0100, 0x104, 0x108, 0, 1, 7, 0x1c8, 2), + MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", + sspxtp_parents, 0x0100, 0x104, 0x108, 8, 1, 15, + 0x1C8, 3), + MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL, + "mcusys_backup_625m_sel", + mcusys_backup_625m_parents, 0x0100, 0x104, 0x108, + 16, 1, 23, 0x1C8, 4), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL, + "netsys_sync_250m_sel", pcie_mbist_250m_parents, + 0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5), + /* CLK_CFG_17 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, + 0x0110, 0x114, 0x118, 0, 2, 7, 0x1c8, 6), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL, + "netsys_tops_400m_sel", netsys_tops_400m_parents, + 0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL, + "netsys_ppefb_250m_sel", pcie_mbist_250m_parents, + 0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", + netsys_parents, 0x0110, 0x114, 0x118, 24, 2, 31, + 0x1C8, 9), + /* CLK_CFG_18 */ + MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", + eth_mii_parents, 0x0120, 0x124, 0x128, 0, 1, 7, + 0x1c8, 10), + MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents, + 0x0120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11), +}; + +static const struct mtk_composite top_aud_divs[] = { + DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420, + 8, 8), +}; + +static int clk_mt7988_topckgen_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + void __iomem *base; + int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) + + ARRAY_SIZE(top_muxes) + ARRAY_SIZE(top_aud_divs); + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s(): ioremap failed\n", __func__); + return -ENOMEM; + } + + clk_data = mtk_alloc_clk_data(nr); + if (!clk_data) + return -ENOMEM; + + mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), + clk_data); + + mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); + + mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, + &mt7988_clk_lock, clk_data); + + mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), + base, &mt7988_clk_lock, clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + + if (r) { + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + goto free_topckgen_data; + } + return r; + +free_topckgen_data: + mtk_free_clk_data(clk_data); + return r; +} + +static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b", + "net1pll_d4" }; + +static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b", + "net1pll_d4" }; + +static struct mtk_composite mcu_muxes[] = { + /* bus_pll_divider_cfg */ + MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel", + mcu_bus_div_parents, 0x7C0, 9, 2, -1, CLK_IS_CRITICAL), + /* mp2_pll_divider_cfg */ + MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel", + mcu_arm_div_parents, 0x7A8, 9, 2, -1, CLK_IS_CRITICAL), +}; + +static int clk_mt7988_mcusys_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + void __iomem *base; + int nr = ARRAY_SIZE(mcu_muxes); + + base = of_iomap(node, 0); + if (!base) { + pr_err("%s(): ioremap failed\n", __func__); + return -ENOMEM; + } + + clk_data = mtk_alloc_clk_data(nr); + if (!clk_data) + return -ENOMEM; + + mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base, + &mt7988_clk_lock, clk_data); + + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); + + if (r) { + pr_err("%s(): could not register clock provider: %d\n", + __func__, r); + goto free_mcusys_data; + } + return r; + +free_mcusys_data: + mtk_free_clk_data(clk_data); + return r; +} + +static const struct of_device_id of_match_clk_mt7988_topckgen[] = { + { + .compatible = "mediatek,mt7988-topckgen", + }, + {} +}; + +static struct platform_driver clk_mt7988_topckgen_drv = { + .probe = clk_mt7988_topckgen_probe, + .driver = { + .name = "clk-mt7988-topckgen", + .of_match_table = of_match_clk_mt7988_topckgen, + }, +}; +builtin_platform_driver(clk_mt7988_topckgen_drv); + +static const struct of_device_id of_match_clk_mt7988_mcusys[] = { + { + .compatible = "mediatek,mt7988-mcusys", + }, + {} +}; + +static struct platform_driver clk_mt7988_mcusys_drv = { + .probe = clk_mt7988_mcusys_probe, + .driver = { + .name = "clk-mt7988-mcusys", + .of_match_table = of_match_clk_mt7988_mcusys, + }, +}; +builtin_platform_driver(clk_mt7988_mcusys_drv); \ No newline at end of file diff --git a/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7988.c new file mode 100644 index 00000000000000..80a7e19f7a2d0d --- /dev/null +++ b/target/linux/mediatek/files-5.15/drivers/pinctrl/mediatek/pinctrl-mt7988.c @@ -0,0 +1,1281 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * The MT7988 driver based on Linux generic pinctrl binding. + * + * Copyright (C) 2020 MediaTek Inc. + * Author: Sam Shih + */ + +#include "pinctrl-moore.h" + +enum MT7988_PINCTRL_REG_PAGE { + GPIO_BASE, + IOCFG_TR_BASE, + IOCFG_BR_BASE, + IOCFG_RB_BASE, + IOCFG_LB_BASE, + IOCFG_TL_BASE, +}; + +#define MT7988_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4) + +#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 0) + +#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 1) + +static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = { + PIN_FIELD(0, 83, 0x300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = { + PIN_FIELD(0, 83, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_di_range[] = { + PIN_FIELD(0, 83, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_do_range[] = { + PIN_FIELD(0, 83, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = { + PIN_FIELD_BASE(0, 1, 5, 0x30, 0x10, 13, 1), + PIN_FIELD_BASE(2, 3, 5, 0x30, 0x10, 11, 1), + PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(5, 6, 5, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1), + PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1), + PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1), + PIN_FIELD_BASE(13, 14, 1, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(15, 16, 5, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(17, 18, 5, 0x30, 0x10, 3, 1), + PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1), + PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1), + PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1), + PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1), + PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1), + PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1), + PIN_FIELD_BASE(25, 26, 3, 0x50, 0x10, 21, 1), + PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1), + PIN_FIELD_BASE(28, 30, 3, 0x50, 0x10, 25, 1), + PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1), + PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1), + PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1), + PIN_FIELD_BASE(35, 36, 3, 0x50, 0x10, 29, 1), + PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1), + PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1), + PIN_FIELD_BASE(40, 41, 3, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1), + PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(45, 45, 3, 0x50, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, 3, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(47, 47, 3, 0x50, 0x10, 4, 1), + PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1), + PIN_FIELD_BASE(51, 53, 3, 0x50, 0x10, 12, 1), + PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1), + PIN_FIELD_BASE(55, 56, 1, 0x40, 0x10, 14, 1), + PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1), + PIN_FIELD_BASE(58, 60, 1, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1), + PIN_FIELD_BASE(64, 68, 1, 0x40, 0x10, 8, 1), + PIN_FIELD_BASE(69, 70, 5, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(71, 72, 5, 0x30, 0x10, 5, 1), + PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1), + PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1), + PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1), + PIN_FIELD_BASE(76, 76, 4, 0x30, 0x10, 9, 1), + PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1), + PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1), + PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1), + PIN_FIELD_BASE(80, 81, 1, 0x40, 0x10, 18, 1), + PIN_FIELD_BASE(82, 83, 1, 0x40, 0x10, 16, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = { + PIN_FIELD_BASE(0, 1, 5, 0xc0, 0x10, 13, 1), + PIN_FIELD_BASE(2, 3, 5, 0xc0, 0x10, 11, 1), + PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1), + PIN_FIELD_BASE(5, 6, 5, 0xc0, 0x10, 9, 1), + PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1), + PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1), + PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1), + PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1), + PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1), + PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1), + PIN_FIELD_BASE(13, 14, 1, 0xe0, 0x10, 1, 1), + PIN_FIELD_BASE(15, 16, 5, 0xc0, 0x10, 7, 1), + PIN_FIELD_BASE(17, 18, 5, 0xc0, 0x10, 3, 1), + PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1), + PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1), + PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1), + PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1), + PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1), + PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1), + PIN_FIELD_BASE(25, 26, 3, 0x140, 0x10, 21, 1), + PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1), + PIN_FIELD_BASE(28, 30, 3, 0x140, 0x10, 25, 1), + PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1), + PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1), + PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1), + PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1), + PIN_FIELD_BASE(35, 36, 3, 0x140, 0x10, 29, 1), + PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1), + PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1), + PIN_FIELD_BASE(40, 41, 3, 0x140, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1), + PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1), + PIN_FIELD_BASE(45, 45, 3, 0x140, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, 3, 0x140, 0x10, 5, 1), + PIN_FIELD_BASE(47, 47, 3, 0x140, 0x10, 4, 1), + PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1), + PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1), + PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1), + PIN_FIELD_BASE(51, 53, 3, 0x140, 0x10, 12, 1), + PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1), + PIN_FIELD_BASE(55, 56, 1, 0xe0, 0x10, 14, 1), + PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1), + PIN_FIELD_BASE(58, 60, 1, 0xe0, 0x10, 4, 1), + PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1), + PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1), + PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1), + PIN_FIELD_BASE(64, 68, 1, 0xe0, 0x10, 8, 1), + PIN_FIELD_BASE(69, 70, 5, 0xc0, 0x10, 1, 1), + PIN_FIELD_BASE(71, 72, 5, 0xc0, 0x10, 5, 1), + PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1), + PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1), + PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1), + PIN_FIELD_BASE(76, 76, 4, 0xb0, 0x10, 9, 1), + PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1), + PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1), + PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1), + PIN_FIELD_BASE(80, 81, 1, 0xe0, 0x10, 18, 1), + PIN_FIELD_BASE(82, 83, 1, 0xe0, 0x10, 16, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = { + PIN_FIELD_BASE(7, 7, 4, 0x60, 0x10, 5, 1), + PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1), + PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1), + PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(13, 14, 1, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1), + PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1), + PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1), + PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(78, 78, 4, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(79, 79, 4, 0x60, 0x10, 8, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = { + PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 5, 1), + PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1), + PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(13, 14, 1, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(15, 16, 5, 0x40, 0x10, 4, 1), + PIN_FIELD_BASE(17, 18, 5, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(71, 72, 5, 0x40, 0x10, 2, 1), + PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1), + PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1), + PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1), + PIN_FIELD_BASE(78, 78, 4, 0x40, 0x10, 0, 1), + PIN_FIELD_BASE(79, 79, 4, 0x40, 0x10, 8, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = { + PIN_FIELD_BASE(0, 1, 5, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(2, 3, 5, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(5, 6, 5, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3), + PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3), + PIN_FIELD_BASE(13, 14, 1, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3), + PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3), + PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3), + PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3), + PIN_FIELD_BASE(25, 26, 3, 0x20, 0x10, 3, 3), + PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3), + PIN_FIELD_BASE(28, 30, 3, 0x20, 0x10, 15, 3), + PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3), + PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3), + PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3), + PIN_FIELD_BASE(34, 34, 3, 0x30, 0x10, 3, 3), + PIN_FIELD_BASE(35, 35, 3, 0x20, 0x10, 27, 3), + PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 0, 3), + PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3), + PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3), + PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(40, 41, 3, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(45, 45, 3, 0x00, 0x10, 18, 3), + PIN_FIELD_BASE(46, 46, 3, 0x00, 0x10, 15, 3), + PIN_FIELD_BASE(47, 47, 3, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3), + PIN_FIELD_BASE(51, 53, 3, 0x10, 0x10, 6, 3), + PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3), + PIN_FIELD_BASE(55, 56, 1, 0x10, 0x10, 12, 3), + PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3), + PIN_FIELD_BASE(58, 60, 1, 0x00, 0x10, 12, 3), + PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3), + PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3), + PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3), + PIN_FIELD_BASE(64, 65, 1, 0x00, 0x10, 24, 3), + PIN_FIELD_BASE(66, 68, 1, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(69, 70, 5, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3), + PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3), + PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3), + PIN_FIELD_BASE(76, 76, 4, 0x00, 0x10, 27, 3), + PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3), + PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3), + PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3), + PIN_FIELD_BASE(80, 81, 1, 0x10, 0x10, 24, 3), + PIN_FIELD_BASE(82, 83, 1, 0x10, 0x10, 18, 3), +}; + +static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = { + PIN_FIELD_BASE(0, 1, 5, 0x50, 0x10, 7, 1), + PIN_FIELD_BASE(2, 3, 5, 0x50, 0x10, 5, 1), + PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(5, 6, 5, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1), + PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1), + PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1), + PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1), + PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1), + PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1), + PIN_FIELD_BASE(25, 26, 3, 0x70, 0x10, 21, 1), + PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1), + PIN_FIELD_BASE(28, 30, 3, 0x70, 0x10, 25, 1), + PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1), + PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1), + PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1), + PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1), + PIN_FIELD_BASE(35, 36, 3, 0x70, 0x10, 29, 1), + PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1), + PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1), + PIN_FIELD_BASE(40, 41, 3, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1), + PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1), + PIN_FIELD_BASE(45, 45, 3, 0x70, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, 3, 0x70, 0x10, 5, 1), + PIN_FIELD_BASE(47, 47, 3, 0x70, 0x10, 4, 1), + PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1), + PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1), + PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1), + PIN_FIELD_BASE(51, 53, 3, 0x70, 0x10, 12, 1), + PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1), + PIN_FIELD_BASE(55, 56, 1, 0x60, 0x10, 12, 1), + PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1), + PIN_FIELD_BASE(58, 60, 1, 0x60, 0x10, 2, 1), + PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1), + PIN_FIELD_BASE(64, 68, 1, 0x60, 0x10, 6, 1), + PIN_FIELD_BASE(69, 70, 5, 0x50, 0x10, 1, 1), + PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1), + PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1), + PIN_FIELD_BASE(80, 81, 1, 0x60, 0x10, 16, 1), + PIN_FIELD_BASE(82, 83, 1, 0x60, 0x10, 14, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = { + PIN_FIELD_BASE(0, 1, 5, 0x60, 0x10, 7, 1), + PIN_FIELD_BASE(2, 3, 5, 0x60, 0x10, 5, 1), + PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1), + PIN_FIELD_BASE(5, 6, 5, 0x60, 0x10, 3, 1), + PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1), + PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1), + PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1), + PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1), + PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1), + PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1), + PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1), + PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1), + PIN_FIELD_BASE(25, 26, 3, 0x90, 0x10, 21, 1), + PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1), + PIN_FIELD_BASE(28, 30, 3, 0x90, 0x10, 25, 1), + PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1), + PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1), + PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1), + PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1), + PIN_FIELD_BASE(35, 36, 3, 0x90, 0x10, 29, 1), + PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1), + PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1), + PIN_FIELD_BASE(40, 41, 3, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1), + PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1), + PIN_FIELD_BASE(45, 45, 3, 0x90, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, 3, 0x90, 0x10, 5, 1), + PIN_FIELD_BASE(47, 47, 3, 0x90, 0x10, 4, 1), + PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1), + PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1), + PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1), + PIN_FIELD_BASE(51, 53, 3, 0x90, 0x10, 12, 1), + PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1), + PIN_FIELD_BASE(55, 56, 1, 0x80, 0x10, 12, 1), + PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1), + PIN_FIELD_BASE(58, 60, 1, 0x80, 0x10, 2, 1), + PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1), + PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1), + PIN_FIELD_BASE(64, 68, 1, 0x80, 0x10, 6, 1), + PIN_FIELD_BASE(69, 70, 5, 0x60, 0x10, 1, 1), + PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1), + PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(80, 81, 1, 0x80, 0x10, 16, 1), + PIN_FIELD_BASE(82, 83, 1, 0x80, 0x10, 14, 1), +}; + +static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = { + PIN_FIELD_BASE(0, 1, 5, 0x70, 0x10, 7, 1), + PIN_FIELD_BASE(2, 3, 5, 0x70, 0x10, 5, 1), + PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1), + PIN_FIELD_BASE(5, 6, 5, 0x70, 0x10, 3, 1), + PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1), + PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1), + PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1), + PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1), + PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1), + PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1), + PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1), + PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1), + PIN_FIELD_BASE(25, 26, 3, 0xb0, 0x10, 21, 1), + PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1), + PIN_FIELD_BASE(28, 30, 3, 0xb0, 0x10, 25, 1), + PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1), + PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1), + PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1), + PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1), + PIN_FIELD_BASE(35, 36, 3, 0xb0, 0x10, 29, 1), + PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1), + PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1), + PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1), + PIN_FIELD_BASE(40, 41, 3, 0xb0, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1), + PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1), + PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1), + PIN_FIELD_BASE(45, 45, 3, 0xb0, 0x10, 6, 1), + PIN_FIELD_BASE(46, 46, 3, 0xb0, 0x10, 5, 1), + PIN_FIELD_BASE(47, 47, 3, 0xb0, 0x10, 4, 1), + PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1), + PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1), + PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1), + PIN_FIELD_BASE(51, 53, 3, 0xb0, 0x10, 12, 1), + PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1), + PIN_FIELD_BASE(55, 56, 1, 0x90, 0x10, 12, 1), + PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1), + PIN_FIELD_BASE(58, 60, 1, 0x90, 0x10, 2, 1), + PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1), + PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1), + PIN_FIELD_BASE(64, 68, 1, 0x90, 0x10, 6, 1), + PIN_FIELD_BASE(69, 70, 5, 0x70, 0x10, 1, 1), + PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1), + PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1), + PIN_FIELD_BASE(80, 81, 1, 0x90, 0x10, 16, 1), + PIN_FIELD_BASE(82, 83, 1, 0x90, 0x10, 14, 1), +}; + +static const struct mtk_pin_reg_calc mt7988_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range), +}; + +static const struct mtk_pin_desc mt7988_pins[] = { + MT7988_PIN(0, "UART2_RXD"), + MT7988_PIN(1, "UART2_TXD"), + MT7988_PIN(2, "UART2_CTS"), + MT7988_PIN(3, "UART2_RTS"), + MT7988_PIN(4, "GPIO_A"), + MT7988_PIN(5, "SMI_0_MDC"), + MT7988_PIN(6, "SMI_0_MDIO"), + MT7988_PIN(7, "PCIE30_2L_0_WAKE_N"), + MT7988_PIN(8, "PCIE30_2L_0_CLKREQ_N"), + MT7988_PIN(9, "PCIE30_1L_1_WAKE_N"), + MT7988_PIN(10, "PCIE30_1L_1_CLKREQ_N"), + MT7988_PIN(11, "GPIO_P"), + MT7988_PIN(12, "WATCHDOG"), + MT7988_PIN(13, "GPIO_RESET"), + MT7988_PIN(14, "GPIO_WPS"), + MT7988_PIN(15, "PMIC_I2C_SCL"), + MT7988_PIN(16, "PMIC_I2C_SDA"), + MT7988_PIN(17, "I2C_1_SCL"), + MT7988_PIN(18, "I2C_1_SDA"), + MT7988_PIN(19, "PCIE30_2L_0_PRESET_N"), + MT7988_PIN(20, "PCIE30_1L_1_PRESET_N"), + MT7988_PIN(21, "PWMD1"), + MT7988_PIN(22, "SPI0_WP"), + MT7988_PIN(23, "SPI0_HOLD"), + MT7988_PIN(24, "SPI0_CSB"), + MT7988_PIN(25, "SPI0_MISO"), + MT7988_PIN(26, "SPI0_MOSI"), + MT7988_PIN(27, "SPI0_CLK"), + MT7988_PIN(28, "SPI1_CSB"), + MT7988_PIN(29, "SPI1_MISO"), + MT7988_PIN(30, "SPI1_MOSI"), + MT7988_PIN(31, "SPI1_CLK"), + MT7988_PIN(32, "SPI2_CLK"), + MT7988_PIN(33, "SPI2_MOSI"), + MT7988_PIN(34, "SPI2_MISO"), + MT7988_PIN(35, "SPI2_CSB"), + MT7988_PIN(36, "SPI2_HOLD"), + MT7988_PIN(37, "SPI2_WP"), + MT7988_PIN(38, "EMMC_RSTB"), + MT7988_PIN(39, "EMMC_DSL"), + MT7988_PIN(40, "EMMC_CK"), + MT7988_PIN(41, "EMMC_CMD"), + MT7988_PIN(42, "EMMC_DATA_7"), + MT7988_PIN(43, "EMMC_DATA_6"), + MT7988_PIN(44, "EMMC_DATA_5"), + MT7988_PIN(45, "EMMC_DATA_4"), + MT7988_PIN(46, "EMMC_DATA_3"), + MT7988_PIN(47, "EMMC_DATA_2"), + MT7988_PIN(48, "EMMC_DATA_1"), + MT7988_PIN(49, "EMMC_DATA_0"), + MT7988_PIN(50, "PCM_FS_I2S_LRCK"), + MT7988_PIN(51, "PCM_CLK_I2S_BCLK"), + MT7988_PIN(52, "PCM_DRX_I2S_DIN"), + MT7988_PIN(53, "PCM_DTX_I2S_DOUT"), + MT7988_PIN(54, "PCM_MCK_I2S_MCLK"), + MT7988_PIN(55, "UART0_RXD"), + MT7988_PIN(56, "UART0_TXD"), + MT7988_PIN(57, "PWMD0"), + MT7988_PIN(58, "JTAG_JTDI"), + MT7988_PIN(59, "JTAG_JTDO"), + MT7988_PIN(60, "JTAG_JTMS"), + MT7988_PIN(61, "JTAG_JTCLK"), + MT7988_PIN(62, "JTAG_JTRST_N"), + MT7988_PIN(63, "USB_DRV_VBUS_P1"), + MT7988_PIN(64, "LED_A"), + MT7988_PIN(65, "LED_B"), + MT7988_PIN(66, "LED_C"), + MT7988_PIN(67, "LED_D"), + MT7988_PIN(68, "LED_E"), + MT7988_PIN(69, "GPIO_B"), + MT7988_PIN(70, "GPIO_C"), + MT7988_PIN(71, "I2C_2_SCL"), + MT7988_PIN(72, "I2C_2_SDA"), + MT7988_PIN(73, "PCIE30_2L_1_PRESET_N"), + MT7988_PIN(74, "PCIE30_1L_0_PRESET_N"), + MT7988_PIN(75, "PCIE30_2L_1_WAKE_N"), + MT7988_PIN(76, "PCIE30_2L_1_CLKREQ_N"), + MT7988_PIN(77, "PCIE30_1L_0_WAKE_N"), + MT7988_PIN(78, "PCIE30_1L_0_CLKREQ_N"), + MT7988_PIN(79, "USB_DRV_VBUS_P0"), + MT7988_PIN(80, "UART1_RXD"), + MT7988_PIN(81, "UART1_TXD"), + MT7988_PIN(82, "UART1_CTS"), + MT7988_PIN(83, "UART1_RTS"), +}; + +/* jtag */ +static int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 }; +static int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 }; + +static int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 }; +static int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 }; + +static int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 }; +static int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 }; + +static int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 }; +static int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 }; + +static int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 }; +static int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 }; + +static int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 }; +static int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 }; + +/* int_usxgmii */ +static int mt7988_int_usxgmii_pins[] = { 2, 3 }; +static int mt7988_int_usxgmii_funcs[] = { 3, 3 }; + +/* pwm */ +static int mt7988_pwm0_pins[] = { 57 }; +static int mt7988_pwm0_funcs[] = { 1 }; + +static int mt7988_pwm1_pins[] = { 21 }; +static int mt7988_pwm1_funcs[] = { 1 }; + +static int mt7988_pwm2_pins[] = { 80 }; +static int mt7988_pwm2_funcs[] = { 2 }; + +static int mt7988_pwm3_pins[] = { 81 }; +static int mt7988_pwm3_funcs[] = { 2 }; + +static int mt7988_pwm4_pins[] = { 82 }; +static int mt7988_pwm4_funcs[] = { 2 }; + +static int mt7988_pwm5_pins[] = { 83 }; +static int mt7988_pwm5_funcs[] = { 2 }; + +static int mt7988_pwm6_pins[] = { 69 }; +static int mt7988_pwm6_funcs[] = { 3 }; + +static int mt7988_pwm7_pins[] = { 70 }; +static int mt7988_pwm7_funcs[] = { 3 }; + +/* dfd */ +static int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 }; +static int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 }; + +/* i2c */ +static int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 }; +static int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 }; + +static int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 }; +static int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 }; + +static int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 }; +static int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 }; + +static int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 }; +static int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 }; + +static int mt7988_i2c0_0_pins[] = { 5, 6 }; +static int mt7988_i2c0_0_funcs[] = { 2, 2 }; + +static int mt7988_i2c1_sfp_pins[] = { 5, 6 }; +static int mt7988_i2c1_sfp_funcs[] = { 4, 4 }; + +static int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 }; +static int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 }; + +static int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 }; +static int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 }; + +static int mt7988_i2c0_1_pins[] = { 15, 16 }; +static int mt7988_i2c0_1_funcs[] = { 1, 1 }; + +static int mt7988_u30_phy_i2c0_pins[] = { 15, 16 }; +static int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 }; + +static int mt7988_u32_phy_i2c0_pins[] = { 15, 16 }; +static int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 }; + +static int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 }; +static int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 }; + +static int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 }; +static int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 }; + +static int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 }; +static int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 }; + +static int mt7988_i2c1_0_pins[] = { 17, 18 }; +static int mt7988_i2c1_0_funcs[] = { 1, 1 }; + +static int mt7988_u30_phy_i2c1_pins[] = { 17, 18 }; +static int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 }; + +static int mt7988_u32_phy_i2c1_pins[] = { 17, 18 }; +static int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 }; + +static int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 }; +static int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 }; + +static int mt7988_sgmii0_i2c_pins[] = { 17, 18 }; +static int mt7988_sgmii0_i2c_funcs[] = { 5, 5 }; + +static int mt7988_sgmii1_i2c_pins[] = { 17, 18 }; +static int mt7988_sgmii1_i2c_funcs[] = { 6, 6 }; + +static int mt7988_i2c1_2_pins[] = { 69, 70 }; +static int mt7988_i2c1_2_funcs[] = { 2, 2 }; + +static int mt7988_i2c2_0_pins[] = { 69, 70 }; +static int mt7988_i2c2_0_funcs[] = { 4, 4 }; + +static int mt7988_i2c2_1_pins[] = { 71, 72 }; +static int mt7988_i2c2_1_funcs[] = { 1, 1 }; + +/* eth */ +static int mt7988_mdc_mdio0_pins[] = { 5, 6 }; +static int mt7988_mdc_mdio0_funcs[] = { 1, 1 }; + +static int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 }; +static int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 }; + +static int mt7988_gbe_ext_mdio_pins[] = { 30, 31 }; +static int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 }; + +static int mt7988_mdc_mdio1_pins[] = { 69, 70 }; +static int mt7988_mdc_mdio1_funcs[] = { 1, 1 }; + +/* pcie */ +static int mt7988_pcie_wake_n0_0_pins[] = { 7 }; +static int mt7988_pcie_wake_n0_0_funcs[] = { 1 }; + +static int mt7988_pcie_clk_req_n0_0_pins[] = { 8 }; +static int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 }; + +static int mt7988_pcie_wake_n3_0_pins[] = { 9 }; +static int mt7988_pcie_wake_n3_0_funcs[] = { 1 }; + +static int mt7988_pcie_clk_req_n3_pins[] = { 10 }; +static int mt7988_pcie_clk_req_n3_funcs[] = { 1 }; + +static int mt7988_pcie_clk_req_n0_1_pins[] = { 10 }; +static int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 }; + +static int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 }; +static int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 }; + +static int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 }; +static int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 }; + +static int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 }; +static int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 }; + +static int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 }; +static int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 }; + +static int mt7988_ckm_phy_i2c_pins[] = { 9, 10 }; +static int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 }; + +static int mt7988_pcie_wake_n0_1_pins[] = { 13 }; +static int mt7988_pcie_wake_n0_1_funcs[] = { 2 }; + +static int mt7988_pcie_wake_n3_1_pins[] = { 14 }; +static int mt7988_pcie_wake_n3_1_funcs[] = { 2 }; + +static int mt7988_pcie_2l_0_pereset_pins[] = { 19 }; +static int mt7988_pcie_2l_0_pereset_funcs[] = { 1 }; + +static int mt7988_pcie_1l_1_pereset_pins[] = { 20 }; +static int mt7988_pcie_1l_1_pereset_funcs[] = { 1 }; + +static int mt7988_pcie_clk_req_n2_1_pins[] = { 63 }; +static int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 }; + +static int mt7988_pcie_2l_1_pereset_pins[] = { 73 }; +static int mt7988_pcie_2l_1_pereset_funcs[] = { 1 }; + +static int mt7988_pcie_1l_0_pereset_pins[] = { 74 }; +static int mt7988_pcie_1l_0_pereset_funcs[] = { 1 }; + +static int mt7988_pcie_wake_n1_0_pins[] = { 75 }; +static int mt7988_pcie_wake_n1_0_funcs[] = { 1 }; + +static int mt7988_pcie_clk_req_n1_pins[] = { 76 }; +static int mt7988_pcie_clk_req_n1_funcs[] = { 1 }; + +static int mt7988_pcie_wake_n2_0_pins[] = { 77 }; +static int mt7988_pcie_wake_n2_0_funcs[] = { 1 }; + +static int mt7988_pcie_clk_req_n2_0_pins[] = { 78 }; +static int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 }; + +static int mt7988_pcie_wake_n2_1_pins[] = { 79 }; +static int mt7988_pcie_wake_n2_1_funcs[] = { 2 }; + +/* pmic */ +static int mt7988_pmic_pins[] = { 11 }; +static int mt7988_pmic_funcs[] = { 1 }; + +/* watchdog */ +static int mt7988_watchdog_pins[] = { 12 }; +static int mt7988_watchdog_funcs[] = { 1 }; + +/* spi */ +static int mt7988_spi0_wp_hold_pins[] = { 22, 23 }; +static int mt7988_spi0_wp_hold_funcs[] = { 1, 1 }; + +static int mt7988_spi0_pins[] = { 24, 25, 26, 27 }; +static int mt7988_spi0_funcs[] = { 1, 1, 1, 1 }; + +static int mt7988_spi1_pins[] = { 28, 29, 30, 31 }; +static int mt7988_spi1_funcs[] = { 1, 1, 1, 1 }; + +static int mt7988_spi2_pins[] = { 32, 33, 34, 35 }; +static int mt7988_spi2_funcs[] = { 1, 1, 1, 1 }; + +static int mt7988_spi2_wp_hold_pins[] = { 36, 37 }; +static int mt7988_spi2_wp_hold_funcs[] = { 1, 1 }; + +/* flash */ +static int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 }; +static int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; + +static int mt7988_emmc_45_pins[] = { + 21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 +}; +static int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 }; + +static int mt7988_sdcard_pins[] = { 32, 33, 34, 35, 36, 37 }; +static int mt7988_sdcard_funcs[] = { 5, 5, 5, 5, 5, 5 }; + +static int mt7988_emmc_51_pins[] = { 38, 39, 40, 41, 42, 43, + 44, 45, 46, 47, 48, 49 }; +static int mt7988_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; + +/* uart */ +static int mt7988_uart2_pins[] = { 0, 1, 2, 3 }; +static int mt7988_uart2_funcs[] = { 1, 1, 1, 1 }; + +static int mt7988_tops_uart0_0_pins[] = { 22, 23 }; +static int mt7988_tops_uart0_0_funcs[] = { 3, 3 }; + +static int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 }; +static int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 }; + +static int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 }; +static int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 }; + +static int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 }; +static int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 }; + +static int mt7988_net_wo0_uart_txd_0_pins[] = { 28 }; +static int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 }; + +static int mt7988_net_wo1_uart_txd_0_pins[] = { 29 }; +static int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 }; + +static int mt7988_net_wo2_uart_txd_0_pins[] = { 30 }; +static int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 }; + +static int mt7988_tops_uart1_0_pins[] = { 28, 29 }; +static int mt7988_tops_uart1_0_funcs[] = { 4, 4 }; + +static int mt7988_tops_uart0_1_pins[] = { 30, 31 }; +static int mt7988_tops_uart0_1_funcs[] = { 4, 4 }; + +static int mt7988_tops_uart1_1_pins[] = { 36, 37 }; +static int mt7988_tops_uart1_1_funcs[] = { 3, 3 }; + +static int mt7988_uart0_pins[] = { 55, 56 }; +static int mt7988_uart0_funcs[] = { 1, 1 }; + +static int mt7988_tops_uart0_2_pins[] = { 55, 56 }; +static int mt7988_tops_uart0_2_funcs[] = { 2, 2 }; + +static int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 }; +static int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 }; + +static int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 }; +static int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 }; + +static int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 }; +static int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 }; + +static int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 }; +static int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 }; + +static int mt7988_tops_uart1_2_pins[] = { 80, 81 }; +static int mt7988_tops_uart1_2_funcs[] = { + 4, + 4, +}; + +static int mt7988_net_wo0_uart_txd_1_pins[] = { 80 }; +static int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 }; + +static int mt7988_net_wo1_uart_txd_1_pins[] = { 81 }; +static int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 }; + +static int mt7988_net_wo2_uart_txd_1_pins[] = { 82 }; +static int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 }; + +/* udi */ +static int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 }; +static int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 }; + +/* i2s */ +static int mt7988_i2s_pins[] = { 50, 51, 52, 53, 54 }; +static int mt7988_i2s_funcs[] = { 1, 1, 1, 1, 1 }; + +/* pcm */ +static int mt7988_pcm_pins[] = { 50, 51, 52, 53 }; +static int mt7988_pcm_funcs[] = { 1, 1, 1, 1 }; + +/* led */ +static int mt7988_gbe0_led1_pins[] = { 58 }; +static int mt7988_gbe0_led1_funcs[] = { 6 }; +static int mt7988_gbe1_led1_pins[] = { 59 }; +static int mt7988_gbe1_led1_funcs[] = { 6 }; +static int mt7988_gbe2_led1_pins[] = { 60 }; +static int mt7988_gbe2_led1_funcs[] = { 6 }; +static int mt7988_gbe3_led1_pins[] = { 61 }; +static int mt7988_gbe3_led1_funcs[] = { 6 }; + +static int mt7988_2p5gbe_led1_pins[] = { 62 }; +static int mt7988_2p5gbe_led1_funcs[] = { 6 }; + +static int mt7988_gbe0_led0_pins[] = { 64 }; +static int mt7988_gbe0_led0_funcs[] = { 1 }; +static int mt7988_gbe1_led0_pins[] = { 65 }; +static int mt7988_gbe1_led0_funcs[] = { 1 }; +static int mt7988_gbe2_led0_pins[] = { 66 }; +static int mt7988_gbe2_led0_funcs[] = { 1 }; +static int mt7988_gbe3_led0_pins[] = { 67 }; +static int mt7988_gbe3_led0_funcs[] = { 1 }; + +static int mt7988_2p5gbe_led0_pins[] = { 68 }; +static int mt7988_2p5gbe_led0_funcs[] = { 1 }; + +/* usb */ +static int mt7988_drv_vbus_p1_pins[] = { 63 }; +static int mt7988_drv_vbus_p1_funcs[] = { 1 }; + +static int mt7988_drv_vbus_pins[] = { 79 }; +static int mt7988_drv_vbus_funcs[] = { 1 }; + +static const struct group_desc mt7988_groups[] = { + /* @GPIO(0,1,2,3): uart2 */ + PINCTRL_PIN_GROUP("uart2", mt7988_uart2), + /* @GPIO(0,1,2,3,4): tops_jtag0_0 */ + PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0), + /* @GPIO(2,3): int_usxgmii */ + PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii), + /* @GPIO(0,1,2,3,4): dfd */ + PINCTRL_PIN_GROUP("dfd", mt7988_dfd), + /* @GPIO(0,1): xfi_phy0_i2c0 */ + PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0), + /* @GPIO(0,1): xfi_phy1_i2c0 */ + PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0), + /* @GPIO(3,4): xfi_phy_pll_i2c0 */ + PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0), + /* @GPIO(3,4): xfi_phy_pll_i2c1 */ + PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1), + /* @GPIO(5,6) i2c0_0 */ + PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0), + /* @GPIO(5,6) i2c1_sfp */ + PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp), + /* @GPIO(5,6) xfi_pextp_phy0_i2c */ + PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c), + /* @GPIO(5,6) xfi_pextp_phy1_i2c */ + PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c), + /* @GPIO(5,6) mdc_mdio0 */ + PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0), + /* @GPIO(7): pcie_wake_n0_0 */ + PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0), + /* @GPIO(8): pcie_clk_req_n0_0 */ + PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0), + /* @GPIO(9): pcie_wake_n3_0 */ + PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0), + /* @GPIO(10): pcie_clk_req_n3 */ + PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3), + /* @GPIO(10): pcie_clk_req_n0_1 */ + PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1), + /* @GPIO(7,8) pcie_p0_phy_i2c */ + PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c), + /* @GPIO(7,8) pcie_p1_phy_i2c */ + PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c), + /* @GPIO(7,8) pcie_p2_phy_i2c */ + PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c), + /* @GPIO(9,10) pcie_p3_phy_i2c */ + PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c), + /* @GPIO(9,10) ckm_phy_i2c */ + PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c), + /* @GPIO(11): pmic */ + PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic), + /* @GPIO(12): watchdog */ + PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog), + /* @GPIO(13): pcie_wake_n0_1 */ + PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1), + /* @GPIO(14): pcie_wake_n3_1 */ + PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1), + /* @GPIO(15,16) i2c0_1 */ + PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1), + /* @GPIO(15,16) u30_phy_i2c0 */ + PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0), + /* @GPIO(15,16) u32_phy_i2c0 */ + PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0), + /* @GPIO(15,16) xfi_phy0_i2c1 */ + PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1), + /* @GPIO(15,16) xfi_phy1_i2c1 */ + PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1), + /* @GPIO(15,16) xfi_phy_pll_i2c2 */ + PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2), + /* @GPIO(17,18) i2c1_0 */ + PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0), + /* @GPIO(17,18) u30_phy_i2c1 */ + PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1), + /* @GPIO(17,18) u32_phy_i2c1 */ + PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1), + /* @GPIO(17,18) xfi_phy_pll_i2c3 */ + PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3), + /* @GPIO(17,18) sgmii0_i2c */ + PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c), + /* @GPIO(17,18) sgmii1_i2c */ + PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c), + /* @GPIO(19): pcie_2l_0_pereset */ + PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset), + /* @GPIO(20): pcie_1l_1_pereset */ + PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset), + /* @GPIO(21): pwm1 */ + PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1), + /* @GPIO(22,23) spi0_wp_hold */ + PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold), + /* @GPIO(24,25,26,27) spi0 */ + PINCTRL_PIN_GROUP("spi0", mt7988_spi0), + /* @GPIO(28,29,30,31) spi1 */ + PINCTRL_PIN_GROUP("spi1", mt7988_spi1), + /* @GPIO(32,33,34,35) spi2 */ + PINCTRL_PIN_GROUP("spi2", mt7988_spi2), + /* @GPIO(36,37) spi2_wp_hold */ + PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold), + /* @GPIO(22,23,24,25,26,27) snfi */ + PINCTRL_PIN_GROUP("snfi", mt7988_snfi), + /* @GPIO(22,23) tops_uart0_0 */ + PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0), + /* @GPIO(28,29,30,31) uart2_0 */ + PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0), + /* @GPIO(32,33,34,35) uart1_0 */ + PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0), + /* @GPIO(32,33,34,35) uart2_1 */ + PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1), + /* @GPIO(28) net_wo0_uart_txd_0 */ + PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), + /* @GPIO(29) net_wo1_uart_txd_0 */ + PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), + /* @GPIO(30) net_wo2_uart_txd_0 */ + PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), + /* @GPIO(28,29) tops_uart1_0 */ + PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0), + /* @GPIO(30,31) tops_uart0_1 */ + PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1), + /* @GPIO(36,37) tops_uart1_1 */ + PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1), + /* @GPIO(32,33,34,35,36) udi */ + PINCTRL_PIN_GROUP("udi", mt7988_udi), + /* @GPIO(21,28,29,30,31,32,33,34,35,36,37) emmc_45 */ + PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45), + /* @GPIO(32,33,34,35,36,37) sdcard */ + PINCTRL_PIN_GROUP("sdcard", mt7988_sdcard), + /* @GPIO(38,39,40,41,42,43,44,45,46,47,48,49) emmc_51 */ + PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51), + /* @GPIO(28,29) 2p5g_ext_mdio */ + PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio), + /* @GPIO(30,31) gbe_ext_mdio */ + PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio), + /* @GPIO(50,51,52,53,54) i2s */ + PINCTRL_PIN_GROUP("i2s", mt7988_i2s), + /* @GPIO(50,51,52,53) pcm */ + PINCTRL_PIN_GROUP("pcm", mt7988_pcm), + /* @GPIO(55,56) uart0 */ + PINCTRL_PIN_GROUP("uart0", mt7988_uart0), + /* @GPIO(55,56) tops_uart0_2 */ + PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2), + /* @GPIO(50,51,52,53) uart2_2 */ + PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2), + /* @GPIO(50,51,52,53,54) wo0_jtag */ + PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag), + /* @GPIO(50,51,52,53,54) wo1-wo1_jtag */ + PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag), + /* @GPIO(50,51,52,53,54) wo2_jtag */ + PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag), + /* @GPIO(57) pwm0 */ + PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0), + /* @GPIO(58,59,60,61,62) jtag */ + PINCTRL_PIN_GROUP("jtag", mt7988_jtag), + /* @GPIO(58,59,60,61,62) tops_jtag0_1 */ + PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1), + /* @GPIO(58,59,60,61) uart2_3 */ + PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3), + /* @GPIO(58,59,60,61) uart1_1 */ + PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1), + /* @GPIO(58,59,60,61) gbe_led1 */ + PINCTRL_PIN_GROUP("gbe0_led1", mt7988_gbe0_led1), + PINCTRL_PIN_GROUP("gbe1_led1", mt7988_gbe1_led1), + PINCTRL_PIN_GROUP("gbe2_led1", mt7988_gbe2_led1), + PINCTRL_PIN_GROUP("gbe3_led1", mt7988_gbe3_led1), + /* @GPIO(62) 2p5gbe_led1 */ + PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1), + /* @GPIO(64,65,66,67) gbe_led0 */ + PINCTRL_PIN_GROUP("gbe0_led0", mt7988_gbe0_led0), + PINCTRL_PIN_GROUP("gbe1_led0", mt7988_gbe1_led0), + PINCTRL_PIN_GROUP("gbe2_led0", mt7988_gbe2_led0), + PINCTRL_PIN_GROUP("gbe3_led0", mt7988_gbe3_led0), + /* @GPIO(68) 2p5gbe_led0 */ + PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0), + /* @GPIO(63) drv_vbus_p1 */ + PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1), + /* @GPIO(63) pcie_clk_req_n2_1 */ + PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1), + /* @GPIO(69, 70) mdc_mdio1 */ + PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1), + /* @GPIO(69, 70) i2c1_2 */ + PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2), + /* @GPIO(69) pwm6 */ + PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6), + /* @GPIO(70) pwm7 */ + PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7), + /* @GPIO(69,70) i2c2_0 */ + PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0), + /* @GPIO(71,72) i2c2_1 */ + PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1), + /* @GPIO(73) pcie_2l_1_pereset */ + PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset), + /* @GPIO(74) pcie_1l_0_pereset */ + PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset), + /* @GPIO(75) pcie_wake_n1_0 */ + PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0), + /* @GPIO(76) pcie_clk_req_n1 */ + PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1), + /* @GPIO(77) pcie_wake_n2_0 */ + PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0), + /* @GPIO(78) pcie_clk_req_n2_0 */ + PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0), + /* @GPIO(79) drv_vbus */ + PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus), + /* @GPIO(79) pcie_wake_n2_1 */ + PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1), + /* @GPIO(80,81,82,83) uart1_2 */ + PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2), + /* @GPIO(80) pwm2 */ + PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2), + /* @GPIO(81) pwm3 */ + PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3), + /* @GPIO(82) pwm4 */ + PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4), + /* @GPIO(83) pwm5 */ + PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5), + /* @GPIO(80) net_wo0_uart_txd_0 */ + PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), + /* @GPIO(81) net_wo1_uart_txd_0 */ + PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), + /* @GPIO(82) net_wo2_uart_txd_0 */ + PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), + /* @GPIO(80,81) tops_uart1_2 */ + PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2), + /* @GPIO(80) net_wo0_uart_txd_1 */ + PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1), + /* @GPIO(81) net_wo1_uart_txd_1 */ + PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1), + /* @GPIO(82) net_wo2_uart_txd_1 */ + PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1), +}; + +/* Joint those groups owning the same capability in user point of view which + * allows that people tend to use through the device tree. + */ +static const char *mt7988_jtag_groups[] = { + "tops_jtag0_0", "wo0_jtag", "wo1_jtag", + "wo2_jtag", "jtag", "tops_jtag0_1", +}; +static const char *mt7988_int_usxgmii_groups[] = { + "int_usxgmii", +}; +static const char *mt7988_pwm_groups[] = { + "pwm0", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7" +}; +static const char *mt7988_dfd_groups[] = { + "dfd", +}; +static const char *mt7988_i2c_groups[] = { + "xfi_phy0_i2c0", + "xfi_phy1_i2c0", + "xfi_phy_pll_i2c0", + "xfi_phy_pll_i2c1", + "i2c0_0", + "i2c1_sfp", + "xfi_pextp_phy0_i2c", + "xfi_pextp_phy1_i2c", + "i2c0_1", + "u30_phy_i2c0", + "u32_phy_i2c0", + "xfi_phy0_i2c1", + "xfi_phy1_i2c1", + "xfi_phy_pll_i2c2", + "i2c1_0", + "u30_phy_i2c1", + "u32_phy_i2c1", + "xfi_phy_pll_i2c3", + "sgmii0_i2c", + "sgmii1_i2c", + "i2c1_2", + "i2c2_0", + "i2c2_1", +}; +static const char *mt7988_ethernet_groups[] = { + "mdc_mdio0", + "2p5g_ext_mdio", + "gbe_ext_mdio", + "mdc_mdio1", +}; +static const char *mt7988_pcie_groups[] = { + "pcie_wake_n0_0", "pcie_clk_req_n0_0", "pcie_wake_n3_0", + "pcie_clk_req_n3", "pcie_p0_phy_i2c", "pcie_p1_phy_i2c", + "pcie_p3_phy_i2c", "pcie_p2_phy_i2c", "ckm_phy_i2c", + "pcie_wake_n0_1", "pcie_wake_n3_1", "pcie_2l_0_pereset", + "pcie_1l_1_pereset", "pcie_clk_req_n2_1", "pcie_2l_1_pereset", + "pcie_1l_0_pereset", "pcie_wake_n1_0", "pcie_clk_req_n1", + "pcie_wake_n2_0", "pcie_clk_req_n2_0", "pcie_wake_n2_1", + "pcie_clk_req_n0_1" +}; +static const char *mt7988_pmic_groups[] = { + "pmic", +}; +static const char *mt7988_wdt_groups[] = { + "watchdog", +}; +static const char *mt7988_spi_groups[] = { + "spi0", "spi0_wp_hold", "spi1", "spi2", "spi2_wp_hold", +}; +static const char *mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi", + "emmc_51" }; +static const char *mt7988_uart_groups[] = { + "uart2", + "tops_uart0_0", + "uart2_0", + "uart1_0", + "uart2_1", + "net_wo0_uart_txd_0", + "net_wo1_uart_txd_0", + "net_wo2_uart_txd_0", + "tops_uart1_0", + "ops_uart0_1", + "ops_uart1_1", + "uart0", + "tops_uart0_2", + "uart1_1", + "uart2_3", + "uart1_2", + "tops_uart1_2", + "net_wo0_uart_txd_1", + "net_wo1_uart_txd_1", + "net_wo2_uart_txd_1", +}; +static const char *mt7988_udi_groups[] = { + "udi", +}; +static const char *mt7988_audio_groups[] = { + "i2s", "pcm", +}; +static const char *mt7988_led_groups[] = { + "gbe0_led1", "gbe1_led1", "gbe2_led1", "gbe3_led1", "2p5gbe_led1", + "gbe0_led0", "gbe1_led0", "gbe2_led0", "gbe3_led0", "2p5gbe_led0", + "wf5g_led0", "wf5g_led1", +}; +static const char *mt7988_usb_groups[] = { + "drv_vbus", + "drv_vbus_p1", +}; + +static const struct function_desc mt7988_functions[] = { + { "audio", mt7988_audio_groups, ARRAY_SIZE(mt7988_audio_groups) }, + { "jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups) }, + { "int_usxgmii", mt7988_int_usxgmii_groups, + ARRAY_SIZE(mt7988_int_usxgmii_groups) }, + { "pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups) }, + { "dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups) }, + { "i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups) }, + { "eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups) }, + { "pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups) }, + { "pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups) }, + { "watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups) }, + { "spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups) }, + { "flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups) }, + { "uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups) }, + { "udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups) }, + { "usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups) }, + { "led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups) }, +}; + +static const struct mtk_eint_hw mt7988_eint_hw = { + .port_mask = 7, + .ports = 7, + .ap_num = ARRAY_SIZE(mt7988_pins), + .db_cnt = 16, +}; + +static const char *mt7988_pinctrl_register_base_names[] = { + "gpio_base", "iocfg_tr_base", "iocfg_br_base", + "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base", +}; + +static struct mtk_pin_soc mt7988_data = { + .reg_cal = mt7988_reg_cals, + .pins = mt7988_pins, + .npins = ARRAY_SIZE(mt7988_pins), + .grps = mt7988_groups, + .ngrps = ARRAY_SIZE(mt7988_groups), + .funcs = mt7988_functions, + .nfuncs = ARRAY_SIZE(mt7988_functions), + .eint_hw = &mt7988_eint_hw, + .gpio_m = 0, + .ies_present = false, + .base_names = mt7988_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names), + .bias_disable_set = mtk_pinconf_bias_disable_set, + .bias_disable_get = mtk_pinconf_bias_disable_get, + .bias_set = mtk_pinconf_bias_set, + .bias_get = mtk_pinconf_bias_get, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, + .adv_pull_get = mtk_pinconf_adv_pull_get, + .adv_pull_set = mtk_pinconf_adv_pull_set, +}; + +static const struct of_device_id mt7988_pinctrl_of_match[] = { + { + .compatible = "mediatek,mt7988-pinctrl", + }, + {} +}; + +static int mt7988_pinctrl_probe(struct platform_device *pdev) +{ + return mtk_moore_pinctrl_probe(pdev, &mt7988_data); +} + +static struct platform_driver mt7988_pinctrl_driver = { + .driver = { + .name = "mt7988-pinctrl", + .of_match_table = mt7988_pinctrl_of_match, + }, + .probe = mt7988_pinctrl_probe, +}; + +static int __init mt7988_pinctrl_init(void) +{ + return platform_driver_register(&mt7988_pinctrl_driver); +} +arch_initcall(mt7988_pinctrl_init); diff --git a/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mediatek,mt7988-clk.h b/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mediatek,mt7988-clk.h new file mode 100644 index 00000000000000..77cfea4a8eaf6a --- /dev/null +++ b/target/linux/mediatek/files-5.15/include/dt-bindings/clock/mediatek,mt7988-clk.h @@ -0,0 +1,276 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023 MediaTek Inc. + * Author: Sam Shih + * Author: Xiufeng Li + */ + +#ifndef _DT_BINDINGS_CLK_MT7988_H +#define _DT_BINDINGS_CLK_MT7988_H + +/* APMIXEDSYS */ + +#define CLK_APMIXED_NETSYSPLL 0 +#define CLK_APMIXED_MPLL 1 +#define CLK_APMIXED_MMPLL 2 +#define CLK_APMIXED_APLL2 3 +#define CLK_APMIXED_NET1PLL 4 +#define CLK_APMIXED_NET2PLL 5 +#define CLK_APMIXED_WEDMCUPLL 6 +#define CLK_APMIXED_SGMPLL 7 +#define CLK_APMIXED_ARM_B 8 +#define CLK_APMIXED_CCIPLL2_B 9 +#define CLK_APMIXED_USXGMIIPLL 10 +#define CLK_APMIXED_MSDCPLL 11 + +/* TOPCKGEN */ + +#define CLK_TOP_XTAL 0 +#define CLK_TOP_XTAL_D2 1 +#define CLK_TOP_RTC_32K 2 +#define CLK_TOP_RTC_32P7K 3 +#define CLK_TOP_MPLL_D2 4 +#define CLK_TOP_MPLL_D3_D2 5 +#define CLK_TOP_MPLL_D4 6 +#define CLK_TOP_MPLL_D8 7 +#define CLK_TOP_MPLL_D8_D2 8 +#define CLK_TOP_MMPLL_D2 9 +#define CLK_TOP_MMPLL_D3_D5 10 +#define CLK_TOP_MMPLL_D4 11 +#define CLK_TOP_MMPLL_D6_D2 12 +#define CLK_TOP_MMPLL_D8 13 +#define CLK_TOP_APLL2_D4 14 +#define CLK_TOP_NET1PLL_D4 15 +#define CLK_TOP_NET1PLL_D5 16 +#define CLK_TOP_NET1PLL_D5_D2 17 +#define CLK_TOP_NET1PLL_D5_D4 18 +#define CLK_TOP_NET1PLL_D8 19 +#define CLK_TOP_NET1PLL_D8_D2 20 +#define CLK_TOP_NET1PLL_D8_D4 21 +#define CLK_TOP_NET1PLL_D8_D8 22 +#define CLK_TOP_NET1PLL_D8_D16 23 +#define CLK_TOP_NET2PLL_D2 24 +#define CLK_TOP_NET2PLL_D4 25 +#define CLK_TOP_NET2PLL_D4_D4 26 +#define CLK_TOP_NET2PLL_D4_D8 27 +#define CLK_TOP_NET2PLL_D6 28 +#define CLK_TOP_NET2PLL_D8 29 +#define CLK_TOP_NETSYS_SEL 30 +#define CLK_TOP_NETSYS_500M_SEL 31 +#define CLK_TOP_NETSYS_2X_SEL 32 +#define CLK_TOP_NETSYS_GSW_SEL 33 +#define CLK_TOP_ETH_GMII_SEL 34 +#define CLK_TOP_NETSYS_MCU_SEL 35 +#define CLK_TOP_NETSYS_PAO_2X_SEL 36 +#define CLK_TOP_EIP197_SEL 37 +#define CLK_TOP_AXI_INFRA_SEL 38 +#define CLK_TOP_UART_SEL 39 +#define CLK_TOP_EMMC_250M_SEL 40 +#define CLK_TOP_EMMC_400M_SEL 41 +#define CLK_TOP_SPI_SEL 42 +#define CLK_TOP_SPIM_MST_SEL 43 +#define CLK_TOP_NFI1X_SEL 44 +#define CLK_TOP_SPINFI_SEL 45 +#define CLK_TOP_PWM_SEL 46 +#define CLK_TOP_I2C_SEL 47 +#define CLK_TOP_PCIE_MBIST_250M_SEL 48 +#define CLK_TOP_PEXTP_TL_SEL 49 +#define CLK_TOP_PEXTP_TL_P1_SEL 50 +#define CLK_TOP_PEXTP_TL_P2_SEL 51 +#define CLK_TOP_PEXTP_TL_P3_SEL 52 +#define CLK_TOP_USB_SYS_SEL 53 +#define CLK_TOP_USB_SYS_P1_SEL 54 +#define CLK_TOP_USB_XHCI_SEL 55 +#define CLK_TOP_USB_XHCI_P1_SEL 56 +#define CLK_TOP_USB_FRMCNT_SEL 57 +#define CLK_TOP_USB_FRMCNT_P1_SEL 58 +#define CLK_TOP_AUD_SEL 59 +#define CLK_TOP_A1SYS_SEL 60 +#define CLK_TOP_AUD_L_SEL 61 +#define CLK_TOP_A_TUNER_SEL 62 +#define CLK_TOP_SSPXTP_SEL 63 +#define CLK_TOP_USB_PHY_SEL 64 +#define CLK_TOP_USXGMII_SBUS_0_SEL 65 +#define CLK_TOP_USXGMII_SBUS_1_SEL 66 +#define CLK_TOP_SGM_0_SEL 67 +#define CLK_TOP_SGM_SBUS_0_SEL 68 +#define CLK_TOP_SGM_1_SEL 69 +#define CLK_TOP_SGM_SBUS_1_SEL 70 +#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71 +#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72 +#define CLK_TOP_SYSAXI_SEL 73 +#define CLK_TOP_SYSAPB_SEL 74 +#define CLK_TOP_ETH_REFCK_50M_SEL 75 +#define CLK_TOP_ETH_SYS_200M_SEL 76 +#define CLK_TOP_ETH_SYS_SEL 77 +#define CLK_TOP_ETH_XGMII_SEL 78 +#define CLK_TOP_BUS_TOPS_SEL 79 +#define CLK_TOP_NPU_TOPS_SEL 80 +#define CLK_TOP_DRAMC_SEL 81 +#define CLK_TOP_DRAMC_MD32_SEL 82 +#define CLK_TOP_INFRA_F26M_SEL 83 +#define CLK_TOP_PEXTP_P0_SEL 84 +#define CLK_TOP_PEXTP_P1_SEL 85 +#define CLK_TOP_PEXTP_P2_SEL 86 +#define CLK_TOP_PEXTP_P3_SEL 87 +#define CLK_TOP_DA_XTP_GLB_P0_SEL 88 +#define CLK_TOP_DA_XTP_GLB_P1_SEL 89 +#define CLK_TOP_DA_XTP_GLB_P2_SEL 90 +#define CLK_TOP_DA_XTP_GLB_P3_SEL 91 +#define CLK_TOP_CKM_SEL 92 +#define CLK_TOP_DA_SEL 93 +#define CLK_TOP_PEXTP_SEL 94 +#define CLK_TOP_TOPS_P2_26M_SEL 95 +#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96 +#define CLK_TOP_NETSYS_SYNC_250M_SEL 97 +#define CLK_TOP_MACSEC_SEL 98 +#define CLK_TOP_NETSYS_TOPS_400M_SEL 99 +#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100 +#define CLK_TOP_NETSYS_WARP_SEL 101 +#define CLK_TOP_ETH_MII_SEL 102 +#define CLK_TOP_NPU_SEL 103 +#define CLK_TOP_AUD_I2S_M 104 + +/* MCUSYS */ + +#define CLK_MCU_BUS_DIV_SEL 0 +#define CLK_MCU_ARM_DIV_SEL 1 + +/* INFRACFG_AO */ + +#define CLK_INFRA_MUX_UART0_SEL 0 +#define CLK_INFRA_MUX_UART1_SEL 1 +#define CLK_INFRA_MUX_UART2_SEL 2 +#define CLK_INFRA_MUX_SPI0_SEL 3 +#define CLK_INFRA_MUX_SPI1_SEL 4 +#define CLK_INFRA_MUX_SPI2_SEL 5 +#define CLK_INFRA_PWM_SEL 6 +#define CLK_INFRA_PWM_CK1_SEL 7 +#define CLK_INFRA_PWM_CK2_SEL 8 +#define CLK_INFRA_PWM_CK3_SEL 9 +#define CLK_INFRA_PWM_CK4_SEL 10 +#define CLK_INFRA_PWM_CK5_SEL 11 +#define CLK_INFRA_PWM_CK6_SEL 12 +#define CLK_INFRA_PWM_CK7_SEL 13 +#define CLK_INFRA_PWM_CK8_SEL 14 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17 +#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18 + +/* INFRACFG */ + +#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19 +#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20 +#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21 +#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22 +#define CLK_INFRA_66M_GPT_BCK 23 +#define CLK_INFRA_66M_PWM_HCK 24 +#define CLK_INFRA_66M_PWM_BCK 25 +#define CLK_INFRA_66M_PWM_CK1 26 +#define CLK_INFRA_66M_PWM_CK2 27 +#define CLK_INFRA_66M_PWM_CK3 28 +#define CLK_INFRA_66M_PWM_CK4 29 +#define CLK_INFRA_66M_PWM_CK5 30 +#define CLK_INFRA_66M_PWM_CK6 31 +#define CLK_INFRA_66M_PWM_CK7 32 +#define CLK_INFRA_66M_PWM_CK8 33 +#define CLK_INFRA_133M_CQDMA_BCK 34 +#define CLK_INFRA_66M_AUD_SLV_BCK 35 +#define CLK_INFRA_AUD_26M 36 +#define CLK_INFRA_AUD_L 37 +#define CLK_INFRA_AUD_AUD 38 +#define CLK_INFRA_AUD_EG2 39 +#define CLK_INFRA_DRAMC_F26M 40 +#define CLK_INFRA_133M_DBG_ACKM 41 +#define CLK_INFRA_66M_AP_DMA_BCK 42 +#define CLK_INFRA_66M_SEJ_BCK 43 +#define CLK_INFRA_PRE_CK_SEJ_F13M 44 +#define CLK_INFRA_26M_THERM_SYSTEM 45 +#define CLK_INFRA_I2C_BCK 46 +#define CLK_INFRA_52M_UART0_CK 47 +#define CLK_INFRA_52M_UART1_CK 48 +#define CLK_INFRA_52M_UART2_CK 49 +#define CLK_INFRA_NFI 50 +#define CLK_INFRA_SPINFI 51 +#define CLK_INFRA_66M_NFI_HCK 52 +#define CLK_INFRA_104M_SPI0 53 +#define CLK_INFRA_104M_SPI1 54 +#define CLK_INFRA_104M_SPI2_BCK 55 +#define CLK_INFRA_66M_SPI0_HCK 56 +#define CLK_INFRA_66M_SPI1_HCK 57 +#define CLK_INFRA_66M_SPI2_HCK 58 +#define CLK_INFRA_66M_FLASHIF_AXI 59 +#define CLK_INFRA_RTC 60 +#define CLK_INFRA_26M_ADC_BCK 61 +#define CLK_INFRA_RC_ADC 62 +#define CLK_INFRA_MSDC400 63 +#define CLK_INFRA_MSDC2_HCK 64 +#define CLK_INFRA_133M_MSDC_0_HCK 65 +#define CLK_INFRA_66M_MSDC_0_HCK 66 +#define CLK_INFRA_133M_CPUM_BCK 67 +#define CLK_INFRA_BIST2FPC 68 +#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69 +#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70 +#define CLK_INFRA_133M_USB_HCK 71 +#define CLK_INFRA_133M_USB_HCK_CK_P1 72 +#define CLK_INFRA_66M_USB_HCK 73 +#define CLK_INFRA_66M_USB_HCK_CK_P1 74 +#define CLK_INFRA_USB_SYS 75 +#define CLK_INFRA_USB_SYS_CK_P1 76 +#define CLK_INFRA_USB_REF 77 +#define CLK_INFRA_USB_CK_P1 78 +#define CLK_INFRA_USB_FRMCNT 79 +#define CLK_INFRA_USB_FRMCNT_CK_P1 80 +#define CLK_INFRA_USB_PIPE 81 +#define CLK_INFRA_USB_PIPE_CK_P1 82 +#define CLK_INFRA_USB_UTMI 83 +#define CLK_INFRA_USB_UTMI_CK_P1 84 +#define CLK_INFRA_USB_XHCI 85 +#define CLK_INFRA_USB_XHCI_CK_P1 86 +#define CLK_INFRA_PCIE_GFMUX_TL_P0 87 +#define CLK_INFRA_PCIE_GFMUX_TL_P1 88 +#define CLK_INFRA_PCIE_GFMUX_TL_P2 89 +#define CLK_INFRA_PCIE_GFMUX_TL_P3 90 +#define CLK_INFRA_PCIE_PIPE_P0 91 +#define CLK_INFRA_PCIE_PIPE_P1 92 +#define CLK_INFRA_PCIE_PIPE_P2 93 +#define CLK_INFRA_PCIE_PIPE_P3 94 +#define CLK_INFRA_133M_PCIE_CK_P0 95 +#define CLK_INFRA_133M_PCIE_CK_P1 96 +#define CLK_INFRA_133M_PCIE_CK_P2 97 +#define CLK_INFRA_133M_PCIE_CK_P3 98 + +/* ETHDMA */ + +#define CLK_ETHDMA_XGP1_EN 0 +#define CLK_ETHDMA_XGP2_EN 1 +#define CLK_ETHDMA_XGP3_EN 2 +#define CLK_ETHDMA_FE_EN 3 +#define CLK_ETHDMA_GP2_EN 4 +#define CLK_ETHDMA_GP1_EN 5 +#define CLK_ETHDMA_GP3_EN 6 +#define CLK_ETHDMA_ESW_EN 7 +#define CLK_ETHDMA_CRYPT0_EN 8 +#define CLK_ETHDMA_NR_CLK 9 + +/* SGMIISYS_0 */ + +#define CLK_SGM0_TX_EN 0 +#define CLK_SGM0_RX_EN 1 +#define CLK_SGMII0_NR_CLK 2 + +/* SGMIISYS_1 */ + +#define CLK_SGM1_TX_EN 0 +#define CLK_SGM1_RX_EN 1 +#define CLK_SGMII1_NR_CLK 2 + +/* ETHWARP */ + +#define CLK_ETHWARP_WOCPU2_EN 0 +#define CLK_ETHWARP_WOCPU1_EN 1 +#define CLK_ETHWARP_WOCPU0_EN 2 +#define CLK_ETHWARP_NR_CLK 3 + +#endif /* _DT_BINDINGS_CLK_MT7988_H */ diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index c2c50f6b5fd6f0..8ff7059ee76642 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -9,13 +9,16 @@ mediatek_setup_interfaces() case $board in asus,tuf-ax4200|\ - netcore,n60) + jdcloud,re-cs-05|\ + netcore,n60|\ + ruijie,rg-x60-pro) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" eth1 ;; bananapi,bpi-r3) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 sfp2" "eth1 wan" ;; cetron,ct3003*|\ + fzs,5gcpe-p3|\ jcg,q30-pro|\ qihoo,360t7) ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" wan @@ -31,6 +34,9 @@ mediatek_setup_interfaces() mediatek,mt7986b-rfb) ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" eth1 ;; + mediatek,mt7988a-dsa-10g-spim-snand) + ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" "eth1 eth2" + ;; glinet,gl-mt6000|\ tplink,tl-xdr4288|\ tplink,tl-xdr6088|\ @@ -83,11 +89,21 @@ mediatek_setup_macs() lan_mac=$(macaddr_add "$wan_mac" 1) label_mac=$wan_mac ;; + jdcloud,re-cs-05) + wan_mac=$(mmc_get_mac_binary factory 0x24) + lan_mac=$(mmc_get_mac_binary factory 0x2a) + label_mac=$lan_mac + ;; qihoo,360t7) lan_mac=$(mtd_get_mac_ascii factory lanMac) wan_mac=$(macaddr_add "$lan_mac" 1) label_mac=$wan_mac ;; + ruijie,rg-x60-pro) + label_mac=$(mtd_get_mac_ascii product_info ethaddr) + wan_mac=$label_mac + lan_mac=$(macaddr_add "$label_mac" 1) + ;; xiaomi,mi-router-wr30u|\ xiaomi,mi-router-ax3000t|\ xiaomi,redmi-router-ax6000) diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata index 6437dfbe621032..56a704f5a16868 100644 --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata @@ -17,7 +17,8 @@ case "$FIRMWARE" in ;; "mediatek/mt7986_eeprom_mt7976_dual.bin") case "$board" in - glinet,gl-mt6000) + glinet,gl-mt6000|\ + jdcloud,re-cs-05) caldata_extract_mmc "factory" 0x0 0x1000 ;; esac diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac index 1d3d162d12f303..42e877fac46d56 100644 --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac @@ -50,6 +50,11 @@ case "$board" in [ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress ;; + ruijie,rg-x60-pro) + addr=$(mtd_get_mac_ascii product_info ethaddr) + [ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress + ;; tplink,tl-xdr4288|\ tplink,tl-xdr6086|\ tplink,tl-xdr6088) diff --git a/target/linux/mediatek/filogic/base-files/lib/preinit/81_fix_eeprom b/target/linux/mediatek/filogic/base-files/lib/preinit/81_fix_eeprom index bbda755a979245..ee36ffe7cd6c4c 100644 --- a/target/linux/mediatek/filogic/base-files/lib/preinit/81_fix_eeprom +++ b/target/linux/mediatek/filogic/base-files/lib/preinit/81_fix_eeprom @@ -2,7 +2,8 @@ preinit_fix_eeprom() { case $(board_name) in - glinet,gl-mt6000) + glinet,gl-mt6000|\ + jdcloud,re-cs-05) mmc_part=$(find_mmc_part factory) FIRMWARE="mediatek/mt7986_eeprom_mt7976_dual.bin" [ ! -e /lib/firmware/"$FIRMWARE" ] && \ diff --git a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh index 9649a2c99b1b8a..8619c72b860ffe 100755 --- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh @@ -30,7 +30,8 @@ platform_do_upgrade() { esac ;; glinet,gl-mt2500|\ - glinet,gl-mt6000) + glinet,gl-mt6000|\ + jdcloud,re-cs-05) CI_KERNPART="kernel" CI_ROOTPART="rootfs" emmc_do_upgrade "$1" @@ -76,7 +77,8 @@ platform_copy_config() { esac ;; glinet,gl-mt2500|\ - glinet,gl-mt6000) + glinet,gl-mt6000|\ + jdcloud,re-cs-05) emmc_copy_config ;; esac diff --git a/target/linux/mediatek/filogic/config-5.15 b/target/linux/mediatek/filogic/config-5.15 index 4e15e1e1921667..31b2741cabfd5e 100644 --- a/target/linux/mediatek/filogic/config-5.15 +++ b/target/linux/mediatek/filogic/config-5.15 @@ -61,6 +61,7 @@ CONFIG_COMMON_CLK_MT7981=y CONFIG_COMMON_CLK_MT7981_ETHSYS=y CONFIG_COMMON_CLK_MT7986=y CONFIG_COMMON_CLK_MT7986_ETHSYS=y +CONFIG_COMMON_CLK_MT7988=y # CONFIG_COMMON_CLK_MT8173 is not set # CONFIG_COMMON_CLK_MT8183 is not set # CONFIG_COMMON_CLK_MT8516 is not set @@ -316,6 +317,7 @@ CONFIG_PINCTRL=y # CONFIG_PINCTRL_MT7622 is not set CONFIG_PINCTRL_MT7981=y CONFIG_PINCTRL_MT7986=y +CONFIG_PINCTRL_MT7988=y # CONFIG_PINCTRL_MT8173 is not set # CONFIG_PINCTRL_MT8183 is not set CONFIG_PINCTRL_MT8516=y @@ -361,6 +363,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_MT6380=y CONFIG_REGULATOR_RT5190A=y CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_TI_SYSCON=y CONFIG_RFS_ACCEL=y CONFIG_RODATA_FULL_DEFAULT_ENABLED=y CONFIG_RPS=y diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index 9f07d894a044f7..0e3868741b12ec 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -146,6 +146,20 @@ define Device/cetron_ct3003-mod endef TARGET_DEVICES += cetron_ct3003-mod +define Device/fzs_5gcpe-p3 + DEVICE_VENDOR := FZS + DEVICE_MODEL := 5GCPE P3 + DEVICE_DTS := mt7981b-fzs-5gcpe-p3 + DEVICE_DTS_DIR := ../dts + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 128k + PAGESIZE := 2048 + KERNEL_IN_UBI := 1 + DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3 + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef +TARGET_DEVICES += fzs_5gcpe-p3 + define Device/glinet_gl-mt2500 DEVICE_VENDOR := GL.iNet DEVICE_MODEL := GL-MT2500 @@ -215,6 +229,16 @@ define Device/jcg_q30-pro endef TARGET_DEVICES += jcg_q30-pro +define Device/jdcloud_re-cs-05 + DEVICE_VENDOR := JDCloud + DEVICE_MODEL := AX6000 + DEVICE_DTS := mt7986a-jdcloud-re-cs-05 + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := e2fsprogs f2fsck mkf2fs kmod-mt7986-firmware mt7986-wo-firmware + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef +TARGET_DEVICES += jdcloud_re-cs-05 + define Device/mediatek_mt7986a-rfb DEVICE_VENDOR := MediaTek DEVICE_MODEL := MTK7986 rfba AP @@ -256,6 +280,24 @@ define Device/mediatek_mt7986b-rfb endef TARGET_DEVICES += mediatek_mt7986b-rfb +define Device/mediatek_mt7988a-rfb-nand + DEVICE_VENDOR := MediaTek + DEVICE_MODEL := MT7988a nand rfb + DEVICE_DTS := mt7988a-dsa-10g-spim-nand + DEVICE_DTS_DIR := $(DTS_DIR)/ + KERNEL_LOADADDR := 0x48000000 + SUPPORTED_DEVICES := mediatek,mt7988a-rfb + UBINIZE_OPTS := -E 5 + BLOCKSIZE := 128k + PAGESIZE := 2048 + IMAGE_SIZE := 65536k + KERNEL_IN_UBI := 1 + IMAGES += factory.bin + IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE) + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef +TARGET_DEVICES += mediatek_mt7988a-rfb-nand + define Device/netcore_n60 DEVICE_VENDOR := Netcore DEVICE_MODEL := N60 @@ -284,6 +326,16 @@ define Device/qihoo_360t7 endef TARGET_DEVICES += qihoo_360t7 +define Device/ruijie_rg-x60-pro + DEVICE_VENDOR := Ruijie + DEVICE_MODEL := RG-X60 Pro + DEVICE_DTS := mt7986a-ruijie-rg-x60-pro + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef +TARGET_DEVICES += ruijie_rg-x60-pro + define Device/tplink_tl-common DEVICE_VENDOR := TP-Link DEVICE_DTS_DIR := ../dts diff --git a/target/linux/mediatek/mt7622/config-5.15 b/target/linux/mediatek/mt7622/config-5.15 index ce51a74867d471..47df81b14536e5 100644 --- a/target/linux/mediatek/mt7622/config-5.15 +++ b/target/linux/mediatek/mt7622/config-5.15 @@ -73,6 +73,7 @@ CONFIG_COMMON_CLK_MT7622_ETHSYS=y CONFIG_COMMON_CLK_MT7622_HIFSYS=y # CONFIG_COMMON_CLK_MT7981 is not set # CONFIG_COMMON_CLK_MT7986 is not set +# CONFIG_COMMON_CLK_MT7988 is not set # CONFIG_COMMON_CLK_MT8173 is not set # CONFIG_COMMON_CLK_MT8183 is not set # CONFIG_COMMON_CLK_MT8183_AUDIOSYS is not set @@ -339,6 +340,7 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_MT7622=y # CONFIG_PINCTRL_MT7981 is not set # CONFIG_PINCTRL_MT7986 is not set +# CONFIG_PINCTRL_MT7988 is not set # CONFIG_PINCTRL_MT8173 is not set # CONFIG_PINCTRL_MT8183 is not set CONFIG_PINCTRL_MT8516=y diff --git a/target/linux/mediatek/mt7623/config-5.15 b/target/linux/mediatek/mt7623/config-5.15 index e6a4beba77c333..5ae596d4109299 100644 --- a/target/linux/mediatek/mt7623/config-5.15 +++ b/target/linux/mediatek/mt7623/config-5.15 @@ -71,6 +71,7 @@ CONFIG_COMMON_CLK_MT2701_VDECSYS=y # CONFIG_COMMON_CLK_MT7629 is not set # CONFIG_COMMON_CLK_MT7981 is not set # CONFIG_COMMON_CLK_MT7986 is not set +# CONFIG_COMMON_CLK_MT7988 is not set # CONFIG_COMMON_CLK_MT8135 is not set # CONFIG_COMMON_CLK_MT8173 is not set CONFIG_COMMON_CLK_MT8516=y diff --git a/target/linux/mediatek/mt7629/config-5.15 b/target/linux/mediatek/mt7629/config-5.15 index ddee4c5d6e9457..fcf7ae32f6e95b 100644 --- a/target/linux/mediatek/mt7629/config-5.15 +++ b/target/linux/mediatek/mt7629/config-5.15 @@ -55,6 +55,7 @@ CONFIG_COMMON_CLK_MT7629_ETHSYS=y CONFIG_COMMON_CLK_MT7629_HIFSYS=y # CONFIG_COMMON_CLK_MT7981 is not set # CONFIG_COMMON_CLK_MT7986 is not set +# CONFIG_COMMON_CLK_MT7988 is not set # CONFIG_COMMON_CLK_MT8135 is not set # CONFIG_COMMON_CLK_MT8173 is not set CONFIG_COMMON_CLK_MT8516=y diff --git a/target/linux/mediatek/patches-5.15/100-dts-update-mt7622-rfb1.patch b/target/linux/mediatek/patches-5.15/100-dts-update-mt7622-rfb1.patch index 7224a9882c02a7..1f9e24a4d29e77 100644 --- a/target/linux/mediatek/patches-5.15/100-dts-update-mt7622-rfb1.patch +++ b/target/linux/mediatek/patches-5.15/100-dts-update-mt7622-rfb1.patch @@ -40,7 +40,7 @@ }; }; - memory { + memory@40000000 { - reg = <0 0x40000000 0 0x20000000>; + reg = <0 0x40000000 0 0x40000000>; }; diff --git a/target/linux/mediatek/patches-5.15/113-dts-fix-bpi64-leds-and-buttons.patch b/target/linux/mediatek/patches-5.15/113-dts-fix-bpi64-leds-and-buttons.patch index f88dbc71955a02..f728b965642c7c 100644 --- a/target/linux/mediatek/patches-5.15/113-dts-fix-bpi64-leds-and-buttons.patch +++ b/target/linux/mediatek/patches-5.15/113-dts-fix-bpi64-leds-and-buttons.patch @@ -53,4 +53,4 @@ + */ }; - memory { + memory@40000000 { diff --git a/target/linux/mediatek/patches-5.15/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch b/target/linux/mediatek/patches-5.15/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch new file mode 100644 index 00000000000000..cbee45bc1f89d2 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch @@ -0,0 +1,26 @@ +--- a/drivers/pinctrl/mediatek/Kconfig ++++ b/drivers/pinctrl/mediatek/Kconfig +@@ -134,6 +134,13 @@ config PINCTRL_MT7986 + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_MOORE + ++config PINCTRL_MT7988 ++ bool "Mediatek MT7988 pin control" ++ depends on OF ++ depends on ARM64 || COMPILE_TEST ++ default ARCH_MEDIATEK ++ select PINCTRL_MTK_MOORE ++ + config PINCTRL_MT8167 + bool "Mediatek MT8167 pin control" + depends on OF +--- a/drivers/pinctrl/mediatek/Makefile ++++ b/drivers/pinctrl/mediatek/Makefile +@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl- + obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o + obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7981.o + obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o ++obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o + obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o + obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o + obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o diff --git a/target/linux/mediatek/patches-5.15/241-clk-mediatek-Add-pcw-chg-shift-control.patch b/target/linux/mediatek/patches-5.15/241-clk-mediatek-Add-pcw-chg-shift-control.patch new file mode 100644 index 00000000000000..23a5b7c911a5da --- /dev/null +++ b/target/linux/mediatek/patches-5.15/241-clk-mediatek-Add-pcw-chg-shift-control.patch @@ -0,0 +1,24 @@ +--- a/drivers/clk/mediatek/clk-mtk.h ++++ b/drivers/clk/mediatek/clk-mtk.h +@@ -233,6 +233,7 @@ struct mtk_pll_data { + u32 pcw_reg; + int pcw_shift; + u32 pcw_chg_reg; ++ int pcw_chg_shift; + const struct mtk_pll_div_table *div_table; + const char *parent_name; + u32 en_reg; +--- a/drivers/clk/mediatek/clk-pll.c ++++ b/drivers/clk/mediatek/clk-pll.c +@@ -137,7 +137,10 @@ static void mtk_pll_set_rate_regs(struct + pll->data->pcw_shift); + val |= pcw << pll->data->pcw_shift; + writel(val, pll->pcw_addr); +- chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; ++ if (pll->data->pcw_chg_shift) ++ chg = readl(pll->pcw_chg_addr) | BIT(pll->data->pcw_chg_shift); ++ else ++ chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; + writel(chg, pll->pcw_chg_addr); + if (pll->tuner_addr) + writel(val + 1, pll->tuner_addr); diff --git a/target/linux/mediatek/patches-5.15/242-clk-mediatek-add-mt7988-clock-support.patch b/target/linux/mediatek/patches-5.15/242-clk-mediatek-add-mt7988-clock-support.patch new file mode 100644 index 00000000000000..bf9146352a6154 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/242-clk-mediatek-add-mt7988-clock-support.patch @@ -0,0 +1,31 @@ +--- a/drivers/clk/mediatek/Kconfig ++++ b/drivers/clk/mediatek/Kconfig +@@ -378,6 +378,15 @@ config COMMON_CLK_MT7986_ETHSYS + This driver add support for clocks for Ethernet and SGMII + required on MediaTek MT7986 SoC. + ++config COMMON_CLK_MT7988 ++ bool "Clock driver for MediaTek MT7988" ++ depends on ARCH_MEDIATEK || COMPILE_TEST ++ select COMMON_CLK_MEDIATEK ++ default ARCH_MEDIATEK ++ help ++ This driver supports MediaTek MT7988 basic clocks and clocks ++ required for various periperals found on MediaTek. ++ + config COMMON_CLK_MT8135 + bool "Clock driver for MediaTek MT8135" + depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST +--- a/drivers/clk/mediatek/Makefile ++++ b/drivers/clk/mediatek/Makefile +@@ -54,6 +54,10 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m + obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o + obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o + obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o ++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o ++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o ++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o ++obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o + obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o + obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o + obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o diff --git a/target/linux/mediatek/patches-5.15/351-cpufreq-mediatek-correct-voltages-for-MT7622-and-MT7.patch b/target/linux/mediatek/patches-5.15/351-cpufreq-mediatek-correct-voltages-for-MT7622-and-MT7.patch new file mode 100644 index 00000000000000..6ab05b897c3e39 --- /dev/null +++ b/target/linux/mediatek/patches-5.15/351-cpufreq-mediatek-correct-voltages-for-MT7622-and-MT7.patch @@ -0,0 +1,53 @@ +From e7697814c142c99f470c3458d49e41b25a575f23 Mon Sep 17 00:00:00 2001 +From: Daniel Golle +Date: Fri, 26 May 2023 10:31:40 +0100 +Subject: [PATCH] cpufreq: mediatek: correct voltages for MT7622 and MT7623 + +The MT6380 regulator typically used together with MT7622 does not +support the current maximum processor and SRAM voltage in the cpufreq +driver (1360000uV). +For MT7622 limit processor and SRAM supply voltages to 1350000uV to +avoid having the tracking algorithm request unsupported voltages from +the regulator. + +On MT7623 there is no separate SRAM supply and the maximum voltage used +is 1300000uV. Create dedicated platform data for MT7623 to cover that +case as well. + +Fixes: 0883426fd07e3 ("cpufreq: mediatek: Raise proc and sram max voltage for MT7622/7623") +Suggested-by: Jia-wei Chang +Signed-off-by: Daniel Golle +--- + drivers/cpufreq/mediatek-cpufreq.c | 13 ++++++++++--- + 1 file changed, 10 insertions(+), 3 deletions(-) + +--- a/drivers/cpufreq/mediatek-cpufreq.c ++++ b/drivers/cpufreq/mediatek-cpufreq.c +@@ -696,9 +696,16 @@ static const struct mtk_cpufreq_platform + static const struct mtk_cpufreq_platform_data mt7622_platform_data = { + .min_volt_shift = 100000, + .max_volt_shift = 200000, +- .proc_max_volt = 1360000, ++ .proc_max_volt = 1350000, + .sram_min_volt = 0, +- .sram_max_volt = 1360000, ++ .sram_max_volt = 1350000, ++ .ccifreq_supported = false, ++}; ++ ++static const struct mtk_cpufreq_platform_data mt7623_platform_data = { ++ .min_volt_shift = 100000, ++ .max_volt_shift = 200000, ++ .proc_max_volt = 1300000, + .ccifreq_supported = false, + }; + +@@ -743,7 +750,7 @@ static const struct of_device_id mtk_cpu + { .compatible = "mediatek,mt2701", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt2712", .data = &mt2701_platform_data }, + { .compatible = "mediatek,mt7622", .data = &mt7622_platform_data }, +- { .compatible = "mediatek,mt7623", .data = &mt7622_platform_data }, ++ { .compatible = "mediatek,mt7623", .data = &mt7623_platform_data }, + { .compatible = "mediatek,mt7988", .data = &mt7988_platform_data }, + { .compatible = "mediatek,mt8167", .data = &mt8516_platform_data }, + { .compatible = "mediatek,mt817x", .data = &mt2701_platform_data }, diff --git a/target/linux/mediatek/patches-5.15/351-cpufreq-mediatek-don-t-request-unsupported-voltage.patch b/target/linux/mediatek/patches-5.15/351-cpufreq-mediatek-don-t-request-unsupported-voltage.patch deleted file mode 100644 index a7a4bd8ea2bba9..00000000000000 --- a/target/linux/mediatek/patches-5.15/351-cpufreq-mediatek-don-t-request-unsupported-voltage.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 20aad28ba5d62f1618408c264384d0b2ad7417db Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Mon, 22 May 2023 23:25:48 +0100 -Subject: [PATCH] cpufreq: mediatek: don't request unsupported voltage - -PMICs on MT7622 and MT7623 boards only support up to 1350000uV despite -the SoC's processor and SRAM voltage can be up to 1360000uV. As a -work-around specify max. processor and SRAM voltage as 1350000uV to -avoid requesting an unsupported voltage from the regulator. - -Signed-off-by: Daniel Golle ---- - drivers/cpufreq/mediatek-cpufreq.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/cpufreq/mediatek-cpufreq.c -+++ b/drivers/cpufreq/mediatek-cpufreq.c -@@ -696,9 +696,9 @@ static const struct mtk_cpufreq_platform - static const struct mtk_cpufreq_platform_data mt7622_platform_data = { - .min_volt_shift = 100000, - .max_volt_shift = 200000, -- .proc_max_volt = 1360000, -+ .proc_max_volt = 1350000, - .sram_min_volt = 0, -- .sram_max_volt = 1360000, -+ .sram_max_volt = 1350000, - .ccifreq_supported = false, - }; - diff --git a/target/linux/mediatek/patches-5.15/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch b/target/linux/mediatek/patches-5.15/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch index 0d9fa0550b23d1..69f2d2a545dcf4 100644 --- a/target/linux/mediatek/patches-5.15/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch +++ b/target/linux/mediatek/patches-5.15/850-v6.0-i2c-move-drivers-from-strlcpy-to-strscpy.patch @@ -237,7 +237,7 @@ Signed-off-by: Wolfram Sang priv->adap.algo = &hix5hd2_i2c_algorithm; --- a/drivers/i2c/busses/i2c-i801.c +++ b/drivers/i2c/busses/i2c-i801.c -@@ -1111,7 +1111,7 @@ static void dmi_check_onboard_device(u8 +@@ -1110,7 +1110,7 @@ static void dmi_check_onboard_device(u8 memset(&info, 0, sizeof(struct i2c_board_info)); info.addr = dmi_devices[i].i2c_addr; @@ -246,7 +246,7 @@ Signed-off-by: Wolfram Sang i2c_new_client_device(adap, &info); break; } -@@ -1267,7 +1267,7 @@ static void register_dell_lis3lv02d_i2c_ +@@ -1266,7 +1266,7 @@ static void register_dell_lis3lv02d_i2c_ memset(&info, 0, sizeof(struct i2c_board_info)); info.addr = dell_lis3lv02d_devices[i].i2c_addr; @@ -403,7 +403,7 @@ Signed-off-by: Wolfram Sang /* Slow down if we can't sense SCL */ --- a/drivers/i2c/busses/i2c-pxa.c +++ b/drivers/i2c/busses/i2c-pxa.c -@@ -1403,7 +1403,7 @@ static int i2c_pxa_probe(struct platform +@@ -1463,7 +1463,7 @@ static int i2c_pxa_probe(struct platform spin_lock_init(&i2c->lock); init_waitqueue_head(&i2c->wait); diff --git a/target/linux/mediatek/patches-5.15/901-arm-add-cmdline-override.patch b/target/linux/mediatek/patches-5.15/901-arm-add-cmdline-override.patch index 9557279c3d5b19..c51f7576d06432 100644 --- a/target/linux/mediatek/patches-5.15/901-arm-add-cmdline-override.patch +++ b/target/linux/mediatek/patches-5.15/901-arm-add-cmdline-override.patch @@ -37,7 +37,7 @@ * managed to set the command line, unless CONFIG_CMDLINE_FORCE --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig -@@ -2058,6 +2058,14 @@ config CMDLINE_FORCE +@@ -2060,6 +2060,14 @@ config CMDLINE_FORCE endchoice diff --git a/target/linux/mpc85xx/patches-5.10/102-powerpc-add-cmdline-override.patch b/target/linux/mpc85xx/patches-5.10/102-powerpc-add-cmdline-override.patch index a56cb665821d29..95ce5f2bb914a6 100644 --- a/target/linux/mpc85xx/patches-5.10/102-powerpc-add-cmdline-override.patch +++ b/target/linux/mpc85xx/patches-5.10/102-powerpc-add-cmdline-override.patch @@ -17,9 +17,9 @@ help --- a/drivers/of/fdt.c +++ b/drivers/of/fdt.c -@@ -1056,6 +1056,17 @@ int __init early_init_dt_scan_chosen(uns +@@ -1058,6 +1058,17 @@ int __init early_init_dt_scan_chosen(uns if (p != NULL && l > 0) - strlcpy(data, p, min(l, COMMAND_LINE_SIZE)); + strlcat(data, p, min_t(int, strlen(data) + (int)l, COMMAND_LINE_SIZE)); + /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different + * device tree option of chosen/bootargs-override. This is diff --git a/target/linux/mpc85xx/patches-5.4/102-powerpc-add-cmdline-override.patch b/target/linux/mpc85xx/patches-5.4/102-powerpc-add-cmdline-override.patch index 924ce9307e2711..34247aa778f5e4 100644 --- a/target/linux/mpc85xx/patches-5.4/102-powerpc-add-cmdline-override.patch +++ b/target/linux/mpc85xx/patches-5.4/102-powerpc-add-cmdline-override.patch @@ -17,7 +17,7 @@ help --- a/drivers/of/fdt.c +++ b/drivers/of/fdt.c -@@ -1060,6 +1060,17 @@ int __init early_init_dt_scan_chosen(uns +@@ -1059,6 +1059,17 @@ int __init early_init_dt_scan_chosen(uns if (p != NULL && l > 0) strlcpy(data, p, min(l, COMMAND_LINE_SIZE)); diff --git a/target/linux/mvebu/patches-5.10/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/mvebu/patches-5.10/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch index 04c80113c15234..c220e906cfa85a 100644 --- a/target/linux/mvebu/patches-5.10/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch +++ b/target/linux/mvebu/patches-5.10/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch @@ -28,7 +28,7 @@ Signed-off-by: Michael Gray --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig -@@ -1777,6 +1777,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN +@@ -1778,6 +1778,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN The command-line arguments provided by the boot loader will be appended to the the device tree bootargs property. @@ -176,7 +176,7 @@ Signed-off-by: Michael Gray } --- a/init/main.c +++ b/init/main.c -@@ -110,6 +110,10 @@ +@@ -108,6 +108,10 @@ #include @@ -187,7 +187,7 @@ Signed-off-by: Michael Gray static int kernel_init(void *); extern void init_IRQ(void); -@@ -904,6 +908,18 @@ asmlinkage __visible void __init __no_sa +@@ -901,6 +905,18 @@ asmlinkage __visible void __init __no_sa page_alloc_init(); pr_notice("Kernel command line: %s\n", saved_command_line); diff --git a/target/linux/mvebu/patches-5.10/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch b/target/linux/mvebu/patches-5.10/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch index 577a9b40def5f8..a216b8c08b2443 100644 --- a/target/linux/mvebu/patches-5.10/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch +++ b/target/linux/mvebu/patches-5.10/907-MAINTAINERS-Add-an-entry-for-the-IEI-WT61P803-PUZZLE.patch @@ -16,7 +16,7 @@ Cc: Robert Marko --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -8538,6 +8538,22 @@ F: include/net/nl802154.h +@@ -8531,6 +8531,22 @@ F: include/net/nl802154.h F: net/ieee802154/ F: net/mac802154/ diff --git a/target/linux/mvebu/patches-5.15/102-leds-turris-omnia-support-HW-controlled-mode-via-pri.patch b/target/linux/mvebu/patches-5.15/102-leds-turris-omnia-support-HW-controlled-mode-via-pri.patch index c14469460a76cf..34e3ce9a13925c 100644 --- a/target/linux/mvebu/patches-5.15/102-leds-turris-omnia-support-HW-controlled-mode-via-pri.patch +++ b/target/linux/mvebu/patches-5.15/102-leds-turris-omnia-support-HW-controlled-mode-via-pri.patch @@ -54,9 +54,9 @@ Signed-off-by: Marek Behún side of CZ.NIC's Turris Omnia router. There are 12 RGB LEDs on the --- a/drivers/leds/leds-turris-omnia.c +++ b/drivers/leds/leds-turris-omnia.c -@@ -41,6 +41,39 @@ struct omnia_leds { - struct omnia_led leds[]; - }; +@@ -72,6 +72,39 @@ static int omnia_cmd_read_u8(const struc + return -EIO; + } +static struct led_hw_trigger_type omnia_hw_trigger_type; + @@ -94,7 +94,7 @@ Signed-off-by: Marek Behún static int omnia_led_brightness_set_blocking(struct led_classdev *cdev, enum led_brightness brightness) { -@@ -112,6 +145,8 @@ static int omnia_led_register(struct i2c +@@ -143,6 +176,8 @@ static int omnia_led_register(struct i2c cdev = &led->mc_cdev.led_cdev; cdev->max_brightness = 255; cdev->brightness_set_blocking = omnia_led_brightness_set_blocking; @@ -102,8 +102,8 @@ Signed-off-by: Marek Behún + cdev->default_trigger = omnia_hw_trigger.name; /* put the LED into software mode */ - ret = i2c_smbus_write_byte_data(client, CMD_LED_MODE, -@@ -228,6 +263,12 @@ static int omnia_leds_probe(struct i2c_c + ret = omnia_cmd_write_u8(client, CMD_LED_MODE, +@@ -249,6 +284,12 @@ static int omnia_leds_probe(struct i2c_c mutex_init(&leds->lock); diff --git a/target/linux/mvebu/patches-5.15/103-leds-turris-omnia-initialize-multi-intensity-to-full.patch b/target/linux/mvebu/patches-5.15/103-leds-turris-omnia-initialize-multi-intensity-to-full.patch index 1fe76b8f2cfcf4..b6f7da64a72214 100644 --- a/target/linux/mvebu/patches-5.15/103-leds-turris-omnia-initialize-multi-intensity-to-full.patch +++ b/target/linux/mvebu/patches-5.15/103-leds-turris-omnia-initialize-multi-intensity-to-full.patch @@ -17,7 +17,7 @@ Signed-off-by: Marek Behún --- a/drivers/leds/leds-turris-omnia.c +++ b/drivers/leds/leds-turris-omnia.c -@@ -131,10 +131,13 @@ static int omnia_led_register(struct i2c +@@ -162,10 +162,13 @@ static int omnia_led_register(struct i2c } led->subled_info[0].color_index = LED_COLOR_ID_RED; diff --git a/target/linux/mvebu/patches-5.15/104-leds-turris-omnia-change-max-brightness-from-255-to-.patch b/target/linux/mvebu/patches-5.15/104-leds-turris-omnia-change-max-brightness-from-255-to-.patch index fb8864dfd1d39f..6d6d4cec706738 100644 --- a/target/linux/mvebu/patches-5.15/104-leds-turris-omnia-change-max-brightness-from-255-to-.patch +++ b/target/linux/mvebu/patches-5.15/104-leds-turris-omnia-change-max-brightness-from-255-to-.patch @@ -20,7 +20,7 @@ Signed-off-by: Marek Behún --- a/drivers/leds/leds-turris-omnia.c +++ b/drivers/leds/leds-turris-omnia.c -@@ -146,7 +146,7 @@ static int omnia_led_register(struct i2c +@@ -177,7 +177,7 @@ static int omnia_led_register(struct i2c init_data.fwnode = &np->fwnode; cdev = &led->mc_cdev.led_cdev; diff --git a/target/linux/mvebu/patches-5.15/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/mvebu/patches-5.15/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch index a54a424e23aee7..72041e000579b1 100644 --- a/target/linux/mvebu/patches-5.15/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch +++ b/target/linux/mvebu/patches-5.15/300-mvebu-Mangle-bootloader-s-kernel-arguments.patch @@ -187,7 +187,7 @@ Signed-off-by: Michael Gray static int kernel_init(void *); extern void init_IRQ(void); -@@ -988,6 +992,18 @@ asmlinkage __visible void __init __no_sa +@@ -992,6 +996,18 @@ asmlinkage __visible void __init __no_sa page_alloc_init(); pr_notice("Kernel command line: %s\n", saved_command_line); diff --git a/target/linux/oxnas/patches-5.10/996-generic-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/oxnas/patches-5.10/996-generic-Mangle-bootloader-s-kernel-arguments.patch index 8f56bdbf9c291c..de2868ce979d6c 100644 --- a/target/linux/oxnas/patches-5.10/996-generic-Mangle-bootloader-s-kernel-arguments.patch +++ b/target/linux/oxnas/patches-5.10/996-generic-Mangle-bootloader-s-kernel-arguments.patch @@ -22,7 +22,7 @@ Signed-off-by: Adrian Panella --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig -@@ -1777,6 +1777,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN +@@ -1778,6 +1778,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN The command-line arguments provided by the boot loader will be appended to the the device tree bootargs property. @@ -157,7 +157,7 @@ Signed-off-by: Adrian Panella } --- a/init/main.c +++ b/init/main.c -@@ -110,6 +110,10 @@ +@@ -108,6 +108,10 @@ #include @@ -168,7 +168,7 @@ Signed-off-by: Adrian Panella static int kernel_init(void *); extern void init_IRQ(void); -@@ -904,6 +908,18 @@ asmlinkage __visible void __init __no_sa +@@ -901,6 +905,18 @@ asmlinkage __visible void __init __no_sa page_alloc_init(); pr_notice("Kernel command line: %s\n", saved_command_line); diff --git a/target/linux/oxnas/patches-5.10/999-libata-hacks.patch b/target/linux/oxnas/patches-5.10/999-libata-hacks.patch index 461a1b87f4c2ff..beceb91062daa3 100644 --- a/target/linux/oxnas/patches-5.10/999-libata-hacks.patch +++ b/target/linux/oxnas/patches-5.10/999-libata-hacks.patch @@ -36,7 +36,7 @@ --- a/include/linux/libata.h +++ b/include/linux/libata.h -@@ -912,6 +912,8 @@ struct ata_port_operations { +@@ -916,6 +916,8 @@ struct ata_port_operations { enum ata_completion_errors (*qc_prep)(struct ata_queued_cmd *qc); unsigned int (*qc_issue)(struct ata_queued_cmd *qc); bool (*qc_fill_rtf)(struct ata_queued_cmd *qc); @@ -45,7 +45,7 @@ /* * Configuration and exception handling -@@ -1002,6 +1004,9 @@ struct ata_port_operations { +@@ -1006,6 +1008,9 @@ struct ata_port_operations { void (*phy_reset)(struct ata_port *ap); void (*eng_timeout)(struct ata_port *ap); diff --git a/target/linux/ramips/patches-5.10/314-MIPS-add-bootargs-override-property.patch b/target/linux/ramips/patches-5.10/314-MIPS-add-bootargs-override-property.patch index a5df046ba745a4..ef45aac61bda92 100644 --- a/target/linux/ramips/patches-5.10/314-MIPS-add-bootargs-override-property.patch +++ b/target/linux/ramips/patches-5.10/314-MIPS-add-bootargs-override-property.patch @@ -17,7 +17,7 @@ Signed-off-by: David Bauer --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c -@@ -542,8 +542,28 @@ static int __init bootcmdline_scan_chose +@@ -545,8 +545,28 @@ static int __init bootcmdline_scan_chose #endif /* CONFIG_OF_EARLY_FLATTREE */ @@ -46,7 +46,7 @@ Signed-off-by: David Bauer bool dt_bootargs = false; /* -@@ -557,6 +577,14 @@ static void __init bootcmdline_init(void +@@ -560,6 +580,14 @@ static void __init bootcmdline_init(void } /* diff --git a/target/linux/ramips/patches-5.10/315-owrt-hack-fix-mt7688-cache-issue.patch b/target/linux/ramips/patches-5.10/315-owrt-hack-fix-mt7688-cache-issue.patch index 59d4b3ce564fbf..0476847c3ba48d 100644 --- a/target/linux/ramips/patches-5.10/315-owrt-hack-fix-mt7688-cache-issue.patch +++ b/target/linux/ramips/patches-5.10/315-owrt-hack-fix-mt7688-cache-issue.patch @@ -10,7 +10,7 @@ Signed-off-by: John Crispin --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c -@@ -694,8 +694,6 @@ static void __init arch_mem_init(char ** +@@ -697,8 +697,6 @@ static void __init arch_mem_init(char ** if (crashk_res.start != crashk_res.end) memblock_reserve(crashk_res.start, resource_size(&crashk_res)); #endif @@ -19,7 +19,7 @@ Signed-off-by: John Crispin /* * In order to reduce the possibility of kernel panic when failed to * get IO TLB memory under CONFIG_SWIOTLB, it is better to allocate -@@ -815,6 +813,7 @@ void __init setup_arch(char **cmdline_p) +@@ -818,6 +816,7 @@ void __init setup_arch(char **cmdline_p) cpu_cache_init(); paging_init(); diff --git a/target/linux/ramips/patches-5.10/405-mtd-spi-nor-Add-support-for-BoHong-bh25q128as.patch b/target/linux/ramips/patches-5.10/405-mtd-spi-nor-Add-support-for-BoHong-bh25q128as.patch index a887171139bc51..d45b99812f9f5a 100644 --- a/target/linux/ramips/patches-5.10/405-mtd-spi-nor-Add-support-for-BoHong-bh25q128as.patch +++ b/target/linux/ramips/patches-5.10/405-mtd-spi-nor-Add-support-for-BoHong-bh25q128as.patch @@ -55,7 +55,7 @@ Signed-off-by: David Bauer +}; --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c -@@ -2021,6 +2021,7 @@ int spi_nor_sr2_bit7_quad_enable(struct +@@ -2022,6 +2022,7 @@ int spi_nor_sr2_bit7_quad_enable(struct static const struct spi_nor_manufacturer *manufacturers[] = { &spi_nor_atmel, diff --git a/target/linux/ramips/patches-5.10/700-net-ethernet-mediatek-support-net-labels.patch b/target/linux/ramips/patches-5.10/700-net-ethernet-mediatek-support-net-labels.patch index 8eeecfc2595b0e..7148ec3e81f360 100644 --- a/target/linux/ramips/patches-5.10/700-net-ethernet-mediatek-support-net-labels.patch +++ b/target/linux/ramips/patches-5.10/700-net-ethernet-mediatek-support-net-labels.patch @@ -14,7 +14,7 @@ Signed-off-by: René van Dorst --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -2979,6 +2979,7 @@ static const struct net_device_ops mtk_n +@@ -2982,6 +2982,7 @@ static const struct net_device_ops mtk_n static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) { @@ -22,7 +22,7 @@ Signed-off-by: René van Dorst const __be32 *_id = of_get_property(np, "reg", NULL); phy_interface_t phy_mode; struct phylink *phylink; -@@ -3074,6 +3075,9 @@ static int mtk_add_mac(struct mtk_eth *e +@@ -3077,6 +3078,9 @@ static int mtk_add_mac(struct mtk_eth *e else eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; diff --git a/target/linux/ramips/patches-5.10/720-Revert-net-phy-simplify-phy_link_change-arguments.patch b/target/linux/ramips/patches-5.10/720-Revert-net-phy-simplify-phy_link_change-arguments.patch index f3df206f3e18a3..6f2ddd1dd05d18 100644 --- a/target/linux/ramips/patches-5.10/720-Revert-net-phy-simplify-phy_link_change-arguments.patch +++ b/target/linux/ramips/patches-5.10/720-Revert-net-phy-simplify-phy_link_change-arguments.patch @@ -95,7 +95,7 @@ still required by target/linux/ramips/files/drivers/net/ethernet/ralink/mdio.c phydev->mii_ts->link_state(phydev->mii_ts, phydev); --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c -@@ -931,7 +931,8 @@ void phylink_destroy(struct phylink *pl) +@@ -932,7 +932,8 @@ void phylink_destroy(struct phylink *pl) } EXPORT_SYMBOL_GPL(phylink_destroy); diff --git a/target/linux/ramips/patches-5.10/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch b/target/linux/ramips/patches-5.10/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch index 544b1d267e5126..746a3ac70a5c13 100644 --- a/target/linux/ramips/patches-5.10/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch +++ b/target/linux/ramips/patches-5.10/830-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch @@ -25,7 +25,7 @@ Signed-off-by: John Crispin --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig -@@ -1102,3 +1102,5 @@ config MMC_OWL +@@ -1103,3 +1103,5 @@ config MMC_OWL config MMC_SDHCI_EXTERNAL_DMA bool diff --git a/target/linux/ramips/patches-5.10/903-mtkhnat-add-support-for-interface-acceleration.patch b/target/linux/ramips/patches-5.10/903-mtkhnat-add-support-for-interface-acceleration.patch index 4e2fd231446e70..a6b27de4b023ea 100644 --- a/target/linux/ramips/patches-5.10/903-mtkhnat-add-support-for-interface-acceleration.patch +++ b/target/linux/ramips/patches-5.10/903-mtkhnat-add-support-for-interface-acceleration.patch @@ -1,6 +1,6 @@ --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h -@@ -1027,6 +1027,8 @@ struct netdev_net_notifier { +@@ -1030,6 +1030,8 @@ struct netdev_net_notifier { struct notifier_block *nb; }; @@ -9,7 +9,7 @@ /* * This structure defines the management hooks for network devices. * The following hooks can be defined; unless noted otherwise, they are -@@ -1568,6 +1570,7 @@ struct net_device_ops { +@@ -1571,6 +1573,7 @@ struct net_device_ops { struct net_device * (*ndo_get_peer_dev)(struct net_device *dev); int (*ndo_fill_forward_path)(struct net_device_path_ctx *ctx, struct net_device_path *path); diff --git a/target/linux/ramips/patches-5.15/700-net-ethernet-mediatek-support-net-labels.patch b/target/linux/ramips/patches-5.15/700-net-ethernet-mediatek-support-net-labels.patch index 315d85f34e4409..cd3c3e262bd8bd 100644 --- a/target/linux/ramips/patches-5.15/700-net-ethernet-mediatek-support-net-labels.patch +++ b/target/linux/ramips/patches-5.15/700-net-ethernet-mediatek-support-net-labels.patch @@ -14,7 +14,7 @@ Signed-off-by: René van Dorst --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c -@@ -4246,6 +4246,7 @@ static const struct net_device_ops mtk_n +@@ -4618,6 +4618,7 @@ static const struct net_device_ops mtk_n static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) { @@ -22,7 +22,7 @@ Signed-off-by: René van Dorst const __be32 *_id = of_get_property(np, "reg", NULL); phy_interface_t phy_mode; struct phylink *phylink; -@@ -4385,6 +4386,9 @@ static int mtk_add_mac(struct mtk_eth *e +@@ -4787,6 +4788,9 @@ static int mtk_add_mac(struct mtk_eth *e register_netdevice_notifier(&mac->device_notifier); } diff --git a/target/linux/ramips/patches-5.15/720-Revert-net-phy-simplify-phy_link_change-arguments.patch b/target/linux/ramips/patches-5.15/720-Revert-net-phy-simplify-phy_link_change-arguments.patch index e12356a2d7fc2c..f04a264a082277 100644 --- a/target/linux/ramips/patches-5.15/720-Revert-net-phy-simplify-phy_link_change-arguments.patch +++ b/target/linux/ramips/patches-5.15/720-Revert-net-phy-simplify-phy_link_change-arguments.patch @@ -95,7 +95,7 @@ still required by target/linux/ramips/files/drivers/net/ethernet/ralink/mdio.c phydev->mii_ts->link_state(phydev->mii_ts, phydev); --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c -@@ -1333,7 +1333,8 @@ void phylink_destroy(struct phylink *pl) +@@ -1334,7 +1334,8 @@ void phylink_destroy(struct phylink *pl) } EXPORT_SYMBOL_GPL(phylink_destroy); diff --git a/target/linux/ramips/patches-5.4/0024-GPIO-add-named-gpio-exports.patch b/target/linux/ramips/patches-5.4/0024-GPIO-add-named-gpio-exports.patch index a7f1a48bd94734..e213b850e1bbff 100644 --- a/target/linux/ramips/patches-5.4/0024-GPIO-add-named-gpio-exports.patch +++ b/target/linux/ramips/patches-5.4/0024-GPIO-add-named-gpio-exports.patch @@ -93,7 +93,7 @@ Signed-off-by: John Crispin +module_platform_driver(gpio_export_driver); --- a/drivers/gpio/gpiolib-sysfs.c +++ b/drivers/gpio/gpiolib-sysfs.c -@@ -571,7 +571,7 @@ static struct class gpio_class = { +@@ -574,7 +574,7 @@ static struct class gpio_class = { * * Returns zero on success, else an error. */ @@ -102,7 +102,7 @@ Signed-off-by: John Crispin { struct gpio_chip *chip; struct gpio_device *gdev; -@@ -633,6 +633,8 @@ int gpiod_export(struct gpio_desc *desc, +@@ -636,6 +636,8 @@ int gpiod_export(struct gpio_desc *desc, offset = gpio_chip_hwgpio(desc); if (chip->names && chip->names[offset]) ioname = chip->names[offset]; @@ -111,7 +111,7 @@ Signed-off-by: John Crispin dev = device_create_with_groups(&gpio_class, &gdev->dev, MKDEV(0, 0), data, gpio_groups, -@@ -654,6 +656,12 @@ err_unlock: +@@ -657,6 +659,12 @@ err_unlock: gpiod_dbg(desc, "%s: status %d\n", __func__, status); return status; } diff --git a/target/linux/rockchip/patches-5.10/002-net-usb-r8152-add-LED-configuration-from-OF.patch b/target/linux/rockchip/patches-5.10/002-net-usb-r8152-add-LED-configuration-from-OF.patch index 51b4d87e6caf61..63e1feb83e0777 100644 --- a/target/linux/rockchip/patches-5.10/002-net-usb-r8152-add-LED-configuration-from-OF.patch +++ b/target/linux/rockchip/patches-5.10/002-net-usb-r8152-add-LED-configuration-from-OF.patch @@ -22,7 +22,7 @@ Signed-off-by: David Bauer #include #include #include -@@ -6782,6 +6783,22 @@ static void rtl_tally_reset(struct r8152 +@@ -6785,6 +6786,22 @@ static void rtl_tally_reset(struct r8152 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); } @@ -45,7 +45,7 @@ Signed-off-by: David Bauer static void r8152b_init(struct r8152 *tp) { u32 ocp_data; -@@ -6823,6 +6840,8 @@ static void r8152b_init(struct r8152 *tp +@@ -6826,6 +6843,8 @@ static void r8152b_init(struct r8152 *tp ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); @@ -54,7 +54,7 @@ Signed-off-by: David Bauer } static void r8153_init(struct r8152 *tp) -@@ -6963,6 +6982,8 @@ static void r8153_init(struct r8152 *tp) +@@ -6966,6 +6985,8 @@ static void r8153_init(struct r8152 *tp) tp->coalesce = COALESCE_SLOW; break; } @@ -63,7 +63,7 @@ Signed-off-by: David Bauer } static void r8153b_init(struct r8152 *tp) -@@ -7045,6 +7066,8 @@ static void r8153b_init(struct r8152 *tp +@@ -7048,6 +7069,8 @@ static void r8153b_init(struct r8152 *tp rtl_tally_reset(tp); tp->coalesce = 15000; /* 15 us */ diff --git a/target/linux/rockchip/patches-5.10/104-rockchip-use-USB-host-by-default-on-rk3399-rock-pi-4.patch b/target/linux/rockchip/patches-5.10/104-rockchip-use-USB-host-by-default-on-rk3399-rock-pi-4.patch deleted file mode 100644 index 56166783a5815a..00000000000000 --- a/target/linux/rockchip/patches-5.10/104-rockchip-use-USB-host-by-default-on-rk3399-rock-pi-4.patch +++ /dev/null @@ -1,32 +0,0 @@ -From e12f67fe83446432ef16704c22ec23bd1dbcd094 Mon Sep 17 00:00:00 2001 -From: Vicente Bergas -Date: Tue, 1 Dec 2020 16:41:32 +0100 -Subject: arm64: dts: rockchip: use USB host by default on rk3399-rock-pi-4 - -Based on the board schematics at -https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi_4c_v12_sch_20200620.pdf -on page 19 there is an USB Type-A receptacle being used as an USB-OTG port. - -But the Type-A connector is not valid for OTG operation, for this reason -there is a switch to select host or device role. -This is non-compliant and error prone because switching is manual. -So, use host mode as it corresponds for a Type-A receptacle. - -Signed-off-by: Vicente Bergas -Link: https://lore.kernel.org/r/20201201154132.1286-4-vicencb@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -@@ -679,7 +679,7 @@ - - &usbdrd_dwc3_0 { - status = "okay"; -- dr_mode = "otg"; -+ dr_mode = "host"; - }; - - &usbdrd3_1 { diff --git a/target/linux/rockchip/patches-5.10/107-mmc-core-set-initial-signal-voltage-on-power-off.patch b/target/linux/rockchip/patches-5.10/107-mmc-core-set-initial-signal-voltage-on-power-off.patch index 454ce107f75aa2..9f92e4bea87016 100644 --- a/target/linux/rockchip/patches-5.10/107-mmc-core-set-initial-signal-voltage-on-power-off.patch +++ b/target/linux/rockchip/patches-5.10/107-mmc-core-set-initial-signal-voltage-on-power-off.patch @@ -24,7 +24,7 @@ Signed-off-by: Jonas Karlman --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c -@@ -1360,6 +1360,8 @@ void mmc_power_off(struct mmc_host *host +@@ -1365,6 +1365,8 @@ void mmc_power_off(struct mmc_host *host mmc_pwrseq_power_off(host); diff --git a/target/linux/rockchip/patches-5.10/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch b/target/linux/rockchip/patches-5.10/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch index 4f18b5c8d50600..e53e4bfdf5bf05 100644 --- a/target/linux/rockchip/patches-5.10/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch +++ b/target/linux/rockchip/patches-5.10/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch @@ -31,7 +31,7 @@ Signed-off-by: wevsty reg = <0x0 0xff100000 0x0 0x1000>; --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1905,6 +1905,16 @@ +@@ -1907,6 +1907,16 @@ }; }; diff --git a/target/linux/rockchip/patches-5.10/805-PM-devfreq-rockchip-dfi-add-more-soc-support.patch b/target/linux/rockchip/patches-5.10/805-PM-devfreq-rockchip-dfi-add-more-soc-support.patch index 283e4abd2f8b5a..a8f2af81792af8 100644 --- a/target/linux/rockchip/patches-5.10/805-PM-devfreq-rockchip-dfi-add-more-soc-support.patch +++ b/target/linux/rockchip/patches-5.10/805-PM-devfreq-rockchip-dfi-add-more-soc-support.patch @@ -557,12 +557,11 @@ Signed-off-by: hmz007 data->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(data->regs)) -@@ -202,21 +582,97 @@ static int rockchip_dfi_probe(struct pla - if (IS_ERR(data->regmap_pmu)) - return PTR_ERR(data->regmap_pmu); - } +@@ -203,21 +583,95 @@ static int rockchip_dfi_probe(struct pla + if (IS_ERR(data->regmap_pmu)) + return PTR_ERR(data->regmap_pmu); + - data->dev = dev; -+ + regmap_read(data->regmap_pmu, PMUGRF_OS_REG2, &val); + data->dram_type = READ_DRAMTYPE_INFO(val); + data->ch_msk = READ_CH_INFO(val); @@ -645,7 +644,6 @@ Signed-off-by: hmz007 + } else { + return 0; + } -+ desc->driver_data = data; desc->name = np->name; data->desc = desc; diff --git a/target/linux/rockchip/patches-5.15/010-v5.16-net-stmmac-Add-GFP_DMA32-for-rx-buffers-if-no-64.patch b/target/linux/rockchip/patches-5.15/010-v5.16-net-stmmac-Add-GFP_DMA32-for-rx-buffers-if-no-64.patch index 1075c754c1c912..ce479f9734691a 100644 --- a/target/linux/rockchip/patches-5.15/010-v5.16-net-stmmac-Add-GFP_DMA32-for-rx-buffers-if-no-64.patch +++ b/target/linux/rockchip/patches-5.15/010-v5.16-net-stmmac-Add-GFP_DMA32-for-rx-buffers-if-no-64.patch @@ -15,7 +15,7 @@ Signed-off-by: David S. Miller --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c -@@ -1487,16 +1487,20 @@ static int stmmac_init_rx_buffers(struct +@@ -1488,16 +1488,20 @@ static int stmmac_init_rx_buffers(struct { struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; @@ -38,7 +38,7 @@ Signed-off-by: David S. Miller if (!buf->sec_page) return -ENOMEM; -@@ -4633,6 +4637,10 @@ static inline void stmmac_rx_refill(stru +@@ -4631,6 +4635,10 @@ static inline void stmmac_rx_refill(stru struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; int dirty = stmmac_rx_dirty(priv, queue); unsigned int entry = rx_q->dirty_rx; @@ -49,7 +49,7 @@ Signed-off-by: David S. Miller while (dirty-- > 0) { struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; -@@ -4645,13 +4653,13 @@ static inline void stmmac_rx_refill(stru +@@ -4643,13 +4651,13 @@ static inline void stmmac_rx_refill(stru p = rx_q->dma_rx + entry; if (!buf->page) { diff --git a/target/linux/rockchip/patches-5.15/072-v6.2-net-phy-Add-driver-for-Motorcomm-yt8521.patch b/target/linux/rockchip/patches-5.15/072-v6.2-net-phy-Add-driver-for-Motorcomm-yt8521.patch index 6ab8248578d2ee..8dd5e6338d74a6 100644 --- a/target/linux/rockchip/patches-5.15/072-v6.2-net-phy-Add-driver-for-Motorcomm-yt8521.patch +++ b/target/linux/rockchip/patches-5.15/072-v6.2-net-phy-Add-driver-for-Motorcomm-yt8521.patch @@ -21,7 +21,7 @@ Signed-off-by: David S. Miller --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -12691,6 +12691,7 @@ F: include/uapi/linux/meye.h +@@ -12694,6 +12694,7 @@ F: include/uapi/linux/meye.h MOTORCOMM PHY DRIVER M: Peter Geis diff --git a/target/linux/rockchip/patches-5.15/101-net-realtek-r8169-add-LED-configuration-from-OF.patch b/target/linux/rockchip/patches-5.15/101-net-realtek-r8169-add-LED-configuration-from-OF.patch index 88c7c0bbd01323..f98917ef31fb6d 100644 --- a/target/linux/rockchip/patches-5.15/101-net-realtek-r8169-add-LED-configuration-from-OF.patch +++ b/target/linux/rockchip/patches-5.15/101-net-realtek-r8169-add-LED-configuration-from-OF.patch @@ -25,7 +25,7 @@ Subject: [PATCH] r8169: add LED configuration from OF TxDescStartAddrLow = 0x20, TxDescStartAddrHigh = 0x24, TxHDescStartAddrLow = 0x28, -@@ -5274,6 +5276,22 @@ done: +@@ -5309,6 +5311,22 @@ done: rtl_rar_set(tp, mac_addr); } @@ -48,7 +48,7 @@ Subject: [PATCH] r8169: add LED configuration from OF static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) { struct rtl8169_private *tp; -@@ -5438,6 +5456,7 @@ static int rtl_init_one(struct pci_dev * +@@ -5473,6 +5491,7 @@ static int rtl_init_one(struct pci_dev * if (!tp->counters) return -ENOMEM; diff --git a/target/linux/rockchip/patches-5.15/107-mmc-core-set-initial-signal-voltage-on-power-off.patch b/target/linux/rockchip/patches-5.15/107-mmc-core-set-initial-signal-voltage-on-power-off.patch index 136afaf8815614..aac8b7a6de2bf7 100644 --- a/target/linux/rockchip/patches-5.15/107-mmc-core-set-initial-signal-voltage-on-power-off.patch +++ b/target/linux/rockchip/patches-5.15/107-mmc-core-set-initial-signal-voltage-on-power-off.patch @@ -24,7 +24,7 @@ Signed-off-by: Jonas Karlman --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c -@@ -1364,6 +1364,8 @@ void mmc_power_off(struct mmc_host *host +@@ -1369,6 +1369,8 @@ void mmc_power_off(struct mmc_host *host mmc_pwrseq_power_off(host); diff --git a/target/linux/rockchip/patches-5.15/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch b/target/linux/rockchip/patches-5.15/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch index 01e430ac2f7e19..5c04d81eae7f5d 100644 --- a/target/linux/rockchip/patches-5.15/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch +++ b/target/linux/rockchip/patches-5.15/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch @@ -31,7 +31,7 @@ Signed-off-by: wevsty reg = <0x0 0xff100000 0x0 0x1000>; --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1937,6 +1937,16 @@ +@@ -1939,6 +1939,16 @@ }; }; diff --git a/target/linux/rockchip/patches-5.15/805-PM-devfreq-rockchip-dfi-add-more-soc-support.patch b/target/linux/rockchip/patches-5.15/805-PM-devfreq-rockchip-dfi-add-more-soc-support.patch index 283e4abd2f8b5a..a8f2af81792af8 100644 --- a/target/linux/rockchip/patches-5.15/805-PM-devfreq-rockchip-dfi-add-more-soc-support.patch +++ b/target/linux/rockchip/patches-5.15/805-PM-devfreq-rockchip-dfi-add-more-soc-support.patch @@ -557,12 +557,11 @@ Signed-off-by: hmz007 data->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(data->regs)) -@@ -202,21 +582,97 @@ static int rockchip_dfi_probe(struct pla - if (IS_ERR(data->regmap_pmu)) - return PTR_ERR(data->regmap_pmu); - } +@@ -203,21 +583,95 @@ static int rockchip_dfi_probe(struct pla + if (IS_ERR(data->regmap_pmu)) + return PTR_ERR(data->regmap_pmu); + - data->dev = dev; -+ + regmap_read(data->regmap_pmu, PMUGRF_OS_REG2, &val); + data->dram_type = READ_DRAMTYPE_INFO(val); + data->ch_msk = READ_CH_INFO(val); @@ -645,7 +644,6 @@ Signed-off-by: hmz007 + } else { + return 0; + } -+ desc->driver_data = data; desc->name = np->name; data->desc = desc; diff --git a/target/linux/rockchip/patches-5.15/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch b/target/linux/rockchip/patches-5.15/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch index 315ac0e34a3e6b..9444776e8e34c7 100644 --- a/target/linux/rockchip/patches-5.15/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch +++ b/target/linux/rockchip/patches-5.15/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch @@ -31,7 +31,7 @@ Signed-off-by: Leonidas P. Papadakos + }; + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; -+ opp-microvolt = <1400000>; ++ opp-microvolt = <1450000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { diff --git a/target/linux/rockchip/patches-5.4/105-mmc-core-set-initial-signal-voltage-on-power-off.patch b/target/linux/rockchip/patches-5.4/105-mmc-core-set-initial-signal-voltage-on-power-off.patch index f70cbb9e23834e..921028c0b9e1e0 100644 --- a/target/linux/rockchip/patches-5.4/105-mmc-core-set-initial-signal-voltage-on-power-off.patch +++ b/target/linux/rockchip/patches-5.4/105-mmc-core-set-initial-signal-voltage-on-power-off.patch @@ -24,7 +24,7 @@ Signed-off-by: Jonas Karlman --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c -@@ -1377,6 +1377,8 @@ void mmc_power_off(struct mmc_host *host +@@ -1382,6 +1382,8 @@ void mmc_power_off(struct mmc_host *host mmc_pwrseq_power_off(host); diff --git a/target/linux/rockchip/patches-6.1/101-net-realtek-r8169-add-LED-configuration-from-OF.patch b/target/linux/rockchip/patches-6.1/101-net-realtek-r8169-add-LED-configuration-from-OF.patch index eec258f7cdf0ba..1ae4663e3dd565 100644 --- a/target/linux/rockchip/patches-6.1/101-net-realtek-r8169-add-LED-configuration-from-OF.patch +++ b/target/linux/rockchip/patches-6.1/101-net-realtek-r8169-add-LED-configuration-from-OF.patch @@ -25,7 +25,7 @@ Subject: [PATCH] r8169: add LED configuration from OF TxDescStartAddrLow = 0x20, TxDescStartAddrHigh = 0x24, TxHDescStartAddrLow = 0x28, -@@ -5132,6 +5134,22 @@ static bool rtl_aspm_is_safe(struct rtl8 +@@ -5179,6 +5181,22 @@ static bool rtl_aspm_is_safe(struct rtl8 return false; } @@ -48,7 +48,7 @@ Subject: [PATCH] r8169: add LED configuration from OF static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) { struct rtl8169_private *tp; -@@ -5299,6 +5317,7 @@ static int rtl_init_one(struct pci_dev * +@@ -5347,6 +5365,7 @@ static int rtl_init_one(struct pci_dev * if (!tp->counters) return -ENOMEM; diff --git a/target/linux/rockchip/patches-6.1/107-mmc-core-set-initial-signal-voltage-on-power-off.patch b/target/linux/rockchip/patches-6.1/107-mmc-core-set-initial-signal-voltage-on-power-off.patch index 9b1f0bb0aaba43..d462899007ceb4 100644 --- a/target/linux/rockchip/patches-6.1/107-mmc-core-set-initial-signal-voltage-on-power-off.patch +++ b/target/linux/rockchip/patches-6.1/107-mmc-core-set-initial-signal-voltage-on-power-off.patch @@ -24,7 +24,7 @@ Signed-off-by: Jonas Karlman --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c -@@ -1366,6 +1366,8 @@ void mmc_power_off(struct mmc_host *host +@@ -1371,6 +1371,8 @@ void mmc_power_off(struct mmc_host *host mmc_pwrseq_power_off(host); diff --git a/target/linux/rockchip/patches-6.1/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch b/target/linux/rockchip/patches-6.1/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch index 64619dcb13f648..3e9af2bd93ac35 100644 --- a/target/linux/rockchip/patches-6.1/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch +++ b/target/linux/rockchip/patches-6.1/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch @@ -31,7 +31,7 @@ Signed-off-by: wevsty reg = <0x0 0xff100000 0x0 0x1000>; --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -2043,6 +2043,16 @@ +@@ -2045,6 +2045,16 @@ }; }; diff --git a/target/linux/rockchip/patches-6.1/805-PM-devfreq-rockchip-dfi-add-more-soc-support.patch b/target/linux/rockchip/patches-6.1/805-PM-devfreq-rockchip-dfi-add-more-soc-support.patch index 0bde4e1c243997..9b5437cd8b7bfe 100644 --- a/target/linux/rockchip/patches-6.1/805-PM-devfreq-rockchip-dfi-add-more-soc-support.patch +++ b/target/linux/rockchip/patches-6.1/805-PM-devfreq-rockchip-dfi-add-more-soc-support.patch @@ -557,12 +557,11 @@ Signed-off-by: hmz007 data->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(data->regs)) -@@ -201,21 +581,97 @@ static int rockchip_dfi_probe(struct pla - if (IS_ERR(data->regmap_pmu)) - return PTR_ERR(data->regmap_pmu); - } +@@ -202,21 +582,95 @@ static int rockchip_dfi_probe(struct pla + if (IS_ERR(data->regmap_pmu)) + return PTR_ERR(data->regmap_pmu); + - data->dev = dev; -+ + regmap_read(data->regmap_pmu, PMUGRF_OS_REG2, &val); + data->dram_type = READ_DRAMTYPE_INFO(val); + data->ch_msk = READ_CH_INFO(val); @@ -645,7 +644,6 @@ Signed-off-by: hmz007 + } else { + return 0; + } -+ desc->driver_data = data; desc->name = np->name; data->desc = desc; diff --git a/target/linux/rockchip/patches-6.1/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch b/target/linux/rockchip/patches-6.1/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch index 315ac0e34a3e6b..9444776e8e34c7 100644 --- a/target/linux/rockchip/patches-6.1/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch +++ b/target/linux/rockchip/patches-6.1/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch @@ -31,7 +31,7 @@ Signed-off-by: Leonidas P. Papadakos + }; + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; -+ opp-microvolt = <1400000>; ++ opp-microvolt = <1450000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { diff --git a/target/linux/x86/image/Makefile b/target/linux/x86/image/Makefile index 677b758e01ce19..30a903515d56ed 100644 --- a/target/linux/x86/image/Makefile +++ b/target/linux/x86/image/Makefile @@ -53,7 +53,7 @@ define Build/combined $@ \ $(CONFIG_TARGET_KERNEL_PARTSIZE) $@.boot \ $(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS) \ - 256 + 1024 endef define Build/grub-config diff --git a/target/linux/x86/patches-5.15/998-add-a-sysctl-to-enable-disable-tcp_collapse-logic.patch b/target/linux/x86/patches-5.15/998-add-a-sysctl-to-enable-disable-tcp_collapse-logic.patch index 61e9cb9888dd0e..5ca127c499cc4e 100644 --- a/target/linux/x86/patches-5.15/998-add-a-sysctl-to-enable-disable-tcp_collapse-logic.patch +++ b/target/linux/x86/patches-5.15/998-add-a-sysctl-to-enable-disable-tcp_collapse-logic.patch @@ -81,7 +81,7 @@ and performance for all other cases. --- a/net/ipv4/tcp_input.c +++ b/net/ipv4/tcp_input.c -@@ -5384,6 +5384,7 @@ static bool tcp_prune_ofo_queue(struct s +@@ -5388,6 +5388,7 @@ static bool tcp_prune_ofo_queue(struct s static int tcp_prune_queue(struct sock *sk) { struct tcp_sock *tp = tcp_sk(sk); @@ -89,7 +89,7 @@ and performance for all other cases. NET_INC_STATS(sock_net(sk), LINUX_MIB_PRUNECALLED); -@@ -5395,6 +5396,39 @@ static int tcp_prune_queue(struct sock * +@@ -5399,6 +5400,39 @@ static int tcp_prune_queue(struct sock * if (atomic_read(&sk->sk_rmem_alloc) <= sk->sk_rcvbuf) return 0; @@ -129,7 +129,7 @@ and performance for all other cases. tcp_collapse_ofo_queue(sk); if (!skb_queue_empty(&sk->sk_receive_queue)) tcp_collapse(sk, &sk->sk_receive_queue, NULL, -@@ -5414,6 +5448,8 @@ static int tcp_prune_queue(struct sock * +@@ -5418,6 +5452,8 @@ static int tcp_prune_queue(struct sock * if (atomic_read(&sk->sk_rmem_alloc) <= sk->sk_rcvbuf) return 0; @@ -140,7 +140,7 @@ and performance for all other cases. * and hopefully then we'll have sufficient space. --- a/net/ipv4/tcp_ipv4.c +++ b/net/ipv4/tcp_ipv4.c -@@ -3214,6 +3214,8 @@ static int __net_init tcp_sk_init(struct +@@ -3211,6 +3211,8 @@ static int __net_init tcp_sk_init(struct else net->ipv4.tcp_congestion_control = &tcp_reno; diff --git a/target/linux/x86/patches-6.1/998-add-a-sysctl-to-enable-disable-tcp_collapse-logic.patch b/target/linux/x86/patches-6.1/998-add-a-sysctl-to-enable-disable-tcp_collapse-logic.patch index 074285c4909f09..0ab685a8f3cb51 100644 --- a/target/linux/x86/patches-6.1/998-add-a-sysctl-to-enable-disable-tcp_collapse-logic.patch +++ b/target/linux/x86/patches-6.1/998-add-a-sysctl-to-enable-disable-tcp_collapse-logic.patch @@ -81,7 +81,7 @@ and performance for all other cases. --- a/net/ipv4/tcp_input.c +++ b/net/ipv4/tcp_input.c -@@ -5403,6 +5403,7 @@ static bool tcp_prune_ofo_queue(struct s +@@ -5407,6 +5407,7 @@ static bool tcp_prune_ofo_queue(struct s static int tcp_prune_queue(struct sock *sk) { struct tcp_sock *tp = tcp_sk(sk); @@ -89,7 +89,7 @@ and performance for all other cases. NET_INC_STATS(sock_net(sk), LINUX_MIB_PRUNECALLED); -@@ -5414,6 +5415,39 @@ static int tcp_prune_queue(struct sock * +@@ -5418,6 +5419,39 @@ static int tcp_prune_queue(struct sock * if (atomic_read(&sk->sk_rmem_alloc) <= sk->sk_rcvbuf) return 0; @@ -129,7 +129,7 @@ and performance for all other cases. tcp_collapse_ofo_queue(sk); if (!skb_queue_empty(&sk->sk_receive_queue)) tcp_collapse(sk, &sk->sk_receive_queue, NULL, -@@ -5432,6 +5466,8 @@ static int tcp_prune_queue(struct sock * +@@ -5436,6 +5470,8 @@ static int tcp_prune_queue(struct sock * if (atomic_read(&sk->sk_rmem_alloc) <= sk->sk_rcvbuf) return 0;