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Pull VFIO updates from Alex Williamson: - Introduce new device migration uAPI and implement device specific mlx5 vfio-pci variant driver supporting new protocol (Jason Gunthorpe, Yishai Hadas, Leon Romanovsky) - New HiSilicon acc vfio-pci variant driver, also supporting migration interface (Shameer Kolothum, Longfang Liu) - D3hot fixes for vfio-pci-core (Abhishek Sahu) - Document new vfio-pci variant driver acceptance criteria (Alex Williamson) - Fix UML build unresolved ioport_{un}map() functions (Alex Williamson) - Fix MAINTAINERS due to header movement (Lukas Bulwahn) * tag 'vfio-v5.18-rc1' of https://github.com/awilliam/linux-vfio: (31 commits) vfio-pci: Provide reviewers and acceptance criteria for variant drivers MAINTAINERS: adjust entry for header movement in hisilicon qm driver hisi_acc_vfio_pci: Use its own PCI reset_done error handler hisi_acc_vfio_pci: Add support for VFIO live migration crypto: hisilicon/qm: Set the VF QM state register hisi_acc_vfio_pci: Add helper to retrieve the struct pci_driver hisi_acc_vfio_pci: Restrict access to VF dev BAR2 migration region hisi_acc_vfio_pci: add new vfio_pci driver for HiSilicon ACC devices hisi_acc_qm: Move VF PCI device IDs to common header crypto: hisilicon/qm: Move few definitions to common header crypto: hisilicon/qm: Move the QM header to include/linux vfio/mlx5: Fix to not use 0 as NULL pointer PCI/IOV: Fix wrong kernel-doc identifier vfio/mlx5: Use its own PCI reset_done error handler vfio/pci: Expose vfio_pci_core_aer_err_detected() vfio/mlx5: Implement vfio_pci driver for mlx5 devices vfio/mlx5: Expose migration commands over mlx5 device vfio: Remove migration protocol v1 documentation vfio: Extend the device migration protocol with RUNNING_P2P vfio: Define device migration protocol v2 ...
2 parents 66711cf + f621eb1 commit 7403e6d

40 files changed

+3558
-358
lines changed

‎Documentation/driver-api/index.rst‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -103,6 +103,7 @@ available subsections can be seen below.
103103
sync_file
104104
vfio-mediated-device
105105
vfio
106+
vfio-pci-device-specific-driver-acceptance
106107
xilinx/index
107108
xillybus
108109
zorro

‎Documentation/driver-api/vfio-pci-device-specific-driver-acceptance.rst‎

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,35 @@
1+
.. SPDX-License-Identifier: GPL-2.0
2+
3+
Acceptance criteria for vfio-pci device specific driver variants
4+
================================================================
5+
6+
Overview
7+
--------
8+
The vfio-pci driver exists as a device agnostic driver using the
9+
system IOMMU and relying on the robustness of platform fault
10+
handling to provide isolated device access to userspace. While the
11+
vfio-pci driver does include some device specific support, further
12+
extensions for yet more advanced device specific features are not
13+
sustainable. The vfio-pci driver has therefore split out
14+
vfio-pci-core as a library that may be reused to implement features
15+
requiring device specific knowledge, ex. saving and loading device
16+
state for the purposes of supporting migration.
17+
18+
In support of such features, it's expected that some device specific
19+
variants may interact with parent devices (ex. SR-IOV PF in support of
20+
a user assigned VF) or other extensions that may not be otherwise
21+
accessible via the vfio-pci base driver. Authors of such drivers
22+
should be diligent not to create exploitable interfaces via these
23+
interactions or allow unchecked userspace data to have an effect
24+
beyond the scope of the assigned device.
25+
26+
New driver submissions are therefore requested to have approval via
27+
sign-off/ack/review/etc for any interactions with parent drivers.
28+
Additionally, drivers should make an attempt to provide sufficient
29+
documentation for reviewers to understand the device specific
30+
extensions, for example in the case of migration data, how is the
31+
device state composed and consumed, which portions are not otherwise
32+
available to the user via vfio-pci, what safeguards exist to validate
33+
the data, etc. To that extent, authors should additionally expect to
34+
require reviews from at least one of the listed reviewers, in addition
35+
to the overall vfio maintainer.

‎Documentation/maintainer/maintainer-entry-profile.rst‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -103,3 +103,4 @@ to do something different in the near future.
103103
../nvdimm/maintainer-entry-profile
104104
../riscv/patch-acceptance
105105
../driver-api/media/maintainer-entry-profile
106+
../driver-api/vfio-pci-device-specific-driver-acceptance

‎MAINTAINERS‎

Lines changed: 24 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8722,9 +8722,9 @@ L: linux-crypto@vger.kernel.org
87228722
S: Maintained
87238723
F: Documentation/ABI/testing/debugfs-hisi-zip
87248724
F: drivers/crypto/hisilicon/qm.c
8725-
F: drivers/crypto/hisilicon/qm.h
87268725
F: drivers/crypto/hisilicon/sgl.c
87278726
F: drivers/crypto/hisilicon/zip/
8727+
F: include/linux/hisi_acc_qm.h
87288728

87298729
HISILICON ROCE DRIVER
87308730
M: Wenpeng Liang <liangwenpeng@huawei.com>
@@ -20399,6 +20399,13 @@ L: kvm@vger.kernel.org
2039920399
S: Maintained
2040020400
F: drivers/vfio/fsl-mc/
2040120401

20402+
VFIO HISILICON PCI DRIVER
20403+
M: Longfang Liu <liulongfang@huawei.com>
20404+
M: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
20405+
L: kvm@vger.kernel.org
20406+
S: Maintained
20407+
F: drivers/vfio/pci/hisilicon/
20408+
2040220409
VFIO MEDIATED DEVICE DRIVERS
2040320410
M: Kirti Wankhede <kwankhede@nvidia.com>
2040420411
L: kvm@vger.kernel.org
@@ -20408,12 +20415,28 @@ F: drivers/vfio/mdev/
2040820415
F: include/linux/mdev.h
2040920416
F: samples/vfio-mdev/
2041020417

20418+
VFIO PCI DEVICE SPECIFIC DRIVERS
20419+
R: Jason Gunthorpe <jgg@nvidia.com>
20420+
R: Yishai Hadas <yishaih@nvidia.com>
20421+
R: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
20422+
R: Kevin Tian <kevin.tian@intel.com>
20423+
L: kvm@vger.kernel.org
20424+
S: Maintained
20425+
P: Documentation/driver-api/vfio-pci-device-specific-driver-acceptance.rst
20426+
F: drivers/vfio/pci/*/
20427+
2041120428
VFIO PLATFORM DRIVER
2041220429
M: Eric Auger <eric.auger@redhat.com>
2041320430
L: kvm@vger.kernel.org
2041420431
S: Maintained
2041520432
F: drivers/vfio/platform/
2041620433

20434+
VFIO MLX5 PCI DRIVER
20435+
M: Yishai Hadas <yishaih@nvidia.com>
20436+
L: kvm@vger.kernel.org
20437+
S: Maintained
20438+
F: drivers/vfio/pci/mlx5/
20439+
2041720440
VGA_SWITCHEROO
2041820441
R: Lukas Wunner <lukas@wunner.de>
2041920442
S: Maintained

‎drivers/crypto/hisilicon/hpre/hpre.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
#define __HISI_HPRE_H
55

66
#include <linux/list.h>
7-
#include "../qm.h"
7+
#include <linux/hisi_acc_qm.h>
88

99
#define HPRE_SQE_SIZE sizeof(struct hpre_sqe)
1010
#define HPRE_PF_DEF_Q_NUM 64

‎drivers/crypto/hisilicon/hpre/hpre_main.c‎

Lines changed: 12 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -68,8 +68,7 @@
6868
#define HPRE_REG_RD_INTVRL_US 10
6969
#define HPRE_REG_RD_TMOUT_US 1000
7070
#define HPRE_DBGFS_VAL_MAX_LEN 20
71-
#define HPRE_PCI_DEVICE_ID 0xa258
72-
#define HPRE_PCI_VF_DEVICE_ID 0xa259
71+
#define PCI_DEVICE_ID_HUAWEI_HPRE_PF 0xa258
7372
#define HPRE_QM_USR_CFG_MASK GENMASK(31, 1)
7473
#define HPRE_QM_AXI_CFG_MASK GENMASK(15, 0)
7574
#define HPRE_QM_VFG_AX_MASK GENMASK(7, 0)
@@ -111,8 +110,8 @@
111110
static const char hpre_name[] = "hisi_hpre";
112111
static struct dentry *hpre_debugfs_root;
113112
static const struct pci_device_id hpre_dev_ids[] = {
114-
{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HPRE_PCI_DEVICE_ID) },
115-
{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HPRE_PCI_VF_DEVICE_ID) },
113+
{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_HPRE_PF) },
114+
{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_HPRE_VF) },
116115
{ 0, }
117116
};
118117

@@ -242,7 +241,7 @@ MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC);
242241

243242
static int pf_q_num_set(const char *val, const struct kernel_param *kp)
244243
{
245-
return q_num_set(val, kp, HPRE_PCI_DEVICE_ID);
244+
return q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_HPRE_PF);
246245
}
247246

248247
static const struct kernel_param_ops hpre_pf_q_num_ops = {
@@ -921,7 +920,7 @@ static int hpre_debugfs_init(struct hisi_qm *qm)
921920
qm->debug.sqe_mask_len = HPRE_SQE_MASK_LEN;
922921
hisi_qm_debug_init(qm);
923922

924-
if (qm->pdev->device == HPRE_PCI_DEVICE_ID) {
923+
if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_HPRE_PF) {
925924
ret = hpre_ctrl_debug_init(qm);
926925
if (ret)
927926
goto failed_to_create;
@@ -958,7 +957,7 @@ static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
958957
qm->sqe_size = HPRE_SQE_SIZE;
959958
qm->dev_name = hpre_name;
960959

961-
qm->fun_type = (pdev->device == HPRE_PCI_DEVICE_ID) ?
960+
qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_HPRE_PF) ?
962961
QM_HW_PF : QM_HW_VF;
963962
if (qm->fun_type == QM_HW_PF) {
964963
qm->qp_base = HPRE_PF_DEF_Q_BASE;
@@ -1191,6 +1190,12 @@ static struct pci_driver hpre_pci_driver = {
11911190
.driver.pm = &hpre_pm_ops,
11921191
};
11931192

1193+
struct pci_driver *hisi_hpre_get_pf_driver(void)
1194+
{
1195+
return &hpre_pci_driver;
1196+
}
1197+
EXPORT_SYMBOL_GPL(hisi_hpre_get_pf_driver);
1198+
11941199
static void hpre_register_debugfs(void)
11951200
{
11961201
if (!debugfs_initialized())

‎drivers/crypto/hisilicon/qm.c‎

Lines changed: 27 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@
1515
#include <linux/uacce.h>
1616
#include <linux/uaccess.h>
1717
#include <uapi/misc/uacce/hisi_qm.h>
18-
#include "qm.h"
18+
#include <linux/hisi_acc_qm.h>
1919

2020
/* eq/aeq irq enable */
2121
#define QM_VF_AEQ_INT_SOURCE 0x0
@@ -33,23 +33,6 @@
3333
#define QM_ABNORMAL_EVENT_IRQ_VECTOR 3
3434

3535
/* mailbox */
36-
#define QM_MB_CMD_SQC 0x0
37-
#define QM_MB_CMD_CQC 0x1
38-
#define QM_MB_CMD_EQC 0x2
39-
#define QM_MB_CMD_AEQC 0x3
40-
#define QM_MB_CMD_SQC_BT 0x4
41-
#define QM_MB_CMD_CQC_BT 0x5
42-
#define QM_MB_CMD_SQC_VFT_V2 0x6
43-
#define QM_MB_CMD_STOP_QP 0x8
44-
#define QM_MB_CMD_SRC 0xc
45-
#define QM_MB_CMD_DST 0xd
46-
47-
#define QM_MB_CMD_SEND_BASE 0x300
48-
#define QM_MB_EVENT_SHIFT 8
49-
#define QM_MB_BUSY_SHIFT 13
50-
#define QM_MB_OP_SHIFT 14
51-
#define QM_MB_CMD_DATA_ADDR_L 0x304
52-
#define QM_MB_CMD_DATA_ADDR_H 0x308
5336
#define QM_MB_PING_ALL_VFS 0xffff
5437
#define QM_MB_CMD_DATA_SHIFT 32
5538
#define QM_MB_CMD_DATA_MASK GENMASK(31, 0)
@@ -103,19 +86,12 @@
10386
#define QM_DB_CMD_SHIFT_V1 16
10487
#define QM_DB_INDEX_SHIFT_V1 32
10588
#define QM_DB_PRIORITY_SHIFT_V1 48
106-
#define QM_DOORBELL_SQ_CQ_BASE_V2 0x1000
107-
#define QM_DOORBELL_EQ_AEQ_BASE_V2 0x2000
10889
#define QM_QUE_ISO_CFG_V 0x0030
10990
#define QM_PAGE_SIZE 0x0034
11091
#define QM_QUE_ISO_EN 0x100154
11192
#define QM_CAPBILITY 0x100158
11293
#define QM_QP_NUN_MASK GENMASK(10, 0)
11394
#define QM_QP_DB_INTERVAL 0x10000
114-
#define QM_QP_MAX_NUM_SHIFT 11
115-
#define QM_DB_CMD_SHIFT_V2 12
116-
#define QM_DB_RAND_SHIFT_V2 16
117-
#define QM_DB_INDEX_SHIFT_V2 32
118-
#define QM_DB_PRIORITY_SHIFT_V2 48
11995

12096
#define QM_MEM_START_INIT 0x100040
12197
#define QM_MEM_INIT_DONE 0x100044
@@ -693,14 +669,15 @@ static void qm_mb_pre_init(struct qm_mailbox *mailbox, u8 cmd,
693669
}
694670

695671
/* return 0 mailbox ready, -ETIMEDOUT hardware timeout */
696-
static int qm_wait_mb_ready(struct hisi_qm *qm)
672+
int hisi_qm_wait_mb_ready(struct hisi_qm *qm)
697673
{
698674
u32 val;
699675

700676
return readl_relaxed_poll_timeout(qm->io_base + QM_MB_CMD_SEND_BASE,
701677
val, !((val >> QM_MB_BUSY_SHIFT) &
702678
0x1), POLL_PERIOD, POLL_TIMEOUT);
703679
}
680+
EXPORT_SYMBOL_GPL(hisi_qm_wait_mb_ready);
704681

705682
/* 128 bit should be written to hardware at one time to trigger a mailbox */
706683
static void qm_mb_write(struct hisi_qm *qm, const void *src)
@@ -726,14 +703,14 @@ static void qm_mb_write(struct hisi_qm *qm, const void *src)
726703

727704
static int qm_mb_nolock(struct hisi_qm *qm, struct qm_mailbox *mailbox)
728705
{
729-
if (unlikely(qm_wait_mb_ready(qm))) {
706+
if (unlikely(hisi_qm_wait_mb_ready(qm))) {
730707
dev_err(&qm->pdev->dev, "QM mailbox is busy to start!\n");
731708
goto mb_busy;
732709
}
733710

734711
qm_mb_write(qm, mailbox);
735712

736-
if (unlikely(qm_wait_mb_ready(qm))) {
713+
if (unlikely(hisi_qm_wait_mb_ready(qm))) {
737714
dev_err(&qm->pdev->dev, "QM mailbox operation timeout!\n");
738715
goto mb_busy;
739716
}
@@ -745,8 +722,8 @@ static int qm_mb_nolock(struct hisi_qm *qm, struct qm_mailbox *mailbox)
745722
return -EBUSY;
746723
}
747724

748-
static int qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
749-
bool op)
725+
int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
726+
bool op)
750727
{
751728
struct qm_mailbox mailbox;
752729
int ret;
@@ -762,6 +739,7 @@ static int qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
762739

763740
return ret;
764741
}
742+
EXPORT_SYMBOL_GPL(hisi_qm_mb);
765743

766744
static void qm_db_v1(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)
767745
{
@@ -1351,7 +1329,7 @@ static int qm_get_vft_v2(struct hisi_qm *qm, u32 *base, u32 *number)
13511329
u64 sqc_vft;
13521330
int ret;
13531331

1354-
ret = qm_mb(qm, QM_MB_CMD_SQC_VFT_V2, 0, 0, 1);
1332+
ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_VFT_V2, 0, 0, 1);
13551333
if (ret)
13561334
return ret;
13571335

@@ -1725,12 +1703,12 @@ static int dump_show(struct hisi_qm *qm, void *info,
17251703

17261704
static int qm_dump_sqc_raw(struct hisi_qm *qm, dma_addr_t dma_addr, u16 qp_id)
17271705
{
1728-
return qm_mb(qm, QM_MB_CMD_SQC, dma_addr, qp_id, 1);
1706+
return hisi_qm_mb(qm, QM_MB_CMD_SQC, dma_addr, qp_id, 1);
17291707
}
17301708

17311709
static int qm_dump_cqc_raw(struct hisi_qm *qm, dma_addr_t dma_addr, u16 qp_id)
17321710
{
1733-
return qm_mb(qm, QM_MB_CMD_CQC, dma_addr, qp_id, 1);
1711+
return hisi_qm_mb(qm, QM_MB_CMD_CQC, dma_addr, qp_id, 1);
17341712
}
17351713

17361714
static int qm_sqc_dump(struct hisi_qm *qm, const char *s)
@@ -1842,7 +1820,7 @@ static int qm_eqc_aeqc_dump(struct hisi_qm *qm, char *s, size_t size,
18421820
if (IS_ERR(xeqc))
18431821
return PTR_ERR(xeqc);
18441822

1845-
ret = qm_mb(qm, cmd, xeqc_dma, 0, 1);
1823+
ret = hisi_qm_mb(qm, cmd, xeqc_dma, 0, 1);
18461824
if (ret)
18471825
goto err_free_ctx;
18481826

@@ -2495,7 +2473,7 @@ static int qm_ping_pf(struct hisi_qm *qm, u64 cmd)
24952473

24962474
static int qm_stop_qp(struct hisi_qp *qp)
24972475
{
2498-
return qm_mb(qp->qm, QM_MB_CMD_STOP_QP, 0, qp->qp_id, 0);
2476+
return hisi_qm_mb(qp->qm, QM_MB_CMD_STOP_QP, 0, qp->qp_id, 0);
24992477
}
25002478

25012479
static int qm_set_msi(struct hisi_qm *qm, bool set)
@@ -2763,7 +2741,7 @@ static int qm_sq_ctx_cfg(struct hisi_qp *qp, int qp_id, u32 pasid)
27632741
return -ENOMEM;
27642742
}
27652743

2766-
ret = qm_mb(qm, QM_MB_CMD_SQC, sqc_dma, qp_id, 0);
2744+
ret = hisi_qm_mb(qm, QM_MB_CMD_SQC, sqc_dma, qp_id, 0);
27672745
dma_unmap_single(dev, sqc_dma, sizeof(struct qm_sqc), DMA_TO_DEVICE);
27682746
kfree(sqc);
27692747

@@ -2804,7 +2782,7 @@ static int qm_cq_ctx_cfg(struct hisi_qp *qp, int qp_id, u32 pasid)
28042782
return -ENOMEM;
28052783
}
28062784

2807-
ret = qm_mb(qm, QM_MB_CMD_CQC, cqc_dma, qp_id, 0);
2785+
ret = hisi_qm_mb(qm, QM_MB_CMD_CQC, cqc_dma, qp_id, 0);
28082786
dma_unmap_single(dev, cqc_dma, sizeof(struct qm_cqc), DMA_TO_DEVICE);
28092787
kfree(cqc);
28102788

@@ -3514,6 +3492,12 @@ static void hisi_qm_pci_uninit(struct hisi_qm *qm)
35143492
pci_disable_device(pdev);
35153493
}
35163494

3495+
static void hisi_qm_set_state(struct hisi_qm *qm, u8 state)
3496+
{
3497+
if (qm->ver > QM_HW_V2 && qm->fun_type == QM_HW_VF)
3498+
writel(state, qm->io_base + QM_VF_STATE);
3499+
}
3500+
35173501
/**
35183502
* hisi_qm_uninit() - Uninitialize qm.
35193503
* @qm: The qm needed uninit.
@@ -3542,6 +3526,7 @@ void hisi_qm_uninit(struct hisi_qm *qm)
35423526
dma_free_coherent(dev, qm->qdma.size,
35433527
qm->qdma.va, qm->qdma.dma);
35443528
}
3529+
hisi_qm_set_state(qm, QM_NOT_READY);
35453530
up_write(&qm->qps_lock);
35463531

35473532
qm_irq_unregister(qm);
@@ -3655,7 +3640,7 @@ static int qm_eq_ctx_cfg(struct hisi_qm *qm)
36553640
return -ENOMEM;
36563641
}
36573642

3658-
ret = qm_mb(qm, QM_MB_CMD_EQC, eqc_dma, 0, 0);
3643+
ret = hisi_qm_mb(qm, QM_MB_CMD_EQC, eqc_dma, 0, 0);
36593644
dma_unmap_single(dev, eqc_dma, sizeof(struct qm_eqc), DMA_TO_DEVICE);
36603645
kfree(eqc);
36613646

@@ -3684,7 +3669,7 @@ static int qm_aeq_ctx_cfg(struct hisi_qm *qm)
36843669
return -ENOMEM;
36853670
}
36863671

3687-
ret = qm_mb(qm, QM_MB_CMD_AEQC, aeqc_dma, 0, 0);
3672+
ret = hisi_qm_mb(qm, QM_MB_CMD_AEQC, aeqc_dma, 0, 0);
36883673
dma_unmap_single(dev, aeqc_dma, sizeof(struct qm_aeqc), DMA_TO_DEVICE);
36893674
kfree(aeqc);
36903675

@@ -3723,11 +3708,11 @@ static int __hisi_qm_start(struct hisi_qm *qm)
37233708
if (ret)
37243709
return ret;
37253710

3726-
ret = qm_mb(qm, QM_MB_CMD_SQC_BT, qm->sqc_dma, 0, 0);
3711+
ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_BT, qm->sqc_dma, 0, 0);
37273712
if (ret)
37283713
return ret;
37293714

3730-
ret = qm_mb(qm, QM_MB_CMD_CQC_BT, qm->cqc_dma, 0, 0);
3715+
ret = hisi_qm_mb(qm, QM_MB_CMD_CQC_BT, qm->cqc_dma, 0, 0);
37313716
if (ret)
37323717
return ret;
37333718

@@ -3767,6 +3752,7 @@ int hisi_qm_start(struct hisi_qm *qm)
37673752
if (!ret)
37683753
atomic_set(&qm->status.flags, QM_START);
37693754

3755+
hisi_qm_set_state(qm, QM_READY);
37703756
err_unlock:
37713757
up_write(&qm->qps_lock);
37723758
return ret;

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