diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PeripheralNames.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PeripheralNames.h index ad81ea0f98f..820b1ca5f74 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PeripheralNames.h +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PeripheralNames.h @@ -25,9 +25,8 @@ extern "C" { // TODO typedef enum { - // TODO: need to define peripherals in device/CC3220SF.h - UART_0 = 0, //(int)CC3220SF_UART0_BASE, - UART_1 = 1 //(int)CC3220SF_UART1_BASE, + UART_0 = (int)CC3220SF_UARTA0_BASE, + UART_1 = (int)CC3220SF_UARTA1_BASE } UARTName; typedef enum { diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF.h index b3e64ba934c..a45a169f257 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF.h +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF.h @@ -52,40 +52,40 @@ typedef enum IRQn SysTick_IRQn = -1, /*!< -1 System Tick Timer */ /* =========================================== CC3220SF Specific Interrupt Numbers ========================================= */ - INT_GPIOA0 = 16, // GPIO Port S0 - INT_GPIOA1 = 17, // GPIO Port S1 - INT_GPIOA2 = 18, // GPIO Port S2 - INT_GPIOA3 = 19, // GPIO Port S3 - INT_UARTA0 = 21, // UART0 Rx and Tx - INT_UARTA1 = 22, // UART1 Rx and Tx - INT_I2CA0 = 24, // I2C controller - INT_ADCCH0 = 30, // ADC Sequence 0 - INT_ADCCH1 = 31, // ADC Sequence 1 - INT_ADCCH2 = 32, // ADC Sequence 2 - INT_ADCCH3 = 33, // ADC Sequence 3 - INT_WDT = 34, // Watchdog Timer0 - INT_TIMERA0A = 35, // Timer 0 subtimer A - INT_TIMERA0B = 36, // Timer 0 subtimer B - INT_TIMERA1A = 37, // Timer 1 subtimer A - INT_TIMERA1B = 38, // Timer 1 subtimer B - INT_TIMERA2A = 39, // Timer 2 subtimer A - INT_TIMERA2B = 40, // Timer 2 subtimer B - INT_FLASH = 45, // FLASH Control - INT_TIMERA3A = 51, // Timer 3 subtimer A - INT_TIMERA3B = 52, // Timer 3 subtimer B - INT_UDMA = 62, // uDMA controller - INT_UDMAERR = 63, // uDMA Error - INT_SHA = 164, // SHA - INT_AES = 167, // AES - INT_DES = 169, // DES - INT_MMCHS = 175, // SDIO - INT_I2S = 177, // McAPS - INT_CAMERA = 179, // Camera - INT_NWPIC = 187, // Interprocessor communication - INT_PRCM = 188, // Power, Reset and Clock Module - INT_SSPI = 191, // Shared SPI - INT_GSPI = 192, // Generic SPI - INT_LSPI = 193 // Link SPI + INT_GPIOA0_IRQn = 16, // GPIO Port S0 + INT_GPIOA1_IRQn = 17, // GPIO Port S1 + INT_GPIOA2_IRQn = 18, // GPIO Port S2 + INT_GPIOA3_IRQn = 19, // GPIO Port S3 + INT_UARTA0_IRQn = 21, // UART0 Rx and Tx + INT_UARTA1_IRQn = 22, // UART1 Rx and Tx + INT_I2CA0_IRQn = 24, // I2C controller + INT_ADCCH0_IRQn = 30, // ADC Sequence 0 + INT_ADCCH1_IRQn = 31, // ADC Sequence 1 + INT_ADCCH2_IRQn = 32, // ADC Sequence 2 + INT_ADCCH3_IRQn = 33, // ADC Sequence 3 + INT_WDT_IRQn = 34, // Watchdog Timer0 + INT_TIMERA0A_IRQn = 35, // Timer 0 subtimer A + INT_TIMERA0B_IRQn = 36, // Timer 0 subtimer B + INT_TIMERA1A_IRQn = 37, // Timer 1 subtimer A + INT_TIMERA1B_IRQn = 38, // Timer 1 subtimer B + INT_TIMERA2A_IRQn = 39, // Timer 2 subtimer A + INT_TIMERA2B_IRQn = 40, // Timer 2 subtimer B + INT_FLASH_IRQn = 45, // FLASH Control + INT_TIMERA3A_IRQn = 51, // Timer 3 subtimer A + INT_TIMERA3B_IRQn = 52, // Timer 3 subtimer B + INT_UDMA_IRQn = 62, // uDMA controller + INT_UDMAERR_IRQn = 63, // uDMA Error + INT_SHA_IRQn = 164, // SHA + INT_AES_IRQn = 167, // AES + INT_DES_IRQn = 169, // DES + INT_MMCHS_IRQn = 175, // SDIO + INT_I2S_IRQn = 177, // McAPS + INT_CAMERA_IRQn = 179, // Camera + INT_NWPIC_IRQn = 187, // Interprocessor communication + INT_PRCM_IRQn = 188, // Power, Reset and Clock Module + INT_SSPI_IRQn = 191, // Shared SPI + INT_GSPI_IRQn = 192, // Generic SPI + INT_LSPI_IRQn = 193 // Link SPI } IRQn_Type; @@ -175,7 +175,7 @@ typedef struct //__IO uint32_t 9BITMASK; /*!< Address offset : 0xA8 */ //__IO uint32_t PP; /*!< Address offset : 0xFC0 */ //__IO uint32_t CC; /*!< Address offset : 0xFC8 */ -} UART_TypeDef; +} CC3220SF_UART_TypeDef; /* =========================================================================================================================== */ /* ================ Device Specific Peripheral Address Map ================ */ @@ -187,43 +187,43 @@ typedef struct */ /* Peripheral and SRAM base address */ -#define FLASH_BASE 0x01000000 -#define SRAM_BASE 0x20000000 -#define WDT_BASE 0x40000000 -#define GPIOA0_BASE 0x40004000 -#define GPIOA1_BASE 0x40005000 -#define GPIOA2_BASE 0x40006000 -#define GPIOA3_BASE 0x40007000 -#define GPIOA4_BASE 0x40024000 -#define UARTA0_BASE 0x4000C000 -#define UARTA1_BASE 0x4000D000 -#define I2CA0_BASE 0x40020000 -#define TIMERA0_BASE 0x40030000 -#define TIMERA1_BASE 0x40031000 -#define TIMERA2_BASE 0x40032000 -#define TIMERA3_BASE 0x40033000 -#define STACKDIE_CTRL_BASE 0x400F5000 -#define COMMON_REG_BASE 0x400F7000 -#define FLASH_CONTROL_BASE 0x400FD000 -#define SYSTEM_CONTROL_BASE 0x400FE000 -#define UDMA_BASE 0x400FF000 -#define SDHOST_BASE 0x44010000 -#define CAMERA_BASE 0x44018000 -#define I2S_BASE 0x4401C000 -#define SSPI_BASE 0x44020000 -#define GSPI_BASE 0x44021000 -#define LSPI_BASE 0x44022000 -#define ARCM_BASE 0x44025000 -#define APPS_CONFIG_BASE 0x44026000 -#define GPRCM_BASE 0x4402D000 -#define OCP_SHARED_BASE 0x4402E000 -#define ADC_BASE 0x4402E800 -#define HIB1P2_BASE 0x4402F000 -#define HIB3P3_BASE 0x4402F800 -#define DTHE_BASE 0x44030000 -#define SHAMD5_BASE 0x44035000 -#define AES_BASE 0x44037000 -#define DES_BASE 0x44039000 +#define CC3220SF_FLASH_BASE 0x01000000 +#define CC3220SF_SRAM_BASE 0x20000000 +#define CC3220SF_WDT_BASE 0x40000000 +#define CC3220SF_GPIOA0_BASE 0x40004000 +#define CC3220SF_GPIOA1_BASE 0x40005000 +#define CC3220SF_GPIOA2_BASE 0x40006000 +#define CC3220SF_GPIOA3_BASE 0x40007000 +#define CC3220SF_GPIOA4_BASE 0x40024000 +#define CC3220SF_UARTA0_BASE 0x4000C000 +#define CC3220SF_UARTA1_BASE 0x4000D000 +#define CC3220SF_I2CA0_BASE 0x40020000 +#define CC3220SF_TIMERA0_BASE 0x40030000 +#define CC3220SF_TIMERA1_BASE 0x40031000 +#define CC3220SF_TIMERA2_BASE 0x40032000 +#define CC3220SF_TIMERA3_BASE 0x40033000 +#define CC3220SF_STACKDIE_CTRL_BASE 0x400F5000 +#define CC3220SF_COMMON_REG_BASE 0x400F7000 +#define CC3220SF_FLASH_CONTROL_BASE 0x400FD000 +#define CC3220SF_SYSTEM_CONTROL_BASE 0x400FE000 +#define CC3220SF_UDMA_BASE 0x400FF000 +#define CC3220SF_SDHOST_BASE 0x44010000 +#define CC3220SF_CAMERA_BASE 0x44018000 +#define CC3220SF_I2S_BASE 0x4401C000 +#define CC3220SF_SSPI_BASE 0x44020000 +#define CC3220SF_GSPI_BASE 0x44021000 +#define CC3220SF_LSPI_BASE 0x44022000 +#define CC3220SF_ARCM_BASE 0x44025000 +#define CC3220SF_APPS_CONFIG_BASE 0x44026000 +#define CC3220SF_GPRCM_BASE 0x4402D000 +#define CC3220SF_OCP_SHARED_BASE 0x4402E000 +#define CC3220SF_ADC_BASE 0x4402E800 +#define CC3220SF_HIB1P2_BASE 0x4402F000 +#define CC3220SF_HIB3P3_BASE 0x4402F800 +#define CC3220SF_DTHE_BASE 0x44030000 +#define CC3220SF_SHAMD5_BASE 0x44035000 +#define CC3220SF_AES_BASE 0x44037000 +#define CC3220SF_DES_BASE 0x44039000 /** * @} @@ -243,381 +243,9 @@ typedef struct /* */ /******************************************************************************/ -#define UART0 ((UART_TypeDef *) UARTA0_BASE) -#define UART1 ((UART_TypeDef *) UARTA1_BASE) - -//***************************************************************************** -// -// The following are defines for the UART register offsets. -// -//***************************************************************************** -#define UART_O_DR 0x00000000 -#define UART_O_RSR 0x00000004 -#define UART_O_ECR 0x00000004 -#define UART_O_FR 0x00000018 -#define UART_O_ILPR 0x00000020 -#define UART_O_IBRD 0x00000024 -#define UART_O_FBRD 0x00000028 -#define UART_O_LCRH 0x0000002C -#define UART_O_CTL 0x00000030 -#define UART_O_IFLS 0x00000034 -#define UART_O_IM 0x00000038 -#define UART_O_RIS 0x0000003C -#define UART_O_MIS 0x00000040 -#define UART_O_ICR 0x00000044 -#define UART_O_DMACTL 0x00000048 -#define UART_O_LCTL 0x00000090 -#define UART_O_LSS 0x00000094 -#define UART_O_LTIM 0x00000098 -#define UART_O_9BITADDR 0x000000A4 -#define UART_O_9BITAMASK 0x000000A8 -#define UART_O_PP 0x00000FC0 -#define UART_O_CC 0x00000FC8 -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_DR register. -// -//****************************************************************************** -#define UART_DR_OE 0x00000800 // UART Overrun Error -#define UART_DR_BE 0x00000400 // UART Break Error -#define UART_DR_PE 0x00000200 // UART Parity Error -#define UART_DR_FE 0x00000100 // UART Framing Error -#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received -#define UART_DR_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_RSR register. -// -//****************************************************************************** -#define UART_RSR_OE 0x00000008 // UART Overrun Error -#define UART_RSR_BE 0x00000004 // UART Break Error -#define UART_RSR_PE 0x00000002 // UART Parity Error -#define UART_RSR_FE 0x00000001 // UART Framing Error -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ECR register. -// -//****************************************************************************** -#define UART_ECR_DATA_M 0x000000FF // Error Clear -#define UART_ECR_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_FR register. -// -//****************************************************************************** -#define UART_FR_RI 0x00000100 // Ring Indicator -#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty -#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full -#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full -#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty -#define UART_FR_BUSY 0x00000008 // UART Busy -#define UART_FR_DCD 0x00000004 // Data Carrier Detect -#define UART_FR_DSR 0x00000002 // Data Set Ready -#define UART_FR_CTS 0x00000001 // Clear To Send -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ILPR register. -// -//****************************************************************************** -#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor -#define UART_ILPR_ILPDVSR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IBRD register. -// -//****************************************************************************** -#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor -#define UART_IBRD_DIVINT_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_FBRD register. -// -//****************************************************************************** -#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor -#define UART_FBRD_DIVFRAC_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_LCRH register. -// -//****************************************************************************** -#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select -#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length 0x00000000 : - // UART_LCRH_WLEN_5 : 5 bits - // (default) 0x00000020 : - // UART_LCRH_WLEN_6 : 6 bits - // 0x00000040 : UART_LCRH_WLEN_7 : 7 - // bits 0x00000060 : - // UART_LCRH_WLEN_8 : 8 bits -#define UART_LCRH_WLEN_S 5 -#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs -#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select -#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select -#define UART_LCRH_PEN 0x00000002 // UART Parity Enable -#define UART_LCRH_BRK 0x00000001 // UART Send Break -#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length -#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) -#define UART_LCRH_WLEN_6 0x00000020 // 6 bits -#define UART_LCRH_WLEN_7 0x00000040 // 7 bits -#define UART_LCRH_WLEN_8 0x00000060 // 8 bits -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_CTL register. -// -//****************************************************************************** -#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send -#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send -#define UART_CTL_RI 0x00002000 // Ring Indicator -#define UART_CTL_DCD 0x00001000 // Data Carrier Detect -#define UART_CTL_RTS 0x00000800 // Request to Send -#define UART_CTL_DTR 0x00000400 // Data Terminal Ready -#define UART_CTL_RXE 0x00000200 // UART Receive Enable -#define UART_CTL_TXE 0x00000100 // UART Transmit Enable -#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable -#define UART_CTL_LIN 0x00000040 // LIN Mode Enable -#define UART_CTL_HSE 0x00000020 // High-Speed Enable -#define UART_CTL_EOT 0x00000010 // End of Transmission -#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support -#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode -#define UART_CTL_SIREN 0x00000002 // UART SIR Enable -#define UART_CTL_UARTEN 0x00000001 // UART Enable -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IFLS register. -// -//****************************************************************************** -#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO - // Level Select -#define UART_IFLS_RX_S 3 -#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO - // Level Select -#define UART_IFLS_TX_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IM register. -// -//****************************************************************************** -#define UART_IM_DMATXIM 0x00020000 // Transmit DMA Interrupt Mask -#define UART_IM_DMARXIM 0x00010000 // Receive DMA Interrupt Mask -#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask -#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask -#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt - // Mask -#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask -#define UART_IM_EOTIM 0x00000800 // End of Transmission Interrupt - // Mask -#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt - // Mask -#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask -#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask -#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt - // Mask -#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt - // Mask -#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask -#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask -#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem - // Interrupt Mask -#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem - // Interrupt Mask -#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem - // Interrupt Mask -#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem - // Interrupt Mask -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_RIS register. -// -//****************************************************************************** -#define UART_RIS_DMATXRIS 0x00020000 // Transmit DMA Raw Interrupt - // Status -#define UART_RIS_DMARXRIS 0x00010000 // Receive DMA Raw Interrupt Status -#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt - // Status -#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt - // Status -#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw - // Interrupt Status -#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status -#define UART_RIS_EOTRIS 0x00000800 // End of Transmission Raw - // Interrupt Status -#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt - // Status -#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt - // Status -#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt - // Status -#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt - // Status -#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw - // Interrupt Status -#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt - // Status -#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt - // Status -#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw - // Interrupt Status -#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem - // Raw Interrupt Status -#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw - // Interrupt Status -#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw - // Interrupt Status -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_MIS register. -// -//****************************************************************************** -#define UART_MIS_DMATXMIS 0x00020000 // Transmit DMA Masked Interrupt - // Status -#define UART_MIS_DMARXMIS 0x00010000 // Receive DMA Masked Interrupt - // Status -#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt - // Status -#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt - // Status -#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked - // Interrupt Status -#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt - // Status -#define UART_MIS_EOTMIS 0x00000800 // End of Transmission Masked - // Interrupt Status -#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked - // Interrupt Status -#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked - // Interrupt Status -#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked - // Interrupt Status -#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked - // Interrupt Status -#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked - // Interrupt Status -#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt - // Status -#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt - // Status -#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked - // Interrupt Status -#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem - // Masked Interrupt Status -#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked - // Interrupt Status -#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked - // Interrupt Status -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ICR register. -// -//****************************************************************************** -#define UART_ICR_DMATXIC 0x00020000 // Transmit DMA Interrupt Clear -#define UART_ICR_DMARXIC 0x00010000 // Receive DMA Interrupt Clear -#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear -#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear -#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt - // Clear -#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear -#define UART_ICR_EOTIC 0x00000800 // End of Transmission Interrupt - // Clear -#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear -#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear -#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear -#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear -#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear -#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear -#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear -#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem - // Interrupt Clear -#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem - // Interrupt Clear -#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem - // Interrupt Clear -#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem - // Interrupt Clear -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_DMACTL register. -// -//****************************************************************************** -#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error -#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable -#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_LCTL register. -// -//****************************************************************************** -#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length 0x00000000 : - // UART_LCTL_BLEN_13T : Sync break - // length is 13T bits (default) - // 0x00000010 : UART_LCTL_BLEN_14T : - // Sync break length is 14T bits - // 0x00000020 : UART_LCTL_BLEN_15T : - // Sync break length is 15T bits - // 0x00000030 : UART_LCTL_BLEN_16T : - // Sync break length is 16T bits -#define UART_LCTL_BLEN_S 4 -#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_LSS register. -// -//****************************************************************************** -#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot -#define UART_LSS_TSS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_LTIM register. -// -//****************************************************************************** -#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value -#define UART_LTIM_TIMER_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// UART_O_9BITADDR register. -// -//****************************************************************************** -#define UART_9BITADDR_9BITEN \ - 0x00008000 // Enable 9-Bit Mode - -#define UART_9BITADDR_ADDR_M \ - 0x000000FF // Self Address for 9-Bit Mode - -#define UART_9BITADDR_ADDR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// UART_O_9BITAMASK register. -// -//****************************************************************************** -#define UART_9BITAMASK_RANGE_M \ - 0x0000FF00 // Self Address Range for 9-Bit - // Mode - -#define UART_9BITAMASK_RANGE_S 8 -#define UART_9BITAMASK_MASK_M \ - 0x000000FF // Self Address Mask for 9-Bit Mode - -#define UART_9BITAMASK_MASK_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_PP register. -// -//****************************************************************************** -#define UART_PP_MSE 0x00000008 // Modem Support Extended -#define UART_PP_MS 0x00000004 // Modem Support -#define UART_PP_NB 0x00000002 // 9-Bit Support -#define UART_PP_SC 0x00000001 // Smart Card Support -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_CC register. -// -//****************************************************************************** -#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source - // 0x00000005 : UART_CC_CS_PIOSC : - // PIOSC 0x00000000 : - // UART_CC_CS_SYSCLK : The system - // clock (default) -#define UART_CC_CS_S 0 +#define CC3220SF_UART0 ((CC3220SF_UART_TypeDef *) CC3220SF_UARTA0_BASE) +#define CC3220SF_UART1 ((CC3220SF_UART_TypeDef *) CC3220SF_UARTA1_BASE) + /** diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/objects.h b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/objects.h index 01531d16279..59e70143960 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/objects.h +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/objects.h @@ -32,6 +32,7 @@ typedef struct { } gpio_t; struct serial_s { + CC3220SF_UART_TypeDef *uart; int index; }; diff --git a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/serial_api.c b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/serial_api.c index 5ab833d3138..2a4e0ca3136 100644 --- a/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/serial_api.c +++ b/targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/serial_api.c @@ -82,6 +82,26 @@ static const PinMap PinMap_UART_CTS[] = { {NC, NC, 0} }; +static const uint32_t dataLength[] = { + UART_CONFIG_WLEN_5, /* UART_LEN_5 = 0 */ + UART_CONFIG_WLEN_6, /* UART_LEN_6 = 1 */ + UART_CONFIG_WLEN_7, /* UART_LEN_7 = 2 */ + UART_CONFIG_WLEN_8 /* UART_LEN_8 = 3 */ +}; + +static const uint32_t stopBits[] = { + UART_CONFIG_STOP_ONE, /* UART_STOP_ONE = 0 */ + UART_CONFIG_STOP_TWO /* UART_STOP_TWO = 1 */ +}; + +static const uint32_t parityType[] = { + UART_CONFIG_PAR_NONE, /* UART_PAR_NONE = 0 */ + UART_CONFIG_PAR_EVEN, /* UART_PAR_EVEN = 1 */ + UART_CONFIG_PAR_ODD, /* UART_PAR_ODD = 2 */ + UART_CONFIG_PAR_ZERO, /* UART_PAR_ZERO = 3 */ + UART_CONFIG_PAR_ONE /* UART_PAR_ONE = 4 */ +}; + static uart_irq_handler irq_handler; int stdio_uart_inited = 0; @@ -104,7 +124,64 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx); MBED_ASSERT((int)uart != NC); - // TODO + obj->uart = (CC3220SF_UART_TypeDef *)uart; + switch(uart) { + case UART_0: { + unsigned long ulBase = (long) CC3220SF_UARTA0_BASE; + /* Enable UART and its interrupt. */ + UARTIntClear(ulBase, UART_INT_TX | UART_INT_RX | UART_INT_RT); + UARTEnable(ulBase); + /* Set the FIFO level to 7/8 empty and 4/8 full. */ + UARTFIFOLevelSet(ulBase, UART_FIFO_TX1_8, UART_FIFO_RX1_8); + /* Set flow control */ + //UARTFlowControlSet(ulBase, UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX); + UARTFlowControlSet(ulBase, UART_FLOWCONTROL_NONE); + UARTIntEnable(ulBase, UART_INT_RX | UART_INT_RT | + UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE); + } + break; + case UART_1: { + unsigned long ulBase = (long) CC3220SF_UARTA1_BASE; + /* Enable UART and its interrupt. */ + UARTIntClear(ulBase, UART_INT_TX | UART_INT_RX | UART_INT_RT); + UARTEnable(ulBase); + /* Set the FIFO level to 7/8 empty and 4/8 full. */ + UARTFIFOLevelSet(ulBase, UART_FIFO_TX1_8, UART_FIFO_RX1_8); + /* Set flow control */ + //UARTFlowControlSet(ulBase, UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX); + UARTFlowControlSet(ulBase, UART_FLOWCONTROL_NONE); + UARTIntEnable(ulBase, UART_INT_RX | UART_INT_RT | + UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE); + } + break; + } + + // set default baud rate and format + serial_baud(obj, 9600); + + // pinout the chosen uart + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + switch (uart) { + case UART_0: + obj->index = 0; + break; + case UART_1: + obj->index = 1; + break; + } + + uart_data[obj->index].sw_rts.pin = NC; + uart_data[obj->index].sw_cts.pin = NC; + serial_set_flow_control(obj, FlowControlNone, NC, NC); + + is_stdio_uart = (uart == STDIO_UART) ? (1) : (0); + + if (is_stdio_uart) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } } void serial_free(serial_t *obj) { @@ -119,6 +196,9 @@ void serial_baud(serial_t *obj, int baudrate) { void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { // TODO + /**UARTConfigSetExpClk(ulBase, freq.lo, (long) 9600, + dataLength[object->dataLength] | stopBits[object->stopBits] | + parityType[object->parityType]); **/ } /****************************************************************************** @@ -179,5 +259,5 @@ void serial_break_clear(serial_t *obj) { } void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) { - // TODO + //UARTFlowControlSet(ulBase, UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX); }