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[ExportVerilog] Fix ifdef of macro w/ Verilog name #20760

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[ExportVerilog] Fix ifdef of macro w/ Verilog name

[ExportVerilog] Fix ifdef of macro w/ Verilog name #20760

Triggered via pull request December 4, 2024 22:49
@seldridgeseldridge
opened #7947
dev/seldridge/fix-ifdef-text-macro-identifier-emission
Status Success
Total duration 11m 20s
Artifacts –

shortIntegrationTests.yml

on: pull_request
Matrix: Build and Test
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