[ExportVerilog] Fix ifdef of macro w/ Verilog name

Fix a bug in the emission of `sv.ifdef` (and its procedural variant) where
the symbol name was always used instead of using the symbol name only if a
Verilog name was not specified.

This is done to fix an issue related to lowering of FIRRTL inline layers
where the `LowerLayers` pass generates new `sv.macro.decl` symbols that
will replace existing `firrtl.layer` symbols.  However, it relies on a
namespace to generate these and will result in suffixed symbol names.  (It
could obviously do more work to conserve symbols or generate in-pass
invalid IR with duplicate symbols.)  Nonetheless, the real bug here is
that the `ExportVerilog` conversion is not doing the right thing with the
Verilog name attribute.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

lib/Conversion/ExportVerilog/ExportVerilog.cpp

@@ -5007,7 +5007,9 @@ LogicalResult StmtEmitter::emitIfDef(Operation *op, MacroIdentAttr cond) {
   if (hasSVAttributes(op))
     emitError(op, "SV attributes emission is unimplemented for the op");
 
-  auto ident = PPExtString(cond.getName());
+  auto ident = PPExtString(
+      cast<MacroDeclOp>(state.symbolCache.getDefinition(cond.getIdent()))
+          .getMacroIdentifier());
 
   startStatement();
   bool hasEmptyThen = op->getRegion(0).front().empty();

test/Conversion/ExportVerilog/verilog-basic.mlir

@@ -771,6 +771,20 @@ hw.module @W422_Foo() {
   hw.output
 }
 
+sv.macro.decl @MacroWithoutVerilogName
+sv.macro.decl @MacroWithVerilogName["A"]
+// CHECK-LABEL: module ModuleUsingMacroWithVerilogName(
+hw.module @ModuleUsingMacroWithVerilogName(in %a : i1) {
+  // CHECK: `ifdef MacroWithoutVerilogName
+  sv.ifdef @MacroWithoutVerilogName {
+    %b = hw.wire %a : i1
+  }
+  // CHECK: `ifdef A
+  sv.ifdef @MacroWithVerilogName {
+    %b = hw.wire %a : i1
+  }
+}
+
 hw.module @BindInterface() {
   %bar = sv.interface.instance sym @__Interface__ {doNotPrint} : !sv.interface<@Interface>
   hw.output