[CIR][CIRGen] Support __builtin_signbitl

llvm · Nov 13, 2024 · 517aa65 · 517aa65
1 parent 5c5d584
commit 517aa65
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Showing 2 changed files with 15 additions and 2 deletions.
diff --git a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp
@@ -4333,8 +4333,11 @@ class CIRSignBitOpLowering : public mlir::OpConversionPattern<cir::SignBitOp> {
     if (auto longDoubleType =
             mlir::dyn_cast<cir::LongDoubleType>(op.getInput().getType())) {
       if (mlir::isa<cir::FP80Type>(longDoubleType.getUnderlying())) {
-        // see https://github.com/llvm/clangir/issues/1057
-        llvm_unreachable("NYI");
+        // If the underlying type of LongDouble is FP80Type,
+        // DataLayout::getTypeSizeInBits returns 128.
+        // See https://github.com/llvm/clangir/issues/1057.
+        // Set the width to 80 manually.
+        width = 80;
       }
     }
     auto intTy = mlir::IntegerType::get(rewriter.getContext(), width);

diff --git a/clang/test/CIR/CodeGen/builtin-signbit.c b/clang/test/CIR/CodeGen/builtin-signbit.c
@@ -23,3 +23,13 @@ void test_signbit_double(double val) {
     // LLVM: %{{.+}} = zext i1 [[TMP2]] to i32
     __builtin_signbitf(val);
 }
+
+void test_signbit_long_double(long double val) {
+    // CIR: test_signbit_long_double
+    // LLVM: test_signbit_long_double
+    __builtin_signbitl(val);
+    // CIR: %{{.+}} = cir.signbit %{{.+}} : !cir.long_double<!cir.f80> -> !s32i
+    // LLVM: [[TMP1:%.*]] = bitcast x86_fp80 %{{.+}} to i80
+    // LLVM: [[TMP2:%.*]] = icmp slt i80 [[TMP1]], 0
+    // LLVM: %{{.+}} = zext i1 [[TMP2]] to i32
+}