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[RISCV][MC] Enable printing of zext.b alias (#133502)
The comment shows that at the time we were worried about producing the alias in assembly that might be ingested by a binutils version that doesn't yet support it. binutils gained support over 4 years ago <https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=c2137f55ad04e451d834048d4bfec1de2daea20e>. With all the changes in areas such as ELF attributes, if you tried to use LLVM's RISC-V assembler output with a binutils that old then zext.b would be the least of your worries.
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‎llvm/lib/Target/RISCV/RISCVInstrInfo.td‎

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1118,10 +1118,7 @@ def : MnemonicAlias<"move", "mv">;
11181118
def : MnemonicAlias<"scall", "ecall">;
11191119
def : MnemonicAlias<"sbreak", "ebreak">;
11201120

1121-
// This alias was added to the spec in December 2020. Don't print it by default
1122-
// to allow assembly we print to be compatible with versions of GNU assembler
1123-
// that don't support this alias.
1124-
def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF), 0>;
1121+
def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 0xFF)>;
11251122

11261123
let Predicates = [HasStdExtZicfilp] in {
11271124
def : InstAlias<"lpad $imm20", (AUIPC X0, uimm20:$imm20)>;

‎llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -49,15 +49,15 @@ entry:
4949
define i32 @add_i8_zeroext_i32(i8 %a, i8 %b) {
5050
; RV32IM-LABEL: add_i8_zeroext_i32:
5151
; RV32IM: # %bb.0: # %entry
52-
; RV32IM-NEXT: andi a0, a0, 255
53-
; RV32IM-NEXT: andi a1, a1, 255
52+
; RV32IM-NEXT: zext.b a0, a0
53+
; RV32IM-NEXT: zext.b a1, a1
5454
; RV32IM-NEXT: add a0, a0, a1
5555
; RV32IM-NEXT: ret
5656
;
5757
; RV64IM-LABEL: add_i8_zeroext_i32:
5858
; RV64IM: # %bb.0: # %entry
59-
; RV64IM-NEXT: andi a0, a0, 255
60-
; RV64IM-NEXT: andi a1, a1, 255
59+
; RV64IM-NEXT: zext.b a0, a0
60+
; RV64IM-NEXT: zext.b a1, a1
6161
; RV64IM-NEXT: addw a0, a0, a1
6262
; RV64IM-NEXT: ret
6363
entry:

‎llvm/test/CodeGen/RISCV/GlobalISel/div-by-constant.ll‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -227,15 +227,15 @@ define i64 @udiv64_constant_add(i64 %a) nounwind {
227227
define i8 @udiv8_constant_no_add(i8 %a) nounwind {
228228
; RV32-LABEL: udiv8_constant_no_add:
229229
; RV32: # %bb.0:
230-
; RV32-NEXT: andi a0, a0, 255
230+
; RV32-NEXT: zext.b a0, a0
231231
; RV32-NEXT: li a1, 205
232232
; RV32-NEXT: mul a0, a0, a1
233233
; RV32-NEXT: srli a0, a0, 10
234234
; RV32-NEXT: ret
235235
;
236236
; RV64-LABEL: udiv8_constant_no_add:
237237
; RV64: # %bb.0:
238-
; RV64-NEXT: andi a0, a0, 255
238+
; RV64-NEXT: zext.b a0, a0
239239
; RV64-NEXT: li a1, 205
240240
; RV64-NEXT: mul a0, a0, a1
241241
; RV64-NEXT: srli a0, a0, 10
@@ -248,28 +248,28 @@ define i8 @udiv8_constant_add(i8 %a) nounwind {
248248
; RV32-LABEL: udiv8_constant_add:
249249
; RV32: # %bb.0:
250250
; RV32-NEXT: li a1, 37
251-
; RV32-NEXT: andi a2, a0, 255
251+
; RV32-NEXT: zext.b a2, a0
252252
; RV32-NEXT: mul a1, a2, a1
253253
; RV32-NEXT: srli a1, a1, 8
254254
; RV32-NEXT: sub a0, a0, a1
255-
; RV32-NEXT: andi a0, a0, 255
255+
; RV32-NEXT: zext.b a0, a0
256256
; RV32-NEXT: srli a0, a0, 1
257257
; RV32-NEXT: add a0, a0, a1
258-
; RV32-NEXT: andi a0, a0, 255
258+
; RV32-NEXT: zext.b a0, a0
259259
; RV32-NEXT: srli a0, a0, 2
260260
; RV32-NEXT: ret
261261
;
262262
; RV64-LABEL: udiv8_constant_add:
263263
; RV64: # %bb.0:
264264
; RV64-NEXT: li a1, 37
265-
; RV64-NEXT: andi a2, a0, 255
265+
; RV64-NEXT: zext.b a2, a0
266266
; RV64-NEXT: mul a1, a2, a1
267267
; RV64-NEXT: srli a1, a1, 8
268268
; RV64-NEXT: subw a0, a0, a1
269-
; RV64-NEXT: andi a0, a0, 255
269+
; RV64-NEXT: zext.b a0, a0
270270
; RV64-NEXT: srli a0, a0, 1
271271
; RV64-NEXT: add a0, a0, a1
272-
; RV64-NEXT: andi a0, a0, 255
272+
; RV64-NEXT: zext.b a0, a0
273273
; RV64-NEXT: srli a0, a0, 2
274274
; RV64-NEXT: ret
275275
%1 = udiv i8 %a, 7

‎llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -855,15 +855,15 @@ define zeroext i8 @fcvt_wu_s_i8(double %a) nounwind {
855855
; CHECKIFD-LABEL: fcvt_wu_s_i8:
856856
; CHECKIFD: # %bb.0:
857857
; CHECKIFD-NEXT: fcvt.wu.d a0, fa0, rtz
858-
; CHECKIFD-NEXT: andi a0, a0, 255
858+
; CHECKIFD-NEXT: zext.b a0, a0
859859
; CHECKIFD-NEXT: ret
860860
;
861861
; RV32I-LABEL: fcvt_wu_s_i8:
862862
; RV32I: # %bb.0:
863863
; RV32I-NEXT: addi sp, sp, -16
864864
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
865865
; RV32I-NEXT: call __fixunsdfsi
866-
; RV32I-NEXT: andi a0, a0, 255
866+
; RV32I-NEXT: zext.b a0, a0
867867
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
868868
; RV32I-NEXT: addi sp, sp, 16
869869
; RV32I-NEXT: ret
@@ -873,7 +873,7 @@ define zeroext i8 @fcvt_wu_s_i8(double %a) nounwind {
873873
; RV64I-NEXT: addi sp, sp, -16
874874
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
875875
; RV64I-NEXT: call __fixunsdfsi
876-
; RV64I-NEXT: andi a0, a0, 255
876+
; RV64I-NEXT: zext.b a0, a0
877877
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
878878
; RV64I-NEXT: addi sp, sp, 16
879879
; RV64I-NEXT: ret

‎llvm/test/CodeGen/RISCV/GlobalISel/float-convert.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -790,15 +790,15 @@ define zeroext i8 @fcvt_wu_s_i8(float %a) nounwind {
790790
; CHECKIF-LABEL: fcvt_wu_s_i8:
791791
; CHECKIF: # %bb.0:
792792
; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rtz
793-
; CHECKIF-NEXT: andi a0, a0, 255
793+
; CHECKIF-NEXT: zext.b a0, a0
794794
; CHECKIF-NEXT: ret
795795
;
796796
; RV32I-LABEL: fcvt_wu_s_i8:
797797
; RV32I: # %bb.0:
798798
; RV32I-NEXT: addi sp, sp, -16
799799
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
800800
; RV32I-NEXT: call __fixunssfsi
801-
; RV32I-NEXT: andi a0, a0, 255
801+
; RV32I-NEXT: zext.b a0, a0
802802
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
803803
; RV32I-NEXT: addi sp, sp, 16
804804
; RV32I-NEXT: ret
@@ -808,7 +808,7 @@ define zeroext i8 @fcvt_wu_s_i8(float %a) nounwind {
808808
; RV64I-NEXT: addi sp, sp, -16
809809
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
810810
; RV64I-NEXT: call __fixunssfsi
811-
; RV64I-NEXT: andi a0, a0, 255
811+
; RV64I-NEXT: zext.b a0, a0
812812
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
813813
; RV64I-NEXT: addi sp, sp, 16
814814
; RV64I-NEXT: ret

‎llvm/test/CodeGen/RISCV/GlobalISel/fp128.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -469,7 +469,7 @@ define fp128 @uitofp_i8(i8 %x) nounwind {
469469
; CHECK: # %bb.0:
470470
; CHECK-NEXT: addi sp, sp, -16
471471
; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
472-
; CHECK-NEXT: andi a0, a0, 255
472+
; CHECK-NEXT: zext.b a0, a0
473473
; CHECK-NEXT: call __floatunsitf
474474
; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
475475
; CHECK-NEXT: addi sp, sp, 16

‎llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb-zbkb.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -327,7 +327,7 @@ define i64 @rori_i64_fshr(i64 %a) nounwind {
327327
define i8 @srli_i8(i8 %a) nounwind {
328328
; CHECK-LABEL: srli_i8:
329329
; CHECK: # %bb.0:
330-
; CHECK-NEXT: andi a0, a0, 255
330+
; CHECK-NEXT: zext.b a0, a0
331331
; CHECK-NEXT: srli a0, a0, 6
332332
; CHECK-NEXT: ret
333333
%1 = lshr i8 %a, 6

‎llvm/test/CodeGen/RISCV/GlobalISel/rv32zbkb.ll‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -110,7 +110,7 @@ define i32 @packh_i32(i32 %a, i32 %b) nounwind {
110110
; CHECK-LABEL: packh_i32:
111111
; CHECK: # %bb.0:
112112
; CHECK-NEXT: lui a2, 16
113-
; CHECK-NEXT: andi a0, a0, 255
113+
; CHECK-NEXT: zext.b a0, a0
114114
; CHECK-NEXT: addi a2, a2, -256
115115
; CHECK-NEXT: slli a1, a1, 8
116116
; CHECK-NEXT: and a1, a1, a2
@@ -126,8 +126,8 @@ define i32 @packh_i32(i32 %a, i32 %b) nounwind {
126126
define i32 @packh_i32_2(i32 %a, i32 %b) nounwind {
127127
; RV32I-LABEL: packh_i32_2:
128128
; RV32I: # %bb.0:
129-
; RV32I-NEXT: andi a0, a0, 255
130-
; RV32I-NEXT: andi a1, a1, 255
129+
; RV32I-NEXT: zext.b a0, a0
130+
; RV32I-NEXT: zext.b a1, a1
131131
; RV32I-NEXT: slli a1, a1, 8
132132
; RV32I-NEXT: or a0, a1, a0
133133
; RV32I-NEXT: ret
@@ -148,7 +148,7 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind {
148148
; CHECK-LABEL: packh_i64:
149149
; CHECK: # %bb.0:
150150
; CHECK-NEXT: lui a1, 16
151-
; CHECK-NEXT: andi a0, a0, 255
151+
; CHECK-NEXT: zext.b a0, a0
152152
; CHECK-NEXT: addi a1, a1, -256
153153
; CHECK-NEXT: slli a2, a2, 8
154154
; CHECK-NEXT: and a1, a2, a1
@@ -166,16 +166,16 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind {
166166
define i64 @packh_i64_2(i64 %a, i64 %b) nounwind {
167167
; RV32I-LABEL: packh_i64_2:
168168
; RV32I: # %bb.0:
169-
; RV32I-NEXT: andi a0, a0, 255
170-
; RV32I-NEXT: andi a1, a2, 255
169+
; RV32I-NEXT: zext.b a0, a0
170+
; RV32I-NEXT: zext.b a1, a2
171171
; RV32I-NEXT: slli a2, a1, 8
172172
; RV32I-NEXT: srli a1, a1, 24
173173
; RV32I-NEXT: or a0, a2, a0
174174
; RV32I-NEXT: ret
175175
;
176176
; RV32ZBKB-LABEL: packh_i64_2:
177177
; RV32ZBKB: # %bb.0:
178-
; RV32ZBKB-NEXT: andi a1, a2, 255
178+
; RV32ZBKB-NEXT: zext.b a1, a2
179179
; RV32ZBKB-NEXT: srli a1, a1, 24
180180
; RV32ZBKB-NEXT: packh a0, a0, a2
181181
; RV32ZBKB-NEXT: ret
@@ -210,7 +210,7 @@ define zeroext i16 @packh_i16_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2) {
210210
; RV32I-LABEL: packh_i16_2:
211211
; RV32I: # %bb.0:
212212
; RV32I-NEXT: add a0, a1, a0
213-
; RV32I-NEXT: andi a0, a0, 255
213+
; RV32I-NEXT: zext.b a0, a0
214214
; RV32I-NEXT: slli a0, a0, 8
215215
; RV32I-NEXT: or a0, a0, a2
216216
; RV32I-NEXT: ret
@@ -232,7 +232,7 @@ define void @packh_i16_3(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, ptr %p) {
232232
; RV32I-LABEL: packh_i16_3:
233233
; RV32I: # %bb.0:
234234
; RV32I-NEXT: add a0, a1, a0
235-
; RV32I-NEXT: andi a0, a0, 255
235+
; RV32I-NEXT: zext.b a0, a0
236236
; RV32I-NEXT: slli a0, a0, 8
237237
; RV32I-NEXT: or a0, a0, a2
238238
; RV32I-NEXT: sh a0, 0(a3)

‎llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -405,7 +405,7 @@ define i64 @rori_i64_fshr(i64 %a) nounwind {
405405
define i8 @srli_i8(i8 %a) nounwind {
406406
; CHECK-LABEL: srli_i8:
407407
; CHECK: # %bb.0:
408-
; CHECK-NEXT: andi a0, a0, 255
408+
; CHECK-NEXT: zext.b a0, a0
409409
; CHECK-NEXT: srli a0, a0, 6
410410
; CHECK-NEXT: ret
411411
%1 = lshr i8 %a, 6

‎llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -140,7 +140,7 @@ define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {
140140
; RV64I-LABEL: packh_i32:
141141
; RV64I: # %bb.0:
142142
; RV64I-NEXT: lui a2, 16
143-
; RV64I-NEXT: andi a0, a0, 255
143+
; RV64I-NEXT: zext.b a0, a0
144144
; RV64I-NEXT: addiw a2, a2, -256
145145
; RV64I-NEXT: slli a1, a1, 8
146146
; RV64I-NEXT: and a1, a1, a2
@@ -150,7 +150,7 @@ define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {
150150
; RV64ZBKB-LABEL: packh_i32:
151151
; RV64ZBKB: # %bb.0:
152152
; RV64ZBKB-NEXT: lui a2, 16
153-
; RV64ZBKB-NEXT: andi a0, a0, 255
153+
; RV64ZBKB-NEXT: zext.b a0, a0
154154
; RV64ZBKB-NEXT: addiw a2, a2, -256
155155
; RV64ZBKB-NEXT: slli a1, a1, 8
156156
; RV64ZBKB-NEXT: and a1, a1, a2
@@ -166,8 +166,8 @@ define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {
166166
define i32 @packh_i32_2(i32 %a, i32 %b) nounwind {
167167
; RV64I-LABEL: packh_i32_2:
168168
; RV64I: # %bb.0:
169-
; RV64I-NEXT: andi a0, a0, 255
170-
; RV64I-NEXT: andi a1, a1, 255
169+
; RV64I-NEXT: zext.b a0, a0
170+
; RV64I-NEXT: zext.b a1, a1
171171
; RV64I-NEXT: slli a1, a1, 8
172172
; RV64I-NEXT: or a0, a1, a0
173173
; RV64I-NEXT: ret
@@ -188,7 +188,7 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind {
188188
; RV64I-LABEL: packh_i64:
189189
; RV64I: # %bb.0:
190190
; RV64I-NEXT: lui a2, 16
191-
; RV64I-NEXT: andi a0, a0, 255
191+
; RV64I-NEXT: zext.b a0, a0
192192
; RV64I-NEXT: addiw a2, a2, -256
193193
; RV64I-NEXT: slli a1, a1, 8
194194
; RV64I-NEXT: and a1, a1, a2
@@ -198,7 +198,7 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind {
198198
; RV64ZBKB-LABEL: packh_i64:
199199
; RV64ZBKB: # %bb.0:
200200
; RV64ZBKB-NEXT: lui a2, 16
201-
; RV64ZBKB-NEXT: andi a0, a0, 255
201+
; RV64ZBKB-NEXT: zext.b a0, a0
202202
; RV64ZBKB-NEXT: addiw a2, a2, -256
203203
; RV64ZBKB-NEXT: slli a1, a1, 8
204204
; RV64ZBKB-NEXT: and a1, a1, a2
@@ -214,8 +214,8 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind {
214214
define i64 @packh_i64_2(i64 %a, i64 %b) nounwind {
215215
; RV64I-LABEL: packh_i64_2:
216216
; RV64I: # %bb.0:
217-
; RV64I-NEXT: andi a0, a0, 255
218-
; RV64I-NEXT: andi a1, a1, 255
217+
; RV64I-NEXT: zext.b a0, a0
218+
; RV64I-NEXT: zext.b a1, a1
219219
; RV64I-NEXT: slli a1, a1, 8
220220
; RV64I-NEXT: or a0, a1, a0
221221
; RV64I-NEXT: ret
@@ -253,7 +253,7 @@ define zeroext i16 @packh_i16_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2) {
253253
; RV64I-LABEL: packh_i16_2:
254254
; RV64I: # %bb.0:
255255
; RV64I-NEXT: add a0, a1, a0
256-
; RV64I-NEXT: andi a0, a0, 255
256+
; RV64I-NEXT: zext.b a0, a0
257257
; RV64I-NEXT: slli a0, a0, 8
258258
; RV64I-NEXT: or a0, a0, a2
259259
; RV64I-NEXT: ret
@@ -275,7 +275,7 @@ define void @packh_i16_3(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, ptr %p) {
275275
; RV64I-LABEL: packh_i16_3:
276276
; RV64I: # %bb.0:
277277
; RV64I-NEXT: add a0, a1, a0
278-
; RV64I-NEXT: andi a0, a0, 255
278+
; RV64I-NEXT: zext.b a0, a0
279279
; RV64I-NEXT: slli a0, a0, 8
280280
; RV64I-NEXT: or a0, a0, a2
281281
; RV64I-NEXT: sh a0, 0(a3)

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