diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index 2f72165814ffa7..42b8248006d1fd 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -1731,16 +1731,12 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
   setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
 
-  setOperationAction(ISD::ADDC, MVT::i32, Custom);
-  setOperationAction(ISD::ADDE, MVT::i32, Custom);
-  setOperationAction(ISD::SUBC, MVT::i32, Custom);
-  setOperationAction(ISD::SUBE, MVT::i32, Custom);
+  setOperationAction(ISD::ADDC, MVT::i32, Legal);
+  setOperationAction(ISD::ADDE, MVT::i32, Legal);
+  setOperationAction(ISD::SUBC, MVT::i32, Legal);
+  setOperationAction(ISD::SUBE, MVT::i32, Legal);
 
   if (Subtarget->is64Bit()) {
-    setOperationAction(ISD::ADDC, MVT::i64, Custom);
-    setOperationAction(ISD::ADDE, MVT::i64, Custom);
-    setOperationAction(ISD::SUBC, MVT::i64, Custom);
-    setOperationAction(ISD::SUBE, MVT::i64, Custom);
     setOperationAction(ISD::BITCAST, MVT::f64, Expand);
     setOperationAction(ISD::BITCAST, MVT::i64, Expand);
     setOperationAction(ISD::SELECT, MVT::i64, Expand);
@@ -3102,55 +3098,6 @@ static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
   return DstReg128;
 }
 
-static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
-
-  if (Op.getValueType() != MVT::i64)
-    return Op;
-
-  SDLoc dl(Op);
-  SDValue Src1 = Op.getOperand(0);
-  SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1);
-  SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1,
-                               DAG.getConstant(32, dl, MVT::i64));
-  Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi);
-
-  SDValue Src2 = Op.getOperand(1);
-  SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2);
-  SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2,
-                               DAG.getConstant(32, dl, MVT::i64));
-  Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi);
-
-
-  bool hasChain = false;
-  unsigned hiOpc = Op.getOpcode();
-  switch (Op.getOpcode()) {
-  default: llvm_unreachable("Invalid opcode");
-  case ISD::ADDC: hiOpc = ISD::ADDE; break;
-  case ISD::ADDE: hasChain = true; break;
-  case ISD::SUBC: hiOpc = ISD::SUBE; break;
-  case ISD::SUBE: hasChain = true; break;
-  }
-  SDValue Lo;
-  SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Glue);
-  if (hasChain) {
-    Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo,
-                     Op.getOperand(2));
-  } else {
-    Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo);
-  }
-  SDValue Hi = DAG.getNode(hiOpc, dl, VTs, Src1Hi, Src2Hi, Lo.getValue(1));
-  SDValue Carry = Hi.getValue(1);
-
-  Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo);
-  Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi);
-  Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi,
-                   DAG.getConstant(32, dl, MVT::i64));
-
-  SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo);
-  SDValue Ops[2] = { Dst, Carry };
-  return DAG.getMergeValues(Ops, dl);
-}
-
 static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) {
   if (isStrongerThanMonotonic(cast<AtomicSDNode>(Op)->getSuccessOrdering())) {
     // Expand with a fence.
@@ -3225,10 +3172,6 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   case ISD::FNEG:               return LowerFNEGorFABS(Op, DAG, isV9);
   case ISD::FP_EXTEND:          return LowerF128_FPEXTEND(Op, DAG, *this);
   case ISD::FP_ROUND:           return LowerF128_FPROUND(Op, DAG, *this);
-  case ISD::ADDC:
-  case ISD::ADDE:
-  case ISD::SUBC:
-  case ISD::SUBE:               return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
   case ISD::ATOMIC_LOAD:
   case ISD::ATOMIC_STORE:       return LowerATOMIC_LOAD_STORE(Op, DAG);
   case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
diff --git a/llvm/test/CodeGen/SPARC/2011-01-11-CC.ll b/llvm/test/CodeGen/SPARC/2011-01-11-CC.ll
index c7bf71bb06c5b8..62cf06d7ee3c84 100644
--- a/llvm/test/CodeGen/SPARC/2011-01-11-CC.ll
+++ b/llvm/test/CodeGen/SPARC/2011-01-11-CC.ll
@@ -1,128 +1,459 @@
-; RUN: llc -march=sparc <%s | FileCheck %s -check-prefix=V8
-; RUN: llc -march=sparc -mattr=v9 <%s | FileCheck %s -check-prefix=V9
-; RUN: llc -mtriple=sparc64-unknown-linux <%s | FileCheck %s -check-prefix=SPARC64
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -march=sparc %s -o - | FileCheck %s -check-prefix=V8
+; RUN: llc -march=sparc -mattr=v9 %s -o - | FileCheck %s -check-prefix=V9
+; RUN: llc -mtriple=sparc64-unknown-linux %s -o - | FileCheck %s -check-prefix=SPARC64
 
-
-define i32 @test_addx(i64 %a, i64 %b, i64 %c) nounwind readnone noinline {
+define i32 @test_addx(i64 %a, i64 %b, i64 %c) nounwind {
+; V8-LABEL: test_addx:
+; V8:       ! %bb.0: ! %entry
+; V8-NEXT:    addcc %o1, %o3, %o3
+; V8-NEXT:    addxcc %o0, %o2, %o1
+; V8-NEXT:    mov 1, %o0
+; V8-NEXT:    cmp %o1, %o4
+; V8-NEXT:    bleu .LBB0_4
+; V8-NEXT:    mov %o0, %o2
+; V8-NEXT:  ! %bb.1: ! %entry
+; V8-NEXT:    cmp %o3, %o5
+; V8-NEXT:    bleu .LBB0_5
+; V8-NEXT:    nop
+; V8-NEXT:  .LBB0_2: ! %entry
+; V8-NEXT:    cmp %o1, %o4
+; V8-NEXT:    bne .LBB0_6
+; V8-NEXT:    nop
+; V8-NEXT:  .LBB0_3: ! %entry
+; V8-NEXT:    retl
+; V8-NEXT:    nop
+; V8-NEXT:  .LBB0_4: ! %entry
+; V8-NEXT:    mov %g0, %o2
+; V8-NEXT:    cmp %o3, %o5
+; V8-NEXT:    bgu .LBB0_2
+; V8-NEXT:    nop
+; V8-NEXT:  .LBB0_5: ! %entry
+; V8-NEXT:    mov %g0, %o0
+; V8-NEXT:    cmp %o1, %o4
+; V8-NEXT:    be .LBB0_3
+; V8-NEXT:    nop
+; V8-NEXT:  .LBB0_6: ! %entry
+; V8-NEXT:    retl
+; V8-NEXT:    mov %o2, %o0
+;
+; V9-LABEL: test_addx:
+; V9:       ! %bb.0: ! %entry
+; V9-NEXT:    mov %g0, %g2
+; V9-NEXT:    mov %g0, %g3
+; V9-NEXT:    addcc %o1, %o3, %o1
+; V9-NEXT:    addxcc %o0, %o2, %o0
+; V9-NEXT:    cmp %o0, %o4
+; V9-NEXT:    movgu %icc, 1, %g2
+; V9-NEXT:    cmp %o1, %o5
+; V9-NEXT:    movgu %icc, 1, %g3
+; V9-NEXT:    cmp %o0, %o4
+; V9-NEXT:    move %icc, %g3, %g2
+; V9-NEXT:    retl
+; V9-NEXT:    mov %g2, %o0
+;
+; SPARC64-LABEL: test_addx:
+; SPARC64:       ! %bb.0: ! %entry
+; SPARC64-NEXT:    mov %g0, %o3
+; SPARC64-NEXT:    add %o0, %o1, %o0
+; SPARC64-NEXT:    cmp %o0, %o2
+; SPARC64-NEXT:    movgu %xcc, 1, %o3
+; SPARC64-NEXT:    retl
+; SPARC64-NEXT:    srl %o3, 0, %o0
 entry:
-; V8: addcc
-; V8-NOT: subcc
-; V8: addx
-; V9: addcc
-; V9-NOT: subcc
-; V9: addx
-; V9: mov{{e|ne}} %icc
   %0 = add i64 %a, %b
   %1 = icmp ugt i64 %0, %c
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
-
-define i32 @test_select_int_icc(i32 %a, i32 %b, i32 %c) nounwind readnone noinline {
+define i32 @test_select_int_icc(i32 %a, i32 %b, i32 %c) nounwind {
+; V8-LABEL: test_select_int_icc:
+; V8:       ! %bb.0: ! %entry
+; V8-NEXT:    cmp %o0, 0
+; V8-NEXT:    be .LBB1_2
+; V8-NEXT:    mov %o1, %o0
+; V8-NEXT:  ! %bb.1: ! %entry
+; V8-NEXT:    mov %o2, %o0
+; V8-NEXT:  .LBB1_2: ! %entry
+; V8-NEXT:    retl
+; V8-NEXT:    nop
+;
+; V9-LABEL: test_select_int_icc:
+; V9:       ! %bb.0: ! %entry
+; V9-NEXT:    cmp %o0, 0
+; V9-NEXT:    move %icc, %o1, %o2
+; V9-NEXT:    retl
+; V9-NEXT:    mov %o2, %o0
+;
+; SPARC64-LABEL: test_select_int_icc:
+; SPARC64:       ! %bb.0: ! %entry
+; SPARC64-NEXT:    cmp %o0, 0
+; SPARC64-NEXT:    move %icc, %o1, %o2
+; SPARC64-NEXT:    retl
+; SPARC64-NEXT:    mov %o2, %o0
 entry:
-; V8: test_select_int_icc
-; V8: cmp
-; V8: {{be|bne}}
-; V9: test_select_int_icc
-; V9: cmp
-; V9-NOT: {{be|bne}}
-; V9: mov{{e|ne}} %icc
   %0 = icmp eq i32 %a, 0
   %1 = select i1 %0, i32 %b, i32 %c
   ret i32 %1
 }
 
-
-define float @test_select_fp_icc(i32 %a, float %f1, float %f2) nounwind readnone noinline {
+define float @test_select_fp_icc(i32 %a, float %f1, float %f2) nounwind {
+; V8-LABEL: test_select_fp_icc:
+; V8:       ! %bb.0: ! %entry
+; V8-NEXT:    add %sp, -104, %sp
+; V8-NEXT:    st %o2, [%sp+100]
+; V8-NEXT:    cmp %o0, 0
+; V8-NEXT:    be .LBB2_2
+; V8-NEXT:    st %o1, [%sp+96]
+; V8-NEXT:  ! %bb.1: ! %entry
+; V8-NEXT:    ld [%sp+100], %f0
+; V8-NEXT:    retl
+; V8-NEXT:    add %sp, 104, %sp
+; V8-NEXT:  .LBB2_2:
+; V8-NEXT:    ld [%sp+96], %f0
+; V8-NEXT:    retl
+; V8-NEXT:    add %sp, 104, %sp
+;
+; V9-LABEL: test_select_fp_icc:
+; V9:       ! %bb.0: ! %entry
+; V9-NEXT:    add %sp, -104, %sp
+; V9-NEXT:    st %o2, [%sp+100]
+; V9-NEXT:    st %o1, [%sp+96]
+; V9-NEXT:    ld [%sp+100], %f0
+; V9-NEXT:    ld [%sp+96], %f1
+; V9-NEXT:    cmp %o0, 0
+; V9-NEXT:    fmovse %icc, %f1, %f0
+; V9-NEXT:    retl
+; V9-NEXT:    add %sp, 104, %sp
+;
+; SPARC64-LABEL: test_select_fp_icc:
+; SPARC64:       ! %bb.0: ! %entry
+; SPARC64-NEXT:    fmovs %f5, %f0
+; SPARC64-NEXT:    cmp %o0, 0
+; SPARC64-NEXT:    retl
+; SPARC64-NEXT:    fmovse %icc, %f3, %f0
 entry:
-; V8: test_select_fp_icc
-; V8: cmp
-; V8: {{be|bne}}
-; V9: test_select_fp_icc
-; V9: cmp
-; V9-NOT: {{be|bne}}
-; V9: fmovs{{e|ne}} %icc
   %0 = icmp eq i32 %a, 0
   %1 = select i1 %0, float %f1, float %f2
   ret float %1
 }
 
-define double @test_select_dfp_icc(i32 %a, double %f1, double %f2) nounwind readnone noinline {
+define double @test_select_dfp_icc(i32 %a, double %f1, double %f2) nounwind {
+; V8-LABEL: test_select_dfp_icc:
+; V8:       ! %bb.0: ! %entry
+; V8-NEXT:    add %sp, -112, %sp
+; V8-NEXT:    mov %o4, %o5
+; V8-NEXT:    mov %o2, %g3
+; V8-NEXT:    mov %o3, %o4
+; V8-NEXT:    std %o4, [%sp+96]
+; V8-NEXT:    cmp %o0, 0
+; V8-NEXT:    mov %o1, %g2
+; V8-NEXT:    be .LBB3_2
+; V8-NEXT:    std %g2, [%sp+104]
+; V8-NEXT:  ! %bb.1: ! %entry
+; V8-NEXT:    ldd [%sp+96], %f0
+; V8-NEXT:    retl
+; V8-NEXT:    add %sp, 112, %sp
+; V8-NEXT:  .LBB3_2:
+; V8-NEXT:    ldd [%sp+104], %f0
+; V8-NEXT:    retl
+; V8-NEXT:    add %sp, 112, %sp
+;
+; V9-LABEL: test_select_dfp_icc:
+; V9:       ! %bb.0: ! %entry
+; V9-NEXT:    add %sp, -112, %sp
+; V9-NEXT:    mov %o4, %o5
+; V9-NEXT:    mov %o2, %g3
+; V9-NEXT:    mov %o3, %o4
+; V9-NEXT:    std %o4, [%sp+96]
+; V9-NEXT:    mov %o1, %g2
+; V9-NEXT:    std %g2, [%sp+104]
+; V9-NEXT:    ldd [%sp+96], %f0
+; V9-NEXT:    ldd [%sp+104], %f2
+; V9-NEXT:    cmp %o0, 0
+; V9-NEXT:    fmovde %icc, %f2, %f0
+; V9-NEXT:    retl
+; V9-NEXT:    add %sp, 112, %sp
+;
+; SPARC64-LABEL: test_select_dfp_icc:
+; SPARC64:       ! %bb.0: ! %entry
+; SPARC64-NEXT:    fmovd %f4, %f0
+; SPARC64-NEXT:    cmp %o0, 0
+; SPARC64-NEXT:    retl
+; SPARC64-NEXT:    fmovde %icc, %f2, %f0
 entry:
-; V8: test_select_dfp_icc
-; V8: cmp
-; V8: {{be|bne}}
-; V9: test_select_dfp_icc
-; V9: cmp
-; V9-NOT: {{be|bne}}
-; V9: fmovd{{e|ne}} %icc
   %0 = icmp eq i32 %a, 0
   %1 = select i1 %0, double %f1, double %f2
   ret double %1
 }
 
-define i32 @test_select_int_fcc(float %f, i32 %a, i32 %b) nounwind readnone noinline {
+define i32 @test_select_int_fcc(float %f, i32 %a, i32 %b) nounwind {
+; V8-LABEL: test_select_int_fcc:
+; V8:       ! %bb.0: ! %entry
+; V8-NEXT:    add %sp, -96, %sp
+; V8-NEXT:    st %o0, [%sp+92]
+; V8-NEXT:    ld [%sp+92], %f0
+; V8-NEXT:    sethi %hi(.LCPI4_0), %o0
+; V8-NEXT:    ld [%o0+%lo(.LCPI4_0)], %f1
+; V8-NEXT:    fcmps %f0, %f1
+; V8-NEXT:    nop
+; V8-NEXT:    fbne .LBB4_2
+; V8-NEXT:    mov %o1, %o0
+; V8-NEXT:  ! %bb.1: ! %entry
+; V8-NEXT:    mov %o2, %o0
+; V8-NEXT:  .LBB4_2: ! %entry
+; V8-NEXT:    retl
+; V8-NEXT:    add %sp, 96, %sp
+;
+; V9-LABEL: test_select_int_fcc:
+; V9:       ! %bb.0: ! %entry
+; V9-NEXT:    add %sp, -96, %sp
+; V9-NEXT:    st %o0, [%sp+92]
+; V9-NEXT:    ld [%sp+92], %f0
+; V9-NEXT:    sethi %hi(.LCPI4_0), %o0
+; V9-NEXT:    ld [%o0+%lo(.LCPI4_0)], %f1
+; V9-NEXT:    mov %o2, %o0
+; V9-NEXT:    fcmps %fcc0, %f0, %f1
+; V9-NEXT:    movne %fcc0, %o1, %o0
+; V9-NEXT:    retl
+; V9-NEXT:    add %sp, 96, %sp
+;
+; SPARC64-LABEL: test_select_int_fcc:
+; SPARC64:       ! %bb.0: ! %entry
+; SPARC64-NEXT:    sethi %h44(.LCPI4_0), %o0
+; SPARC64-NEXT:    add %o0, %m44(.LCPI4_0), %o0
+; SPARC64-NEXT:    sllx %o0, 12, %o0
+; SPARC64-NEXT:    ld [%o0+%l44(.LCPI4_0)], %f0
+; SPARC64-NEXT:    mov %o2, %o0
+; SPARC64-NEXT:    fcmps %fcc0, %f1, %f0
+; SPARC64-NEXT:    retl
+; SPARC64-NEXT:    movne %fcc0, %o1, %o0
 entry:
-;V8-LABEL: test_select_int_fcc:
-;V8: fcmps
-;V8-NEXT: nop
-;V8: {{fbe|fbne}}
-;V9-LABEL: test_select_int_fcc:
-;V9: fcmps
-;V9-NOT: nop
-;V9-NOT: {{fbe|fbne}}
-;V9: mov{{e|ne}} %fcc0
   %0 = fcmp une float %f, 0.000000e+00
   %a.b = select i1 %0, i32 %a, i32 %b
   ret i32 %a.b
 }
 
-
-define float @test_select_fp_fcc(float %f, float %f1, float %f2) nounwind readnone noinline {
+define float @test_select_fp_fcc(float %f, float %f1, float %f2) nounwind {
+; V8-LABEL: test_select_fp_fcc:
+; V8:       ! %bb.0: ! %entry
+; V8-NEXT:    add %sp, -104, %sp
+; V8-NEXT:    st %o0, [%sp+92]
+; V8-NEXT:    st %o2, [%sp+100]
+; V8-NEXT:    st %o1, [%sp+96]
+; V8-NEXT:    ld [%sp+92], %f0
+; V8-NEXT:    sethi %hi(.LCPI5_0), %o0
+; V8-NEXT:    ld [%o0+%lo(.LCPI5_0)], %f1
+; V8-NEXT:    fcmps %f0, %f1
+; V8-NEXT:    nop
+; V8-NEXT:    fbne .LBB5_2
+; V8-NEXT:    nop
+; V8-NEXT:  ! %bb.1: ! %entry
+; V8-NEXT:    ld [%sp+100], %f0
+; V8-NEXT:    retl
+; V8-NEXT:    add %sp, 104, %sp
+; V8-NEXT:  .LBB5_2:
+; V8-NEXT:    ld [%sp+96], %f0
+; V8-NEXT:    retl
+; V8-NEXT:    add %sp, 104, %sp
+;
+; V9-LABEL: test_select_fp_fcc:
+; V9:       ! %bb.0: ! %entry
+; V9-NEXT:    add %sp, -104, %sp
+; V9-NEXT:    st %o0, [%sp+92]
+; V9-NEXT:    st %o2, [%sp+100]
+; V9-NEXT:    st %o1, [%sp+96]
+; V9-NEXT:    ld [%sp+92], %f1
+; V9-NEXT:    ld [%sp+100], %f0
+; V9-NEXT:    sethi %hi(.LCPI5_0), %o0
+; V9-NEXT:    ld [%o0+%lo(.LCPI5_0)], %f2
+; V9-NEXT:    ld [%sp+96], %f3
+; V9-NEXT:    fcmps %fcc0, %f1, %f2
+; V9-NEXT:    fmovsne %fcc0, %f3, %f0
+; V9-NEXT:    retl
+; V9-NEXT:    add %sp, 104, %sp
+;
+; SPARC64-LABEL: test_select_fp_fcc:
+; SPARC64:       ! %bb.0: ! %entry
+; SPARC64-NEXT:    sethi %h44(.LCPI5_0), %o0
+; SPARC64-NEXT:    add %o0, %m44(.LCPI5_0), %o0
+; SPARC64-NEXT:    sllx %o0, 12, %o0
+; SPARC64-NEXT:    ld [%o0+%l44(.LCPI5_0)], %f2
+; SPARC64-NEXT:    fmovs %f5, %f0
+; SPARC64-NEXT:    fcmps %fcc0, %f1, %f2
+; SPARC64-NEXT:    retl
+; SPARC64-NEXT:    fmovsne %fcc0, %f3, %f0
 entry:
-;V8-LABEL: test_select_fp_fcc:
-;V8: fcmps
-;V8: {{fbe|fbne}}
-;V9-LABEL: test_select_fp_fcc:
-;V9: fcmps
-;V9-NOT: {{fbe|fbne}}
-;V9: fmovs{{e|ne}} %fcc0
   %0 = fcmp une float %f, 0.000000e+00
   %1 = select i1 %0, float %f1, float %f2
   ret float %1
 }
 
-define double @test_select_dfp_fcc(double %f, double %f1, double %f2) nounwind readnone noinline {
+define double @test_select_dfp_fcc(double %f, double %f1, double %f2) nounwind {
+; V8-LABEL: test_select_dfp_fcc:
+; V8:       ! %bb.0: ! %entry
+; V8-NEXT:    add %sp, -120, %sp
+; V8-NEXT:    ! kill: def $o1 killed $o1 killed $o0_o1 def $o0_o1
+; V8-NEXT:    ! kill: def $o5 killed $o5 killed $o4_o5 def $o4_o5
+; V8-NEXT:    ! kill: def $o3 killed $o3 killed $o2_o3 def $o2_o3
+; V8-NEXT:    ! kill: def $o0 killed $o0 killed $o0_o1 def $o0_o1
+; V8-NEXT:    std %o0, [%sp+112]
+; V8-NEXT:    ! kill: def $o4 killed $o4 killed $o4_o5 def $o4_o5
+; V8-NEXT:    std %o4, [%sp+96]
+; V8-NEXT:    ! kill: def $o2 killed $o2 killed $o2_o3 def $o2_o3
+; V8-NEXT:    std %o2, [%sp+104]
+; V8-NEXT:    ldd [%sp+112], %f0
+; V8-NEXT:    sethi %hi(.LCPI6_0), %o0
+; V8-NEXT:    ldd [%o0+%lo(.LCPI6_0)], %f2
+; V8-NEXT:    fcmpd %f0, %f2
+; V8-NEXT:    nop
+; V8-NEXT:    fbne .LBB6_2
+; V8-NEXT:    nop
+; V8-NEXT:  ! %bb.1: ! %entry
+; V8-NEXT:    ldd [%sp+96], %f0
+; V8-NEXT:    retl
+; V8-NEXT:    add %sp, 120, %sp
+; V8-NEXT:  .LBB6_2:
+; V8-NEXT:    ldd [%sp+104], %f0
+; V8-NEXT:    retl
+; V8-NEXT:    add %sp, 120, %sp
+;
+; V9-LABEL: test_select_dfp_fcc:
+; V9:       ! %bb.0: ! %entry
+; V9-NEXT:    add %sp, -120, %sp
+; V9-NEXT:    ! kill: def $o1 killed $o1 killed $o0_o1 def $o0_o1
+; V9-NEXT:    ! kill: def $o5 killed $o5 killed $o4_o5 def $o4_o5
+; V9-NEXT:    ! kill: def $o3 killed $o3 killed $o2_o3 def $o2_o3
+; V9-NEXT:    ! kill: def $o0 killed $o0 killed $o0_o1 def $o0_o1
+; V9-NEXT:    std %o0, [%sp+112]
+; V9-NEXT:    ! kill: def $o4 killed $o4 killed $o4_o5 def $o4_o5
+; V9-NEXT:    std %o4, [%sp+96]
+; V9-NEXT:    ! kill: def $o2 killed $o2 killed $o2_o3 def $o2_o3
+; V9-NEXT:    std %o2, [%sp+104]
+; V9-NEXT:    ldd [%sp+112], %f2
+; V9-NEXT:    ldd [%sp+96], %f0
+; V9-NEXT:    sethi %hi(.LCPI6_0), %o0
+; V9-NEXT:    ldd [%o0+%lo(.LCPI6_0)], %f4
+; V9-NEXT:    ldd [%sp+104], %f6
+; V9-NEXT:    fcmpd %fcc0, %f2, %f4
+; V9-NEXT:    fmovdne %fcc0, %f6, %f0
+; V9-NEXT:    retl
+; V9-NEXT:    add %sp, 120, %sp
+;
+; SPARC64-LABEL: test_select_dfp_fcc:
+; SPARC64:       ! %bb.0: ! %entry
+; SPARC64-NEXT:    sethi %h44(.LCPI6_0), %o0
+; SPARC64-NEXT:    add %o0, %m44(.LCPI6_0), %o0
+; SPARC64-NEXT:    sllx %o0, 12, %o0
+; SPARC64-NEXT:    ldd [%o0+%l44(.LCPI6_0)], %f6
+; SPARC64-NEXT:    fcmpd %fcc0, %f0, %f6
+; SPARC64-NEXT:    fmovdne %fcc0, %f2, %f4
+; SPARC64-NEXT:    fmovd %f4, %f0
+; SPARC64-NEXT:    retl
+; SPARC64-NEXT:    nop
 entry:
-;V8-LABEL: test_select_dfp_fcc:
-;V8: fcmpd
-;V8-NEXT: nop
-;V8: {{fbne|fbe}}
-;V9-LABEL: test_select_dfp_fcc:
-;V9: fcmpd
-;V9-NOT: nop
-;V9-NOT: {{fbne|fbe}}
-;V9: fmovd{{e|ne}} %fcc0
   %0 = fcmp une double %f, 0.000000e+00
   %1 = select i1 %0, double %f1, double %f2
   ret double %1
 }
 
-define i32 @test_float_cc(double %a, double %b, i32 %c, i32 %d) {
+define i32 @test_float_cc(double %a, double %b, i32 %c, i32 %d) nounwind {
+; V8-LABEL: test_float_cc:
+; V8:       ! %bb.0: ! %entry
+; V8-NEXT:    add %sp, -112, %sp
+; V8-NEXT:    ! kill: def $o3 killed $o3 killed $o2_o3 def $o2_o3
+; V8-NEXT:    ! kill: def $o1 killed $o1 killed $o0_o1 def $o0_o1
+; V8-NEXT:    ! kill: def $o2 killed $o2 killed $o2_o3 def $o2_o3
+; V8-NEXT:    std %o2, [%sp+96]
+; V8-NEXT:    ! kill: def $o0 killed $o0 killed $o0_o1 def $o0_o1
+; V8-NEXT:    std %o0, [%sp+104]
+; V8-NEXT:    ldd [%sp+104], %f2
+; V8-NEXT:    sethi %hi(.LCPI7_0), %o0
+; V8-NEXT:    ldd [%o0+%lo(.LCPI7_0)], %f0
+; V8-NEXT:    fcmpd %f2, %f0
+; V8-NEXT:    nop
+; V8-NEXT:    fbuge .LBB7_3
+; V8-NEXT:    nop
+; V8-NEXT:  ! %bb.1: ! %loop.2
+; V8-NEXT:    ldd [%sp+96], %f2
+; V8-NEXT:    fcmpd %f2, %f0
+; V8-NEXT:    nop
+; V8-NEXT:    fbule .LBB7_3
+; V8-NEXT:    nop
+; V8-NEXT:  ! %bb.2: ! %exit.1
+; V8-NEXT:    mov 1, %o0
+; V8-NEXT:    retl
+; V8-NEXT:    add %sp, 112, %sp
+; V8-NEXT:  .LBB7_3: ! %loop
+; V8-NEXT:    ! =>This Inner Loop Header: Depth=1
+; V8-NEXT:    cmp %o4, 10
+; V8-NEXT:    be .LBB7_3
+; V8-NEXT:    nop
+; V8-NEXT:  ! %bb.4: ! %exit.0
+; V8-NEXT:    mov %g0, %o0
+; V8-NEXT:    retl
+; V8-NEXT:    add %sp, 112, %sp
+;
+; V9-LABEL: test_float_cc:
+; V9:       ! %bb.0: ! %entry
+; V9-NEXT:    add %sp, -112, %sp
+; V9-NEXT:    ! kill: def $o3 killed $o3 killed $o2_o3 def $o2_o3
+; V9-NEXT:    ! kill: def $o1 killed $o1 killed $o0_o1 def $o0_o1
+; V9-NEXT:    ! kill: def $o2 killed $o2 killed $o2_o3 def $o2_o3
+; V9-NEXT:    std %o2, [%sp+96]
+; V9-NEXT:    ! kill: def $o0 killed $o0 killed $o0_o1 def $o0_o1
+; V9-NEXT:    std %o0, [%sp+104]
+; V9-NEXT:    ldd [%sp+104], %f2
+; V9-NEXT:    sethi %hi(.LCPI7_0), %o0
+; V9-NEXT:    ldd [%o0+%lo(.LCPI7_0)], %f0
+; V9-NEXT:    fcmpd %fcc0, %f2, %f0
+; V9-NEXT:    fbuge %fcc0, .LBB7_3
+; V9-NEXT:    nop
+; V9-NEXT:  ! %bb.1: ! %loop.2
+; V9-NEXT:    ldd [%sp+96], %f2
+; V9-NEXT:    fcmpd %fcc0, %f2, %f0
+; V9-NEXT:    fbule %fcc0, .LBB7_3
+; V9-NEXT:    nop
+; V9-NEXT:  ! %bb.2: ! %exit.1
+; V9-NEXT:    mov 1, %o0
+; V9-NEXT:    retl
+; V9-NEXT:    add %sp, 112, %sp
+; V9-NEXT:  .LBB7_3: ! %loop
+; V9-NEXT:    ! =>This Inner Loop Header: Depth=1
+; V9-NEXT:    cmp %o4, 10
+; V9-NEXT:    be %icc, .LBB7_3
+; V9-NEXT:    nop
+; V9-NEXT:  ! %bb.4: ! %exit.0
+; V9-NEXT:    mov %g0, %o0
+; V9-NEXT:    retl
+; V9-NEXT:    add %sp, 112, %sp
+;
+; SPARC64-LABEL: test_float_cc:
+; SPARC64:       ! %bb.0: ! %entry
+; SPARC64-NEXT:    sethi %h44(.LCPI7_0), %o0
+; SPARC64-NEXT:    add %o0, %m44(.LCPI7_0), %o0
+; SPARC64-NEXT:    sllx %o0, 12, %o0
+; SPARC64-NEXT:    ldd [%o0+%l44(.LCPI7_0)], %f4
+; SPARC64-NEXT:    fcmpd %fcc0, %f0, %f4
+; SPARC64-NEXT:    fbuge %fcc0, .LBB7_3
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:  ! %bb.1: ! %loop.2
+; SPARC64-NEXT:    fcmpd %fcc0, %f2, %f4
+; SPARC64-NEXT:    fbule %fcc0, .LBB7_3
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:  ! %bb.2: ! %exit.1
+; SPARC64-NEXT:    retl
+; SPARC64-NEXT:    mov 1, %o0
+; SPARC64-NEXT:  .LBB7_3: ! %loop
+; SPARC64-NEXT:    ! =>This Inner Loop Header: Depth=1
+; SPARC64-NEXT:    cmp %o2, 10
+; SPARC64-NEXT:    be %icc, .LBB7_3
+; SPARC64-NEXT:    nop
+; SPARC64-NEXT:  ! %bb.4: ! %exit.0
+; SPARC64-NEXT:    retl
+; SPARC64-NEXT:    mov %g0, %o0
 entry:
-; V8-LABEL: test_float_cc
-; V8:       fcmpd
-; V8:       {{fbl|fbuge}} .LBB
-; V8:       fcmpd
-; V8:       {{fbule|fbg}} .LBB
-
-; V9-LABEL: test_float_cc
-; V9:       fcmpd %fcc0
-; V9:       {{fbl|fbuge}} %fcc0, .LBB
-; V9:       fcmpd %fcc0
-; V9:       {{fbule|fbg}} %fcc0, .LBB
-
    %0 = fcmp uge double %a, 0.000000e+00
    br i1 %0, label %loop, label %loop.2
 
@@ -141,39 +472,92 @@ exit.1:
    ret i32 1
 }
 
-; V8-LABEL: test_adde_sube
-; V8:       addcc
-; V8:       addxcc
-; V8:       addxcc
-; V8:       addxcc
-; V8:       subcc
-; V8:       subxcc
-; V8:       subxcc
-; V8:       subxcc
-
-
-; V9-LABEL: test_adde_sube
-; V9:       addcc
-; V9:       addxcc
-; V9:       addxcc
-; V9:       addxcc
-; V9:       subcc
-; V9:       subxcc
-; V9:       subxcc
-; V9:       subxcc
-
-; SPARC64-LABEL: test_adde_sube
-; SPARC64:       addcc
-; SPARC64:       addxcc
-; SPARC64:       addxcc
-; SPARC64:       addxcc
-; SPARC64:       subcc
-; SPARC64:       subxcc
-; SPARC64:       subxcc
-; SPARC64:       subxcc
-
-
-define void @test_adde_sube(ptr %a, ptr %b, ptr %sum, ptr %diff) {
+define void @test_adde_sube(ptr %a, ptr %b, ptr %sum, ptr %diff) nounwind {
+; V8-LABEL: test_adde_sube:
+; V8:       ! %bb.0: ! %entry
+; V8-NEXT:    save %sp, -96, %sp
+; V8-NEXT:    ldd [%i0+8], %i4
+; V8-NEXT:    ldd [%i1+8], %l0
+; V8-NEXT:    ldd [%i0], %g2
+; V8-NEXT:    ldd [%i1], %l2
+; V8-NEXT:    addcc %i5, %l1, %l5
+; V8-NEXT:    addxcc %i4, %l0, %l4
+; V8-NEXT:    addxcc %g3, %l3, %l1
+; V8-NEXT:    addxcc %g2, %l2, %l0
+; V8-NEXT:    std %l4, [%i2+8]
+; V8-NEXT:    std %l0, [%i2]
+; V8-NEXT:    !APP
+; V8-NEXT:    !NO_APP
+; V8-NEXT:    ldd [%i0+8], %l0
+; V8-NEXT:    ldd [%i0], %i0
+; V8-NEXT:    subcc %i5, %l1, %l3
+; V8-NEXT:    subxcc %i4, %l0, %l2
+; V8-NEXT:    subxcc %g3, %i1, %i5
+; V8-NEXT:    subxcc %g2, %i0, %i4
+; V8-NEXT:    std %l2, [%i3+8]
+; V8-NEXT:    std %i4, [%i3]
+; V8-NEXT:    ret
+; V8-NEXT:    restore
+;
+; V9-LABEL: test_adde_sube:
+; V9:       ! %bb.0: ! %entry
+; V9-NEXT:    save %sp, -96, %sp
+; V9-NEXT:    ldd [%i0+8], %i4
+; V9-NEXT:    ldd [%i1+8], %l0
+; V9-NEXT:    ldd [%i0], %g2
+; V9-NEXT:    ldd [%i1], %l2
+; V9-NEXT:    addcc %i5, %l1, %l5
+; V9-NEXT:    addxcc %i4, %l0, %l4
+; V9-NEXT:    addxcc %g3, %l3, %l1
+; V9-NEXT:    addxcc %g2, %l2, %l0
+; V9-NEXT:    std %l4, [%i2+8]
+; V9-NEXT:    std %l0, [%i2]
+; V9-NEXT:    !APP
+; V9-NEXT:    !NO_APP
+; V9-NEXT:    ldd [%i0+8], %l0
+; V9-NEXT:    ldd [%i0], %i0
+; V9-NEXT:    subcc %i5, %l1, %l3
+; V9-NEXT:    subxcc %i4, %l0, %l2
+; V9-NEXT:    subxcc %g3, %i1, %i5
+; V9-NEXT:    subxcc %g2, %i0, %i4
+; V9-NEXT:    std %l2, [%i3+8]
+; V9-NEXT:    std %i4, [%i3]
+; V9-NEXT:    ret
+; V9-NEXT:    restore
+;
+; SPARC64-LABEL: test_adde_sube:
+; SPARC64:         .register %g2, #scratch
+; SPARC64-NEXT:    .register %g3, #scratch
+; SPARC64-NEXT:  ! %bb.0: ! %entry
+; SPARC64-NEXT:    save %sp, -128, %sp
+; SPARC64-NEXT:    ldx [%i0+8], %i4
+; SPARC64-NEXT:    ldx [%i0], %i5
+; SPARC64-NEXT:    ldx [%i1], %g2
+; SPARC64-NEXT:    ldx [%i1+8], %i1
+; SPARC64-NEXT:    mov %g0, %g3
+; SPARC64-NEXT:    add %i5, %g2, %g2
+; SPARC64-NEXT:    add %i4, %i1, %i1
+; SPARC64-NEXT:    cmp %i1, %i4
+; SPARC64-NEXT:    movcs %xcc, 1, %g3
+; SPARC64-NEXT:    srl %g3, 0, %g3
+; SPARC64-NEXT:    add %g2, %g3, %g2
+; SPARC64-NEXT:    stx %i1, [%i2+8]
+; SPARC64-NEXT:    stx %g2, [%i2]
+; SPARC64-NEXT:    !APP
+; SPARC64-NEXT:    !NO_APP
+; SPARC64-NEXT:    ldx [%i0+8], %i1
+; SPARC64-NEXT:    mov %g0, %i2
+; SPARC64-NEXT:    ldx [%i0], %i0
+; SPARC64-NEXT:    cmp %i4, %i1
+; SPARC64-NEXT:    movcs %xcc, 1, %i2
+; SPARC64-NEXT:    srl %i2, 0, %i2
+; SPARC64-NEXT:    sub %i5, %i0, %i0
+; SPARC64-NEXT:    sub %i0, %i2, %i0
+; SPARC64-NEXT:    sub %i4, %i1, %i1
+; SPARC64-NEXT:    stx %i1, [%i3+8]
+; SPARC64-NEXT:    stx %i0, [%i3]
+; SPARC64-NEXT:    ret
+; SPARC64-NEXT:    restore
 entry:
    %0 = bitcast ptr %a to ptr
    %1 = bitcast ptr %b to ptr
diff --git a/llvm/test/CodeGen/SPARC/fp128-split.ll b/llvm/test/CodeGen/SPARC/fp128-split.ll
index c87cfb932b7819..8a127c9c28cc71 100644
--- a/llvm/test/CodeGen/SPARC/fp128-split.ll
+++ b/llvm/test/CodeGen/SPARC/fp128-split.ll
@@ -8,45 +8,33 @@
 define fp128 @testcase(fp128 %0) {
   ; CHECK-LABEL: name: testcase
   ; CHECK: bb.0.Entry:
-  ; CHECK:   liveins: $q0
-  ; CHECK:   [[COPY:%[0-9]+]]:qfpregs = COPY $q0
-  ; CHECK:   [[COPY1:%[0-9]+]]:dfpregs = COPY [[COPY]].sub_odd64
-  ; CHECK:   [[ADDri:%[0-9]+]]:i64regs = ADDri %stack.0, 0
-  ; CHECK:   [[ORri:%[0-9]+]]:i64regs = ORri killed [[ADDri]], 8
-  ; CHECK:   STDFrr [[ORri]], $g0, killed [[COPY1]] :: (store (s64) into %stack.0 + 8)
-  ; CHECK:   [[COPY2:%[0-9]+]]:dfpregs = COPY [[COPY]].sub_even64
-  ; CHECK:   STDFri %stack.0, 0, killed [[COPY2]] :: (store (s64) into %stack.0, align 16)
-  ; CHECK:   [[LDXrr:%[0-9]+]]:i64regs = LDXrr [[ORri]], $g0 :: (load (s64) from %stack.0 + 8)
-  ; CHECK:   [[LDXri:%[0-9]+]]:i64regs = LDXri %stack.0, 0 :: (load (s64) from %stack.0, align 16)
-  ; CHECK:   [[COPY3:%[0-9]+]]:intregs = COPY [[LDXrr]]
-  ; CHECK:   [[COPY4:%[0-9]+]]:intregs = COPY [[LDXri]]
-  ; CHECK:   [[SRLXri:%[0-9]+]]:i64regs = SRLXri [[LDXrr]], 32
-  ; CHECK:   [[COPY5:%[0-9]+]]:intregs = COPY [[SRLXri]]
-  ; CHECK:   [[SRLXri1:%[0-9]+]]:i64regs = SRLXri [[LDXri]], 32
-  ; CHECK:   [[COPY6:%[0-9]+]]:intregs = COPY [[SRLXri1]]
-  ; CHECK:   [[ADDCCri:%[0-9]+]]:intregs = ADDCCri killed [[COPY3]], -1, implicit-def $icc
-  ; CHECK:   [[ADDEri:%[0-9]+]]:intregs = ADDEri killed [[COPY5]], -1, implicit-def $icc, implicit $icc
-  ; CHECK:   [[ADDEri1:%[0-9]+]]:intregs = ADDEri killed [[COPY4]], -1, implicit-def $icc, implicit $icc
-  ; CHECK:   [[ADDEri2:%[0-9]+]]:intregs = ADDEri killed [[COPY6]], -1, implicit-def dead $icc, implicit $icc
-  ; CHECK:   [[SRLri:%[0-9]+]]:i64regs = SRLri killed [[ADDCCri]], 0
-  ; CHECK:   [[COPY7:%[0-9]+]]:i64regs = COPY [[ADDEri]]
-  ; CHECK:   [[SLLXri:%[0-9]+]]:i64regs = SLLXri killed [[COPY7]], 32
-  ; CHECK:   [[ORrr:%[0-9]+]]:i64regs = ORrr killed [[SLLXri]], killed [[SRLri]]
-  ; CHECK:   [[ADDri1:%[0-9]+]]:i64regs = ADDri %stack.1, 0
-  ; CHECK:   [[ORri1:%[0-9]+]]:i64regs = ORri killed [[ADDri1]], 8
-  ; CHECK:   STXrr [[ORri1]], $g0, killed [[ORrr]] :: (store (s64) into %stack.1 + 8, basealign 16)
-  ; CHECK:   [[SRLri1:%[0-9]+]]:i64regs = SRLri killed [[ADDEri1]], 0
-  ; CHECK:   [[COPY8:%[0-9]+]]:i64regs = COPY [[ADDEri2]]
-  ; CHECK:   [[SLLXri1:%[0-9]+]]:i64regs = SLLXri killed [[COPY8]], 32
-  ; CHECK:   [[ORrr1:%[0-9]+]]:i64regs = ORrr killed [[SLLXri1]], killed [[SRLri1]]
-  ; CHECK:   STXri %stack.1, 0, killed [[ORrr1]] :: (store (s64) into %stack.1, align 16)
-  ; CHECK:   [[LDDFri:%[0-9]+]]:dfpregs = LDDFri %stack.1, 0 :: (load (s64) from %stack.1, align 16)
-  ; CHECK:   [[DEF:%[0-9]+]]:qfpregs = IMPLICIT_DEF
-  ; CHECK:   [[INSERT_SUBREG:%[0-9]+]]:qfpregs = INSERT_SUBREG [[DEF]], killed [[LDDFri]], %subreg.sub_even64
-  ; CHECK:   [[LDDFrr:%[0-9]+]]:dfpregs = LDDFrr [[ORri1]], $g0 :: (load (s64) from %stack.1 + 8)
-  ; CHECK:   [[INSERT_SUBREG1:%[0-9]+]]:qfpregs = INSERT_SUBREG [[INSERT_SUBREG]], killed [[LDDFrr]], %subreg.sub_odd64
-  ; CHECK:   $q0 = COPY [[INSERT_SUBREG1]]
-  ; CHECK:   RETL 8, implicit $q0
+  ; CHECK-NEXT:   liveins: $q0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:qfpregs = COPY $q0
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:dfpregs = COPY [[COPY]].sub_odd64
+  ; CHECK-NEXT:   [[ADDri:%[0-9]+]]:i64regs = ADDri %stack.0, 0
+  ; CHECK-NEXT:   [[ORri:%[0-9]+]]:i64regs = ORri killed [[ADDri]], 8
+  ; CHECK-NEXT:   STDFrr [[ORri]], $g0, killed [[COPY1]] :: (store (s64) into %stack.0 + 8)
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:dfpregs = COPY [[COPY]].sub_even64
+  ; CHECK-NEXT:   STDFri %stack.0, 0, killed [[COPY2]] :: (store (s64) into %stack.0, align 16)
+  ; CHECK-NEXT:   [[LDXrr:%[0-9]+]]:i64regs = LDXrr [[ORri]], $g0 :: (load (s64) from %stack.0 + 8)
+  ; CHECK-NEXT:   [[LDXri:%[0-9]+]]:i64regs = LDXri %stack.0, 0 :: (load (s64) from %stack.0, align 16)
+  ; CHECK-NEXT:   [[ADDri1:%[0-9]+]]:i64regs = ADDri %stack.1, 0
+  ; CHECK-NEXT:   [[ORri1:%[0-9]+]]:i64regs = ORri killed [[ADDri1]], 8
+  ; CHECK-NEXT:   [[ADDri2:%[0-9]+]]:i64regs = ADDri [[LDXrr]], -1
+  ; CHECK-NEXT:   STXrr [[ORri1]], $g0, killed [[ADDri2]] :: (store (s64) into %stack.1 + 8, basealign 16)
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:intregs = COPY $g0
+  ; CHECK-NEXT:   [[MOVRri:%[0-9]+]]:intregs = MOVRri [[LDXrr]], 1, [[COPY3]], 49
+  ; CHECK-NEXT:   [[SRLri:%[0-9]+]]:i64regs = SRLri killed [[MOVRri]], 0
+  ; CHECK-NEXT:   [[SUBrr:%[0-9]+]]:i64regs = SUBrr killed [[LDXri]], killed [[SRLri]]
+  ; CHECK-NEXT:   STXri %stack.1, 0, killed [[SUBrr]] :: (store (s64) into %stack.1, align 16)
+  ; CHECK-NEXT:   [[LDDFri:%[0-9]+]]:dfpregs = LDDFri %stack.1, 0 :: (load (s64) from %stack.1, align 16)
+  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:qfpregs = IMPLICIT_DEF
+  ; CHECK-NEXT:   [[INSERT_SUBREG:%[0-9]+]]:qfpregs = INSERT_SUBREG [[DEF]], killed [[LDDFri]], %subreg.sub_even64
+  ; CHECK-NEXT:   [[LDDFrr:%[0-9]+]]:dfpregs = LDDFrr [[ORri1]], $g0 :: (load (s64) from %stack.1 + 8)
+  ; CHECK-NEXT:   [[INSERT_SUBREG1:%[0-9]+]]:qfpregs = INSERT_SUBREG [[INSERT_SUBREG]], killed [[LDDFrr]], %subreg.sub_odd64
+  ; CHECK-NEXT:   $q0 = COPY [[INSERT_SUBREG1]]
+  ; CHECK-NEXT:   RETL 8, implicit $q0
 Entry:
   %1 = bitcast fp128 %0 to i128
   %2 = add i128 %1, -1
diff --git a/llvm/test/CodeGen/SPARC/smulo-128-legalisation-lowering.ll b/llvm/test/CodeGen/SPARC/smulo-128-legalisation-lowering.ll
index ae1de443bce05f..ac0b1128ca812a 100644
--- a/llvm/test/CodeGen/SPARC/smulo-128-legalisation-lowering.ll
+++ b/llvm/test/CodeGen/SPARC/smulo-128-legalisation-lowering.ll
@@ -2,14 +2,10 @@
 ; RUN: llc < %s -mtriple=sparc-unknown-linux-gnu | FileCheck %s --check-prefixes=SPARC
 ; RUN: llc < %s -mtriple=sparc64-unknown-linux-gnu | FileCheck %s --check-prefixes=SPARC64
 
-define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
+define { i128, i8 } @muloti_test(i128 %l, i128 %r) nounwind {
 ; SPARC-LABEL: muloti_test:
-; SPARC:         .cfi_startproc
-; SPARC-NEXT:  ! %bb.0: ! %start
+; SPARC:       ! %bb.0: ! %start
 ; SPARC-NEXT:    save %sp, -96, %sp
-; SPARC-NEXT:    .cfi_def_cfa_register %fp
-; SPARC-NEXT:    .cfi_window_save
-; SPARC-NEXT:    .cfi_register %o7, %i7
 ; SPARC-NEXT:    ld [%fp+96], %l1
 ; SPARC-NEXT:    mov %i3, %g4
 ; SPARC-NEXT:    mov %i2, %g2
@@ -172,105 +168,97 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
 ; SPARC-NEXT:    restore %g0, %g3, %o1
 ;
 ; SPARC64-LABEL: muloti_test:
-; SPARC64:         .cfi_startproc
-; SPARC64-NEXT:    .register %g2, #scratch
+; SPARC64:         .register %g2, #scratch
 ; SPARC64-NEXT:    .register %g3, #scratch
 ; SPARC64-NEXT:  ! %bb.0: ! %start
 ; SPARC64-NEXT:    save %sp, -176, %sp
-; SPARC64-NEXT:    .cfi_def_cfa_register %fp
-; SPARC64-NEXT:    .cfi_window_save
-; SPARC64-NEXT:    .cfi_register %o7, %i7
-; SPARC64-NEXT:    mov %i3, %i4
-; SPARC64-NEXT:    mov %i1, %i3
-; SPARC64-NEXT:    srax %i0, 63, %o2
-; SPARC64-NEXT:    mov %i2, %o0
-; SPARC64-NEXT:    mov %i4, %o1
-; SPARC64-NEXT:    call __multi3
-; SPARC64-NEXT:    mov %o2, %o3
-; SPARC64-NEXT:    mov %o0, %i1
-; SPARC64-NEXT:    mov %o1, %i5
-; SPARC64-NEXT:    srax %i2, 63, %o0
-; SPARC64-NEXT:    mov %o0, %o1
-; SPARC64-NEXT:    mov %i0, %o2
-; SPARC64-NEXT:    call __multi3
-; SPARC64-NEXT:    mov %i3, %o3
-; SPARC64-NEXT:    srlx %i5, 32, %g2
-; SPARC64-NEXT:    srlx %o1, 32, %g3
-; SPARC64-NEXT:    srlx %i1, 32, %g4
-; SPARC64-NEXT:    srlx %o0, 32, %g5
-; SPARC64-NEXT:    addcc %o1, %i5, %l0
-; SPARC64-NEXT:    addxcc %g3, %g2, %l1
-; SPARC64-NEXT:    addxcc %o0, %i1, %l2
-; SPARC64-NEXT:    addxcc %g5, %g4, %l3
+; SPARC64-NEXT:    mov %i3, %i5
+; SPARC64-NEXT:    mov %i2, %i3
+; SPARC64-NEXT:    mov %i1, %i2
+; SPARC64-NEXT:    mov %i0, %i4
 ; SPARC64-NEXT:    mov %g0, %o0
-; SPARC64-NEXT:    mov %i3, %o1
+; SPARC64-NEXT:    mov %i1, %o1
 ; SPARC64-NEXT:    mov %g0, %o2
 ; SPARC64-NEXT:    call __multi3
-; SPARC64-NEXT:    mov %i4, %o3
-; SPARC64-NEXT:    mov %o0, %i5
+; SPARC64-NEXT:    mov %i5, %o3
+; SPARC64-NEXT:    mov %o0, %i0
 ; SPARC64-NEXT:    mov %o1, %i1
 ; SPARC64-NEXT:    mov %g0, %o0
-; SPARC64-NEXT:    mov %i0, %o1
+; SPARC64-NEXT:    mov %i4, %o1
 ; SPARC64-NEXT:    mov %g0, %o2
 ; SPARC64-NEXT:    call __multi3
-; SPARC64-NEXT:    mov %i4, %o3
-; SPARC64-NEXT:    srlx %i5, 32, %i4
-; SPARC64-NEXT:    srlx %o1, 32, %g2
-; SPARC64-NEXT:    srlx %o0, 32, %g3
-; SPARC64-NEXT:    addcc %o1, %i5, %i5
-; SPARC64-NEXT:    addxcc %g2, %i4, %i4
-; SPARC64-NEXT:    addxcc %o0, 0, %l4
-; SPARC64-NEXT:    addxcc %g3, 0, %l5
+; SPARC64-NEXT:    mov %i5, %o3
+; SPARC64-NEXT:    mov %g0, %g2
+; SPARC64-NEXT:    add %o1, %i0, %i0
+; SPARC64-NEXT:    cmp %i0, %o1
+; SPARC64-NEXT:    movcs %xcc, 1, %g2
+; SPARC64-NEXT:    srl %g2, 0, %g2
+; SPARC64-NEXT:    add %o0, %g2, %l0
 ; SPARC64-NEXT:    mov %g0, %o0
-; SPARC64-NEXT:    mov %i3, %o1
+; SPARC64-NEXT:    mov %i2, %o1
 ; SPARC64-NEXT:    mov %g0, %o2
 ; SPARC64-NEXT:    call __multi3
-; SPARC64-NEXT:    mov %i2, %o3
-; SPARC64-NEXT:    srlx %o1, 32, %g2
-; SPARC64-NEXT:    srlx %o0, 32, %g3
-; SPARC64-NEXT:    addcc %o1, %i5, %i3
-; SPARC64-NEXT:    addxcc %g2, %i4, %i4
-; SPARC64-NEXT:    addxcc %o0, 0, %i5
-; SPARC64-NEXT:    addxcc %g3, 0, %g2
-; SPARC64-NEXT:    addcc %l4, %i5, %i5
-; SPARC64-NEXT:    addxcc %l5, %g2, %l4
-; SPARC64-NEXT:    addxcc %g0, 0, %l5
-; SPARC64-NEXT:    addxcc %g0, 0, %l6
+; SPARC64-NEXT:    mov %i3, %o3
+; SPARC64-NEXT:    mov %g0, %g2
+; SPARC64-NEXT:    mov %g0, %g3
+; SPARC64-NEXT:    add %o1, %i0, %i0
+; SPARC64-NEXT:    cmp %i0, %o1
+; SPARC64-NEXT:    movcs %xcc, 1, %g2
+; SPARC64-NEXT:    srl %g2, 0, %g2
+; SPARC64-NEXT:    add %o0, %g2, %g2
+; SPARC64-NEXT:    add %l0, %g2, %l1
+; SPARC64-NEXT:    cmp %l1, %l0
+; SPARC64-NEXT:    movcs %xcc, 1, %g3
+; SPARC64-NEXT:    srl %g3, 0, %l0
 ; SPARC64-NEXT:    mov %g0, %o0
-; SPARC64-NEXT:    mov %i0, %o1
+; SPARC64-NEXT:    mov %i4, %o1
 ; SPARC64-NEXT:    mov %g0, %o2
 ; SPARC64-NEXT:    call __multi3
+; SPARC64-NEXT:    mov %i3, %o3
+; SPARC64-NEXT:    mov %g0, %g2
+; SPARC64-NEXT:    add %o0, %l0, %g3
+; SPARC64-NEXT:    add %o1, %l1, %l1
+; SPARC64-NEXT:    cmp %l1, %o1
+; SPARC64-NEXT:    movcs %xcc, 1, %g2
+; SPARC64-NEXT:    srl %g2, 0, %g2
+; SPARC64-NEXT:    add %g3, %g2, %l2
+; SPARC64-NEXT:    srax %i4, 63, %o2
+; SPARC64-NEXT:    mov %i3, %o0
+; SPARC64-NEXT:    mov %i5, %o1
+; SPARC64-NEXT:    call __multi3
+; SPARC64-NEXT:    mov %o2, %o3
+; SPARC64-NEXT:    mov %o0, %i5
+; SPARC64-NEXT:    mov %o1, %l0
+; SPARC64-NEXT:    srax %i3, 63, %o0
+; SPARC64-NEXT:    mov %o0, %o1
+; SPARC64-NEXT:    mov %i4, %o2
+; SPARC64-NEXT:    call __multi3
 ; SPARC64-NEXT:    mov %i2, %o3
 ; SPARC64-NEXT:    mov %g0, %i2
-; SPARC64-NEXT:    srlx %o1, 32, %i0
-; SPARC64-NEXT:    addcc %o1, %i5, %i5
-; SPARC64-NEXT:    srlx %o0, 32, %g2
-; SPARC64-NEXT:    addxcc %i0, %l4, %i0
-; SPARC64-NEXT:    addxcc %o0, %l5, %g3
-; SPARC64-NEXT:    addxcc %g2, %l6, %g2
-; SPARC64-NEXT:    addcc %i5, %l0, %i5
-; SPARC64-NEXT:    addxcc %i0, %l1, %i0
-; SPARC64-NEXT:    addxcc %g3, %l2, %g3
-; SPARC64-NEXT:    addxcc %g2, %l3, %g2
-; SPARC64-NEXT:    srl %g3, 0, %g3
-; SPARC64-NEXT:    sllx %g2, 32, %g2
-; SPARC64-NEXT:    or %g2, %g3, %g2
-; SPARC64-NEXT:    sllx %i4, 32, %i4
-; SPARC64-NEXT:    srax %i4, 63, %g3
-; SPARC64-NEXT:    xor %g2, %g3, %g2
-; SPARC64-NEXT:    srl %i5, 0, %i5
-; SPARC64-NEXT:    sllx %i0, 32, %i0
-; SPARC64-NEXT:    or %i0, %i5, %i0
-; SPARC64-NEXT:    xor %i0, %g3, %i0
-; SPARC64-NEXT:    or %i0, %g2, %i0
-; SPARC64-NEXT:    movrnz %i0, 1, %i2
-; SPARC64-NEXT:    srl %i3, 0, %i0
-; SPARC64-NEXT:    or %i4, %i0, %i0
+; SPARC64-NEXT:    mov %g0, %i3
+; SPARC64-NEXT:    mov %g0, %i4
+; SPARC64-NEXT:    add %o0, %i5, %i5
+; SPARC64-NEXT:    add %o1, %l0, %g2
+; SPARC64-NEXT:    cmp %g2, %o1
+; SPARC64-NEXT:    movcs %xcc, 1, %i2
 ; SPARC64-NEXT:    srl %i2, 0, %i2
+; SPARC64-NEXT:    add %i5, %i2, %i2
+; SPARC64-NEXT:    add %l2, %i2, %i2
+; SPARC64-NEXT:    add %l1, %g2, %i5
+; SPARC64-NEXT:    cmp %i5, %l1
+; SPARC64-NEXT:    movcs %xcc, 1, %i3
+; SPARC64-NEXT:    srl %i3, 0, %i3
+; SPARC64-NEXT:    add %i2, %i3, %i2
+; SPARC64-NEXT:    srax %i0, 63, %i3
+; SPARC64-NEXT:    xor %i2, %i3, %i2
+; SPARC64-NEXT:    xor %i5, %i3, %i3
+; SPARC64-NEXT:    or %i3, %i2, %i2
+; SPARC64-NEXT:    movrnz %i2, 1, %i4
+; SPARC64-NEXT:    srl %i4, 0, %i2
 ; SPARC64-NEXT:    ret
 ; SPARC64-NEXT:    restore
 start:
-  %0 = tail call { i128, i1 } @llvm.smul.with.overflow.i128(i128 %l, i128 %r) #2
+  %0 = tail call { i128, i1 } @llvm.smul.with.overflow.i128(i128 %l, i128 %r)
   %1 = extractvalue { i128, i1 } %0, 0
   %2 = extractvalue { i128, i1 } %0, 1
   %3 = zext i1 %2 to i8
@@ -279,9 +267,4 @@ start:
   ret { i128, i8 } %5
 }
 
-; Function Attrs: nounwind readnone speculatable
-declare { i128, i1 } @llvm.smul.with.overflow.i128(i128, i128) #1
-
-attributes #0 = { nounwind readnone uwtable }
-attributes #1 = { nounwind readnone speculatable }
-attributes #2 = { nounwind }
+declare { i128, i1 } @llvm.smul.with.overflow.i128(i128, i128)
diff --git a/llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll b/llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll
index 9ca895fe78073d..01383a00c26193 100644
--- a/llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll
+++ b/llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll
@@ -2,14 +2,10 @@
 ; RUN: llc < %s -mtriple=sparc-unknown-linux-gnu | FileCheck %s --check-prefixes=SPARC
 ; RUN: llc < %s -mtriple=sparc64-unknown-linux-gnu | FileCheck %s --check-prefixes=SPARC64
 
-define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
+define { i128, i8 } @muloti_test(i128 %l, i128 %r) nounwind {
 ; SPARC-LABEL: muloti_test:
-; SPARC:         .cfi_startproc
-; SPARC-NEXT:  ! %bb.0: ! %start
+; SPARC:       ! %bb.0: ! %start
 ; SPARC-NEXT:    save %sp, -96, %sp
-; SPARC-NEXT:    .cfi_def_cfa_register %fp
-; SPARC-NEXT:    .cfi_window_save
-; SPARC-NEXT:    .cfi_register %o7, %i7
 ; SPARC-NEXT:    mov %i3, %g2
 ; SPARC-NEXT:    mov %i2, %g4
 ; SPARC-NEXT:    umul %i2, %i5, %i2
@@ -160,14 +156,10 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
 ; SPARC-NEXT:    restore %g0, %g2, %o1
 ;
 ; SPARC64-LABEL: muloti_test:
-; SPARC64:         .cfi_startproc
-; SPARC64-NEXT:    .register %g2, #scratch
+; SPARC64:         .register %g2, #scratch
 ; SPARC64-NEXT:    .register %g3, #scratch
 ; SPARC64-NEXT:  ! %bb.0: ! %start
 ; SPARC64-NEXT:    save %sp, -176, %sp
-; SPARC64-NEXT:    .cfi_def_cfa_register %fp
-; SPARC64-NEXT:    .cfi_window_save
-; SPARC64-NEXT:    .cfi_register %o7, %i7
 ; SPARC64-NEXT:    mov %g0, %o0
 ; SPARC64-NEXT:    mov %i2, %o1
 ; SPARC64-NEXT:    mov %g0, %o2
@@ -208,7 +200,7 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
 ; SPARC64-NEXT:    ret
 ; SPARC64-NEXT:    restore %g0, %o1, %o1
 start:
-  %0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2
+  %0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r)
   %1 = extractvalue { i128, i1 } %0, 0
   %2 = extractvalue { i128, i1 } %0, 1
   %3 = zext i1 %2 to i8
@@ -217,9 +209,4 @@ start:
   ret { i128, i8 } %5
 }
 
-; Function Attrs: nounwind readnone speculatable
-declare { i128, i1 } @llvm.umul.with.overflow.i128(i128, i128) #1
-
-attributes #0 = { nounwind readnone uwtable }
-attributes #1 = { nounwind readnone speculatable }
-attributes #2 = { nounwind }
+declare { i128, i1 } @llvm.umul.with.overflow.i128(i128, i128)