[SPIRV] support capabilities and extensions

This patch supports SPIR-V capabilities and extensions. In addition,
it inserts decorations related to MIFlags and improves support of switches.
Five tests are included to demonstrate the improvement.

Differential Revision: https://reviews.llvm.org/D131221

Co-authored-by: Aleksandr Bezzubikov <zuban32s@gmail.com>
Co-authored-by: Michal Paszkowski <michal.paszkowski@outlook.com>
Co-authored-by: Andrey Tretyakov <andrey1.tretyakov@intel.com>
Co-authored-by: Konrad Trifunovic <konrad.trifunovic@intel.com>

Author: 5 people

llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp

@@ -57,6 +57,7 @@ class SPIRVAsmPrinter : public AsmPrinter {
   void outputMCInst(MCInst &Inst);
   void outputInstruction(const MachineInstr *MI);
   void outputModuleSection(SPIRV::ModuleSectionType MSType);
+  void outputGlobalRequirements();
   void outputEntryPoints();
   void outputDebugSourceAndStrings(const Module &M);
   void outputOpExtInstImports(const Module &M);
@@ -318,6 +319,30 @@ void SPIRVAsmPrinter::outputEntryPoints() {
   }
 }
 
+// Create global OpCapability instructions for the required capabilities.
+void SPIRVAsmPrinter::outputGlobalRequirements() {
+  // Abort here if not all requirements can be satisfied.
+  MAI->Reqs.checkSatisfiable(*ST);
+
+  for (const auto &Cap : MAI->Reqs.getMinimalCapabilities()) {
+    MCInst Inst;
+    Inst.setOpcode(SPIRV::OpCapability);
+    Inst.addOperand(MCOperand::createImm(Cap));
+    outputMCInst(Inst);
+  }
+
+  // Generate the final OpExtensions with strings instead of enums.
+  for (const auto &Ext : MAI->Reqs.getExtensions()) {
+    MCInst Inst;
+    Inst.setOpcode(SPIRV::OpExtension);
+    addStringImm(getSymbolicOperandMnemonic(
+                     SPIRV::OperandCategory::ExtensionOperand, Ext),
+                 Inst);
+    outputMCInst(Inst);
+  }
+  // TODO add a pseudo instr for version number.
+}
+
 void SPIRVAsmPrinter::outputExtFuncDecls() {
   // Insert OpFunctionEnd after each declaration.
   SmallVectorImpl<MachineInstr *>::iterator
@@ -467,8 +492,8 @@ void SPIRVAsmPrinter::outputModuleSections() {
   MAI = &SPIRVModuleAnalysis::MAI;
   assert(ST && TII && MAI && M && "Module analysis is required");
   // Output instructions according to the Logical Layout of a Module:
-  // TODO: 1,2. All OpCapability instructions, then optional OpExtension
-  // instructions.
+  // 1,2. All OpCapability instructions, then optional OpExtension instructions.
+  outputGlobalRequirements();
   // 3. Optional OpExtInstImport instructions.
   outputOpExtInstImports(*M);
   // 4. The single required OpMemoryModel instruction.

llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp

@@ -91,6 +91,56 @@ bool SPIRVInstrInfo::isHeaderInstr(const MachineInstr &MI) const {
   }
 }
 
+bool SPIRVInstrInfo::canUseFastMathFlags(const MachineInstr &MI) const {
+  switch (MI.getOpcode()) {
+  case SPIRV::OpFAddS:
+  case SPIRV::OpFSubS:
+  case SPIRV::OpFMulS:
+  case SPIRV::OpFDivS:
+  case SPIRV::OpFRemS:
+  case SPIRV::OpFAddV:
+  case SPIRV::OpFSubV:
+  case SPIRV::OpFMulV:
+  case SPIRV::OpFDivV:
+  case SPIRV::OpFRemV:
+  case SPIRV::OpFMod:
+    return true;
+  default:
+    return false;
+  }
+}
+
+bool SPIRVInstrInfo::canUseNSW(const MachineInstr &MI) const {
+  switch (MI.getOpcode()) {
+  case SPIRV::OpIAddS:
+  case SPIRV::OpIAddV:
+  case SPIRV::OpISubS:
+  case SPIRV::OpISubV:
+  case SPIRV::OpIMulS:
+  case SPIRV::OpIMulV:
+  case SPIRV::OpShiftLeftLogicalS:
+  case SPIRV::OpShiftLeftLogicalV:
+  case SPIRV::OpSNegate:
+    return true;
+  default:
+    return false;
+  }
+}
+
+bool SPIRVInstrInfo::canUseNUW(const MachineInstr &MI) const {
+  switch (MI.getOpcode()) {
+  case SPIRV::OpIAddS:
+  case SPIRV::OpIAddV:
+  case SPIRV::OpISubS:
+  case SPIRV::OpISubV:
+  case SPIRV::OpIMulS:
+  case SPIRV::OpIMulV:
+    return true;
+  default:
+    return false;
+  }
+}
+
 // Analyze the branching code at the end of MBB, returning
 // true if it cannot be understood (e.g. it's a switch dispatch or isn't
 // implemented for a target).  Upon success, this returns false and returns

llvm/lib/Target/SPIRV/SPIRVInstrInfo.h

@@ -32,6 +32,9 @@ class SPIRVInstrInfo : public SPIRVGenInstrInfo {
   bool isConstantInstr(const MachineInstr &MI) const;
   bool isTypeDeclInstr(const MachineInstr &MI) const;
   bool isDecorationInstr(const MachineInstr &MI) const;
+  bool canUseFastMathFlags(const MachineInstr &MI) const;
+  bool canUseNSW(const MachineInstr &MI) const;
+  bool canUseNUW(const MachineInstr &MI) const;
 
   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
                      MachineBasicBlock *&FBB,