diff --git a/llvm/include/llvm/CodeGen/TargetPassConfig.h b/llvm/include/llvm/CodeGen/TargetPassConfig.h index 85f87de521855..66c79c74f2be5 100644 --- a/llvm/include/llvm/CodeGen/TargetPassConfig.h +++ b/llvm/include/llvm/CodeGen/TargetPassConfig.h @@ -413,7 +413,8 @@ class TargetPassConfig : public ImmutablePass { virtual void addFastRegAlloc(); /// addOptimizedRegAlloc - Add passes related to register allocation. - /// CodeGenCommonTMImpl provides standard regalloc passes for most targets. + /// CodeGenTargetMachineImpl provides standard regalloc passes for most + /// targets. virtual void addOptimizedRegAlloc(); /// addPreRewrite - Add passes to the optimized register allocation pipeline diff --git a/llvm/include/llvm/MC/MCAsmInfo.h b/llvm/include/llvm/MC/MCAsmInfo.h index ccb7c524d45f8..cf31c36cc4cef 100644 --- a/llvm/include/llvm/MC/MCAsmInfo.h +++ b/llvm/include/llvm/MC/MCAsmInfo.h @@ -484,7 +484,7 @@ class MCAsmInfo { /// The integrated assembler should be enabled by default (by the /// constructors) when failing to parse a valid piece of assembly (inline /// or otherwise) is considered a bug. It may then be overridden after - /// construction (see LLVMTargetMachine::initAsmInfo()). + /// construction (see CodeGenTargetMachineImpl::initAsmInfo()). bool UseIntegratedAssembler; /// Use AsmParser to parse inlineAsm when UseIntegratedAssembler is not set. diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index d04387535db0d..7fa6fa118fe55 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -443,7 +443,8 @@ template class CodeGenPassBuilder { Error addFastRegAlloc(AddMachinePass &) const; /// addOptimizedRegAlloc - Add passes related to register allocation. - /// CodeGenCommonTMImpl provides standard regalloc passes for most targets. + /// CodeGenTargetMachineImpl provides standard regalloc passes for most + /// targets. void addOptimizedRegAlloc(AddMachinePass &) const; /// Add passes that optimize machine instructions after register allocation. diff --git a/llvm/lib/Target/ARC/ARCTargetMachine.cpp b/llvm/lib/Target/ARC/ARCTargetMachine.cpp index df8c96a4d9793..57e0177cd3748 100644 --- a/llvm/lib/Target/ARC/ARCTargetMachine.cpp +++ b/llvm/lib/Target/ARC/ARCTargetMachine.cpp @@ -33,11 +33,12 @@ ARCTargetMachine::ARCTargetMachine(const Target &T, const Triple &TT, std::optional RM, std::optional CM, CodeGenOptLevel OL, bool JIT) - : CodeGenCommonTMImpl(T, - "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" - "f32:32:32-i64:32-f64:32-a:0:32-n32", - TT, CPU, FS, Options, getRelocModel(RM), - getEffectiveCodeModel(CM, CodeModel::Small), OL), + : CodeGenTargetMachineImpl( + T, + "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" + "f32:32:32-i64:32-f64:32-a:0:32-n32", + TT, CPU, FS, Options, getRelocModel(RM), + getEffectiveCodeModel(CM, CodeModel::Small), OL), TLOF(std::make_unique()), Subtarget(TT, std::string(CPU), std::string(FS), *this) { initAsmInfo(); diff --git a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp index c256bb2d6a4cd..ae6ef89fdcd07 100644 --- a/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp +++ b/llvm/lib/Target/CSKY/CSKYTargetMachine.cpp @@ -54,9 +54,9 @@ CSKYTargetMachine::CSKYTargetMachine(const Target &T, const Triple &TT, std::optional RM, std::optional CM, CodeGenOptLevel OL, bool JIT) - : CodeGenCommonTMImpl(T, computeDataLayout(TT), TT, CPU, FS, Options, - RM.value_or(Reloc::Static), - getEffectiveCodeModel(CM, CodeModel::Small), OL), + : CodeGenTargetMachineImpl(T, computeDataLayout(TT), TT, CPU, FS, Options, + RM.value_or(Reloc::Static), + getEffectiveCodeModel(CM, CodeModel::Small), OL), TLOF(std::make_unique()) { initAsmInfo(); } diff --git a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp index 914aee4f8b4b9..655427a3e8020 100644 --- a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp +++ b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp @@ -108,7 +108,7 @@ DirectXTargetMachine::DirectXTargetMachine(const Target &T, const Triple &TT, std::optional RM, std::optional CM, CodeGenOptLevel OL, bool JIT) - : CodeGenCommonTMImpl( + : CodeGenTargetMachineImpl( T, "e-m:e-p:32:32-i1:32-i8:8-i16:16-i32:32-i64:64-f16:16-" "f32:32-f64:64-n8:16:32:64", diff --git a/llvm/lib/Target/M68k/M68kTargetMachine.cpp b/llvm/lib/Target/M68k/M68kTargetMachine.cpp index ce5970c5ec95d..2f5a2e8288a26 100644 --- a/llvm/lib/Target/M68k/M68kTargetMachine.cpp +++ b/llvm/lib/Target/M68k/M68kTargetMachine.cpp @@ -100,9 +100,9 @@ M68kTargetMachine::M68kTargetMachine(const Target &T, const Triple &TT, std::optional RM, std::optional CM, CodeGenOptLevel OL, bool JIT) - : CodeGenCommonTMImpl(T, computeDataLayout(TT, CPU, Options), TT, CPU, FS, - Options, getEffectiveRelocModel(TT, RM), - ::getEffectiveCodeModel(CM, JIT), OL), + : CodeGenTargetMachineImpl(T, computeDataLayout(TT, CPU, Options), TT, CPU, + FS, Options, getEffectiveRelocModel(TT, RM), + ::getEffectiveCodeModel(CM, JIT), OL), TLOF(std::make_unique()), Subtarget(TT, CPU, FS, *this) { initAsmInfo(); diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp index a388b44b3ac83..e547e62094404 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp @@ -805,8 +805,8 @@ MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S, ELFObjectWriter &W = getStreamer().getWriter(); // It's possible that MCObjectFileInfo isn't fully initialized at this point - // due to an initialization order problem where CodeGenCommonTMImpl creates - // the target streamer before TargetLoweringObjectFile calls + // due to an initialization order problem where CodeGenTargetMachineImpl + // creates the target streamer before TargetLoweringObjectFile calls // InitializeMCObjectFileInfo. There doesn't seem to be a single place that // covers all cases so this statement covers most cases and direct object // emission must call setPic() once MCObjectFileInfo has been initialized. The diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp index 1f6866383e606..2b64ab9aa6973 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -345,8 +345,8 @@ static ScheduleDAGInstrs *createPPCPostMachineScheduler( // The FeatureString here is a little subtle. We are modifying the feature // string with what are (currently) non-function specific overrides as it goes -// into the CodeGenCommonTMImpl constructor and then using the stored value in -// the Subtarget constructor below it. +// into the CodeGenTargetMachineImpl constructor and then using the stored value +// in the Subtarget constructor below it. PPCTargetMachine::PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, diff --git a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h index 75b622046a630..e8eeb85647b83 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetMachine.h +++ b/llvm/lib/Target/SystemZ/SystemZTargetMachine.h @@ -44,7 +44,7 @@ class SystemZTargetMachine : public CodeGenTargetMachineImpl { // attributes of each function. const SystemZSubtarget *getSubtargetImpl() const = delete; - // Override LLVMTargetMachine + // Override CodeGenTargetMachineImpl TargetPassConfig *createPassConfig(PassManagerBase &PM) override; TargetTransformInfo getTargetTransformInfo(const Function &F) const override; diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp index 7fb998d615c46..634ada375a3dc 100644 --- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp +++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp @@ -50,9 +50,10 @@ XtensaTargetMachine::XtensaTargetMachine(const Target &T, const Triple &TT, std::optional CM, CodeGenOptLevel OL, bool JIT, bool IsLittle) - : CodeGenCommonTMImpl(T, computeDataLayout(TT, CPU, Options, IsLittle), TT, - CPU, FS, Options, getEffectiveRelocModel(JIT, RM), - getEffectiveCodeModel(CM, CodeModel::Small), OL), + : CodeGenTargetMachineImpl(T, computeDataLayout(TT, CPU, Options, IsLittle), + TT, CPU, FS, Options, + getEffectiveRelocModel(JIT, RM), + getEffectiveCodeModel(CM, CodeModel::Small), OL), TLOF(std::make_unique()) { initAsmInfo(); }