From 55f1ff02405cdab0c22c5a32b576f06d020ee3b6 Mon Sep 17 00:00:00 2001 From: Un1q32 Date: Sun, 27 Jul 2025 08:34:45 -0400 Subject: [PATCH 1/6] Reserve R9 on iOS before 3.0 --- llvm/lib/Target/ARM/ARMSubtarget.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index 9f600e0c685ab..d6e226736ba66 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -227,7 +227,10 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { (Options.UnsafeFPMath || isTargetDarwin())) HasNEONForFP = true; - if (isRWPI()) + if (isRWPI() || + (isTargetIOS() && + ARM::parseArch(TargetTriple.getArchName()) == ARM::ArchKind::ARMV6K && + TargetTriple.isOSVersionLT(3, 0))) ReserveR9 = true; // If MVEVectorCostFactor is still 0 (has not been set to anything else), default it to 2 From 2e74395945645d47454ea4f704e5ae15a833c504 Mon Sep 17 00:00:00 2001 From: Un1q32 Date: Tue, 26 Aug 2025 20:32:43 -0400 Subject: [PATCH 2/6] add test for iOS 2 ABI --- llvm/test/CodeGen/ARM/inline-asm-clobber.ll | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/llvm/test/CodeGen/ARM/inline-asm-clobber.ll b/llvm/test/CodeGen/ARM/inline-asm-clobber.ll index 7b1331f3f1e84..42392856df53b 100644 --- a/llvm/test/CodeGen/ARM/inline-asm-clobber.ll +++ b/llvm/test/CodeGen/ARM/inline-asm-clobber.ll @@ -6,12 +6,21 @@ ; RUN: llc <%s -mtriple=arm-none-eabi --frame-pointer=all 2>&1 \ ; RUN: | FileCheck %s -check-prefix=NO_FP_ELIM +; RUN: llc <%s -mtriple=armv6k-apple-ios2 2>&1 | FileCheck %s -check-prefix=IOS2 + +; RUN: llc <%s -mtriple=armv6k-apple-ios3 2>&1 | FileCheck %s -check-prefix=IOS3 + +; RUN: llc <%s -mtriple=armv7-apple-ios2 2>&1 | FileCheck %s -check-prefix=IOSV7 + ; CHECK: warning: inline asm clobber list contains reserved registers: SP, PC ; CHECK: warning: inline asm clobber list contains reserved registers: R11 ; RWPI: warning: inline asm clobber list contains reserved registers: R9, SP, PC ; RWPI: warning: inline asm clobber list contains reserved registers: R11 ; NO_FP_ELIM: warning: inline asm clobber list contains reserved registers: R11, SP, PC ; NO_FP_ELIM: warning: inline asm clobber list contains reserved registers: R11 +; IOS2: warning: inline asm clobber list contains reserved registers: R9, SP, PC +; IOS3: warning: inline asm clobber list contains reserved registers: SP, PC +; IOSV7: warning: inline asm clobber list contains reserved registers: SP, PC define void @foo() nounwind { call void asm sideeffect "mov r7, #1", From 4f3b8351a18903795ee6f7077ef96dfbd0bda856 Mon Sep 17 00:00:00 2001 From: Un1q32 Date: Tue, 26 Aug 2025 20:43:31 -0400 Subject: [PATCH 3/6] apply this to armv6 and armv6k --- llvm/lib/Target/ARM/ARMSubtarget.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index d6e226736ba66..a8309f6eb0554 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -227,9 +227,10 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { (Options.UnsafeFPMath || isTargetDarwin())) HasNEONForFP = true; + const ARM::ArchKind Arch = ARM::parseArch(TargetTriple.getArchName()); if (isRWPI() || (isTargetIOS() && - ARM::parseArch(TargetTriple.getArchName()) == ARM::ArchKind::ARMV6K && + (Arch == ARM::ArchKind::ARMV6K || Arch == ARM::ArchKind::ARMV6) && TargetTriple.isOSVersionLT(3, 0))) ReserveR9 = true; From 1cf6018c4805a51e571985dbe5c1307b776e0e1f Mon Sep 17 00:00:00 2001 From: Un1q32 Date: Wed, 27 Aug 2025 14:24:31 -0400 Subject: [PATCH 4/6] remove whitespace --- llvm/test/CodeGen/ARM/inline-asm-clobber.ll | 2 -- 1 file changed, 2 deletions(-) diff --git a/llvm/test/CodeGen/ARM/inline-asm-clobber.ll b/llvm/test/CodeGen/ARM/inline-asm-clobber.ll index 42392856df53b..c2ec50c12e5d5 100644 --- a/llvm/test/CodeGen/ARM/inline-asm-clobber.ll +++ b/llvm/test/CodeGen/ARM/inline-asm-clobber.ll @@ -7,9 +7,7 @@ ; RUN: | FileCheck %s -check-prefix=NO_FP_ELIM ; RUN: llc <%s -mtriple=armv6k-apple-ios2 2>&1 | FileCheck %s -check-prefix=IOS2 - ; RUN: llc <%s -mtriple=armv6k-apple-ios3 2>&1 | FileCheck %s -check-prefix=IOS3 - ; RUN: llc <%s -mtriple=armv7-apple-ios2 2>&1 | FileCheck %s -check-prefix=IOSV7 ; CHECK: warning: inline asm clobber list contains reserved registers: SP, PC From e3e5f5053b45cffd724649573e782c6a74e0e5a4 Mon Sep 17 00:00:00 2001 From: Un1q32 Date: Mon, 29 Sep 2025 14:44:25 -0400 Subject: [PATCH 5/6] Update llvm/test/CodeGen/ARM/inline-asm-clobber.ll Co-authored-by: Jon Roelofs --- llvm/test/CodeGen/ARM/inline-asm-clobber.ll | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/test/CodeGen/ARM/inline-asm-clobber.ll b/llvm/test/CodeGen/ARM/inline-asm-clobber.ll index c2ec50c12e5d5..da10d2d9f30d6 100644 --- a/llvm/test/CodeGen/ARM/inline-asm-clobber.ll +++ b/llvm/test/CodeGen/ARM/inline-asm-clobber.ll @@ -6,6 +6,7 @@ ; RUN: llc <%s -mtriple=arm-none-eabi --frame-pointer=all 2>&1 \ ; RUN: | FileCheck %s -check-prefix=NO_FP_ELIM +; RUN: llc <%s -mtriple=armv6-apple-ios2 2>&1 | FileCheck %s -check-prefix=IOS2 ; RUN: llc <%s -mtriple=armv6k-apple-ios2 2>&1 | FileCheck %s -check-prefix=IOS2 ; RUN: llc <%s -mtriple=armv6k-apple-ios3 2>&1 | FileCheck %s -check-prefix=IOS3 ; RUN: llc <%s -mtriple=armv7-apple-ios2 2>&1 | FileCheck %s -check-prefix=IOSV7 From f1e3a219352ad79ca0b91021032a508c8c09e43a Mon Sep 17 00:00:00 2001 From: Un1q32 Date: Mon, 29 Sep 2025 15:08:44 -0400 Subject: [PATCH 6/6] oh hey does this work? --- llvm/test/CodeGen/ARM/inline-asm-clobber.ll | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/llvm/test/CodeGen/ARM/inline-asm-clobber.ll b/llvm/test/CodeGen/ARM/inline-asm-clobber.ll index da10d2d9f30d6..f44ad2a896ad4 100644 --- a/llvm/test/CodeGen/ARM/inline-asm-clobber.ll +++ b/llvm/test/CodeGen/ARM/inline-asm-clobber.ll @@ -9,7 +9,7 @@ ; RUN: llc <%s -mtriple=armv6-apple-ios2 2>&1 | FileCheck %s -check-prefix=IOS2 ; RUN: llc <%s -mtriple=armv6k-apple-ios2 2>&1 | FileCheck %s -check-prefix=IOS2 ; RUN: llc <%s -mtriple=armv6k-apple-ios3 2>&1 | FileCheck %s -check-prefix=IOS3 -; RUN: llc <%s -mtriple=armv7-apple-ios2 2>&1 | FileCheck %s -check-prefix=IOSV7 +; RUN: llc <%s -mtriple=armv7-apple-ios2 2>&1 | FileCheck %s -check-prefix=IOS3 ; CHECK: warning: inline asm clobber list contains reserved registers: SP, PC ; CHECK: warning: inline asm clobber list contains reserved registers: R11 @@ -19,7 +19,6 @@ ; NO_FP_ELIM: warning: inline asm clobber list contains reserved registers: R11 ; IOS2: warning: inline asm clobber list contains reserved registers: R9, SP, PC ; IOS3: warning: inline asm clobber list contains reserved registers: SP, PC -; IOSV7: warning: inline asm clobber list contains reserved registers: SP, PC define void @foo() nounwind { call void asm sideeffect "mov r7, #1",