diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 3b738e4cc11a1..96780a51d08fc 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -404,11 +404,9 @@ def FeatureStdExtZcd
                      "Compressed Double-Precision Floating-Point Instructions",
                      [FeatureStdExtD, FeatureStdExtZca]>,
       RISCVExtensionBitmask<1, 4>;
-
-def HasStdExtCOrZcd
-    : Predicate<"Subtarget->hasStdExtCOrZcd()">,
-      AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcd),
-                         "'C' (Compressed Instructions) or "
+def HasStdExtZcd
+    : Predicate<"Subtarget->hasStdExtZcd()">,
+      AssemblerPredicate<(any_of FeatureStdExtZcd),
                          "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
 
 def FeatureStdExtZcf
@@ -416,6 +414,10 @@ def FeatureStdExtZcf
                      "Compressed Single-Precision Floating-Point Instructions",
                      [FeatureStdExtF, FeatureStdExtZca]>,
       RISCVExtensionBitmask<1, 5>;
+def HasStdExtZcf
+    : Predicate<"Subtarget->hasStdExtZcf()">,
+      AssemblerPredicate<(any_of FeatureStdExtZcf),
+                         "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
 
 def FeatureStdExtZclsd
     : RISCVExtension<1, 0,
@@ -431,7 +433,7 @@ def FeatureStdExtZcmp
                      "sequenced instructions for code-size reduction",
                      [FeatureStdExtZca]>,
       RISCVExtensionBitmask<1, 10>;
-def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,
+def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp()">,
                     AssemblerPredicate<(all_of FeatureStdExtZcmp),
                         "'Zcmp' (sequenced instructions for code-size reduction)">;
 
@@ -449,14 +451,6 @@ def FeatureStdExtZce
                      [FeatureStdExtZca, FeatureStdExtZcb, FeatureStdExtZcmp,
                       FeatureStdExtZcmt]>;
 
-def HasStdExtCOrZcfOrZce
-    : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() ||"
-                "Subtarget->hasStdExtZce()">,
-      AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcf,
-                                 FeatureStdExtZce),
-                         "'C' (Compressed Instructions) or "
-                         "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
-
 def FeatureStdExtZcmop
     : RISCVExtension<1, 0, "Compressed May-Be-Operations",
                      [FeatureStdExtZca]>,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index c5551fbdec287..451cc9d06a821 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -301,7 +301,7 @@ def C_ADDI4SPN : RVInst16CIW<0b000, 0b00, (outs GPRC:$rd),
   let Inst{5} = imm{3};
 }
 
-let Predicates = [HasStdExtCOrZcd, HasStdExtD] in
+let Predicates = [HasStdExtZcd, HasStdExtD] in
 def C_FLD  : CLoad_ri<0b001, "c.fld", FPR64C, uimm8_lsb000>,
              Sched<[WriteFLD64, ReadFMemBase]> {
   bits<8> imm;
@@ -327,7 +327,7 @@ def C_LW_INX : CLoad_ri<0b010, "c.lw", GPRF32C, uimm7_lsb00>,
 }
 
 let DecoderNamespace = "RV32Only",
-    Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
+    Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in
 def C_FLW  : CLoad_ri<0b011, "c.flw", FPR32C, uimm7_lsb00>,
              Sched<[WriteFLD32, ReadFMemBase]> {
   bits<7> imm;
@@ -344,7 +344,7 @@ def C_LD : CLoad_ri<0b011, "c.ld", GPRC, uimm8_lsb000>,
   let Inst{6-5} = imm{7-6};
 }
 
-let Predicates = [HasStdExtCOrZcd, HasStdExtD] in
+let Predicates = [HasStdExtZcd, HasStdExtD] in
 def C_FSD  : CStore_rri<0b101, "c.fsd", FPR64C, uimm8_lsb000>,
              Sched<[WriteFST64, ReadFStoreData, ReadFMemBase]> {
   bits<8> imm;
@@ -370,7 +370,7 @@ def C_SW_INX : CStore_rri<0b110, "c.sw", GPRF32C, uimm7_lsb00>,
 }
 
 let DecoderNamespace = "RV32Only",
-    Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32]  in
+    Predicates = [HasStdExtZcf, HasStdExtF, IsRV32]  in
 def C_FSW  : CStore_rri<0b111, "c.fsw", FPR32C, uimm7_lsb00>,
              Sched<[WriteFST32, ReadFStoreData, ReadFMemBase]> {
   bits<7> imm;
@@ -500,7 +500,7 @@ def C_SLLI : RVInst16CI<0b000, 0b10, (outs GPR:$rd_wb),
   let Constraints = "$rd = $rd_wb";
 }
 
-let Predicates = [HasStdExtCOrZcd, HasStdExtD] in
+let Predicates = [HasStdExtZcd, HasStdExtD] in
 def C_FLDSP  : CStackLoad<0b001, "c.fldsp", FPR64, uimm9_lsb000>,
                Sched<[WriteFLD64, ReadFMemBase]> {
   let Inst{4-2} = imm{8-6};
@@ -518,7 +518,7 @@ def C_LWSP_INX : CStackLoad<0b010, "c.lwsp", GPRF32NoX0, uimm8_lsb00>,
 }
 
 let DecoderNamespace = "RV32Only",
-    Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
+    Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in
 def C_FLWSP  : CStackLoad<0b011, "c.flwsp", FPR32, uimm8_lsb00>,
                Sched<[WriteFLD32, ReadFMemBase]> {
   let Inst{3-2} = imm{7-6};
@@ -560,7 +560,7 @@ def C_ADD : RVInst16CR<0b1001, 0b10, (outs GPR:$rd),
   let Constraints = "$rs1 = $rd";
 }
 
-let Predicates = [HasStdExtCOrZcd, HasStdExtD] in
+let Predicates = [HasStdExtZcd, HasStdExtD] in
 def C_FSDSP  : CStackStore<0b101, "c.fsdsp", FPR64, uimm9_lsb000>,
                Sched<[WriteFST64, ReadFStoreData, ReadFMemBase]> {
   let Inst{9-7}   = imm{8-6};
@@ -578,7 +578,7 @@ def C_SWSP_INX : CStackStore<0b110, "c.swsp", GPRF32, uimm8_lsb00>,
 }
 
 let DecoderNamespace = "RV32Only",
-    Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
+    Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in
 def C_FSWSP  : CStackStore<0b111, "c.fswsp", FPR32, uimm8_lsb00>,
                Sched<[WriteFST32, ReadFStoreData, ReadFMemBase]> {
   let Inst{8-7}  = imm{7-6};
@@ -648,14 +648,14 @@ def : InstAlias<"c.ldsp $rd, (${rs1})", (C_LDSP GPRNoX0:$rd, SPMem:$rs1, 0)>;
 def : InstAlias<"c.sdsp $rs2, (${rs1})", (C_SDSP GPR:$rs2, SPMem:$rs1, 0)>;
 }
 
-let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
+let Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in {
 def : InstAlias<"c.flw $rd, (${rs1})", (C_FLW FPR32C:$rd, GPRCMem:$rs1, 0)>;
 def : InstAlias<"c.fsw $rs2, (${rs1})", (C_FSW FPR32C:$rs2, GPRCMem:$rs1, 0)>;
 def : InstAlias<"c.flwsp $rd, (${rs1})", (C_FLWSP FPR32:$rd, SPMem:$rs1, 0)>;
 def : InstAlias<"c.fswsp $rs2, (${rs1})", (C_FSWSP FPR32:$rs2, SPMem:$rs1, 0)>;
 }
 
-let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {
+let Predicates = [HasStdExtZcd, HasStdExtD] in {
 def : InstAlias<"c.fld $rd, (${rs1})", (C_FLD FPR64C:$rd, GPRCMem:$rs1, 0)>;
 def : InstAlias<"c.fsd $rs2, (${rs1})", (C_FSD FPR64C:$rs2, GPRCMem:$rs1, 0)>;
 def : InstAlias<"c.fldsp $rd, (${rs1})", (C_FLDSP FPR64:$rd, SPMem:$rs1, 0)>;
@@ -776,10 +776,10 @@ def : CompressPat<(ADDI GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm),
                   (C_ADDI4SPN GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm)>;
 } // Predicates = [HasStdExtZca]
 
-let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {
+let Predicates = [HasStdExtZcd, HasStdExtD] in {
 def : CompressPat<(FLD FPR64C:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm),
                   (C_FLD FPR64C:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm)>;
-} // Predicates = [HasStdExtCOrZcd, HasStdExtD]
+} // Predicates = [HasStdExtZcd, HasStdExtD]
 
 let Predicates = [HasStdExtZca] in {
 def : CompressPat<(LW GPRC:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm),
@@ -790,20 +790,20 @@ def : CompressPat<(LW_INX GPRF32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm),
                   (C_LW_INX GPRF32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
 } // Predicates = [HasStdExtZca]
 
-let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
+let Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in {
 def : CompressPat<(FLW FPR32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm),
                   (C_FLW FPR32C:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
-} // Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32]
+} // Predicates = [HasStdExtZcf, HasStdExtF, IsRV32]
 
 let Predicates = [HasStdExtZca, IsRV64] in {
 def : CompressPat<(LD GPRC:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm),
                   (C_LD GPRC:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm)>;
 } // Predicates = [HasStdExtZca, IsRV64]
 
-let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {
+let Predicates = [HasStdExtZcd, HasStdExtD] in {
 def : CompressPat<(FSD FPR64C:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm),
                   (C_FSD FPR64C:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm)>;
-} // Predicates = [HasStdExtCOrZcd, HasStdExtD]
+} // Predicates = [HasStdExtZcd, HasStdExtD]
 
 let Predicates = [HasStdExtZca] in {
 def : CompressPat<(SW GPRC:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm),
@@ -814,10 +814,10 @@ def : CompressPat<(SW_INX GPRF32C:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm),
                   (C_SW_INX GPRF32C:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
 } // Predicates = [HasStdExtZca]
 
-let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
+let Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in {
 def : CompressPat<(FSW FPR32C:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm),
                   (C_FSW FPR32C:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
-} // Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32]
+} // Predicates = [HasStdExtZcf, HasStdExtF, IsRV32]
 
 let Predicates = [HasStdExtZca, IsRV64] in {
 def : CompressPat<(SD GPRC:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm),
@@ -907,10 +907,10 @@ def : CompressPat<(SLLI GPRNoX0:$rs1, GPRNoX0:$rs1, uimmlog2xlennonzero:$imm),
                   (C_SLLI GPRNoX0:$rs1, uimmlog2xlennonzero:$imm)>;
 } // Predicates = [HasStdExtZca]
 
-let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {
+let Predicates = [HasStdExtZcd, HasStdExtD] in {
 def : CompressPat<(FLD FPR64:$rd, SPMem:$rs1, uimm9_lsb000:$imm),
                   (C_FLDSP FPR64:$rd, SPMem:$rs1, uimm9_lsb000:$imm)>;
-} // Predicates = [HasStdExtCOrZcd, HasStdExtD]
+} // Predicates = [HasStdExtZcd, HasStdExtD]
 
 let Predicates = [HasStdExtZca] in {
 def : CompressPat<(LW GPRNoX0:$rd, SPMem:$rs1,  uimm8_lsb00:$imm),
@@ -921,10 +921,10 @@ def : CompressPat<(LW_INX GPRF32NoX0:$rd, SPMem:$rs1,  uimm8_lsb00:$imm),
                   (C_LWSP_INX GPRF32NoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>;
 } // Predicates = [HasStdExtZca]
 
-let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
+let Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in {
 def : CompressPat<(FLW FPR32:$rd, SPMem:$rs1, uimm8_lsb00:$imm),
                   (C_FLWSP FPR32:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>;
-} // Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32]
+} // Predicates = [HasStdExtZcf, HasStdExtF, IsRV32]
 
 let Predicates = [HasStdExtZca, IsRV64] in {
 def : CompressPat<(LD GPRNoX0:$rd, SPMem:$rs1, uimm9_lsb000:$imm),
@@ -953,10 +953,10 @@ def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs2, GPRNoX0:$rs1),
                   (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
 } // Predicates = [HasStdExtZca]
 
-let Predicates = [HasStdExtCOrZcd, HasStdExtD] in {
+let Predicates = [HasStdExtZcd, HasStdExtD] in {
 def : CompressPat<(FSD FPR64:$rs2, SPMem:$rs1, uimm9_lsb000:$imm),
                   (C_FSDSP FPR64:$rs2, SPMem:$rs1, uimm9_lsb000:$imm)>;
-} // Predicates = [HasStdExtCOrZcd, HasStdExtD]
+} // Predicates = [HasStdExtZcd, HasStdExtD]
 
 let Predicates = [HasStdExtZca] in {
 def : CompressPat<(SW GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),
@@ -967,10 +967,10 @@ def : CompressPat<(SW_INX GPRF32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),
                   (C_SWSP_INX GPRF32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>;
 } // Predicates = [HasStdExtZca]
 
-let Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in {
+let Predicates = [HasStdExtZcf, HasStdExtF, IsRV32] in {
 def : CompressPat<(FSW FPR32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),
                   (C_FSWSP FPR32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>;
-} // Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32]
+} // Predicates = [HasStdExtZcf, HasStdExtF, IsRV32]
 
 let Predicates = [HasStdExtZca, IsRV64] in {
 def : CompressPat<(SD GPR:$rs2, SPMem:$rs1, uimm9_lsb000:$imm),
diff --git a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
index f8d33ae8d24ca..f77c245eb4aac 100644
--- a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
@@ -211,9 +211,9 @@ static bool isCompressibleLoad(const MachineInstr &MI) {
   case RISCV::LD_RV32:
     return STI.hasStdExtZclsd();
   case RISCV::FLW:
-    return !STI.is64Bit() && STI.hasStdExtCOrZcfOrZce();
+    return !STI.is64Bit() && STI.hasStdExtZcf();
   case RISCV::FLD:
-    return STI.hasStdExtCOrZcd();
+    return STI.hasStdExtZcd();
   }
 }
 
@@ -235,9 +235,9 @@ static bool isCompressibleStore(const MachineInstr &MI) {
   case RISCV::SD_RV32:
     return STI.hasStdExtZclsd();
   case RISCV::FSW:
-    return !STI.is64Bit() && STI.hasStdExtCOrZcfOrZce();
+    return !STI.is64Bit() && STI.hasStdExtZcf();
   case RISCV::FSD:
-    return STI.hasStdExtCOrZcd();
+    return STI.hasStdExtZcd();
   }
 }
 
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index fd57e02c25d05..05f96bd976f72 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -171,10 +171,15 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
 
   LLVM_DEPRECATED("Now Equivalent to hasStdExtZca", "hasStdExtZca")
   bool hasStdExtCOrZca() const { return HasStdExtZca; }
+
+  LLVM_DEPRECATED("Equivalent to hasStdExtZcd", "hasStdExtZcd")
   bool hasStdExtCOrZcd() const { return HasStdExtC || HasStdExtZcd; }
+
+  LLVM_DEPRECATED("Equivalent to hasStdExtZcf", "hasStdExtZcf")
   bool hasStdExtCOrZcfOrZce() const {
     return HasStdExtC || HasStdExtZcf || HasStdExtZce;
   }
+
   bool hasStdExtZvl() const { return ZvlLen != 0; }
   bool hasStdExtFOrZfinx() const { return HasStdExtF || HasStdExtZfinx; }
   bool hasStdExtDOrZdinx() const { return HasStdExtD || HasStdExtZdinx; }
diff --git a/llvm/test/CodeGen/RISCV/compress-float.ll b/llvm/test/CodeGen/RISCV/compress-float.ll
index d12badd658d6e..8667d3b5fd057 100644
--- a/llvm/test/CodeGen/RISCV/compress-float.ll
+++ b/llvm/test/CodeGen/RISCV/compress-float.ll
@@ -5,27 +5,6 @@
 ;
 ; RUN: cat %s > %t.tgtattr
 ; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr
-; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+c,+f -filetype=obj \
-; RUN:   -disable-block-placement < %t.tgtattr \
-; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c,+f -M no-aliases - \
-; RUN:   | FileCheck -check-prefix=RV32IFDC %s
-;
-; RUN: cat %s > %t.fnattr
-; RUN: echo 'attributes #0 = { nounwind "target-features"="+c,+f" }' >> %t.fnattr
-; RUN: llc -mtriple=riscv32 -target-abi ilp32f -filetype=obj \
-; RUN:   -disable-block-placement < %t.fnattr \
-; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c,+f -M no-aliases - \
-; RUN:   | FileCheck -check-prefix=RV32IFDC %s
-;
-; RUN: cat %s > %t.mixedattr
-; RUN: echo 'attributes #0 = { nounwind "target-features"="+f" }' >> %t.mixedattr
-; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+c -filetype=obj \
-; RUN:   -disable-block-placement < %t.mixedattr \
-; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+c,+f -M no-aliases - \
-; RUN:   | FileCheck -check-prefix=RV32IFDC %s
-;
-; RUN: cat %s > %t.tgtattr
-; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr
 ; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zcf,+f -filetype=obj \
 ; RUN:   -disable-block-placement < %t.tgtattr \
 ; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zcf,+f -M no-aliases - \
@@ -44,27 +23,6 @@
 ; RUN:   -disable-block-placement < %t.mixedattr \
 ; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zcf,+f -M no-aliases - \
 ; RUN:   | FileCheck -check-prefix=RV32IFDC %s
-;
-; RUN: cat %s > %t.tgtattr
-; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr
-; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zce,+f -filetype=obj \
-; RUN:   -disable-block-placement < %t.tgtattr \
-; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zce,+f -M no-aliases - \
-; RUN:   | FileCheck -check-prefix=RV32IFDC %s
-;
-; RUN: cat %s > %t.fnattr
-; RUN: echo 'attributes #0 = { nounwind "target-features"="+zce,+f" }' >> %t.fnattr
-; RUN: llc -mtriple=riscv32 -target-abi ilp32f -filetype=obj \
-; RUN:   -disable-block-placement < %t.fnattr \
-; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zce,+f -M no-aliases - \
-; RUN:   | FileCheck -check-prefix=RV32IFDC %s
-;
-; RUN: cat %s > %t.mixedattr
-; RUN: echo 'attributes #0 = { nounwind "target-features"="+f" }' >> %t.mixedattr
-; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zce -filetype=obj \
-; RUN:   -disable-block-placement < %t.mixedattr \
-; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+zce,+f -M no-aliases - \
-; RUN:   | FileCheck -check-prefix=RV32IFDC %s
 
 ; This acts as a basic correctness check for the codegen instruction compression
 ; path, verifying that the assembled file contains compressed instructions when
diff --git a/llvm/test/CodeGen/RISCV/make-compressible.mir b/llvm/test/CodeGen/RISCV/make-compressible.mir
index 03da38a6863e7..068ff7591c83d 100644
--- a/llvm/test/CodeGen/RISCV/make-compressible.mir
+++ b/llvm/test/CodeGen/RISCV/make-compressible.mir
@@ -1,7 +1,7 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -o - %s -mtriple=riscv32 -mattr=+c,+f,+d -simplify-mir \
+# RUN: llc -o - %s -mtriple=riscv32 -mattr=+c,+f,+d,+zcf,+zcd -simplify-mir \
 # RUN:   -run-pass=riscv-make-compressible | FileCheck --check-prefixes=RV32,RV32C %s
-# RUN: llc -o - %s -mtriple=riscv64 -mattr=+c,+f,+d -simplify-mir \
+# RUN: llc -o - %s -mtriple=riscv64 -mattr=+c,+f,+d,+zcd -simplify-mir \
 # RUN:   -run-pass=riscv-make-compressible | FileCheck --check-prefixes=RV64,RV64C %s
 # RUN: llc -o - %s -mtriple=riscv32 -mattr=+d,+zcf -simplify-mir \
 # RUN:   -run-pass=riscv-make-compressible | FileCheck --check-prefixes=RV32,RV32ZCF %s
diff --git a/llvm/test/MC/RISCV/compress-rv32d.s b/llvm/test/MC/RISCV/compress-rv32d.s
index 2bfae212e1fd3..0900f6ee44494 100644
--- a/llvm/test/MC/RISCV/compress-rv32d.s
+++ b/llvm/test/MC/RISCV/compress-rv32d.s
@@ -1,13 +1,3 @@
-# RUN: llvm-mc -triple riscv32 -mattr=+c,+d -show-encoding < %s \
-# RUN:   | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv32 -mattr=+c,+d -show-encoding \
-# RUN:   -M no-aliases < %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc -triple riscv32 -mattr=+c,+d -filetype=obj < %s \
-# RUN:   | llvm-objdump --no-print-imm-hex --triple=riscv32 --mattr=+c,+d -d - \
-# RUN:   | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv32 -mattr=+c,+d -filetype=obj < %s \
-# RUN:   | llvm-objdump --no-print-imm-hex --triple=riscv32 --mattr=+c,+d -d -M no-aliases - \
-# RUN:   | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
 # RUN: llvm-mc -triple riscv32 -mattr=+zcd,+d -show-encoding < %s \
 # RUN:   | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
 # RUN: llvm-mc -triple riscv32 -mattr=+zcd,+d -show-encoding \
@@ -19,16 +9,6 @@
 # RUN:   | llvm-objdump --no-print-imm-hex --triple=riscv32 --mattr=+zcd,+d -d -M no-aliases - \
 # RUN:   | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
 
-# RUN: llvm-mc -triple riscv64 -mattr=+c,+d -show-encoding < %s \
-# RUN:   | FileCheck -check-prefixes=CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv64 -mattr=+c,+d -show-encoding \
-# RUN:   -M no-aliases < %s | FileCheck -check-prefixes=CHECK-INST %s
-# RUN: llvm-mc -triple riscv64 -mattr=+c,+d -filetype=obj < %s \
-# RUN:   | llvm-objdump --no-print-imm-hex --triple=riscv64 --mattr=+c,+d -d - \
-# RUN:   | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv64 -mattr=+c,+d -filetype=obj < %s \
-# RUN:   | llvm-objdump --no-print-imm-hex --triple=riscv64 --mattr=+c,+d -d -M no-aliases - \
-# RUN:   | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
 # RUN: llvm-mc -triple riscv64 -mattr=+zcd,+d -show-encoding < %s \
 # RUN:   | FileCheck -check-prefixes=CHECK-ALIAS %s
 # RUN: llvm-mc -triple riscv64 -mattr=+zcd,+d -show-encoding \
diff --git a/llvm/test/MC/RISCV/compress-rv32f.s b/llvm/test/MC/RISCV/compress-rv32f.s
index 5fc3f41fdf0a5..6ab8e95cc3f26 100644
--- a/llvm/test/MC/RISCV/compress-rv32f.s
+++ b/llvm/test/MC/RISCV/compress-rv32f.s
@@ -1,13 +1,3 @@
-# RUN: llvm-mc -triple riscv32 -mattr=+c,+f -show-encoding < %s \
-# RUN:   | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv32 -mattr=+c,+f -show-encoding \
-# RUN:   -M no-aliases < %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc -triple riscv32 -mattr=+c,+f -filetype=obj < %s \
-# RUN:   | llvm-objdump  --triple=riscv32 --mattr=+c,+f --no-print-imm-hex -d - \
-# RUN:   | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv32 -mattr=+c,+f -filetype=obj < %s \
-# RUN:   | llvm-objdump  --triple=riscv32 --mattr=+c,+f --no-print-imm-hex -d -M no-aliases - \
-# RUN:   | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
 # RUN: llvm-mc -triple riscv32 -mattr=+zcf,+f -show-encoding < %s \
 # RUN:   | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
 # RUN: llvm-mc -triple riscv32 -mattr=+zcf,+f -show-encoding \
diff --git a/llvm/test/MC/RISCV/option-arch.s b/llvm/test/MC/RISCV/option-arch.s
index 0367ef317e71a..79ba0fe70c6dd 100644
--- a/llvm/test/MC/RISCV/option-arch.s
+++ b/llvm/test/MC/RISCV/option-arch.s
@@ -1,7 +1,7 @@
 # RUN: llvm-mc -triple riscv32 -mattr=+experimental -show-encoding < %s \
 # RUN:   | FileCheck -check-prefixes=CHECK %s
 # RUN: llvm-mc -triple riscv32 -mattr=+experimental -filetype=obj < %s \
-# RUN:   | llvm-objdump  --triple=riscv32 --mattr=+c,+m,+a,+f,+zba,+experimental-zicfiss -d -M no-aliases - \
+# RUN:   | llvm-objdump  --triple=riscv32 --mattr=+c,+m,+a,+f,+zba,+experimental-zicfiss,+zcf -d -M no-aliases - \
 # RUN:   | FileCheck -check-prefixes=CHECK-INST %s
 
 # Test '.option arch, +' and '.option arch, -' directive
@@ -127,7 +127,7 @@ addi a0, a1, 0
 # CHECK: .option arch, +zve32x
 
 .option arch, rv32i
-.option arch, +zce, +f
+.option arch, +zce, +f, +zcf
 # CHECK-INST: flw fa0, 0x0(a0)
 # CHECK: # encoding: [0x08,0x61]
 c.flw fa0, 0(a0)
diff --git a/llvm/test/MC/RISCV/rv32dc-invalid.s b/llvm/test/MC/RISCV/rv32dc-invalid.s
index 70fb504b1bb9b..e89d0054d96e9 100644
--- a/llvm/test/MC/RISCV/rv32dc-invalid.s
+++ b/llvm/test/MC/RISCV/rv32dc-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple=riscv32 -mattr=+c,+d < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple=riscv32 -mattr=+zcd < %s 2>&1 | FileCheck %s
 
 ## FPRC
 c.fld  ft3, 8(a5) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv32dc-valid.s b/llvm/test/MC/RISCV/rv32dc-valid.s
index 495c88448a183..7c9c615a59268 100644
--- a/llvm/test/MC/RISCV/rv32dc-valid.s
+++ b/llvm/test/MC/RISCV/rv32dc-valid.s
@@ -1,38 +1,26 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+d -M no-aliases -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+c,+d < %s \
-# RUN:     | llvm-objdump --no-print-imm-hex --mattr=+c,+d -M no-aliases -d -r - \
-# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+zcd,+d -M no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zcd,+d < %s \
 # RUN:     | llvm-objdump --no-print-imm-hex --mattr=+zcd,+d -M no-aliases -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 #
-# RUN: not llvm-mc -triple riscv32 -mattr=+c \
-# RUN:     -M no-aliases -show-encoding < %s 2>&1 \
-# RUN:     | FileCheck -check-prefixes=CHECK-NO-EXT-D %s
 # RUN: not llvm-mc -triple riscv32 -M no-aliases -show-encoding < %s 2>&1 \
 # RUN:     | FileCheck -check-prefixes=CHECK-NO-EXT-DC %s
 
 # CHECK-ASM-AND-OBJ: c.fldsp  fs0, 504(sp)
 # CHECK-ASM: encoding: [0x7e,0x34]
-# CHECK-NO-EXT-D:  error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
-# CHECK-NO-EXT-DC:  error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}}
+# CHECK-NO-EXT-DC:  error: instruction requires the following: 'D' (Double-Precision Floating-Point), 'Zcd' (Compressed Double-Precision Floating-Point Instructions){{$}}
 c.fldsp  fs0, 504(sp)
 # CHECK-ASM-AND-OBJ: c.fsdsp  fa7, 504(sp)
 # CHECK-ASM: encoding: [0xc6,0xbf]
-# CHECK-NO-EXT-D:  error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
-# CHECK-NO-EXT-DC:  error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}}
+# CHECK-NO-EXT-DC:  error: instruction requires the following: 'D' (Double-Precision Floating-Point), 'Zcd' (Compressed Double-Precision Floating-Point Instructions){{$}}
 c.fsdsp  fa7, 504(sp)
 
 # CHECK-ASM-AND-OBJ: c.fld  fa3, 248(a5)
 # CHECK-ASM: encoding: [0xf4,0x3f]
-# CHECK-NO-EXT-D:  error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
-# CHECK-NO-EXT-DC:  error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}}
+# CHECK-NO-EXT-DC:  error: instruction requires the following: 'D' (Double-Precision Floating-Point), 'Zcd' (Compressed Double-Precision Floating-Point Instructions){{$}}
 c.fld  fa3, 248(a5)
 # CHECK-ASM-AND-OBJ: c.fsd  fa2, 248(a1)
 # CHECK-ASM: encoding: [0xf0,0xbd]
-# CHECK-NO-EXT-D:  error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
-# CHECK-NO-EXT-DC:  error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}}
+# CHECK-NO-EXT-DC:  error: instruction requires the following: 'D' (Double-Precision Floating-Point), 'Zcd' (Compressed Double-Precision Floating-Point Instructions){{$}}
 c.fsd  fa2, 248(a1)
diff --git a/llvm/test/MC/RISCV/rv32fc-aliases-valid.s b/llvm/test/MC/RISCV/rv32fc-aliases-valid.s
index f1a1c739677fc..ff88aa818838a 100644
--- a/llvm/test/MC/RISCV/rv32fc-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rv32fc-aliases-valid.s
@@ -1,7 +1,7 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+f -M no-aliases \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zcf -M no-aliases \
 # RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+f < %s \
-# RUN:     | llvm-objdump --mattr=+c,+f --no-print-imm-hex -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zcf < %s \
+# RUN:     | llvm-objdump --mattr=+zcf --no-print-imm-hex -M no-aliases -d - \
 # RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
 
 # CHECK-EXPAND: c.flw fs0, 0(s1)
diff --git a/llvm/test/MC/RISCV/rv32fc-invalid.s b/llvm/test/MC/RISCV/rv32fc-invalid.s
index 5af3df17671fd..834bc5d4b092f 100644
--- a/llvm/test/MC/RISCV/rv32fc-invalid.s
+++ b/llvm/test/MC/RISCV/rv32fc-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple=riscv32 -mattr=+c,+f < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple=riscv32 -mattr=+zcf < %s 2>&1 | FileCheck %s
 
 ## FPRC
 c.flw  ft3, 8(a5) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv32fc-valid.s b/llvm/test/MC/RISCV/rv32fc-valid.s
index af38a636cf804..bc35e3bcb40eb 100644
--- a/llvm/test/MC/RISCV/rv32fc-valid.s
+++ b/llvm/test/MC/RISCV/rv32fc-valid.s
@@ -1,17 +1,9 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+f -M no-aliases -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+c,+f < %s \
-# RUN:     | llvm-objdump --mattr=+c,+f --no-print-imm-hex -M no-aliases -d -r - \
-# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+zcf,+f -M no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zcf,+f < %s \
 # RUN:     | llvm-objdump --mattr=+zcf,+f --no-print-imm-hex -M no-aliases -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 #
-# RUN: not llvm-mc -triple riscv32 -mattr=+c \
-# RUN:     -M no-aliases -show-encoding < %s 2>&1 \
-# RUN:     | FileCheck -check-prefixes=CHECK-NO-EXT-F %s
 # RUN: not llvm-mc -triple riscv32 \
 # RUN:     -M no-aliases -show-encoding < %s 2>&1 \
 # RUN:     | FileCheck -check-prefixes=CHECK-NO-EXT-FC %s
@@ -23,26 +15,22 @@
 
 # CHECK-ASM-AND-OBJ: c.flwsp  fs0, 252(sp)
 # CHECK-ASM: encoding: [0x7e,0x74]
-# CHECK-NO-EXT-F:  error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}}
-# CHECK-NO-EXT-FC:  error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcf' (Compressed Single-Precision Floating-Point Instructions), 'F' (Single-Precision Floating-Point){{$}}
-# CHECK-NO-RV32:  error: instruction requires the following: RV32I Base Instruction Set{{$}}
+# CHECK-NO-EXT-FC:  error: instruction requires the following: 'F' (Single-Precision Floating-Point), 'Zcf' (Compressed Single-Precision Floating-Point Instructions){{$}}
+# CHECK-NO-RV32:  error: instruction requires the following: 'Zcf' (Compressed Single-Precision Floating-Point Instructions), RV32I Base Instruction Set{{$}}
 c.flwsp  fs0, 252(sp)
 # CHECK-ASM-AND-OBJ: c.fswsp  fa7, 252(sp)
 # CHECK-ASM: encoding: [0xc6,0xff]
-# CHECK-NO-EXT-F:  error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}}
-# CHECK-NO-EXT-FC:  error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcf' (Compressed Single-Precision Floating-Point Instructions), 'F' (Single-Precision Floating-Point){{$}}
-# CHECK-NO-RV32:  error: instruction requires the following: RV32I Base Instruction Set{{$}}
+# CHECK-NO-EXT-FC:  error: instruction requires the following: 'F' (Single-Precision Floating-Point), 'Zcf' (Compressed Single-Precision Floating-Point Instructions){{$}}
+# CHECK-NO-RV32:  error: instruction requires the following: 'Zcf' (Compressed Single-Precision Floating-Point Instructions), RV32I Base Instruction Set{{$}}
 c.fswsp  fa7, 252(sp)
 
 # CHECK-ASM-AND-OBJ: c.flw  fa3, 124(a5)
 # CHECK-ASM: encoding: [0xf4,0x7f]
-# CHECK-NO-EXT-F:  error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}}
-# CHECK-NO-EXT-FC:  error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcf' (Compressed Single-Precision Floating-Point Instructions), 'F' (Single-Precision Floating-Point){{$}}
-# CHECK-NO-RV32:  error: instruction requires the following: RV32I Base Instruction Set{{$}}
+# CHECK-NO-EXT-FC:  error: instruction requires the following: 'F' (Single-Precision Floating-Point), 'Zcf' (Compressed Single-Precision Floating-Point Instructions){{$}}
+# CHECK-NO-RV32:  error: instruction requires the following: 'Zcf' (Compressed Single-Precision Floating-Point Instructions), RV32I Base Instruction Set{{$}}
 c.flw  fa3, 124(a5)
 # CHECK-ASM-AND-OBJ: c.fsw  fa2, 124(a1)
 # CHECK-ASM: encoding: [0xf0,0xfd]
-# CHECK-NO-EXT-F:  error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}}
-# CHECK-NO-EXT-FC:  error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcf' (Compressed Single-Precision Floating-Point Instructions), 'F' (Single-Precision Floating-Point){{$}}
-# CHECK-NO-RV32:  error: instruction requires the following: RV32I Base Instruction Set{{$}}
+# CHECK-NO-EXT-FC:  error: instruction requires the following: 'F' (Single-Precision Floating-Point), 'Zcf' (Compressed Single-Precision Floating-Point Instructions){{$}}
+# CHECK-NO-RV32:  error: instruction requires the following: 'Zcf' (Compressed Single-Precision Floating-Point Instructions), RV32I Base Instruction Set{{$}}
 c.fsw  fa2, 124(a1)
diff --git a/llvm/test/MC/RISCV/rv64dc-valid.s b/llvm/test/MC/RISCV/rv64dc-valid.s
index 7f2b8c46b7bb6..cf9aef88d817f 100644
--- a/llvm/test/MC/RISCV/rv64dc-valid.s
+++ b/llvm/test/MC/RISCV/rv64dc-valid.s
@@ -1,38 +1,26 @@
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+c,+d -M no-aliases -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+d < %s \
-# RUN:     | llvm-objdump --no-print-imm-hex --mattr=+c,+d -M no-aliases -d -r - \
-# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+zcd,+d -M no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zcd,+d < %s \
 # RUN:     | llvm-objdump --no-print-imm-hex --mattr=+zcd,+d -M no-aliases -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 #
-# RUN: not llvm-mc -triple riscv64 -mattr=+c \
-# RUN:     -M no-aliases -show-encoding < %s 2>&1 \
-# RUN:     | FileCheck -check-prefixes=CHECK-NO-EXT-D %s
 # RUN: not llvm-mc -triple riscv64 -M no-aliases -show-encoding < %s 2>&1 \
 # RUN:     | FileCheck -check-prefixes=CHECK-NO-EXT-DC %s
 
 # CHECK-ASM-AND-OBJ: c.fldsp  fs0, 504(sp)
 # CHECK-ASM: encoding: [0x7e,0x34]
-# CHECK-NO-EXT-D:  error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
-# CHECK-NO-EXT-DC:  error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}}
+# CHECK-NO-EXT-DC:  error: instruction requires the following: 'D' (Double-Precision Floating-Point), 'Zcd' (Compressed Double-Precision Floating-Point Instructions){{$}}
 c.fldsp  fs0, 504(sp)
 # CHECK-ASM-AND-OBJ: c.fsdsp  fa7, 504(sp)
 # CHECK-ASM: encoding: [0xc6,0xbf]
-# CHECK-NO-EXT-D:  error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
-# CHECK-NO-EXT-DC:  error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}}
+# CHECK-NO-EXT-DC:  error: instruction requires the following: 'D' (Double-Precision Floating-Point), 'Zcd' (Compressed Double-Precision Floating-Point Instructions){{$}}
 c.fsdsp  fa7, 504(sp)
 
 # CHECK-ASM-AND-OBJ: c.fld  fa3, 248(a5)
 # CHECK-ASM: encoding: [0xf4,0x3f]
-# CHECK-NO-EXT-D:  error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
-# CHECK-NO-EXT-DC:  error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}}
+# CHECK-NO-EXT-DC:  error: instruction requires the following: 'D' (Double-Precision Floating-Point), 'Zcd' (Compressed Double-Precision Floating-Point Instructions){{$}}
 c.fld  fa3, 248(a5)
 # CHECK-ASM-AND-OBJ: c.fsd  fa2, 248(a1)
 # CHECK-ASM: encoding: [0xf0,0xbd]
-# CHECK-NO-EXT-D:  error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
-# CHECK-NO-EXT-DC:  error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}}
+# CHECK-NO-EXT-DC:  error: instruction requires the following: 'D' (Double-Precision Floating-Point), 'Zcd' (Compressed Double-Precision Floating-Point Instructions){{$}}
 c.fsd  fa2, 248(a1)
diff --git a/llvm/test/MC/RISCV/rvdc-aliases-valid.s b/llvm/test/MC/RISCV/rvdc-aliases-valid.s
index 083c4d2babedd..5cd47ea1539bd 100644
--- a/llvm/test/MC/RISCV/rvdc-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rvdc-aliases-valid.s
@@ -1,12 +1,12 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+d -M no-aliases \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zcd -M no-aliases \
 # RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+c,+d -M no-aliases \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zcd -M no-aliases \
 # RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+d < %s \
-# RUN:     | llvm-objdump --mattr=+c,+d --no-print-imm-hex -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zcd < %s \
+# RUN:     | llvm-objdump --mattr=+zcd --no-print-imm-hex -M no-aliases -d - \
 # RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c,+d < %s \
-# RUN:     | llvm-objdump --mattr=+c,+d --no-print-imm-hex -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zcd < %s \
+# RUN:     | llvm-objdump --mattr=+zcd --no-print-imm-hex -M no-aliases -d - \
 # RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
 
 c.fld f8, (x9)
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 9cee4ff776da9..06f874abfca3b 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -928,12 +928,6 @@ TEST(ParseArchString, ZceImplication) {
   EXPECT_EQ(ExtsRV64IFZce.count("zcmp"), 1U);
   EXPECT_EQ(ExtsRV64IFZce.count("zcmt"), 1U);
 
-  EXPECT_EQ(ExtsRV64IFZce.count("zca"), 1U);
-  EXPECT_EQ(ExtsRV64IFZce.count("zcb"), 1U);
-  EXPECT_EQ(ExtsRV64IFZce.count("zce"), 1U);
-  EXPECT_EQ(ExtsRV64IFZce.count("zcmp"), 1U);
-  EXPECT_EQ(ExtsRV64IFZce.count("zcmt"), 1U);
-
   auto MaybeRV64IDZce = RISCVISAInfo::parseArchString("rv64idzce", true);
   ASSERT_THAT_EXPECTED(MaybeRV64IDZce, Succeeded());
   const auto &ExtsRV64IDZce = (*MaybeRV64IDZce)->getExtensions();
@@ -949,6 +943,70 @@ TEST(ParseArchString, ZceImplication) {
   EXPECT_EQ(ExtsRV64IDZce.count("zcmt"), 1U);
 }
 
+TEST(ParseArchString, CImplication) {
+  auto MaybeRV32IC = RISCVISAInfo::parseArchString("rv32ic", true);
+  ASSERT_THAT_EXPECTED(MaybeRV32IC, Succeeded());
+  const auto &ExtsRV32IC = (*MaybeRV32IC)->getExtensions();
+  EXPECT_EQ(ExtsRV32IC.size(), 3UL);
+  EXPECT_EQ(ExtsRV32IC.count("i"), 1U);
+  EXPECT_EQ(ExtsRV32IC.count("c"), 1U);
+  EXPECT_EQ(ExtsRV32IC.count("zca"), 1U);
+
+  auto MaybeRV32ICF = RISCVISAInfo::parseArchString("rv32icf", true);
+  ASSERT_THAT_EXPECTED(MaybeRV32ICF, Succeeded());
+  const auto &ExtsRV32ICF = (*MaybeRV32ICF)->getExtensions();
+  EXPECT_EQ(ExtsRV32ICF.size(), 6UL);
+  EXPECT_EQ(ExtsRV32ICF.count("i"), 1U);
+  EXPECT_EQ(ExtsRV32ICF.count("zicsr"), 1U);
+  EXPECT_EQ(ExtsRV32ICF.count("c"), 1U);
+  EXPECT_EQ(ExtsRV32ICF.count("f"), 1U);
+  EXPECT_EQ(ExtsRV32ICF.count("zca"), 1U);
+  EXPECT_EQ(ExtsRV32ICF.count("zcf"), 1U);
+
+  auto MaybeRV32ICD = RISCVISAInfo::parseArchString("rv32icd", true);
+  ASSERT_THAT_EXPECTED(MaybeRV32ICD, Succeeded());
+  const auto &ExtsRV32ICD = (*MaybeRV32ICD)->getExtensions();
+  EXPECT_EQ(ExtsRV32ICD.size(), 8UL);
+  EXPECT_EQ(ExtsRV32ICD.count("i"), 1U);
+  EXPECT_EQ(ExtsRV32ICD.count("zicsr"), 1U);
+  EXPECT_EQ(ExtsRV32ICD.count("c"), 1U);
+  EXPECT_EQ(ExtsRV32ICD.count("d"), 1U);
+  EXPECT_EQ(ExtsRV32ICD.count("f"), 1U);
+  EXPECT_EQ(ExtsRV32ICD.count("zca"), 1U);
+  EXPECT_EQ(ExtsRV32ICD.count("zcd"), 1U);
+  EXPECT_EQ(ExtsRV32ICD.count("zcf"), 1U);
+
+  auto MaybeRV64IC = RISCVISAInfo::parseArchString("rv64ic", true);
+  ASSERT_THAT_EXPECTED(MaybeRV64IC, Succeeded());
+  const auto &ExtsRV64IC = (*MaybeRV64IC)->getExtensions();
+  EXPECT_EQ(ExtsRV64IC.size(), 3UL);
+  EXPECT_EQ(ExtsRV64IC.count("i"), 1U);
+  EXPECT_EQ(ExtsRV64IC.count("c"), 1U);
+  EXPECT_EQ(ExtsRV64IC.count("zca"), 1U);
+
+  auto MaybeRV64ICF = RISCVISAInfo::parseArchString("rv64icf", true);
+  ASSERT_THAT_EXPECTED(MaybeRV64ICF, Succeeded());
+  const auto &ExtsRV64ICF = (*MaybeRV64ICF)->getExtensions();
+  EXPECT_EQ(ExtsRV64ICF.size(), 5UL);
+  EXPECT_EQ(ExtsRV64ICF.count("i"), 1U);
+  EXPECT_EQ(ExtsRV64ICF.count("zicsr"), 1U);
+  EXPECT_EQ(ExtsRV64ICF.count("c"), 1U);
+  EXPECT_EQ(ExtsRV64ICF.count("f"), 1U);
+  EXPECT_EQ(ExtsRV64ICF.count("zca"), 1U);
+
+  auto MaybeRV64ICD = RISCVISAInfo::parseArchString("rv64icd", true);
+  ASSERT_THAT_EXPECTED(MaybeRV64ICD, Succeeded());
+  const auto &ExtsRV64ICD = (*MaybeRV64ICD)->getExtensions();
+  EXPECT_EQ(ExtsRV64ICD.size(), 7UL);
+  EXPECT_EQ(ExtsRV64ICD.count("i"), 1U);
+  EXPECT_EQ(ExtsRV64ICD.count("zicsr"), 1U);
+  EXPECT_EQ(ExtsRV64ICD.count("c"), 1U);
+  EXPECT_EQ(ExtsRV64ICD.count("d"), 1U);
+  EXPECT_EQ(ExtsRV64ICD.count("f"), 1U);
+  EXPECT_EQ(ExtsRV64ICD.count("zca"), 1U);
+  EXPECT_EQ(ExtsRV64ICD.count("zcd"), 1U);
+}
+
 TEST(isSupportedExtensionWithVersion, AcceptsSingleExtensionWithVersion) {
   EXPECT_TRUE(RISCVISAInfo::isSupportedExtensionWithVersion("zbb1p0"));
   EXPECT_FALSE(RISCVISAInfo::isSupportedExtensionWithVersion("zbb"));