From b944890a78cd8716862f92a4b86aa6e653f90373 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp@bytedance.com>
Date: Thu, 21 Sep 2023 21:16:21 +0800
Subject: [PATCH 1/3] [RISCV][NFC] Remove rdty arg of PseudoLoad and the
 default rdty value of PseudoFloatLoad

`rdty` of `PseudoLoad` is always `GPR` and it will never be `GPR` for
`PseudoFloatLoad`.

And `PseudoLoad` is renamed to `PseudoIntLoad` to be symmetric.
---
 llvm/lib/Target/RISCV/RISCVInstrFormats.td |  6 +++---
 llvm/lib/Target/RISCV/RISCVInstrInfo.td    | 14 +++++++-------
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index f19a0b356aafb..0cab8d4c9843b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -241,8 +241,8 @@ class PseudoQuietFCMP<DAGOperand Ty>
 }
 
 // Pseudo load instructions.
-class PseudoLoad<string opcodestr, RegisterClass rdty = GPR>
-    : Pseudo<(outs rdty:$rd), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr"> {
+class PseudoIntLoad<string opcodestr>
+    : Pseudo<(outs GPR:$rd), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr"> {
   let hasSideEffects = 0;
   let mayLoad = 1;
   let mayStore = 0;
@@ -250,7 +250,7 @@ class PseudoLoad<string opcodestr, RegisterClass rdty = GPR>
   let isAsmParserOnly = 1;
 }
 
-class PseudoFloatLoad<string opcodestr, RegisterClass rdty = GPR>
+class PseudoFloatLoad<string opcodestr, RegisterClass rdty>
     : Pseudo<(outs GPR:$tmp, rdty:$rd), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr, $tmp"> {
   let hasSideEffects = 0;
   let mayLoad = 1;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index abbeff78b6e28..0bf3ca1df758d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -920,19 +920,19 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 32,
 def PseudoLI : Pseudo<(outs GPR:$rd), (ins ixlenimm_li:$imm), [],
                       "li", "$rd, $imm">;
 
-def PseudoLB  : PseudoLoad<"lb">;
-def PseudoLBU : PseudoLoad<"lbu">;
-def PseudoLH  : PseudoLoad<"lh">;
-def PseudoLHU : PseudoLoad<"lhu">;
-def PseudoLW  : PseudoLoad<"lw">;
+def PseudoLB  : PseudoIntLoad<"lb">;
+def PseudoLBU : PseudoIntLoad<"lbu">;
+def PseudoLH  : PseudoIntLoad<"lh">;
+def PseudoLHU : PseudoIntLoad<"lhu">;
+def PseudoLW  : PseudoIntLoad<"lw">;
 
 def PseudoSB  : PseudoStore<"sb">;
 def PseudoSH  : PseudoStore<"sh">;
 def PseudoSW  : PseudoStore<"sw">;
 
 let Predicates = [IsRV64] in {
-def PseudoLWU : PseudoLoad<"lwu">;
-def PseudoLD  : PseudoLoad<"ld">;
+def PseudoLWU : PseudoIntLoad<"lwu">;
+def PseudoLD  : PseudoIntLoad<"ld">;
 def PseudoSD  : PseudoStore<"sd">;
 } // Predicates = [IsRV64]
 

From 81aa9e9fb76b5214ab52031ce408db27943a9885 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <137158460+wangpc-pp@users.noreply.github.com>
Date: Thu, 21 Sep 2023 23:37:37 +0800
Subject: [PATCH 2/3] Update RISCVInstrFormats.td

---
 llvm/lib/Target/RISCV/RISCVInstrFormats.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index 0cab8d4c9843b..e80ba26800a13 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -241,7 +241,7 @@ class PseudoQuietFCMP<DAGOperand Ty>
 }
 
 // Pseudo load instructions.
-class PseudoIntLoad<string opcodestr>
+class PseudoLoad<string opcodestr>
     : Pseudo<(outs GPR:$rd), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr"> {
   let hasSideEffects = 0;
   let mayLoad = 1;

From 7933a3281cdd26d004dcc2efdc2fc02e44211600 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <137158460+wangpc-pp@users.noreply.github.com>
Date: Thu, 21 Sep 2023 23:38:57 +0800
Subject: [PATCH 3/3] Update RISCVInstrInfo.td

---
 llvm/lib/Target/RISCV/RISCVInstrInfo.td | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 0bf3ca1df758d..abbeff78b6e28 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -920,19 +920,19 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 32,
 def PseudoLI : Pseudo<(outs GPR:$rd), (ins ixlenimm_li:$imm), [],
                       "li", "$rd, $imm">;
 
-def PseudoLB  : PseudoIntLoad<"lb">;
-def PseudoLBU : PseudoIntLoad<"lbu">;
-def PseudoLH  : PseudoIntLoad<"lh">;
-def PseudoLHU : PseudoIntLoad<"lhu">;
-def PseudoLW  : PseudoIntLoad<"lw">;
+def PseudoLB  : PseudoLoad<"lb">;
+def PseudoLBU : PseudoLoad<"lbu">;
+def PseudoLH  : PseudoLoad<"lh">;
+def PseudoLHU : PseudoLoad<"lhu">;
+def PseudoLW  : PseudoLoad<"lw">;
 
 def PseudoSB  : PseudoStore<"sb">;
 def PseudoSH  : PseudoStore<"sh">;
 def PseudoSW  : PseudoStore<"sw">;
 
 let Predicates = [IsRV64] in {
-def PseudoLWU : PseudoIntLoad<"lwu">;
-def PseudoLD  : PseudoIntLoad<"ld">;
+def PseudoLWU : PseudoLoad<"lwu">;
+def PseudoLD  : PseudoLoad<"ld">;
 def PseudoSD  : PseudoStore<"sd">;
 } // Predicates = [IsRV64]