From b15f8d99cf0a44d5e8d3f6af7ebcedd23a0bbd32 Mon Sep 17 00:00:00 2001 From: Min Hsu Date: Wed, 10 Jan 2024 09:23:48 -0800 Subject: [PATCH] [RISCV][AMDGPU] Mark test/CodeGen/Generic/live-debug-label.ll XFAIL for RISCV and AMDGPU Both RISC-V and AMDGPU(GCN) deploy two VirtRegRewriter in their codegen pipeline. This test prematurely stops at the first one, which doesn't cleanup the virtual register map and cause an assertion failure. Ideally we can solve this by teaching `-stop-after` how to stop at the last instance of a Pass, but we're just marking XFAIL for these two targets for now. --- llvm/test/CodeGen/Generic/live-debug-label.ll | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/llvm/test/CodeGen/Generic/live-debug-label.ll b/llvm/test/CodeGen/Generic/live-debug-label.ll index 5022e1f187d19..3121b8700ed11 100644 --- a/llvm/test/CodeGen/Generic/live-debug-label.ll +++ b/llvm/test/CodeGen/Generic/live-debug-label.ll @@ -2,6 +2,13 @@ ; ; NVPTX produces a different order of the BBs ; XFAIL: target=nvptx{{.*}} +; Both RISC-V and AMDGPU(GCN) deploy two VirtRegRewriter in their codegen +; pipeline. This test prematurely stops at the first one, which doesn't cleanup +; the virtual register map and cause an assertion failure. Ideally we can solve +; this by teaching `-stop-after` how to stop at the last instance of a Pass, +; but we're just marking XFAIL for these two targets for now. +; XFAIL: target=riscv{{.*}} +; XFAIL: target=amdgcn-{{.*}} ; Generated with "clang++ -g -O1 -S -emit-llvm" ;