diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index ab055b723dbb1..56e9090ebfbea 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -4652,8 +4652,16 @@ bool CombinerHelper::matchReassocFoldConstantsInSubTree(GPtrAdd &MI,
   if (!C2)
     return false;
 
+  // Pick correct size for the constant based on the address space
+  const DataLayout &DL = MI.getMF()->getDataLayout();
+  Register Dst = MI.getOperand(0).getReg();
+  unsigned AS = MRI.getType(Dst).getAddressSpace();
+  unsigned NewSize = DL.getIndexSize(AS) * 8;
+  APInt ConstVal = C1->sextOrTrunc(NewSize) + C2->sextOrTrunc(NewSize);
+  LLT ConstType = MRI.getType(Src2Reg).changeElementSize(NewSize);
+
   MatchInfo = [=, &MI](MachineIRBuilder &B) {
-    auto NewCst = B.buildConstant(MRI.getType(Src2Reg), *C1 + *C2);
+    auto NewCst = B.buildConstant(ConstType, ConstVal);
     Observer.changingInstr(MI);
     MI.getOperand(1).setReg(LHSSrc1);
     MI.getOperand(2).setReg(NewCst.getReg(0));
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ptradd-reassociation.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ptradd-reassociation.mir
new file mode 100644
index 0000000000000..7920f65eedebb
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ptradd-reassociation.mir
@@ -0,0 +1,49 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name:            test_different_sizes_64_32
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+
+    ; CHECK-LABEL: name: test_different_sizes_64_32
+    ; CHECK: liveins: $sgpr0_sgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $sgpr0_sgpr1
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[COPY]](s64)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
+    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[INTTOPTR]], [[C]](s64)
+    ; CHECK-NEXT: SI_RETURN implicit [[PTR_ADD]](p1)
+    %0:_(s64) = COPY $sgpr0_sgpr1
+    %1:_(s64) = G_CONSTANT i64 8
+    %2:_(s32) = G_CONSTANT i32 4
+    %3:_(p1) = G_INTTOPTR %0(s64)
+    %4:_(p1) = G_PTR_ADD %3, %1(s64)
+    %5:_(p1) = G_PTR_ADD %4, %2(s32)
+    SI_RETURN implicit %5(p1)
+...
+---
+name:            test_different_sizes_32_64
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+
+    ; CHECK-LABEL: name: test_different_sizes_32_64
+    ; CHECK: liveins: $sgpr0_sgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $sgpr0_sgpr1
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[COPY]](s64)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
+    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[INTTOPTR]], [[C]](s64)
+    ; CHECK-NEXT: SI_RETURN implicit [[PTR_ADD]](p1)
+    %0:_(s64) = COPY $sgpr0_sgpr1
+    %1:_(s64) = G_CONSTANT i64 8
+    %2:_(s32) = G_CONSTANT i32 4
+    %3:_(p1) = G_INTTOPTR %0(s64)
+    %4:_(p1) = G_PTR_ADD %3, %2(s32)
+    %5:_(p1) = G_PTR_ADD %4, %1(s64)
+    SI_RETURN implicit %5(p1)
+...