From b03591387ea112c8853e932d407b1f3b04c958bb Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Fri, 29 Mar 2024 22:34:33 +0800 Subject: [PATCH 1/2] [InstSimplify] Add pre-commit tests. NFC. --- llvm/test/Transforms/InstSimplify/pr87042.ll | 39 ++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 llvm/test/Transforms/InstSimplify/pr87042.ll diff --git a/llvm/test/Transforms/InstSimplify/pr87042.ll b/llvm/test/Transforms/InstSimplify/pr87042.ll new file mode 100644 index 0000000000000..d73a8b9d85d61 --- /dev/null +++ b/llvm/test/Transforms/InstSimplify/pr87042.ll @@ -0,0 +1,39 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt < %s -passes=instsimplify -S | FileCheck %s + +; %or2 cannot be folded into %or1 because %or1 has disjoint. +; TODO: Can we move the logic into InstCombine and drop the disjoint flag? +define i64 @test(i1 %cond, i64 %x) { +; CHECK-LABEL: define i64 @test( +; CHECK-SAME: i1 [[COND:%.*]], i64 [[X:%.*]]) { +; CHECK-NEXT: [[OR1:%.*]] = or disjoint i64 [[X]], 7 +; CHECK-NEXT: ret i64 [[OR1]] +; + %or1 = or disjoint i64 %x, 7 + %sel1 = select i1 %cond, i64 %or1, i64 %x + %or2 = or i64 %sel1, 7 + ret i64 %or2 +} + +define i64 @pr87042(i64 %x) { +; CHECK-LABEL: define i64 @pr87042( +; CHECK-SAME: i64 [[X:%.*]]) { +; CHECK-NEXT: [[AND1:%.*]] = and i64 [[X]], 65535 +; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i64 [[AND1]], 0 +; CHECK-NEXT: [[OR1:%.*]] = or disjoint i64 [[X]], 7 +; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[CMP1]], i64 [[OR1]], i64 [[X]] +; CHECK-NEXT: [[AND2:%.*]] = and i64 [[SEL1]], 16776960 +; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i64 [[AND2]], 0 +; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[CMP2]], i64 [[OR1]], i64 [[SEL1]] +; CHECK-NEXT: ret i64 [[SEL2]] +; + %and1 = and i64 %x, 65535 + %cmp1 = icmp eq i64 %and1, 0 + %or1 = or disjoint i64 %x, 7 + %sel1 = select i1 %cmp1, i64 %or1, i64 %x + %and2 = and i64 %sel1, 16776960 + %cmp2 = icmp eq i64 %and2, 0 + %or2 = or i64 %sel1, 7 + %sel2 = select i1 %cmp2, i64 %or2, i64 %sel1 + ret i64 %sel2 +} From 4ca1c82ae6eda79b408c1f1b4368a4011fdb4259 Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Fri, 29 Mar 2024 22:55:32 +0800 Subject: [PATCH 2/2] [InstSimplify] Make sure the simplified value doesn't generate poison in threadBinOpOverSelect --- llvm/lib/Analysis/InstructionSimplify.cpp | 3 ++- llvm/test/Transforms/InstSimplify/pr87042.ll | 7 +++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp b/llvm/lib/Analysis/InstructionSimplify.cpp index 9ff3faff79902..3c943a09a9c23 100644 --- a/llvm/lib/Analysis/InstructionSimplify.cpp +++ b/llvm/lib/Analysis/InstructionSimplify.cpp @@ -440,7 +440,8 @@ static Value *threadBinOpOverSelect(Instruction::BinaryOps Opcode, Value *LHS, // Check that the simplified value has the form "X op Y" where "op" is the // same as the original operation. Instruction *Simplified = dyn_cast(FV ? FV : TV); - if (Simplified && Simplified->getOpcode() == unsigned(Opcode)) { + if (Simplified && Simplified->getOpcode() == unsigned(Opcode) && + !Simplified->hasPoisonGeneratingFlags()) { // The value that didn't simplify is "UnsimplifiedLHS op UnsimplifiedRHS". // We already know that "op" is the same as for the simplified value. See // if the operands match too. If so, return the simplified value. diff --git a/llvm/test/Transforms/InstSimplify/pr87042.ll b/llvm/test/Transforms/InstSimplify/pr87042.ll index d73a8b9d85d61..800d27c9e6504 100644 --- a/llvm/test/Transforms/InstSimplify/pr87042.ll +++ b/llvm/test/Transforms/InstSimplify/pr87042.ll @@ -7,7 +7,9 @@ define i64 @test(i1 %cond, i64 %x) { ; CHECK-LABEL: define i64 @test( ; CHECK-SAME: i1 [[COND:%.*]], i64 [[X:%.*]]) { ; CHECK-NEXT: [[OR1:%.*]] = or disjoint i64 [[X]], 7 -; CHECK-NEXT: ret i64 [[OR1]] +; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[COND]], i64 [[OR1]], i64 [[X]] +; CHECK-NEXT: [[OR2:%.*]] = or i64 [[SEL1]], 7 +; CHECK-NEXT: ret i64 [[OR2]] ; %or1 = or disjoint i64 %x, 7 %sel1 = select i1 %cond, i64 %or1, i64 %x @@ -24,7 +26,8 @@ define i64 @pr87042(i64 %x) { ; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[CMP1]], i64 [[OR1]], i64 [[X]] ; CHECK-NEXT: [[AND2:%.*]] = and i64 [[SEL1]], 16776960 ; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i64 [[AND2]], 0 -; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[CMP2]], i64 [[OR1]], i64 [[SEL1]] +; CHECK-NEXT: [[OR2:%.*]] = or i64 [[SEL1]], 7 +; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[CMP2]], i64 [[OR2]], i64 [[SEL1]] ; CHECK-NEXT: ret i64 [[SEL2]] ; %and1 = and i64 %x, 65535