diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td index 98ae17ec22a04..cca4367751b92 100644 --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -2601,8 +2601,7 @@ multiclass RVVOutBuiltinSetZvk { if HasVS then { foreach vs2_lmul = ["(SEFixedLog2LMUL:-1)", "(SEFixedLog2LMUL:0)", - "(SEFixedLog2LMUL:1)", "(SEFixedLog2LMUL:2)", - "(SEFixedLog2LMUL:3)"] in { + "(SEFixedLog2LMUL:1)", "(SEFixedLog2LMUL:2)"] in { defvar name = NAME # !if(!eq(NAME, "vaesz"), "", "_vs"); let OverloadedName = name, IRName = NAME # "_vs", Name = NAME # "_vs", IntrinsicTypes = [-1, 1] in diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c index 76a9ddc0d5294..3e37ac4b77499 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesdf_vv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { return __riscv_vaesdf_vv_u32m8(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesdf_vs_u32m8_u32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesdf.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesdf_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesdf_vs_u32m8_u32m8(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c index 468c3f18378d3..c29c1e983fce6 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesdm_vv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { return __riscv_vaesdm_vv_u32m8(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesdm_vs_u32m8_u32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesdm.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesdm_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesdm_vs_u32m8_u32m8(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c index bc6a17e4b6f0f..7ed9f5c36e98d 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesef_vv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { return __riscv_vaesef_vv_u32m8(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesef_vs_u32m8_u32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesef.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesef_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesef_vs_u32m8_u32m8(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c index e0e1662b76f9c..34eec0037491f 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesem_vv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { return __riscv_vaesem_vv_u32m8(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesem_vs_u32m8_u32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesem.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesem_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesem_vs_u32m8_u32m8(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c index 0700b60fa6399..bfe0b0602717f 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c @@ -156,13 +156,3 @@ vuint32m8_t test_vaesz_vs_u32m4_u32m8(vuint32m8_t vd, vuint32m4_t vs2, size_t vl return __riscv_vaesz_vs_u32m4_u32m8(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesz_vs_u32m8_u32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesz.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesz_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesz_vs_u32m8_u32m8(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c index f9d855a72d288..fe9090225596d 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c @@ -206,13 +206,3 @@ vuint32m8_t test_vsm4r_vv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { return __riscv_vsm4r_vv_u32m8(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vsm4r_vs_u32m8_u32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vsm4r.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vsm4r_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vsm4r_vs_u32m8_u32m8(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c index 9c91d2a1192d5..ec3cd1a5a6968 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesdf_vv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { return __riscv_vaesdf_vv(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesdf_vs_u32m8_u32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesdf.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesdf_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesdf_vs(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c index dac9eb38713b4..85d452543db2b 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesdm_vv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { return __riscv_vaesdm_vv(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesdm_vs_u32m8_u32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesdm.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesdm_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesdm_vs(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c index 01875afa525ef..6727ff24b83d3 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesef_vv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { return __riscv_vaesef_vv(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesef_vs_u32m8_u32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesef.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesef_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesef_vs(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c index e9a0add21c92d..6ebfd5ff4962e 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesem_vv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { return __riscv_vaesem_vv(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesem_vs_u32m8_u32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesem.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesem_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesem_vs(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c index c80e4ebce5e5b..fe657a603d7b7 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c @@ -156,13 +156,3 @@ vuint32m8_t test_vaesz_vs_u32m4_u32m8(vuint32m8_t vd, vuint32m4_t vs2, size_t vl return __riscv_vaesz(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesz_vs_u32m8_u32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesz.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesz_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesz(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c index cfc8532835eaa..82f275af3e500 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c @@ -206,13 +206,3 @@ vuint32m8_t test_vsm4r_vv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { return __riscv_vsm4r_vv(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vsm4r_vs_u32m8_u32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vsm4r.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vsm4r_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vsm4r_vs(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c index 8c18e323f7cec..27457c8f3af9b 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesdf_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) return __riscv_vaesdf_vv_u32m8_tu(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesdf_vs_u32m8_u32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesdf.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 2) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesdf_vs_u32m8_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesdf_vs_u32m8_u32m8_tu(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c index 7566be80e9d93..e23194eac3dcb 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesdm_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) return __riscv_vaesdm_vv_u32m8_tu(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesdm_vs_u32m8_u32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesdm.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 2) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesdm_vs_u32m8_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesdm_vs_u32m8_u32m8_tu(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c index ddeed6e78be13..4e99777b57fbc 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesef_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) return __riscv_vaesef_vv_u32m8_tu(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesef_vs_u32m8_u32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesef.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 2) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesef_vs_u32m8_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesef_vs_u32m8_u32m8_tu(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c index 2bd6350798f64..7488792effd42 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesem_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) return __riscv_vaesem_vv_u32m8_tu(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesem_vs_u32m8_u32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesem.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 2) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesem_vs_u32m8_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesem_vs_u32m8_u32m8_tu(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c index 101efd751f86e..08291a2cbca6b 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c @@ -156,13 +156,3 @@ vuint32m8_t test_vaesz_vs_u32m4_u32m8_tu(vuint32m8_t vd, vuint32m4_t vs2, size_t return __riscv_vaesz_vs_u32m4_u32m8_tu(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesz_vs_u32m8_u32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesz.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 2) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesz_vs_u32m8_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesz_vs_u32m8_u32m8_tu(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c index c58f8d22d4601..11faf7f36d23e 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c @@ -206,13 +206,3 @@ vuint32m8_t test_vsm4r_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { return __riscv_vsm4r_vv_u32m8_tu(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vsm4r_vs_u32m8_u32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vsm4r.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 2) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vsm4r_vs_u32m8_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vsm4r_vs_u32m8_u32m8_tu(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdf.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdf.c index 34fd46465c34a..646854e671d79 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdf.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdf.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesdf_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) return __riscv_vaesdf_vv_tu(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesdf_vs_u32m8_u32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesdf.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 2) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesdf_vs_u32m8_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesdf_vs_tu(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdm.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdm.c index 2d0f8e7cafc7e..90668f3f191bd 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdm.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdm.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesdm_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) return __riscv_vaesdm_vv_tu(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesdm_vs_u32m8_u32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesdm.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 2) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesdm_vs_u32m8_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesdm_vs_tu(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c index 26518b9a709fe..8bb3e69233ad3 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesef_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) return __riscv_vaesef_vv_tu(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesef_vs_u32m8_u32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesef.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 2) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesef_vs_u32m8_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesef_vs_tu(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesem.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesem.c index 67e13665eea84..5a83675aa0e6d 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesem.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesem.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesem_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) return __riscv_vaesem_vv_tu(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesem_vs_u32m8_u32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesem.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 2) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesem_vs_u32m8_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesem_vs_tu(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesz.c index 71698175d7b6b..afc7827a18a15 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesz.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesz.c @@ -156,13 +156,3 @@ vuint32m8_t test_vaesz_vs_u32m4_u32m8_tu(vuint32m8_t vd, vuint32m4_t vs2, size_t return __riscv_vaesz_tu(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesz_vs_u32m8_u32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesz.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 2) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesz_vs_u32m8_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesz_tu(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4r.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4r.c index 0df390bd0724a..7b70c4e2a790f 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4r.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4r.c @@ -206,13 +206,3 @@ vuint32m8_t test_vsm4r_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { return __riscv_vsm4r_vv_tu(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vsm4r_vs_u32m8_u32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vsm4r.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 2) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vsm4r_vs_u32m8_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vsm4r_vs_tu(vd, vs2, vl); -} -