diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ff2bd6f7c8ba34..41c257bc559ed5 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -31,6 +31,62 @@
 // MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature" "+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
 // MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"
 
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-x60 | FileCheck -check-prefix=MCPU-SPACEMIT-X60 %s
+// MCPU-SPACEMIT-X60: "-nostdsysteminc" "-target-cpu" "spacemit-x60"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+m"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+a"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+f"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+d"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+c"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+v"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zic64b"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicbom"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicbop"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicboz"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccamoa"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccif"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicclsm"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccrse"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicntr"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicond"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicsr"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zifencei"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zihintpause"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zihpm"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+za64rs"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zfh"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zfhmin"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zba"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbb"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbc"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbkc"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbs"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zkt"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve32f"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve32x"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve64d"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve64f"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve64x"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvfh"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvfhmin"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvkt"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl128b"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl256b"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl32b"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl64b"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ssccptr"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sscofpmf"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sscounterenw"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sstc"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sstvala"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sstvecd"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svade"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svbare"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svinval"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svnapot"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svpbmt"
+// MCPU-SPACEMIT-X60-SAME: "-target-abi" "lp64d"
+
 // We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string.
 // RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
 // RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s
diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c
index 6558fd753d1d12..85fb5f102bee8e 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -85,7 +85,7 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, veyron-v1, xiangshan-nanhu{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
@@ -93,4 +93,4 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 6ebf9f1eb04524..0348b754498364 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -381,3 +381,19 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtHFusion,
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
+                                       NoSchedModel,
+                                       !listconcat(RVA22S64Features,
+                                       [FeatureStdExtV,
+                                        FeatureStdExtSscofpmf,
+                                        FeatureStdExtSstc,
+                                        FeatureStdExtSvnapot,
+                                        FeatureStdExtZbc,
+                                        FeatureStdExtZbkc,
+                                        FeatureStdExtZfh,
+                                        FeatureStdExtZicond,
+                                        FeatureStdExtZvfh,
+                                        FeatureStdExtZvkt,
+                                        FeatureStdExtZvl256b]),
+                                       [TuneDLenFactor2]>;