diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh index a8d1e8eb71..f08ebed0ee 100755 --- a/.travis/fpga_verilog_reg_test.sh +++ b/.travis/fpga_verilog_reg_test.sh @@ -13,8 +13,11 @@ echo -e "FPGA-Verilog Feature Tests"; echo -e "Testing Verilog generation for LUTs: a single mode LUT6 FPGA using micro benchmarks"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/single_mode --debug --show_thread_logs +echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 "; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4 --debug --show_thread_logs + echo -e "Testing Verilog generation for LUTs: simple fracturable LUT6 "; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut6 --debug --show_thread_logs echo -e "Testing Verilog generation for LUTs: LUT6 with intermediate buffers"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/intermediate_buffer --debug --show_thread_logs diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp index c3ab88f1c2..83956dfc94 100644 --- a/openfpga/src/repack/repack.cpp +++ b/openfpga/src/repack/repack.cpp @@ -20,6 +20,73 @@ /* begin namespace openfpga */ namespace openfpga { +/*************************************************************************************** + * Try to find sink pb graph pins through walking through the fan-out edges from + * the source pb graph pin + * Only the sink meeting the following requirements can be considered: + * - All the fan-out edges between the source and sink are from direct interconnection + * - sink is an input of a primitive pb_type + * + * Note: + * - If there is a fan-out of the current source pb graph pin is not a direct interconnection + * the direct search should stop. + * - This function is designed for pb graph without local routing + * For example: direct connection between root pb graph node to the LUT pb graph node + * + * root pb_graph_node + * +----------------------------------------- + * | Intermediate pb_graph_node + * | +---------------------------------- + * | | primitive pb_graph_node + * | | +------------------------- + * I[0] ---->+------>+------->|I[0] LUT + * + * - This function is designed for passing wires inside pb graph + * + * root pb_graph_node + * +------------------------------+ + * | Intermediate pb_graph_node | + * | +-------------+ | + * | | | | + * | | | | + * I[0]----->+------>+--- ... ---->+------->+------>O[0] + * + ***************************************************************************************/ +static +bool rec_direct_search_sink_pb_graph_pins(const t_pb_graph_pin* source_pb_pin, + std::vector& sink_pb_pins) { + + std::vector sink_pb_pins_to_search; + + for (int iedge = 0; iedge < source_pb_pin->num_output_edges; ++iedge) { + if (DIRECT_INTERC != source_pb_pin->output_edges[iedge]->interconnect->type) { + return false; + } + for (int ipin = 0; ipin < source_pb_pin->output_edges[iedge]->num_output_pins; ++ipin) { + t_pb_graph_pin* cand_sink_pb_pin = source_pb_pin->output_edges[iedge]->output_pins[ipin]; + if ( (true == is_primitive_pb_type(cand_sink_pb_pin->parent_node->pb_type)) + && (IN_PORT == cand_sink_pb_pin->port->type)) { + sink_pb_pins.push_back(cand_sink_pb_pin); + } else if ( (true == cand_sink_pb_pin->parent_node->is_root()) + && (OUT_PORT == cand_sink_pb_pin->port->type)) { + sink_pb_pins.push_back(cand_sink_pb_pin); + } else { + sink_pb_pins_to_search.push_back(cand_sink_pb_pin); + } + } + } + + for (t_pb_graph_pin* sink_pb_pin : sink_pb_pins_to_search) { + bool direct_search_status = rec_direct_search_sink_pb_graph_pins(sink_pb_pin, sink_pb_pins); + if (false == direct_search_status) { + return false; + } + } + + /* Reach here, we succeed. */ + return true; +} + /*************************************************************************************** * Try find all the sink pins which is mapped to a routing trace in the context of pb route * This function uses a recursive walk-through over the pb_route @@ -133,13 +200,32 @@ void rec_find_routed_sink_pb_graph_pins(const t_pb* pb, static std::vector find_routed_pb_graph_pins_atom_net(const t_pb* pb, const t_pb_graph_pin* source_pb_pin, + const t_pb_graph_pin* packing_source_pb_pin, const AtomNetId& atom_net_id, const VprDeviceAnnotation& device_annotation, const std::map& pb_pin_mapped_nets, t_pb_graph_pin** pb_graph_pin_lookup_from_index) { std::vector sink_pb_pins; - rec_find_routed_sink_pb_graph_pins(pb, source_pb_pin, atom_net_id, device_annotation, pb_pin_mapped_nets, pb_graph_pin_lookup_from_index, sink_pb_pins); + /* Try to directly search for sink pb_pins from the source_pb_pin, + * which is the actual source pin to be routed from + * Note that the packing source_pb_pin is the source pin considered by + * VPR packer, but may not be the actual source!!! + */ + if (true == source_pb_pin->parent_node->is_root()) { + bool direct_search_status = rec_direct_search_sink_pb_graph_pins(source_pb_pin, sink_pb_pins); + if (true == direct_search_status) { + VTR_ASSERT(!sink_pb_pins.empty()); + /* We have find through direct searching, return now */ + return sink_pb_pins; + } + + /* Cannot find through direct searching, reset results */ + VTR_ASSERT_SAFE(false == direct_search_status); + sink_pb_pins.clear(); + } + + rec_find_routed_sink_pb_graph_pins(pb, packing_source_pb_pin, atom_net_id, device_annotation, pb_pin_mapped_nets, pb_graph_pin_lookup_from_index, sink_pb_pins); return sink_pb_pins; } @@ -339,7 +425,7 @@ void add_lb_router_nets(LbRouter& lb_router, VTR_ASSERT(nullptr != packing_source_pb_pin); /* Find all the sink pins in the pb_route, we walk through the input pins and find the pin */ - std::vector sink_pb_graph_pins = find_routed_pb_graph_pins_atom_net(pb, packing_source_pb_pin, atom_net_id, device_annotation, pb_pin_mapped_nets, pb_graph_pin_lookup_from_index); + std::vector sink_pb_graph_pins = find_routed_pb_graph_pins_atom_net(pb, source_pb_pin, packing_source_pb_pin, atom_net_id, device_annotation, pb_pin_mapped_nets, pb_graph_pin_lookup_from_index); std::vector sink_lb_rr_nodes = find_lb_net_physical_sink_lb_rr_nodes(lb_rr_graph, sink_pb_graph_pins, device_annotation); VTR_ASSERT(sink_lb_rr_nodes.size() == sink_pb_graph_pins.size()); @@ -404,7 +490,7 @@ void add_lb_router_nets(LbRouter& lb_router, VTR_ASSERT(AtomNetId::INVALID() != atom_net_id); /* Find all the sink pins in the pb_route */ - std::vector sink_pb_graph_pins = find_routed_pb_graph_pins_atom_net(pb, source_pb_pin, atom_net_id, device_annotation, pb_pin_mapped_nets, pb_graph_pin_lookup_from_index); + std::vector sink_pb_graph_pins = find_routed_pb_graph_pins_atom_net(pb, physical_source_pb_pin, source_pb_pin, atom_net_id, device_annotation, pb_pin_mapped_nets, pb_graph_pin_lookup_from_index); std::vector sink_lb_rr_nodes = find_lb_net_physical_sink_lb_rr_nodes(lb_rr_graph, sink_pb_graph_pins, device_annotation); VTR_ASSERT(sink_lb_rr_nodes.size() == sink_pb_graph_pins.size()); diff --git a/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga new file mode 100644 index 0000000000..3d5418466f --- /dev/null +++ b/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga @@ -0,0 +1,74 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga index d1c20fb9d9..4889f8414c 100644 --- a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga index 15098c1249..9d9b0aa7db 100644 --- a/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} diff --git a/openfpga_flow/OpenFPGAShellScripts/load_external_arch_bitstream_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/load_external_arch_bitstream_example_script.openfpga index f53e6b1873..8276a91193 100644 --- a/openfpga_flow/OpenFPGAShellScripts/load_external_arch_bitstream_example_script.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/load_external_arch_bitstream_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml new file mode 100644 index 0000000000..ee5c4df5f3 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml @@ -0,0 +1,231 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf index d36f074ae5..89ba177b64 100644 --- a/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf +++ b/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf @@ -20,6 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_external_arch_bitstream_file=${PATH:OPENFPGA_PATH}/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml +openfpga_vpr_device_layout=2x2 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/fpga_verilog/bram/dpram16k/config/task.conf b/openfpga_flow/tasks/fpga_verilog/bram/dpram16k/config/task.conf index a001231df2..b693eab56c 100644 --- a/openfpga_flow/tasks/fpga_verilog/bram/dpram16k/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/bram/dpram16k/config/task.conf @@ -16,9 +16,10 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=3x2 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml diff --git a/openfpga_flow/tasks/fpga_verilog/bram/wide_dpram16k/config/task.conf b/openfpga_flow/tasks/fpga_verilog/bram/wide_dpram16k/config/task.conf index 048f5e2361..bf748e819c 100644 --- a/openfpga_flow/tasks/fpga_verilog/bram/wide_dpram16k/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/bram/wide_dpram16k/config/task.conf @@ -16,9 +16,10 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=4x4 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_chain/adder_chain/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_chain/adder_chain/config/task.conf index f465fe4fbf..71813d7345 100644 --- a/openfpga_flow/tasks/fpga_verilog/fabric_chain/adder_chain/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/fabric_chain/adder_chain/config/task.conf @@ -16,9 +16,10 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=2x2 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_chain/register_chain/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_chain/register_chain/config/task.conf index 08b46bef5c..aa92c76ae6 100644 --- a/openfpga_flow/tasks/fpga_verilog/fabric_chain/register_chain/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/fabric_chain/register_chain/config/task.conf @@ -16,9 +16,10 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=2x2 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_chain/scan_chain/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_chain/scan_chain/config/task.conf index a4737dbfe7..d042a6923f 100644 --- a/openfpga_flow/tasks/fpga_verilog/fabric_chain/scan_chain/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/fabric_chain/scan_chain/config/task.conf @@ -16,9 +16,10 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=2x2 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key/config/task.conf index b6658090ba..d15e024426 100644 --- a/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key/config/task.conf @@ -20,6 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/fabric_keys/k4_N4_2x2_sample_key.xml +openfpga_vpr_device_layout=2x2 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_cc_fpga/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_cc_fpga/config/task.conf index 5931a4a134..41768fc756 100644 --- a/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_cc_fpga/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_cc_fpga/config/task.conf @@ -20,6 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/fabric_keys/k4_N4_2x2_sample_key.xml +openfpga_vpr_device_layout=2x2 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml diff --git a/openfpga_flow/tasks/fpga_verilog/flatten_routing/config/task.conf b/openfpga_flow/tasks/fpga_verilog/flatten_routing/config/task.conf index 7fdd7f4566..6a4c3aad53 100644 --- a/openfpga_flow/tasks/fpga_verilog/flatten_routing/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/flatten_routing/config/task.conf @@ -17,11 +17,12 @@ fpga_flow=vpr_blif [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=4x4 [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/tasks/fpga_verilog/io/aib/config/task.conf b/openfpga_flow/tasks/fpga_verilog/io/aib/config/task.conf index 68741ad1cf..3dc99925de 100644 --- a/openfpga_flow/tasks/fpga_verilog/io/aib/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/io/aib/config/task.conf @@ -16,9 +16,10 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=3x4 ##################################### # Debugging status diff --git a/openfpga_flow/tasks/fpga_verilog/io/multi_io_capacity/config/task.conf b/openfpga_flow/tasks/fpga_verilog/io/multi_io_capacity/config/task.conf index fb326c021e..645339aeeb 100644 --- a/openfpga_flow/tasks/fpga_verilog/io/multi_io_capacity/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/io/multi_io_capacity/config/task.conf @@ -16,9 +16,10 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=3x2 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml diff --git a/openfpga_flow/tasks/fpga_verilog/io/reduced_io/config/task.conf b/openfpga_flow/tasks/fpga_verilog/io/reduced_io/config/task.conf index 88b7b74c81..04d01af539 100644 --- a/openfpga_flow/tasks/fpga_verilog/io/reduced_io/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/io/reduced_io/config/task.conf @@ -16,9 +16,10 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=3x2 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml diff --git a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4/config/task.conf new file mode 100644 index 0000000000..805502d339 --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4/config/task.conf @@ -0,0 +1,49 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml + +[BENCHMARKS] +# +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.blif +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif +# Modelsim is ok with this but icarus fails due to poor support on timing and looping +#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +bench1_top = routing_test +bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.act +bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.v + +bench2_top = and2_or2 +bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act +bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut6/config/task.conf similarity index 100% rename from openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut/config/task.conf rename to openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut6/config/task.conf diff --git a/openfpga_flow/tasks/fpga_verilog/spypad/config/task.conf b/openfpga_flow/tasks/fpga_verilog/spypad/config/task.conf index 0d0bbb547a..63d24e4711 100644 --- a/openfpga_flow/tasks/fpga_verilog/spypad/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/spypad/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml diff --git a/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_narrow_tile/config/task.conf b/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_narrow_tile/config/task.conf index 1e2941de15..7099ff2bcf 100644 --- a/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_narrow_tile/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_narrow_tile/config/task.conf @@ -16,9 +16,10 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=4x4 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml diff --git a/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_wide_tile/config/task.conf b/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_wide_tile/config/task.conf index 5f6de10786..711c7c7c59 100644 --- a/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_wide_tile/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_wide_tile/config/task.conf @@ -16,9 +16,10 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=4x4 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_wide_mem16K_40nm.xml diff --git a/openfpga_flow/tasks/fpga_verilog/untileable/config/task.conf b/openfpga_flow/tasks/fpga_verilog/untileable/config/task.conf index 13c0cdf621..44182f6458 100644 --- a/openfpga_flow/tasks/fpga_verilog/untileable/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/untileable/config/task.conf @@ -16,12 +16,13 @@ timeout_each_job = 20*60 fpga_flow=vpr_blif [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=4x4 [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml index 533704db8a..90a4848807 100644 --- a/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml @@ -63,7 +63,13 @@ - + + + + + + + @@ -71,7 +77,6 @@ - - + + + + + + + @@ -72,7 +78,6 @@ - - + + + + + + + @@ -75,7 +81,6 @@ - + diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml new file mode 100644 index 0000000000..5582a8b7b4 --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml @@ -0,0 +1,449 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml new file mode 100644 index 0000000000..25193bb0f7 --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml @@ -0,0 +1,449 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_40nm.xml index aa9ca9d985..9298097826 100644 --- a/openfpga_flow/vpr_arch/k6_frac_N10_40nm.xml +++ b/openfpga_flow/vpr_arch/k6_frac_N10_40nm.xml @@ -77,7 +77,13 @@ - + + + + + + + @@ -85,7 +91,6 @@ - - + + + + + + + @@ -168,7 +174,6 @@ - - + + + + + + + + + + @@ -205,7 +214,6 @@ - - + + + + + + + @@ -85,7 +91,6 @@ - - + + + + + + + @@ -168,7 +174,6 @@ - - + + + + + + + + + + @@ -205,7 +214,6 @@ - - + + + + + + + + + + + + @@ -237,7 +248,6 @@ - - + + + + + + + + + + + + + @@ -239,7 +251,6 @@ - - + + + + + + + + + + + + @@ -206,9 +217,7 @@ - - - + + + + + + + + + + @@ -205,7 +214,6 @@ - - + + + + + + + @@ -172,7 +178,6 @@ - - + + + + + + + @@ -187,7 +193,6 @@ - - + + + + + + + + + - diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml index 15281812ff..2ee4db8551 100755 --- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml +++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml @@ -184,7 +184,16 @@ This is strongly recommended if you want to PnR large FPGA fabric --> - + + + + + + + + + + diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml index ffefc9146a..aaf06d70ce 100644 --- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml +++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml @@ -201,7 +201,16 @@ - + + + + + + + + + + @@ -212,7 +221,6 @@ - - + + + + + + + + + + @@ -205,7 +214,6 @@ - - + + + + + + + @@ -85,7 +91,6 @@ -