From 5828fd6421d2db35f5c9a52bf2ed49b44c0e983c Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 24 Jan 2025 11:50:47 -0700 Subject: [PATCH 1/8] Updated VTR Pointer --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 8178b7129..c6e1a7b03 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 8178b71295d2579c38403529765c95432c44bd0c +Subproject commit c6e1a7b0387a4143261a6e4ef8cc29304256ccb7 From 0a8ba7bdfb0a6be7149601c8e87171b63c721003 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 24 Jan 2025 11:52:39 -0700 Subject: [PATCH 2/8] Added DEBUG information to build_rr_gsb --- openfpga/src/annotation/annotate_rr_graph.cpp | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index 51c9bd3cc..c624dd23c 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -397,6 +397,14 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, /* Build OPIN node lists for connection blocks */ rr_gsb.build_cb_opin_nodes(vpr_device_ctx.rr_graph); + for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { + SideManager side_manager(side); + VTR_LOG_DEBUG("RRGSB at (%lu, %lu) has %lu chan nodes, %lu ipin nodes, and %lu opin nodes.\n", + rr_gsb.get_x(), rr_gsb.get_y(), + rr_gsb.chan_node_size(side_manager.get_side()), + rr_gsb.ipin_node_size(side_manager.get_side()), + rr_gsb.opin_node_size(side_manager.get_side())); + } return rr_gsb; } From c914b9564c3402c7a1757e2c2059a103bf1a95d2 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Fri, 24 Jan 2025 11:53:35 -0700 Subject: [PATCH 3/8] Fixed write rr_graph GSB writing --- .../annotation/write_xml_device_rr_gsb.cpp | 27 ++++++++++++------- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/openfpga/src/annotation/write_xml_device_rr_gsb.cpp b/openfpga/src/annotation/write_xml_device_rr_gsb.cpp index 552ee361a..897d44f00 100644 --- a/openfpga/src/annotation/write_xml_device_rr_gsb.cpp +++ b/openfpga/src/annotation/write_xml_device_rr_gsb.cpp @@ -50,15 +50,24 @@ static void write_rr_gsb_ipin_connection_to_xml(std::fstream& fp, continue; } - enum e_side chan_side = rr_gsb.get_cb_chan_side(gsb_side); - SideManager chan_side_manager(chan_side); - - /* For channel node, we do not know the node direction - * But we are pretty sure it is either IN_PORT or OUT_PORT - * So we just try and find what is valid - */ - int driver_node_index = - rr_gsb.get_chan_node_index(chan_side, driver_node); + e_side chan_side; + SideManager chan_side_manager = SideManager(); + int driver_node_index = -1; + + for (size_t side = 0; side < NUM_2D_SIDES; ++side) { + chan_side_manager.set_side(side); + chan_side = chan_side_manager.get_side(); + for (PORTS port_direc : {IN_PORT, OUT_PORT}) { + /* For channel node, we do not know the node direction + * But we are pretty sure it is either IN_PORT or OUT_PORT + * So we just try and find what is valid + */ + driver_node_index = rr_gsb.get_chan_node_index(chan_side, driver_node); + if (-1 != driver_node_index) { break; } + } + if (-1 != driver_node_index) { break;} + } + /* We must have a valide node index */ VTR_ASSERT(-1 != driver_node_index); From 2932fed92bdb95fb433623743ed71c9613d70323 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 25 Jan 2025 20:11:19 -0700 Subject: [PATCH 4/8] Fixed file format --- openfpga/src/annotation/annotate_rr_graph.cpp | 4 +++- openfpga/src/annotation/write_xml_device_rr_gsb.cpp | 11 ++++++++--- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index c624dd23c..f07489b8a 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -399,7 +399,9 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) { SideManager side_manager(side); - VTR_LOG_DEBUG("RRGSB at (%lu, %lu) has %lu chan nodes, %lu ipin nodes, and %lu opin nodes.\n", + VTR_LOG_DEBUG( + "RRGSB at (%lu, %lu) has %lu chan nodes, %lu ipin nodes, and %lu opin " + "nodes.\n", rr_gsb.get_x(), rr_gsb.get_y(), rr_gsb.chan_node_size(side_manager.get_side()), rr_gsb.ipin_node_size(side_manager.get_side()), diff --git a/openfpga/src/annotation/write_xml_device_rr_gsb.cpp b/openfpga/src/annotation/write_xml_device_rr_gsb.cpp index 897d44f00..3a0d56a03 100644 --- a/openfpga/src/annotation/write_xml_device_rr_gsb.cpp +++ b/openfpga/src/annotation/write_xml_device_rr_gsb.cpp @@ -62,10 +62,15 @@ static void write_rr_gsb_ipin_connection_to_xml(std::fstream& fp, * But we are pretty sure it is either IN_PORT or OUT_PORT * So we just try and find what is valid */ - driver_node_index = rr_gsb.get_chan_node_index(chan_side, driver_node); - if (-1 != driver_node_index) { break; } + driver_node_index = + rr_gsb.get_chan_node_index(chan_side, driver_node); + if (-1 != driver_node_index) { + break; + } } - if (-1 != driver_node_index) { break;} + if (-1 != driver_node_index) { + break; + } } /* We must have a valide node index */ From 8125a707dba53303aeebe5598f89e1a9a76a50eb Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 25 Jan 2025 20:43:31 -0700 Subject: [PATCH 5/8] Fixed format --- .../src/annotation/write_xml_device_rr_gsb.cpp | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/openfpga/src/annotation/write_xml_device_rr_gsb.cpp b/openfpga/src/annotation/write_xml_device_rr_gsb.cpp index 3a0d56a03..0b1aa8462 100644 --- a/openfpga/src/annotation/write_xml_device_rr_gsb.cpp +++ b/openfpga/src/annotation/write_xml_device_rr_gsb.cpp @@ -55,23 +55,23 @@ static void write_rr_gsb_ipin_connection_to_xml(std::fstream& fp, int driver_node_index = -1; for (size_t side = 0; side < NUM_2D_SIDES; ++side) { - chan_side_manager.set_side(side); - chan_side = chan_side_manager.get_side(); - for (PORTS port_direc : {IN_PORT, OUT_PORT}) { - /* For channel node, we do not know the node direction - * But we are pretty sure it is either IN_PORT or OUT_PORT - * So we just try and find what is valid - */ + chan_side_manager.set_side(side); + chan_side = chan_side_manager.get_side(); + for (PORTS port_direc : {IN_PORT, OUT_PORT}) { + /* For channel node, we do not know the node direction + * But we are pretty sure it is either IN_PORT or OUT_PORT + * So we just try and find what is valid + */ driver_node_index = rr_gsb.get_chan_node_index(chan_side, driver_node); if (-1 != driver_node_index) { break; } - } + } if (-1 != driver_node_index) { break; } - } + } /* We must have a valide node index */ VTR_ASSERT(-1 != driver_node_index); From bac3a451aeee9b41fd2a8dc220885cf8279ac302 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Sat, 25 Jan 2025 20:55:10 -0700 Subject: [PATCH 6/8] Fixed format --- openfpga/src/annotation/annotate_rr_graph.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/openfpga/src/annotation/annotate_rr_graph.cpp b/openfpga/src/annotation/annotate_rr_graph.cpp index f07489b8a..7759819d7 100644 --- a/openfpga/src/annotation/annotate_rr_graph.cpp +++ b/openfpga/src/annotation/annotate_rr_graph.cpp @@ -402,10 +402,10 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx, VTR_LOG_DEBUG( "RRGSB at (%lu, %lu) has %lu chan nodes, %lu ipin nodes, and %lu opin " "nodes.\n", - rr_gsb.get_x(), rr_gsb.get_y(), - rr_gsb.chan_node_size(side_manager.get_side()), - rr_gsb.ipin_node_size(side_manager.get_side()), - rr_gsb.opin_node_size(side_manager.get_side())); + rr_gsb.get_x(), rr_gsb.get_y(), + rr_gsb.chan_node_size(side_manager.get_side()), + rr_gsb.ipin_node_size(side_manager.get_side()), + rr_gsb.opin_node_size(side_manager.get_side())); } return rr_gsb; } From 5a55c07072fdc61bdc624e6211df646cb5b135bf Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Tue, 28 Jan 2025 11:22:41 -0700 Subject: [PATCH 7/8] Update submodule pointer --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index c6e1a7b03..832540f74 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit c6e1a7b0387a4143261a6e4ef8cc29304256ccb7 +Subproject commit 832540f743250b922a33b733829b7121711f0196 From 8e3e7595e4494744b6967a919a722974804a9fcb Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Wed, 29 Jan 2025 14:49:40 -0700 Subject: [PATCH 8/8] Updated write_xml function --- .../annotation/write_xml_device_rr_gsb.cpp | 35 +++++++++++-------- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/openfpga/src/annotation/write_xml_device_rr_gsb.cpp b/openfpga/src/annotation/write_xml_device_rr_gsb.cpp index 0b1aa8462..222788de2 100644 --- a/openfpga/src/annotation/write_xml_device_rr_gsb.cpp +++ b/openfpga/src/annotation/write_xml_device_rr_gsb.cpp @@ -50,27 +50,32 @@ static void write_rr_gsb_ipin_connection_to_xml(std::fstream& fp, continue; } - e_side chan_side; - SideManager chan_side_manager = SideManager(); + enum e_side chan_side = rr_gsb.get_cb_chan_side(gsb_side); int driver_node_index = -1; - for (size_t side = 0; side < NUM_2D_SIDES; ++side) { - chan_side_manager.set_side(side); - chan_side = chan_side_manager.get_side(); - for (PORTS port_direc : {IN_PORT, OUT_PORT}) { - /* For channel node, we do not know the node direction - * But we are pretty sure it is either IN_PORT or OUT_PORT - * So we just try and find what is valid - */ - driver_node_index = - rr_gsb.get_chan_node_index(chan_side, driver_node); + SideManager chan_side_manager(chan_side); + + driver_node_index = rr_gsb.get_chan_node_index(chan_side, driver_node); + + if (-1 == driver_node_index) { + for (size_t side = 0; side < NUM_2D_SIDES; ++side) { + chan_side_manager.set_side(side); + chan_side = chan_side_manager.get_side(); + for (PORTS port_direc : {IN_PORT, OUT_PORT}) { + /* For channel node, we do not know the node direction + * But we are pretty sure it is either IN_PORT or OUT_PORT + * So we just try and find what is valid + */ + driver_node_index = + rr_gsb.get_chan_node_index(chan_side, driver_node); + if (-1 != driver_node_index) { + break; + } + } if (-1 != driver_node_index) { break; } } - if (-1 != driver_node_index) { - break; - } } /* We must have a valide node index */