diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 85921213a..9bde3de65 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -201,7 +201,8 @@ def _printattr(attr, attr_translate):
         if not firsta:
             r += ", "
         firsta = False
-        r += attr_name + " = \"" + attr_value + "\""
+        const_expr = "\"" + attr_value + "\"" if not isinstance(attr_value, int) else str(attr_value)
+        r += attr_name + " = " + const_expr
     if r:
         r = "(* " + r + " *)"
     return r