diff --git a/migen/build/platforms/coraz7_07s.py b/migen/build/platforms/coraz7.py
similarity index 84%
rename from migen/build/platforms/coraz7_07s.py
rename to migen/build/platforms/coraz7.py
index ea98d84a5..aedd534c4 100644
--- a/migen/build/platforms/coraz7_07s.py
+++ b/migen/build/platforms/coraz7.py
@@ -35,10 +35,16 @@
     ("user_dio", 12, Pins("K19"), IOStandard("LVCMOS33")),
 ]
 
+DEVICE_VARIANTS = {
+    "07s": "xc7z007s-clg400-1",
+    "10": "xc7z010-clg400-1",
+}
 
+# Digilent Cora Z7-07S, and Z7-10
 class Platform(XilinxPlatform):
     default_clk_name = "sys_clk"
     default_clk_period = 8
 
-    def __init__(self):
-        XilinxPlatform.__init__(self, "xc7z007s-clg400-1", _io, toolchain="vivado")
+    def __init__(self, device_variant="10"):
+        device = DEVICE_VARIANTS[device_variant]
+        XilinxPlatform.__init__(self, device, _io, toolchain="vivado")