-
Notifications
You must be signed in to change notification settings - Fork 211
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Problem with copy_sources(self, build_dir, subdir="imports") #207
Comments
I do not understand the problem. Can you post the source code of a minimal Migen design that reproduces the issue? We are using this |
I had the same issue, the copy_sources function try to copy an external v file into a non existing directory : imports/homefolder/project/... eg, prj file content : I also solve it using a slightly different manner (with the debug print) :
After doing this change :
Another point now is that randomly in the prj file, the imported v file appear to be the first, then the compiler is not working. eg sometime it write this in the prj file :
|
@Alain94W please post minimal project that exhibits the problem. |
I will do that as soon as possible, as a new father, it's difficult to find time for hobby ... |
Got the same issue ... The root problem is that by the time |
Fixed it with : diff --git a/migen/build/generic_platform.py b/migen/build/generic_platform.py
index c07883b..d09acbe 100644
--- a/migen/build/generic_platform.py
+++ b/migen/build/generic_platform.py
@@ -331,7 +331,7 @@ class GenericPlatform:
# source filenames are assumed relative to the build_dir
src = os.path.join(build_dir, filename)
# copy to path that starts with build_dir
- dest = os.path.join(build_dir, path)
+ dest = path
os.makedirs(os.path.dirname(dest), exist_ok=True)
shutil.copyfile(src, dest) |
So the problem is that specific platform |
I work with a xilinx FPGA (spartan 6), with the ise toolchain, when i try to run the lab002 from fpga_101 i have an xst problem: ERROR: Xst: 2927 - "/home/hyde/Digital/Soc/fpga_101/lab002/build/top.prj "line 1: Source file imports / home / hyde / Digital / Soc / fpga_101 / lab002 / bcd.v does not exist
This is because the file address is not taken well, so modify the generic_platform.py file on line 325: def copy_sources (self, build_dir, subdir = os.getcwd () + "/build/build/imports"):
In this way i solve the error
generic_platform.txt
The text was updated successfully, but these errors were encountered: