diff --git a/firmware/midi-router-x2/midi.cpp b/firmware/midi-router-x2/midi.cpp
index c087bf1..09f44aa 100644
--- a/firmware/midi-router-x2/midi.cpp
+++ b/firmware/midi-router-x2/midi.cpp
@@ -2,6 +2,7 @@
 #include <midi.h>
 #include <uart.h>
 #include <crit_sec.h>
+#include <splitter.h>
 
 namespace {
 
@@ -13,39 +14,67 @@ using uart_c1 = uart_t<port::C1, 31250, rx_midi_traits<1>, tx_midi_traits<1> >;
 template<> uart_c1::tx_ring_t uart_c1::tx_ring = {};
 template<> uint8_t uart_c1::want_write = 0;
 
+using UL = uart_list<uart_c0, uart_c1>;
+
+midi::splitter_t<UL> splitter_state;
+
+void splitter_rx_complete(uint8_t port, uint8_t data, bool ferr) {
+    splitter_state.rx_complete(port, data, ferr);
 }
 
-namespace midi {
+void splitter_process_dre(uint8_t port) {
+    splitter_state.process_dre(port);
+}
+
+template<typename T>
+inline void rx_complete() {
+    crit_sec cs;
+    bool ferr = T::ferr();
+    midi::on_rx_complete(T::rx_traits::id, T::data(), ferr);
+}
+
+template<typename T>
+inline void process_bit() {
+    crit_sec cs;
+    splitter_state.process_bit(T::rx_traits::id, T::rx::read());
+}
 
-void init() {
-    PORTC.INT0MASK = 0;
-    PORTC.INTCTRL = 0;
+template<typename T>
+inline void process_dre() {
+    crit_sec cs;
+    T::on_dre_int();
 
-    uart_c0::setup();
-    uart_c1::setup();
+    midi::on_dre(T::rx_traits::id);
+}
 
-    uart_c0::rxc_int_hi();
-    uart_c1::rxc_int_hi();
 }
 
-void splitter() {
-    uart_c0::disable();
-    uart_c1::disable();
+namespace midi {
+
+void init(process_byte_t cb) {
+    if (cb) {
+        splitter_state.disable();
 
-    uart_c0::port_traits::setup_pins();
-    uart_c1::port_traits::setup_pins();
+        on_rx_complete = cb;
+        on_dre = dummy_process_dre;
+    } else {
+        splitter_state.enable();
 
-    PORTC.INT0MASK = (1 << 2);
-    PORTC.INTCTRL = PORT_INT0LVL_HI_gc;
+        on_rx_complete = splitter_rx_complete;
+        on_dre = splitter_process_dre;
+    }
 }
 
 uint8_t send(uint8_t port, const uint8_t *buf, uint8_t size) {
-    switch (port) {
-    case 0: return uart_c0::write_buf(buf, size);
-    case 1: return uart_c1::write_buf(buf, size);
-    }
+    return UL::write_buf(port, buf, size);
+}
+
+void pending_timeout() {
+    splitter_state.pending_timeout();
+}
 
-    return 0;
+void dump_state() {
+    splitter_state.dump();
 }
 
 }
@@ -53,39 +82,31 @@ uint8_t send(uint8_t port, const uint8_t *buf, uint8_t size) {
 
 ISR(USARTC0_RXC_vect)
 {
-    uart_c0::on_rxc_int();
+    rx_complete<uart_c0>();
 }
 
 ISR(USARTC0_DRE_vect)
 {
-    uart_c0::on_dre_int();
+    process_dre<uart_c0>();
+}
+
+ISR(PORTC_INT0_vect)
+{
+    process_bit<uart_c0>();
 }
 
 
 ISR(USARTC1_RXC_vect)
 {
-    uart_c1::on_rxc_int();
+    rx_complete<uart_c1>();
 }
 
 ISR(USARTC1_DRE_vect)
 {
-    uart_c1::on_dre_int();
+    process_dre<uart_c1>();
 }
 
-
-ISR(PORTC_INT0_vect)
+ISR(PORTC_INT1_vect)
 {
-    crit_sec cs;
-
-    bool v = uart_c0::rx::read();
-
-    if (v) {
-        uart_c0::tx::high();
-        uart_c1::tx::high();
-    } else {
-        uart_c0::tx::low();
-        uart_c1::tx::low();
-
-        midi::rx_ready = 1;
-    }
+    process_bit<uart_c1>();
 }
diff --git a/firmware/midi-router-x4-flat/midi.cpp b/firmware/midi-router-x4-flat/midi.cpp
index c2bf45b..6d5ae96 100644
--- a/firmware/midi-router-x4-flat/midi.cpp
+++ b/firmware/midi-router-x4-flat/midi.cpp
@@ -2,6 +2,7 @@
 #include <midi.h>
 #include <uart.h>
 #include <crit_sec.h>
+#include <splitter.h>
 
 namespace {
 
@@ -21,49 +22,67 @@ using uart_e0 = uart_t<port::E0, 31250, rx_midi_traits<0>, tx_midi_traits<3> >;
 template<> uart_e0::tx_ring_t uart_e0::tx_ring = {};
 template<> uint8_t uart_e0::want_write = 0;
 
+using UL = uart_list<uart_c0, uart_c1, uart_d0, uart_e0>;
+
+midi::splitter_t<UL> splitter_state;
+
+void splitter_rx_complete(uint8_t port, uint8_t data, bool ferr) {
+    splitter_state.rx_complete(port, data, ferr);
 }
 
-namespace midi {
+void splitter_process_dre(uint8_t port) {
+    splitter_state.process_dre(port);
+}
+
+template<typename T>
+inline void rx_complete() {
+    crit_sec cs;
+    bool ferr = T::ferr();
+    midi::on_rx_complete(T::rx_traits::id, T::data(), ferr);
+}
 
-void init() {
-    PORTE.INT0MASK = 0;
-    PORTE.INTCTRL = 0;
+template<typename T>
+inline void process_bit() {
+    crit_sec cs;
+    splitter_state.process_bit(T::rx_traits::id, T::rx::read());
+}
 
-    uart_c0::setup();
-    uart_c1::setup();
-    uart_d0::setup();
-    uart_e0::setup();
+template<typename T>
+inline void process_dre() {
+    crit_sec cs;
+    T::on_dre_int();
 
-    uart_c0::rxc_int_hi();
-    uart_c1::rxc_int_hi();
-    uart_d0::rxc_int_hi();
-    uart_e0::rxc_int_hi();
+    midi::on_dre(T::rx_traits::id);
 }
 
-void splitter() {
-    uart_c0::disable();
-    uart_c1::disable();
-    uart_d0::disable();
-    uart_e0::disable();
+}
+
+namespace midi {
 
-    uart_c0::port_traits::setup_pins();
-    uart_c1::port_traits::setup_pins();
-    uart_d0::port_traits::setup_pins();
-    uart_e0::port_traits::setup_pins();
+void init(process_byte_t cb) {
+    if (cb) {
+        splitter_state.disable();
+
+        on_rx_complete = cb;
+        on_dre = dummy_process_dre;
+    } else {
+        splitter_state.enable();
 
-    PORTE.INT0MASK = uart_e0::port_traits::rx::traits::bit_mask;
-    PORTE.INTCTRL = PORT_INT0LVL_HI_gc;
+        on_rx_complete = splitter_rx_complete;
+        on_dre = splitter_process_dre;
+    }
 }
 
 uint8_t send(uint8_t port, const uint8_t *buf, uint8_t size) {
-    switch (port) {
-    case 0: return uart_c0::write_buf(buf, size);
-    case 1: return uart_c1::write_buf(buf, size);
-    case 2: return uart_d0::write_buf(buf, size);
-    case 3: return uart_e0::write_buf(buf, size);
-    }
+    return UL::write_buf(port, buf, size);
+}
 
-    return 0;
+void pending_timeout() {
+    splitter_state.pending_timeout();
+}
+
+void dump_state() {
+    splitter_state.dump();
 }
 
 }
@@ -71,64 +90,63 @@ uint8_t send(uint8_t port, const uint8_t *buf, uint8_t size) {
 
 ISR(USARTC0_RXC_vect)
 {
-    uart_c0::on_rxc_int();
+    rx_complete<uart_c0>();
 }
 
 ISR(USARTC0_DRE_vect)
 {
-    uart_c0::on_dre_int();
+    process_dre<uart_c0>();
+}
+
+ISR(PORTC_INT0_vect)
+{
+    process_bit<uart_c0>();
 }
 
 
 ISR(USARTC1_RXC_vect)
 {
-    uart_c1::on_rxc_int();
+    rx_complete<uart_c1>();
 }
 
 ISR(USARTC1_DRE_vect)
 {
-    uart_c1::on_dre_int();
+    process_dre<uart_c1>();
+}
+
+ISR(PORTC_INT1_vect)
+{
+    process_bit<uart_c1>();
 }
 
 
 ISR(USARTD0_RXC_vect)
 {
-    uart_d0::on_rxc_int();
+    rx_complete<uart_d0>();
 }
 
 ISR(USARTD0_DRE_vect)
 {
-    uart_d0::on_dre_int();
+    process_dre<uart_d0>();
 }
 
-ISR(PORTE_INT0_vect)
+ISR(PORTD_INT0_vect)
 {
-    crit_sec cs;
-
-    bool v = uart_e0::rx::read();
-
-    if (v) {
-        uart_d0::tx::high();
-        uart_e0::tx::high();
-        uart_c0::tx::high();
-        uart_c1::tx::high();
-    } else {
-        uart_d0::tx::low();
-        uart_e0::tx::low();
-        uart_c0::tx::low();
-        uart_c1::tx::low();
-
-        midi::rx_ready = 1;
-    }
+    process_bit<uart_d0>();
 }
 
 
 ISR(USARTE0_RXC_vect)
 {
-    uart_e0::on_rxc_int();
+    rx_complete<uart_e0>();
 }
 
 ISR(USARTE0_DRE_vect)
 {
-    uart_e0::on_dre_int();
+    process_dre<uart_e0>();
+}
+
+ISR(PORTE_INT0_vect)
+{
+    process_bit<uart_e0>();
 }
diff --git a/firmware/midi-router-x4/midi.cpp b/firmware/midi-router-x4/midi.cpp
index d0e4c28..7aa0f47 100644
--- a/firmware/midi-router-x4/midi.cpp
+++ b/firmware/midi-router-x4/midi.cpp
@@ -2,68 +2,87 @@
 #include <midi.h>
 #include <uart.h>
 #include <crit_sec.h>
+#include <splitter.h>
 
 namespace {
 
-using uart_c0 = uart_t<port::C0, 31250, rx_midi_traits<2>, tx_midi_traits<2> >;
+using uart_c0 = uart_t<port::C0, 31250, rx_midi_traits<2>, tx_midi_traits<0> >;
 template<> uart_c0::tx_ring_t uart_c0::tx_ring = {};
 template<> uint8_t uart_c0::want_write = 0;
 
-using uart_c1 = uart_t<port::C1, 31250, rx_midi_traits<3>, tx_midi_traits<3> >;
+using uart_c1 = uart_t<port::C1, 31250, rx_midi_traits<3>, tx_midi_traits<1> >;
 template<> uart_c1::tx_ring_t uart_c1::tx_ring = {};
 template<> uint8_t uart_c1::want_write = 0;
 
-using uart_d0 = uart_t<port::D0, 31250, rx_midi_traits<0>, tx_midi_traits<0> >;
+using uart_d0 = uart_t<port::D0, 31250, rx_midi_traits<0>, tx_midi_traits<2> >;
 template<> uart_d0::tx_ring_t uart_d0::tx_ring = {};
 template<> uint8_t uart_d0::want_write = 0;
 
-using uart_e0 = uart_t<port::E0, 31250, rx_midi_traits<1>, tx_midi_traits<1> >;
+using uart_e0 = uart_t<port::E0, 31250, rx_midi_traits<1>, tx_midi_traits<3> >;
 template<> uart_e0::tx_ring_t uart_e0::tx_ring = {};
 template<> uint8_t uart_e0::want_write = 0;
 
+using UL = uart_list<uart_c0, uart_c1, uart_d0, uart_e0>;
+
+midi::splitter_t<UL> splitter_state;
+
+void splitter_rx_complete(uint8_t port, uint8_t data, bool ferr) {
+    splitter_state.rx_complete(port, data, ferr);
 }
 
-namespace midi {
+void splitter_process_dre(uint8_t port) {
+    splitter_state.process_dre(port);
+}
+
+template<typename T>
+inline void rx_complete() {
+    crit_sec cs;
+    bool ferr = T::ferr();
+    midi::on_rx_complete(T::rx_traits::id, T::data(), ferr);
+}
+
+template<typename T>
+inline void process_bit() {
+    crit_sec cs;
+    splitter_state.process_bit(T::rx_traits::id, T::rx::read());
+}
 
-void init() {
-    PORTD.INT0MASK = 0;
-    PORTD.INTCTRL = 0;
+template<typename T>
+inline void process_dre() {
+    crit_sec cs;
+    T::on_dre_int();
 
-    uart_c0::setup();
-    uart_c1::setup();
-    uart_d0::setup();
-    uart_e0::setup();
+    midi::on_dre(T::rx_traits::id);
+}
 
-    uart_c0::rxc_int_hi();
-    uart_c1::rxc_int_hi();
-    uart_d0::rxc_int_hi();
-    uart_e0::rxc_int_hi();
 }
 
-void splitter() {
-    uart_c0::disable();
-    uart_c1::disable();
-    uart_d0::disable();
-    uart_e0::disable();
+namespace midi {
 
-    uart_c0::port_traits::setup_pins();
-    uart_c1::port_traits::setup_pins();
-    uart_d0::port_traits::setup_pins();
-    uart_e0::port_traits::setup_pins();
+void init(process_byte_t cb) {
+    if (cb) {
+        splitter_state.disable();
 
-    PORTD.INT0MASK = uart_d0::port_traits::rx::traits::bit_mask;
-    PORTD.INTCTRL = PORT_INT0LVL_HI_gc;
+        on_rx_complete = cb;
+        on_dre = dummy_process_dre;
+    } else {
+        splitter_state.enable();
+
+        on_rx_complete = splitter_rx_complete;
+        on_dre = splitter_process_dre;
+    }
 }
 
 uint8_t send(uint8_t port, const uint8_t *buf, uint8_t size) {
-    switch (port) {
-    case 0: return uart_c0::write_buf(buf, size);
-    case 1: return uart_c1::write_buf(buf, size);
-    case 2: return uart_d0::write_buf(buf, size);
-    case 3: return uart_e0::write_buf(buf, size);
-    }
+    return UL::write_buf(port, buf, size);
+}
 
-    return 0;
+void pending_timeout() {
+    splitter_state.pending_timeout();
+}
+
+void dump_state() {
+    splitter_state.dump();
 }
 
 }
@@ -71,64 +90,63 @@ uint8_t send(uint8_t port, const uint8_t *buf, uint8_t size) {
 
 ISR(USARTC0_RXC_vect)
 {
-    uart_c0::on_rxc_int();
+    rx_complete<uart_c0>();
 }
 
 ISR(USARTC0_DRE_vect)
 {
-    uart_c0::on_dre_int();
+    process_dre<uart_c0>();
+}
+
+ISR(PORTC_INT0_vect)
+{
+    process_bit<uart_c0>();
 }
 
 
 ISR(USARTC1_RXC_vect)
 {
-    uart_c1::on_rxc_int();
+    rx_complete<uart_c1>();
 }
 
 ISR(USARTC1_DRE_vect)
 {
-    uart_c1::on_dre_int();
+    process_dre<uart_c1>();
+}
+
+ISR(PORTC_INT1_vect)
+{
+    process_bit<uart_c1>();
 }
 
 
 ISR(USARTD0_RXC_vect)
 {
-    uart_d0::on_rxc_int();
+    rx_complete<uart_d0>();
 }
 
 ISR(USARTD0_DRE_vect)
 {
-    uart_d0::on_dre_int();
+    process_dre<uart_d0>();
 }
 
 ISR(PORTD_INT0_vect)
 {
-    crit_sec cs;
-
-    bool v = uart_d0::rx::read();
-
-    if (v) {
-        uart_d0::tx::high();
-        uart_e0::tx::high();
-        uart_c0::tx::high();
-        uart_c1::tx::high();
-    } else {
-        uart_d0::tx::low();
-        uart_e0::tx::low();
-        uart_c0::tx::low();
-        uart_c1::tx::low();
-
-        midi::rx_ready = 1;
-    }
+    process_bit<uart_d0>();
 }
 
 
 ISR(USARTE0_RXC_vect)
 {
-    uart_e0::on_rxc_int();
+    rx_complete<uart_e0>();
 }
 
 ISR(USARTE0_DRE_vect)
 {
-    uart_e0::on_dre_int();
+    process_dre<uart_e0>();
+}
+
+ISR(PORTE_INT0_vect)
+{
+    process_bit<uart_e0>();
 }
diff --git a/firmware/midi-router-x7/midi.cpp b/firmware/midi-router-x7/midi.cpp
index ec4d892..0536d3e 100644
--- a/firmware/midi-router-x7/midi.cpp
+++ b/firmware/midi-router-x7/midi.cpp
@@ -2,6 +2,7 @@
 #include <midi.h>
 #include <uart.h>
 #include <crit_sec.h>
+#include <splitter.h>
 
 namespace {
 
@@ -33,167 +34,179 @@ using uart_f1 = uart_t<port::F1, 31250, rx_midi_traits<6>, tx_midi_traits<6> >;
 template<> uart_f1::tx_ring_t uart_f1::tx_ring = {};
 template<> uint8_t uart_f1::want_write = 0;
 
+using UL = uart_list<uart_c0, uart_c1, uart_d0, uart_e0, uart_e1, uart_f0, uart_f1>;
+
+midi::splitter_t<UL> splitter_state;
+
+void splitter_rx_complete(uint8_t port, uint8_t data, bool ferr) {
+    splitter_state.rx_complete(port, data, ferr);
+}
+
+void splitter_process_dre(uint8_t port) {
+    splitter_state.process_dre(port);
+}
+
+template<typename T>
+inline void rx_complete() {
+    crit_sec cs;
+    bool ferr = T::ferr();
+    midi::on_rx_complete(T::rx_traits::id, T::data(), ferr);
+}
+
+template<typename T>
+inline void process_bit() {
+    crit_sec cs;
+    splitter_state.process_bit(T::rx_traits::id, T::rx::read());
+}
+
+template<typename T>
+inline void process_dre() {
+    crit_sec cs;
+    T::on_dre_int();
+
+    midi::on_dre(T::rx_traits::id);
+}
+
 }
 
 namespace midi {
 
-void init() {
-    PORTC.INT0MASK = 0;
-    PORTC.INTCTRL = 0;
-
-    uart_c0::setup();
-    uart_c1::setup();
-    uart_d0::setup();
-    uart_e0::setup();
-    uart_e1::setup();
-    uart_f0::setup();
-    uart_f1::setup();
-
-    uart_c0::rxc_int_hi();
-    uart_c1::rxc_int_hi();
-    uart_d0::rxc_int_hi();
-    uart_e0::rxc_int_hi();
-    uart_e1::rxc_int_hi();
-    uart_f0::rxc_int_hi();
-    uart_f1::rxc_int_hi();
-}
-
-void splitter() {
-    uart_c0::disable();
-    uart_c1::disable();
-    uart_d0::disable();
-    uart_e0::disable();
-    uart_e1::disable();
-    uart_f0::disable();
-    uart_f1::disable();
-
-    uart_c0::port_traits::setup_pins();
-    uart_c1::port_traits::setup_pins();
-    uart_d0::port_traits::setup_pins();
-    uart_e0::port_traits::setup_pins();
-    uart_e1::port_traits::setup_pins();
-    uart_f0::port_traits::setup_pins();
-    uart_f1::port_traits::setup_pins();
-
-    PORTC.INT0MASK = (1 << 2);
-    PORTC.INTCTRL = PORT_INT0LVL_HI_gc;
+void init(process_byte_t cb) {
+    if (cb) {
+        splitter_state.disable();
+
+        on_rx_complete = cb;
+        on_dre = dummy_process_dre;
+    } else {
+        splitter_state.enable();
+
+        on_rx_complete = splitter_rx_complete;
+        on_dre = splitter_process_dre;
+    }
 }
 
 uint8_t send(uint8_t port, const uint8_t *buf, uint8_t size) {
-    switch (port) {
-    case 0: return uart_c0::write_buf(buf, size);
-    case 1: return uart_c1::write_buf(buf, size);
-    case 2: return uart_d0::write_buf(buf, size);
-    case 3: return uart_e0::write_buf(buf, size);
-    case 4: return uart_e1::write_buf(buf, size);
-    case 5: return uart_f0::write_buf(buf, size);
-    case 6: return uart_f1::write_buf(buf, size);
-    }
+    return UL::write_buf(port, buf, size);
+}
 
-    return 0;
+void pending_timeout() {
+    splitter_state.pending_timeout();
 }
 
+void dump_state() {
+    splitter_state.dump();
 }
 
+}
+
+
 ISR(USARTC0_RXC_vect)
 {
-    uart_c0::on_rxc_int();
+    rx_complete<uart_c0>();
 }
 
 ISR(USARTC0_DRE_vect)
 {
-    uart_c0::on_dre_int();
+    process_dre<uart_c0>();
+}
+
+ISR(PORTC_INT0_vect)
+{
+    process_bit<uart_c0>();
 }
 
 
 ISR(USARTC1_RXC_vect)
 {
-    uart_c1::on_rxc_int();
+    rx_complete<uart_c1>();
 }
 
 ISR(USARTC1_DRE_vect)
 {
-    uart_c1::on_dre_int();
+    process_dre<uart_c1>();
+}
+
+ISR(PORTC_INT1_vect)
+{
+    process_bit<uart_c1>();
 }
 
 
 ISR(USARTD0_RXC_vect)
 {
-    uart_d0::on_rxc_int();
+    rx_complete<uart_d0>();
 }
 
 ISR(USARTD0_DRE_vect)
 {
-    uart_d0::on_dre_int();
+    process_dre<uart_d0>();
 }
 
-ISR(PORTC_INT0_vect)
+ISR(PORTD_INT0_vect)
 {
-    crit_sec cs;
-
-    bool v = uart_c0::rx::read();
-
-    if (v) {
-        uart_c0::tx::high();
-        uart_c1::tx::high();
-        uart_d0::tx::high();
-        uart_e0::tx::high();
-        uart_e1::tx::high();
-        uart_f0::tx::high();
-        uart_f1::tx::high();
-    } else {
-        uart_c0::tx::low();
-        uart_c1::tx::low();
-        uart_d0::tx::low();
-        uart_e0::tx::low();
-        uart_e1::tx::low();
-        uart_f0::tx::low();
-        uart_f1::tx::low();
-
-        midi::rx_ready = 1;
-    }
+    process_bit<uart_d0>();
 }
 
 
 ISR(USARTE0_RXC_vect)
 {
-    uart_e0::on_rxc_int();
+    rx_complete<uart_e0>();
 }
 
 ISR(USARTE0_DRE_vect)
 {
-    uart_e0::on_dre_int();
+    process_dre<uart_e0>();
+}
+
+ISR(PORTE_INT0_vect)
+{
+    process_bit<uart_e0>();
 }
 
 
 ISR(USARTE1_RXC_vect)
 {
-    uart_e1::on_rxc_int();
+    rx_complete<uart_e1>();
 }
 
 ISR(USARTE1_DRE_vect)
 {
-    uart_e1::on_dre_int();
+    process_dre<uart_e1>();
+}
+
+ISR(PORTE_INT1_vect)
+{
+    process_bit<uart_e1>();
 }
 
 
 ISR(USARTF0_RXC_vect)
 {
-    uart_f0::on_rxc_int();
+    rx_complete<uart_f0>();
 }
 
 ISR(USARTF0_DRE_vect)
 {
-    uart_f0::on_dre_int();
+    process_dre<uart_f0>();
+}
+
+ISR(PORTF_INT0_vect)
+{
+    process_bit<uart_f0>();
 }
 
 
 ISR(USARTF1_RXC_vect)
 {
-    uart_f1::on_rxc_int();
+    rx_complete<uart_f1>();
 }
 
 ISR(USARTF1_DRE_vect)
 {
-    uart_f1::on_dre_int();
+    process_dre<uart_f1>();
+}
+
+ISR(PORTF_INT1_vect)
+{
+    process_bit<uart_f1>();
 }
diff --git a/firmware/src/artl/bits/port_traits.h b/firmware/src/artl/bits/port_traits.h
index 787816f..05dd94b 100644
--- a/firmware/src/artl/bits/port_traits.h
+++ b/firmware/src/artl/bits/port_traits.h
@@ -14,36 +14,81 @@ namespace port {
     struct traits {
     };
 
+    namespace mega {
+        template<typename PORT>
+        struct traits_base {
+        };
+
+        template<typename PORT>
+        struct traits {
+            using base_type = traits_base<PORT>;
+
+            static volatile uint8_t& dir() { return base_type::dir(); }
+            static void dirset(uint8_t mask) { dir() |= mask; }
+            static void dirclr(uint8_t mask) { dir() &= ~mask; }
+            static void dirtgl(uint8_t mask) { dir() ^= mask; }
+            static uint8_t in() { return base_type::in(); }
+            static volatile uint8_t& out() { return base_type::out(); }
+            static void outset(uint8_t mask) { out() |= mask; }
+            static void outclr(uint8_t mask) { out() &= ~mask; }
+            static void outtgl(uint8_t mask) { out() ^= mask; }
+        };
+    }
+
+    namespace xmega {
+        template<typename PORT>
+        struct traits_base {
+        };
+
+        template<typename PORT>
+        struct traits {
+            using base_type = traits_base<PORT>;
+
+            static volatile uint8_t& dir() { return base_type::port().DIR; }
+            static void dirset(uint8_t mask) { base_type::port().DIRSET = mask; }
+            static void dirclr(uint8_t mask) { base_type::port().DIRCLR = mask; }
+            static void dirtgl(uint8_t mask) { base_type::port().DIRTGL = mask; }
+            static uint8_t in() { return base_type::port().IN; }
+            static volatile uint8_t& out() { return base_type::port().OUT; }
+            static void outset(uint8_t mask) { base_type::port().OUTSET = mask; }
+            static void outclr(uint8_t mask) { base_type::port().OUTCLR = mask; }
+            static void outtgl(uint8_t mask) { base_type::port().OUTTGL = mask; }
+            static volatile uint8_t& intctrl() { return base_type::port().INTCTRL; }
+            static volatile uint8_t& int0mask() { return base_type::port().INT0MASK; }
+            static volatile uint8_t& int1mask() { return base_type::port().INT1MASK; }
+            static volatile uint8_t& intflags() { return base_type::port().INTFLAGS; }
+
+            inline __attribute__((always_inline))
+            static volatile uint8_t* pinctrl() { return &base_type::port().PIN0CTRL; }
+        };
+    }
+
 #if defined(PORTA)
 #if defined(DDRA) && defined(PINA)
 
+    namespace mega {
+        template<>
+        struct traits_base<A> {
+            static volatile uint8_t& dir() { return DDRA; }
+            static uint8_t in() { return PINA; }
+            static volatile uint8_t& out() { return PORTA; }
+        };
+    }
+
     template<>
-    struct traits<A> {
-        static volatile uint8_t& dir() { return DDRA; }
-        static void dirset(uint8_t mask) { dir() |= mask; }
-        static void dirclr(uint8_t mask) { dir() &= ~mask; }
-        static void dirtgl(uint8_t mask) { dir() ^= mask; }
-        static uint8_t in() { return PINA; }
-        static volatile uint8_t& out() { return PORTA; }
-        static void outset(uint8_t mask) { out() |= mask; }
-        static void outclr(uint8_t mask) { out() &= ~mask; }
-        static void outtgl(uint8_t mask) { out() ^= mask; }
-    };
+    struct traits<A> : public mega::traits<A> { };
 
 #else
 
+    namespace xmega {
+        template<>
+        struct traits_base<A> {
+            static volatile PORT_t& port() { return PORTA; }
+        };
+    }
+
     template<>
-    struct traits<A> {
-        static volatile uint8_t& dir() { return PORTA.DIR; }
-        static void dirset(uint8_t mask) { PORTA.DIRSET = mask; }
-        static void dirclr(uint8_t mask) { PORTA.DIRCLR = mask; }
-        static void dirtgl(uint8_t mask) { PORTA.DIRTGL = mask; }
-        static uint8_t in() { return PORTA.IN; }
-        static volatile uint8_t& out() { return PORTA.OUT; }
-        static void outset(uint8_t mask) { PORTA.OUTSET = mask; }
-        static void outclr(uint8_t mask) { PORTA.OUTCLR = mask; }
-        static void outtgl(uint8_t mask) { PORTA.OUTTGL = mask; }
-    };
+    struct traits<A> : public xmega::traits<A> { };
 
 #endif
 #endif
@@ -51,33 +96,29 @@ namespace port {
 #if defined(PORTB)
 #if defined(DDRB) && defined(PINB)
 
+    namespace mega {
+        template<>
+        struct traits_base<B> {
+            static volatile uint8_t& dir() { return DDRB; }
+            static uint8_t in() { return PINB; }
+            static volatile uint8_t& out() { return PORTB; }
+        };
+    }
+
     template<>
-    struct traits<B> {
-        static volatile uint8_t& dir() { return DDRB; }
-        static void dirset(uint8_t mask) { dir() |= mask; }
-        static void dirclr(uint8_t mask) { dir() &= ~mask; }
-        static void dirtgl(uint8_t mask) { dir() ^= mask; }
-        static uint8_t in() { return PINB; }
-        static volatile uint8_t& out() { return PORTB; }
-        static void outset(uint8_t mask) { out() |= mask; }
-        static void outclr(uint8_t mask) { out() &= ~mask; }
-        static void outtgl(uint8_t mask) { out() ^= mask; }
-    };
+    struct traits<B> : public mega::traits<B> { };
 
 #else
 
+    namespace xmega {
+        template<>
+        struct traits_base<B> {
+            static volatile PORT_t& port() { return PORTB; }
+        };
+    }
+
     template<>
-    struct traits<B> {
-        static volatile uint8_t& dir() { return PORTB.DIR; }
-        static void dirset(uint8_t mask) { PORTB.DIRSET = mask; }
-        static void dirclr(uint8_t mask) { PORTB.DIRCLR = mask; }
-        static void dirtgl(uint8_t mask) { PORTB.DIRTGL = mask; }
-        static uint8_t in() { return PORTB.IN; }
-        static volatile uint8_t& out() { return PORTB.OUT; }
-        static void outset(uint8_t mask) { PORTB.OUTSET = mask; }
-        static void outclr(uint8_t mask) { PORTB.OUTCLR = mask; }
-        static void outtgl(uint8_t mask) { PORTB.OUTTGL = mask; }
-    };
+    struct traits<B> : public xmega::traits<B> { };
 
 #endif
 #endif
@@ -85,33 +126,29 @@ namespace port {
 #if defined(PORTC)
 #if defined(DDRC) && defined(PINC)
 
+    namespace mega {
+        template<>
+        struct traits_base<C> {
+            static volatile uint8_t& dir() { return DDRC; }
+            static uint8_t in() { return PINC; }
+            static volatile uint8_t& out() { return PORTC; }
+        };
+    }
+
     template<>
-    struct traits<C> {
-        static volatile uint8_t& dir() { return DDRC; }
-        static void dirset(uint8_t mask) { dir() |= mask; }
-        static void dirclr(uint8_t mask) { dir() &= ~mask; }
-        static void dirtgl(uint8_t mask) { dir() ^= mask; }
-        static uint8_t in() { return PINC; }
-        static volatile uint8_t& out() { return PORTC; }
-        static void outset(uint8_t mask) { out() |= mask; }
-        static void outclr(uint8_t mask) { out() &= ~mask; }
-        static void outtgl(uint8_t mask) { out() ^= mask; }
-    };
+    struct traits<C> : public mega::traits<C> { };
 
 #else
 
+    namespace xmega {
+        template<>
+        struct traits_base<C> {
+            static volatile PORT_t& port() { return PORTC; }
+        };
+    }
+
     template<>
-    struct traits<C> {
-        static volatile uint8_t& dir() { return PORTC.DIR; }
-        static void dirset(uint8_t mask) { PORTC.DIRSET = mask; }
-        static void dirclr(uint8_t mask) { PORTC.DIRCLR = mask; }
-        static void dirtgl(uint8_t mask) { PORTC.DIRTGL = mask; }
-        static uint8_t in() { return PORTC.IN; }
-        static volatile uint8_t& out() { return PORTC.OUT; }
-        static void outset(uint8_t mask) { PORTC.OUTSET = mask; }
-        static void outclr(uint8_t mask) { PORTC.OUTCLR = mask; }
-        static void outtgl(uint8_t mask) { PORTC.OUTTGL = mask; }
-    };
+    struct traits<C> : public xmega::traits<C> { };
 
 #endif
 #endif
@@ -119,33 +156,29 @@ namespace port {
 #if defined(PORTD)
 #if defined(DDRD) && defined(PIND)
 
+    namespace mega {
+        template<>
+        struct traits_base<D> {
+            static volatile uint8_t& dir() { return DDRD; }
+            static uint8_t in() { return PIND; }
+            static volatile uint8_t& out() { return PORTD; }
+        };
+    }
+
     template<>
-    struct traits<D> {
-        static volatile uint8_t& dir() { return DDRD; }
-        static void dirset(uint8_t mask) { dir() |= mask; }
-        static void dirclr(uint8_t mask) { dir() &= ~mask; }
-        static void dirtgl(uint8_t mask) { dir() ^= mask; }
-        static uint8_t in() { return PIND; }
-        static volatile uint8_t& out() { return PORTD; }
-        static void outset(uint8_t mask) { out() |= mask; }
-        static void outclr(uint8_t mask) { out() &= ~mask; }
-        static void outtgl(uint8_t mask) { out() ^= mask; }
-    };
+    struct traits<D> : public mega::traits<D> { };
 
 #else
 
+    namespace xmega {
+        template<>
+        struct traits_base<D> {
+            static volatile PORT_t& port() { return PORTD; }
+        };
+    }
+
     template<>
-    struct traits<D> {
-        static volatile uint8_t& dir() { return PORTD.DIR; }
-        static void dirset(uint8_t mask) { PORTD.DIRSET = mask; }
-        static void dirclr(uint8_t mask) { PORTD.DIRCLR = mask; }
-        static void dirtgl(uint8_t mask) { PORTD.DIRTGL = mask; }
-        static uint8_t in() { return PORTD.IN; }
-        static volatile uint8_t& out() { return PORTD.OUT; }
-        static void outset(uint8_t mask) { PORTD.OUTSET = mask; }
-        static void outclr(uint8_t mask) { PORTD.OUTCLR = mask; }
-        static void outtgl(uint8_t mask) { PORTD.OUTTGL = mask; }
-    };
+    struct traits<D> : public xmega::traits<D> { };
 
 #endif
 #endif
@@ -153,33 +186,29 @@ namespace port {
 #if defined(PORTE)
 #if defined(DDRE) && defined(PINE)
 
+    namespace mega {
+        template<>
+        struct traits_base<E> {
+            static volatile uint8_t& dir() { return DDRE; }
+            static uint8_t in() { return PINE; }
+            static volatile uint8_t& out() { return PORTE; }
+        };
+    }
+
     template<>
-    struct traits<E> {
-        static volatile uint8_t& dir() { return DDRE; }
-        static void dirset(uint8_t mask) { dir() |= mask; }
-        static void dirclr(uint8_t mask) { dir() &= ~mask; }
-        static void dirtgl(uint8_t mask) { dir() ^= mask; }
-        static uint8_t in() { return PINE; }
-        static volatile uint8_t& out() { return PORTE; }
-        static void outset(uint8_t mask) { out() |= mask; }
-        static void outclr(uint8_t mask) { out() &= ~mask; }
-        static void outtgl(uint8_t mask) { out() ^= mask; }
-    };
+    struct traits<E> : public mega::traits<E> { };
 
 #else
 
+    namespace xmega {
+        template<>
+        struct traits_base<E> {
+            static volatile PORT_t& port() { return PORTE; }
+        };
+    }
+
     template<>
-    struct traits<E> {
-        static volatile uint8_t& dir() { return PORTE.DIR; }
-        static void dirset(uint8_t mask) { PORTE.DIRSET = mask; }
-        static void dirclr(uint8_t mask) { PORTE.DIRCLR = mask; }
-        static void dirtgl(uint8_t mask) { PORTE.DIRTGL = mask; }
-        static uint8_t in() { return PORTE.IN; }
-        static volatile uint8_t& out() { return PORTE.OUT; }
-        static void outset(uint8_t mask) { PORTE.OUTSET = mask; }
-        static void outclr(uint8_t mask) { PORTE.OUTCLR = mask; }
-        static void outtgl(uint8_t mask) { PORTE.OUTTGL = mask; }
-    };
+    struct traits<E> : public xmega::traits<E> { };
 
 #endif
 #endif
@@ -187,102 +216,86 @@ namespace port {
 #if defined(PORTF)
 #if defined(DDRF) && defined(PINF)
 
+    namespace mega {
+        template<>
+        struct traits_base<F> {
+            static volatile uint8_t& dir() { return DDRF; }
+            static uint8_t in() { return PINF; }
+            static volatile uint8_t& out() { return PORTF; }
+        };
+    }
+
     template<>
-    struct traits<F> {
-        static volatile uint8_t& dir() { return DDRF; }
-        static void dirset(uint8_t mask) { dir() |= mask; }
-        static void dirclr(uint8_t mask) { dir() &= ~mask; }
-        static void dirtgl(uint8_t mask) { dir() ^= mask; }
-        static uint8_t in() { return PINF; }
-        static volatile uint8_t& out() { return PORTF; }
-        static void outset(uint8_t mask) { out() |= mask; }
-        static void outclr(uint8_t mask) { out() &= ~mask; }
-        static void outtgl(uint8_t mask) { out() ^= mask; }
-    };
+    struct traits<F> : public mega::traits<F> { };
 
 #else
 
+    namespace xmega {
+        template<>
+        struct traits_base<F> {
+            static volatile PORT_t& port() { return PORTF; }
+        };
+    }
+
     template<>
-    struct traits<F> {
-        static volatile uint8_t& dir() { return PORTF.DIR; }
-        static void dirset(uint8_t mask) { PORTF.DIRSET = mask; }
-        static void dirclr(uint8_t mask) { PORTF.DIRCLR = mask; }
-        static void dirtgl(uint8_t mask) { PORTF.DIRTGL = mask; }
-        static uint8_t in() { return PORTF.IN; }
-        static volatile uint8_t& out() { return PORTF.OUT; }
-        static void outset(uint8_t mask) { PORTF.OUTSET = mask; }
-        static void outclr(uint8_t mask) { PORTF.OUTCLR = mask; }
-        static void outtgl(uint8_t mask) { PORTF.OUTTGL = mask; }
-    };
+    struct traits<F> : public xmega::traits<F> { };
 
 #endif
 #endif
 
 #if defined(PORTH)
 
+    namespace xmega {
+        template<>
+        struct traits_base<H> {
+            static volatile PORT_t& port() { return PORTH; }
+        };
+    }
+
     template<>
-    struct traits<H> {
-        static volatile uint8_t& dir() { return PORTH.DIR; }
-        static void dirset(uint8_t mask) { PORTH.DIRSET = mask; }
-        static void dirclr(uint8_t mask) { PORTH.DIRCLR = mask; }
-        static void dirtgl(uint8_t mask) { PORTH.DIRTGL = mask; }
-        static uint8_t in() { return PORTH.IN; }
-        static volatile uint8_t& out() { return PORTH.OUT; }
-        static void outset(uint8_t mask) { PORTH.OUTSET = mask; }
-        static void outclr(uint8_t mask) { PORTH.OUTCLR = mask; }
-        static void outtgl(uint8_t mask) { PORTH.OUTTGL = mask; }
-    };
+    struct traits<H> : public xmega::traits<H> { };
 
 #endif
 
 #if defined(PORTJ)
 
+    namespace xmega {
+        template<>
+        struct traits_base<J> {
+            static volatile PORT_t& port() { return PORTJ; }
+        };
+    }
+
     template<>
-    struct traits<J> {
-        static volatile uint8_t& dir() { return PORTJ.DIR; }
-        static void dirset(uint8_t mask) { PORTJ.DIRSET = mask; }
-        static void dirclr(uint8_t mask) { PORTJ.DIRCLR = mask; }
-        static void dirtgl(uint8_t mask) { PORTJ.DIRTGL = mask; }
-        static uint8_t in() { return PORTJ.IN; }
-        static volatile uint8_t& out() { return PORTJ.OUT; }
-        static void outset(uint8_t mask) { PORTJ.OUTSET = mask; }
-        static void outclr(uint8_t mask) { PORTJ.OUTCLR = mask; }
-        static void outtgl(uint8_t mask) { PORTJ.OUTTGL = mask; }
-    };
+    struct traits<J> : public xmega::traits<J> { };
 
 #endif
 
 #if defined(PORTK)
 
+    namespace xmega {
+        template<>
+        struct traits_base<K> {
+            static volatile PORT_t& port() { return PORTK; }
+        };
+    }
+
     template<>
-    struct traits<K> {
-        static volatile uint8_t& dir() { return PORTK.DIR; }
-        static void dirset(uint8_t mask) { PORTK.DIRSET = mask; }
-        static void dirclr(uint8_t mask) { PORTK.DIRCLR = mask; }
-        static void dirtgl(uint8_t mask) { PORTK.DIRTGL = mask; }
-        static uint8_t in() { return PORTK.IN; }
-        static volatile uint8_t& out() { return PORTK.OUT; }
-        static void outset(uint8_t mask) { PORTK.OUTSET = mask; }
-        static void outclr(uint8_t mask) { PORTK.OUTCLR = mask; }
-        static void outtgl(uint8_t mask) { PORTK.OUTTGL = mask; }
-    };
+    struct traits<K> : public xmega::traits<K> { };
 
 #endif
 
 #if defined(PORTQ)
 
+    namespace xmega {
+        template<>
+        struct traits_base<Q> {
+            static volatile PORT_t& port() { return PORTQ; }
+        };
+    }
+
     template<>
-    struct traits<Q> {
-        static volatile uint8_t& dir() { return PORTQ.DIR; }
-        static void dirset(uint8_t mask) { PORTQ.DIRSET = mask; }
-        static void dirclr(uint8_t mask) { PORTQ.DIRCLR = mask; }
-        static void dirtgl(uint8_t mask) { PORTQ.DIRTGL = mask; }
-        static uint8_t in() { return PORTQ.IN; }
-        static volatile uint8_t& out() { return PORTQ.OUT; }
-        static void outset(uint8_t mask) { PORTQ.OUTSET = mask; }
-        static void outclr(uint8_t mask) { PORTQ.OUTCLR = mask; }
-        static void outtgl(uint8_t mask) { PORTQ.OUTTGL = mask; }
-    };
+    struct traits<Q> : public xmega::traits<Q> { };
 
 #endif
 
diff --git a/firmware/src/artl/timer.h b/firmware/src/artl/timer.h
index c997583..2bd137a 100644
--- a/firmware/src/artl/timer.h
+++ b/firmware/src/artl/timer.h
@@ -11,16 +11,17 @@ template<typename CALLBACK = default_timer_handler>
 struct timer : public CALLBACK {
 
     using CALLBACK::CALLBACK;
+    using time_type = unsigned long;
 
-    constexpr unsigned long max_delay() const {
+    constexpr time_type max_delay() const {
         return ((unsigned long) -1) / 2;
     }
 
-    void schedule(unsigned long t) { at_ = t; }
+    void schedule(time_type t) { at_ = t; }
 
     void cancel() { at_ = 0; }
 
-    bool update(unsigned long t) {
+    bool update(time_type t) {
         if (at_ != 0 && t - at_ < max_delay()) {
             at_ = 0;
             (*this)(t);
@@ -33,8 +34,10 @@ struct timer : public CALLBACK {
 
     bool active() const { return at_ != 0; }
 
+    time_type at() const { return at_; }
+
 private:
-    unsigned long at_ = 0;
+    time_type at_ = 0;
 };
 
 }
diff --git a/firmware/src/blink_state.h b/firmware/src/blink_state.h
index 807f5c4..e33201a 100644
--- a/firmware/src/blink_state.h
+++ b/firmware/src/blink_state.h
@@ -9,6 +9,9 @@ struct blink_state_t {
         ACTIVE = 0x1000,
         MIN_ACTIVE = ACTIVE - 0x100,
         STEP = 0x40,
+
+        START_ERROR = 0x8000,
+        MIN_ERROR = STEP,
     };
 
     static bool get(uint16_t state) {
@@ -22,16 +25,28 @@ struct blink_state_t {
         return ((state & 0xFF) <= p);
     }
 
-    bool get() const { return get(state); }
+    bool get() const {
+        return error_state ? (state > (START_ERROR / 2)) : get(state);
+    }
 
     inline __attribute__((always_inline))
-    void start() { if (state <= MIN) { state = START; } }
+    void start() { if (state <= MIN && !error_state) { state = START; } }
 
     void stop() { state = 0; }
     void active() {
-        active_state = 0x80 * STEP;
+        if (!error_state) {
+            active_state = 0x80;
 
-        if (state < MIN_ACTIVE) { state = ACTIVE; }
+            if (state < MIN_ACTIVE) { state = ACTIVE; }
+        }
+    }
+
+    void error() {
+        if (!error_state) {
+            state = START_ERROR,
+            active_state = 0;
+        }
+        error_state = 5;
     }
 
     operator bool() const { return state != 0; }
@@ -41,7 +56,15 @@ struct blink_state_t {
 
         if (active_state && state < MIN_ACTIVE) {
             state += 0x100;
-            active_state -= STEP;
+            active_state -= 1;
+        }
+
+        if (error_state) {
+            if (state) { state -= STEP; }
+            if (state < MIN_ERROR) {
+                state = START_ERROR;
+                error_state -= 1;
+            }
         }
     }
 
@@ -67,6 +90,7 @@ struct blink_state_t {
     }
 
     uint16_t state = 0;
-    uint16_t active_state = 0;
+    uint8_t active_state = 0;
+    uint8_t error_state = 0;
     bool last_write = false;
 };
diff --git a/firmware/src/cdc_print.h b/firmware/src/cdc_print.h
index 1f71f43..e0988d8 100644
--- a/firmware/src/cdc_print.h
+++ b/firmware/src/cdc_print.h
@@ -1,9 +1,9 @@
 
 #pragma once
 
-namespace {
+extern bool cdc_dtr;
 
-bool cdc_dtr = false;
+namespace {
 
 void _cdc_print_eol() __attribute__((unused));
 void cdc_print_eol() __attribute__((unused));
diff --git a/firmware/src/main.cpp b/firmware/src/main.cpp
index 240656f..414b0a3 100644
--- a/firmware/src/main.cpp
+++ b/firmware/src/main.cpp
@@ -50,6 +50,8 @@ extern "C" {
 #include "rst_blink.h"
 #include "usb_midi_buf.h"
 
+bool cdc_dtr = false;
+
 namespace {
 
 volatile bool cdc_enabled = false;
@@ -67,6 +69,8 @@ uint32_t stat_period = 0;
 bool stat_auto_reset = 0;
 midi_cmd_t current_cmd[MIDI_PORTS];
 
+void usb_midi_enable(bool enable);
+
 template<typename T>
 void usb_midi_send(const T& c, uint8_t jack);
 bool midi_send(const usb_midi_event_t &ev, uint8_t jack, bool stall);
@@ -97,7 +101,7 @@ int main(void)
     ui::powerdown();
 
     sleepmgr_lock_mode(SLEEPMGR_IDLE);
-    midi::splitter();
+    midi::init();
 
     main_read_serial();
 
@@ -132,11 +136,8 @@ int main(void)
                     case 2:
                         ui::led_test_disable();
                         active_test_timer.cancel();
-                        if (usb_midi_enabled) {
-                            udc_stop();
-                        } else {
-                            udc_start();
-                        }
+
+                        usb_midi_enable(!usb_midi_enabled);
                         break;
 
                     case 3:
@@ -156,13 +157,6 @@ int main(void)
                 rst_blink_update(t);
             }
 
-            if (!usb_midi_enabled && midi::rx_ready) {
-                midi::rx_ready = 0;
-
-                ui::rx_blink(0);
-                ui::tx_blink();
-            }
-
             if (stat_timer.update(t)) {
                 stat_timer.schedule(t + stat_period);
 
@@ -172,18 +166,26 @@ int main(void)
             if (active_test_timer.update(t)) {
                 active_test_timer.schedule(t + 300);
 
-                uint8_t b = CMD_SYS_ACTIVE_S;
+                uint8_t b[] = { CMD_SYS_ACTIVE_S, CMD_SYS_TICK };
 
-                for(uint8_t i = 0; i < MIDI_PORTS; ++i) {
-                    midi::port_stat_t &stat = midi::port_stat[i];
+                if (usb_midi_enabled) {
+                    for(uint8_t i = 0; i < MIDI_PORTS; ++i) {
+                        uint8_t res = midi::send(i, &b[i % 2], 1);
+                        if (res == 1) {
+                            midi::port_stat_t &stat = midi::port_stat[i];
 
-                    ++stat.snd_bytes;
-                    ++stat.snd_msgs;
+                            ++stat.snd_bytes;
+                            ++stat.snd_msgs;
 
-                    ui::tx_active(i);
-                    midi::send(i, &b, 1);
+                            ui::tx_data((i % 2) == 0, i);
+                        }
+                    }
                 }
             }
+
+            if (midi::pending_timer.update(t)) {
+                midi::pending_timeout();
+            }
         }
 
         if (last_dtr != cdc_dtr) {
@@ -206,14 +208,19 @@ int main(void)
     }
 }
 
-void midi_process_byte(uint8_t port, uint8_t data) {
+void midi_process_byte(uint8_t port, uint8_t data, bool ferr) {
     ++midi::port_stat[port].rcv_bytes;
     midi::port_stat_update = true;
 
-    if (data == CMD_SYS_ACTIVE_S) {
-        ui::rx_active(port);
+    if (ferr) {
+        ui::rx_error(port);
+        ++midi::port_stat[port].rcv_err;
     } else {
-        ui::rx_blink(port);
+        ui::rx_data(data == CMD_SYS_ACTIVE_S, port);
+    }
+
+    if (!usb_midi_enabled) {
+        return;
     }
 
     if (is_midi_rt(data)) {
@@ -233,10 +240,13 @@ void midi_process_byte(uint8_t port, uint8_t data) {
         current_cmd[port].reset();
     }
 
-    current_cmd[port].read(data);
-    if (current_cmd[port].ready()) {
-        usb_midi_send(current_cmd[port], port);
-        current_cmd[port].reset();
+    midi_cmd_t &cmd = current_cmd[port];
+    cmd.read(data);
+    if (cmd.ready()) {
+        midi_mon(port, true, cmd, cmd.size());
+
+        usb_midi_send(cmd, port);
+        cmd.reset();
 
         ++midi::port_stat[port].rcv_msgs;
     }
@@ -431,11 +441,6 @@ void stat_print(bool auto_update) {
         MAX_FIELD = midi::port_stat_t::MAX_FIELD,
     };
 
-    const char *t[MAX_FIELD] = {
-        "Rbyte", "Rmsg",
-        "Sbyte", "Smsg", "Sovf",
-        "STms", "STbyte", "STmsg" };
-
     uint8_t w[MAX_FIELD];
 
     if (auto_update) {
@@ -449,7 +454,14 @@ void stat_print(bool auto_update) {
     midi::port_stat_update = false;
 
     for (uint8_t j = 0; j < MAX_FIELD; ++j) {
-        w[j] = 1 + strlen(t[j]);
+        w[j] = 1 + midi::port_stat_t::title_len[j];
+
+        for (uint8_t i = 0; i <= MIDI_PORTS; ++i) {
+            const midi::port_stat_t &s = midi::port_stat[i];
+
+            uint8_t m = 1 + cdc_get_width(s[j]);
+            if (m > w[j]) { w[j] = m; }
+        }
     }
 
     for (uint8_t i = 0; i <= MIDI_PORTS; ++i) {
@@ -463,7 +475,7 @@ void stat_print(bool auto_update) {
 
     _cdc_print('#');
     for (uint8_t j = 0; j < MAX_FIELD; ++j) {
-        _cdc_print_w(t[j], w[j]);
+        _cdc_print_w(midi::port_stat_t::title[j], w[j]);
     }
     _cdc_println();
 
@@ -482,6 +494,8 @@ void stat_print(bool auto_update) {
         _cdc_println();
     }
 
+    midi::dump_state();
+
     if (stat_auto_reset) {
         stat_reset();
     }
@@ -549,14 +563,28 @@ void usb_midi_received(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep)
     usb_recv_process();
 }
 
-bool udi_midi_enable(void) {
-    if (!usb_midi_enabled) {
-        usb_midi_enabled = true;
+void usb_midi_enable(bool enable) {
+    if (usb_midi_enabled == enable) {
+        return;
+    }
+
+    usb_midi_enabled = enable;
+
+    if (enable) {
         sleepmgr_unlock_mode(SLEEPMGR_IDLE);
+
+        ui::usb_midi_enable();
+        midi::init(midi_process_byte);
+    } else {
+        sleepmgr_lock_mode(SLEEPMGR_IDLE);
+
+        ui::usb_midi_disable();
+        midi::init();
     }
+}
 
-    ui::usb_midi_enable();
-    midi::init();
+bool udi_midi_enable(void) {
+    usb_midi_enable(true);
 
     udd_ep_run(UDI_MIDI_EP_OUT,
         true,
@@ -586,13 +614,9 @@ void usb_recv_process() {
 }
 
 void udi_midi_disable(void) {
-    if (usb_midi_enabled) {
-        usb_midi_enabled = false;
-        sleepmgr_lock_mode(SLEEPMGR_IDLE);
-    }
+    usb_midi_enable(false);
 
-    ui::usb_midi_disable();
-    midi::splitter();
+    cdc_dtr = false;
 }
 
 void usb_midi_flush();
diff --git a/firmware/src/midi.cpp b/firmware/src/midi.cpp
index 17630fe..f2cd132 100644
--- a/firmware/src/midi.cpp
+++ b/firmware/src/midi.cpp
@@ -3,7 +3,17 @@
 
 namespace midi {
 
-volatile uint8_t rx_ready;
+const char *port_stat_t::title[port_stat_t::MAX_FIELD] = {
+    "Rbyte", "Rmsg", "Rovf", "Rerr", "Rcmd", "Rto",
+    "Sbyte", "Smsg", "Sovf",
+    "STms", "STbyte", "STmsg",
+};
+
+const uint8_t port_stat_t::title_len[port_stat_t::MAX_FIELD] = {
+    5, 4, 4, 4, 4, 3,
+    5, 4, 4,
+    4, 6, 5,
+};
 
 port_stat_t port_stat[MIDI_PORTS + 1];
 bool port_stat_update = false;
@@ -13,6 +23,11 @@ bool port_out_mon[MIDI_PORTS];
 
 bool port_mon = false;
 
+artl::timer<> pending_timer;
+
+process_byte_t on_rx_complete;
+process_dre_t on_dre;
+
 void start_mon() {
     for (uint8_t i = 0; i < MIDI_PORTS; ++i) {
         port_in_mon[i] = true;
@@ -29,4 +44,6 @@ void stop_mon() {
     port_mon = false;
 }
 
+void dummy_process_dre(uint8_t port) { }
+
 }
diff --git a/firmware/src/midi.h b/firmware/src/midi.h
index 69745a7..1b6c3b5 100644
--- a/firmware/src/midi.h
+++ b/firmware/src/midi.h
@@ -5,16 +5,18 @@ extern "C" {
 }
 
 #include "ring.h"
+#include "artl/timer.h"
 
 namespace midi {
 
-extern volatile uint8_t rx_ready;
-
 struct port_stat_t {
     enum {
-        MAX_FIELD = 8,
+        MAX_FIELD = 12,
     };
 
+    static const char *title[MAX_FIELD];
+    static const uint8_t title_len[MAX_FIELD];
+
     uint32_t operator[](uint8_t i) const {
         return (&rcv_bytes)[i];
     }
@@ -22,6 +24,10 @@ struct port_stat_t {
     void reset() {
         rcv_bytes = 0;
         rcv_msgs = 0;
+        rcv_ovf = 0;
+        rcv_err = 0;
+        rcv_cmd = 0;
+        rcv_to = 0;
         snd_bytes = 0;
         snd_msgs = 0;
         snd_ovf = 0;
@@ -32,6 +38,10 @@ struct port_stat_t {
 
     uint32_t rcv_bytes = 0;
     uint32_t rcv_msgs = 0;
+    uint32_t rcv_ovf = 0;
+    uint32_t rcv_err = 0;
+    uint32_t rcv_cmd = 0;
+    uint32_t rcv_to = 0;
     uint32_t snd_bytes = 0;
     uint32_t snd_msgs = 0;
     uint32_t snd_ovf = 0;
@@ -42,6 +52,9 @@ struct port_stat_t {
     uint32_t stall_start = 0;
 };
 
+using process_byte_t = void (*)(uint8_t port, uint8_t data, bool ferr);
+using process_dre_t = void (*)(uint8_t port);
+
 extern port_stat_t port_stat[MIDI_PORTS + 1];
 extern bool port_stat_update;
 
@@ -49,17 +62,25 @@ extern bool port_mon;
 extern bool port_in_mon[MIDI_PORTS];
 extern bool port_out_mon[MIDI_PORTS];
 
-void init();
-void splitter();
+extern artl::timer<> pending_timer;
+
+extern process_byte_t on_rx_complete;
+extern process_dre_t on_dre;
+
+void init(process_byte_t cb = NULL);
 
 uint8_t send(uint8_t port, const uint8_t *buf, uint8_t size);
+void pending_timeout();
+
+void dump_state();
 
 void start_mon();
 void stop_mon();
 
+void dummy_process_dre(uint8_t port);
+
 }
 
-extern void midi_process_byte(uint8_t port, uint8_t data);
 extern void midi_send_ready(uint8_t port, uint8_t size);
 
 template<uint8_t ID>
@@ -69,7 +90,7 @@ struct rx_midi_traits {
     };
 
     static inline void on_rx(uint8_t d) {
-        midi_process_byte(id, d);
+        midi_process_byte(id, d, false);
     }
 };
 
diff --git a/firmware/src/ring.h b/firmware/src/ring.h
index 9fa1f5c..f3e1dfe 100644
--- a/firmware/src/ring.h
+++ b/firmware/src/ring.h
@@ -27,6 +27,7 @@ struct ring {
     bool empty() const { return begin == end; }
     bool full() const { return begin == (end + 1) % MAX; }
     index_t size() const { return (end + MAX - begin) % MAX; }
+    void clear() { begin = end; }
 
     void reset() {
         begin = 0;
diff --git a/firmware/src/splitter.h b/firmware/src/splitter.h
new file mode 100644
index 0000000..be1723d
--- /dev/null
+++ b/firmware/src/splitter.h
@@ -0,0 +1,262 @@
+#pragma once
+
+extern "C" {
+#include "asf.h"
+}
+
+#include "ring.h"
+#include "midi.h"
+#include "midi_cmd.h"
+#include "ui.h"
+#include "timer.h"
+#include "cdc_print.h"
+
+namespace midi {
+
+template<typename UL>
+struct splitter_t {
+    enum {
+        ALL_PORTS_MASK = ((1 << MIDI_PORTS) - 1),
+        PENDING_TIMEOUT_MS = 2,
+    };
+
+    void setup() {
+        UL::setup();
+        UL::rxc_int_hi();
+    }
+
+    inline void enable() {
+        setup();
+
+        dre_wait_mask = 0;
+
+        port_queue_clear();
+        pending_bytes = 0;
+
+        last_byte_time = 0;
+        pending_timer.cancel();
+
+        for (uint8_t i = 0; i < MIDI_PORTS + 1; ++i) {
+            port_byte_queue[i].clear();
+        }
+        rt_queue.clear();
+
+        port_stat_update = true;
+    }
+
+    inline void disable() {
+        dre_wait_mask = 0;
+
+        setup();
+
+        port_stat_update = true;
+    }
+
+    void process_bit(uint8_t port, bool b) {
+        if (b) {
+            UL::tx_high();
+        } else {
+            UL::tx_low();
+        }
+    }
+
+    void rx_complete(uint8_t port, uint8_t data, bool ferr) {
+        port_stat_t &pstat = port_stat[port];
+
+        ++pstat.rcv_bytes;
+        port_stat_update = true;
+
+        if (ferr) {
+            ui::rx_error(port);
+            ++pstat.rcv_err;
+        } else {
+            ui::rx_data(data == CMD_SYS_ACTIVE_S, port);
+        }
+
+        bool is_cmd = is_midi_cmd(data);
+
+        if (is_cmd) {
+            ++pstat.rcv_msgs;
+        }
+
+        if (is_midi_rt(data)) {
+            if (rt_queue.full()) {
+                rt_queue.pop_front();
+                ui::rx_error(port);
+                ++pstat.rcv_ovf;
+            }
+
+            rt_queue.push_back(data);
+
+            if (dre_wait_mask == 0) {
+                process_queue();
+            }
+
+            return;
+        }
+
+        auto &q = port_byte_queue[port];
+
+        if (q.full()) {
+            ui::rx_error(port);
+            ++pstat.rcv_ovf;
+
+            return;
+        }
+
+        if (q.empty() && !is_cmd && (port_queue_mask == 0 || port_queue.front() != port)) {
+            ui::rx_error(port);
+            ++pstat.rcv_cmd;
+
+            return;
+        }
+
+        port_queue_add(port);
+        q.push_back(data);
+
+        if (dre_wait_mask == 0 && port_queue.front() == port) {
+            process_queue();
+
+            return;
+        }
+
+        if (last_byte_time != 0 && !pending_timer.active()) {
+            pending_timer.schedule(last_byte_time + PENDING_TIMEOUT_MS);
+        }
+    }
+
+    void process_dre(uint8_t port) {
+        dre_wait_mask &= ~(1 << port);
+
+        if (dre_wait_mask == 0) {
+            process_queue();
+        }
+    }
+
+    void pending_timeout() {
+        if (dre_wait_mask != 0) {
+            return;
+        }
+
+        uint8_t port = port_queue_pop();
+
+        ui::rx_error(port);
+        ++port_stat[port].rcv_to;
+
+        process_queue();
+    }
+
+    void dump() {
+        cdc_println("drew: ", dre_wait_mask);
+        cdc_println("bp:  ", pending_bytes);
+        cdc_println("pq(m/s/f): ", port_queue_mask, " ", port_queue.size(), " ", port_queue.front());
+    }
+
+private:
+    void send(uint8_t data) {
+        UL::write_byte(data);
+
+        if (!UL::tx_ring_empty()) {
+            dre_wait_mask = ALL_PORTS_MASK;
+        }
+
+        if (is_midi_cmd(data)) {
+            if (data == CMD_SYS_ACTIVE_S) {
+                ui::tx_active();
+            } else {
+                ui::tx_blink();
+            }
+        }
+    }
+
+    inline void port_queue_add(uint8_t port) {
+        if ((port_queue_mask & (1 << port)) == 0) {
+            port_queue_mask |= (1 << port);
+
+            port_queue.push_back(port);
+        }
+    }
+
+    inline uint8_t port_queue_pop() {
+        uint8_t port = port_queue.pop_front();
+        if (port_byte_queue[port].empty()) {
+            port_queue_mask &= ~(1 << port);
+        } else {
+            port_queue.push_back(port);
+        }
+        return port;
+    }
+
+    void port_queue_clear() {
+        port_queue_mask = 0;
+        port_queue.clear();
+    }
+
+    void process_queue() {
+        uint8_t data;
+
+        if (!rt_queue.empty()) {
+            data = rt_queue.pop_front();
+        } else {
+            if (port_queue.empty()) {
+                return false;
+            }
+
+            uint8_t port = port_queue.front();
+            auto &q = port_byte_queue[port];
+
+            if (q.empty()) {
+                return false;
+            }
+
+            data = q.pop_front();
+
+            if (update_pending_bytes(data) == 0) {
+                port_queue_pop();
+            }
+        }
+
+        send(data);
+    }
+
+    inline uint8_t update_pending_bytes(uint8_t data) {
+        uint8_t s = midi_cmd_t::cmd_size(data);
+        if (s == 0) {
+            if (pending_bytes != 0 && pending_bytes != 0xFF) {
+                --pending_bytes;
+            }
+        } else {
+            if (data != CMD_SYS_EX) {
+                pending_bytes = s - 1;
+            } else {
+                pending_bytes = 0xFF;
+            }
+        }
+
+        if (pending_bytes != 0) {
+            last_byte_time = millis_();
+
+            if (port_queue.size() > 1) {
+                pending_timer.schedule(last_byte_time + PENDING_TIMEOUT_MS);
+            }
+        } else {
+            last_byte_time = 0;
+            pending_timer.cancel();
+        }
+
+        return pending_bytes;
+    }
+
+    uint8_t dre_wait_mask = 0;
+
+    ring<MIDI_PORTS + 2, uint8_t> port_queue;
+    uint8_t port_queue_mask = 0;
+
+    uint8_t pending_bytes = 0;
+    unsigned long last_byte_time = 0;
+
+    ring<16, uint8_t> port_byte_queue[MIDI_PORTS + 1];
+    ring<8, uint8_t> rt_queue;
+};
+
+}
diff --git a/firmware/src/uart.h b/firmware/src/uart.h
index d105347..d0f0dfd 100644
--- a/firmware/src/uart.h
+++ b/firmware/src/uart.h
@@ -11,132 +11,84 @@ namespace port {
 template<typename PORT>
 struct traits { };
 
-struct C0 { };
-
-template<>
-struct traits<C0> {
-    using rx = artl::digital_in<artl::port::C, 2>;
-    using tx = artl::digital_out<artl::port::C, 3>;
-
-    static USART_t& uart() { return USARTC0; }
+template<typename PORT, uint8_t RX_BIT, uint8_t TX_BIT>
+struct pin_traits : public artl::port::traits<PORT> {
+    using port_traits = artl::port::traits<PORT>;
+    using rx = artl::digital_in<PORT, RX_BIT>;
+    using tx = artl::digital_out<PORT, TX_BIT>;
 
     static void setup_pins() {
         setup_rx();
         setup_tx();
-        setup_pr();
     }
 
     static void setup_rx() {
-        PORTC.PIN2CTRL = 0;
+        port_traits::pinctrl()[rx::traits::bit_no] = 0;
         rx::input();
         rx::pulldown();
     }
 
     static void setup_tx() {
-        PORTC.PIN3CTRL = 0;
+        port_traits::pinctrl()[tx::traits::bit_no] = 0;
         tx::output();
         tx::high();
     }
-
-    static void setup_pr() {
-        PR.PRPC &= ~PR_USART0_bm;
-    }
 };
 
-struct C1 { };
+struct C0 { };
 
 template<>
-struct traits<C1> {
-    using rx = artl::digital_in<artl::port::C, 6>;
-    using tx = artl::digital_out<artl::port::C, 7>;
-
-    static USART_t& uart() { return USARTC1; }
+struct traits<C0> : public pin_traits<artl::port::C, 2, 3> {
+    static USART_t& uart() { return USARTC0; }
+    static void setup_pr() { PR.PRPC &= ~PR_USART0_bm; }
 
-    static void setup_pins() {
-        setup_rx();
-        setup_tx();
-        setup_pr();
-    }
+    enum {
+        INT_LEVEL = PORT_INT0LVL_HI_gc,
+        INT_FLAGS = PORT_INT0IF_bm,
+    };
+    static volatile uint8_t& intmask() { return port_traits::int0mask(); }
+};
 
-    static void setup_rx() {
-        PORTC.PIN6CTRL = 0;
-        rx::input();
-        rx::pulldown();
-    }
+struct C1 { };
 
-    static void setup_tx() {
-        PORTC.PIN7CTRL = 0;
-        tx::output();
-        tx::high();
-    }
+template<>
+struct traits<C1> : public pin_traits<artl::port::C, 6, 7> {
+    static USART_t& uart() { return USARTC1; }
+    static void setup_pr() { PR.PRPC &= ~PR_USART1_bm; }
 
-    static void setup_pr() {
-        PR.PRPC &= ~PR_USART1_bm;
-    }
+    enum {
+        INT_LEVEL = PORT_INT1LVL_HI_gc,
+        INT_FLAGS = PORT_INT1IF_bm,
+    };
+    static volatile uint8_t& intmask() { return port_traits::int1mask(); }
 };
 
 struct D0 { };
 
 template<>
-struct traits<D0> {
-    using rx = artl::digital_in<artl::port::D, 2>;
-    using tx = artl::digital_out<artl::port::D, 3>;
-
+struct traits<D0> : public pin_traits<artl::port::D, 2, 3> {
     static USART_t& uart() { return USARTD0; }
+    static void setup_pr() { PR.PRPD &= ~PR_USART0_bm; }
 
-    static void setup_pins() {
-        setup_rx();
-        setup_tx();
-        setup_pr();
-    }
-
-    static void setup_rx() {
-        PORTD.PIN2CTRL = 0;
-        rx::input();
-        rx::pulldown();
-    }
-
-    static void setup_tx() {
-        PORTD.PIN3CTRL = 0;
-        tx::output();
-        tx::high();
-    }
-
-    static void setup_pr() {
-        PR.PRPD &= ~PR_USART0_bm;
-    }
+    enum {
+        INT_LEVEL = PORT_INT0LVL_HI_gc,
+        INT_FLAGS = PORT_INT0IF_bm,
+    };
+    static volatile uint8_t& intmask() { return port_traits::int0mask(); }
 };
 
 struct E0 { };
 
 template<>
-struct traits<E0> {
-    using rx = artl::digital_in<artl::port::E, 2>;
-    using tx = artl::digital_out<artl::port::E, 3>;
-
+struct traits<E0> : public pin_traits<artl::port::E, 2, 3> {
     static USART_t& uart() { return USARTE0; }
+    static void setup_pr() { PR.PRPE &= ~PR_USART0_bm; }
 
-    static void setup_pins() {
-        setup_rx();
-        setup_tx();
-        setup_pr();
-    }
-
-    static void setup_rx() {
-        PORTE.PIN2CTRL = 0;
-        rx::input();
-        rx::pulldown();
-    }
-
-    static void setup_tx() {
-        PORTE.PIN3CTRL = 0;
-        tx::output();
-        tx::high();
-    }
-
-    static void setup_pr() {
-        PR.PRPE &= ~PR_USART0_bm;
-    }
+    enum {
+        INT_LEVEL = PORT_INT0LVL_HI_gc,
+        INT_FLAGS = PORT_INT0IF_bm,
+    };
+    static volatile uint8_t& intmask() { return port_traits::int0mask(); }
 };
 
 
@@ -145,33 +97,15 @@ struct traits<E0> {
 struct E1 { };
 
 template<>
-struct traits<E1> {
-    using rx = artl::digital_in<artl::port::E, 6>;
-    using tx = artl::digital_out<artl::port::E, 7>;
-
+struct traits<E1> : public pin_traits<artl::port::E, 6, 7> {
     static USART_t& uart() { return USARTE1; }
+    static void setup_pr() { PR.PRPE &= ~PR_USART1_bm; }
 
-    static void setup_pins() {
-        setup_rx();
-        setup_tx();
-        setup_pr();
-    }
-
-    static void setup_rx() {
-        PORTE.PIN6CTRL = 0;
-        rx::input();
-        rx::pulldown();
-    }
-
-    static void setup_tx() {
-        PORTE.PIN7CTRL = 0;
-        tx::output();
-        tx::high();
-    }
-
-    static void setup_pr() {
-        PR.PRPE &= ~PR_USART1_bm;
-    }
+    enum {
+        INT_LEVEL = PORT_INT1LVL_HI_gc,
+        INT_FLAGS = PORT_INT1IF_bm,
+    };
+    static volatile uint8_t& intmask() { return port_traits::int1mask(); }
 };
 
 #endif
@@ -181,33 +115,15 @@ struct traits<E1> {
 struct F0 { };
 
 template<>
-struct traits<F0> {
-    using rx = artl::digital_in<artl::port::F, 2>;
-    using tx = artl::digital_out<artl::port::F, 3>;
-
+struct traits<F0> : public pin_traits<artl::port::F, 2, 3> {
     static USART_t& uart() { return USARTF0; }
+    static void setup_pr() { PR.PRPF &= ~PR_USART0_bm; }
 
-    static void setup_pins() {
-        setup_rx();
-        setup_tx();
-        setup_pr();
-    }
-
-    static void setup_rx() {
-        PORTF.PIN2CTRL = 0;
-        rx::input();
-        rx::pulldown();
-    }
-
-    static void setup_tx() {
-        PORTF.PIN3CTRL = 0;
-        tx::output();
-        tx::high();
-    }
-
-    static void setup_pr() {
-        PR.PRPF &= ~PR_USART0_bm;
-    }
+    enum {
+        INT_LEVEL = PORT_INT0LVL_HI_gc,
+        INT_FLAGS = PORT_INT0IF_bm,
+    };
+    static volatile uint8_t& intmask() { return port_traits::int0mask(); }
 };
 
 #endif
@@ -217,33 +133,15 @@ struct traits<F0> {
 struct F1 { };
 
 template<>
-struct traits<F1> {
-    using rx = artl::digital_in<artl::port::F, 6>;
-    using tx = artl::digital_out<artl::port::F, 7>;
-
+struct traits<F1> : public pin_traits<artl::port::F, 6, 7> {
     static USART_t& uart() { return USARTF1; }
+    static void setup_pr() { PR.PRPF &= ~PR_USART1_bm; }
 
-    static void setup_pins() {
-        setup_rx();
-        setup_tx();
-        setup_pr();
-    }
-
-    static void setup_rx() {
-        PORTF.PIN6CTRL = 0;
-        rx::input();
-        rx::pulldown();
-    }
-
-    static void setup_tx() {
-        PORTF.PIN7CTRL = 0;
-        tx::output();
-        tx::high();
-    }
-
-    static void setup_pr() {
-        PR.PRPF &= ~PR_USART1_bm;
-    }
+    enum {
+        INT_LEVEL = PORT_INT1LVL_HI_gc,
+        INT_FLAGS = PORT_INT1IF_bm,
+    };
+    static volatile uint8_t& intmask() { return port_traits::int1mask(); }
 };
 
 #endif
@@ -364,11 +262,18 @@ struct uart_t : public RX_TRAITS {
     static bool ferr() { return (uart().STATUS & USART_FERR_bm) != 0; }
     static bool bufovf() { return (uart().STATUS & USART_BUFOVF_bm) != 0; }
 
+    static bool tx_enabled() { return (uart().CTRLB & USART_TXEN_bm) != 0; }
+
     static void rxc_int_off() { uart().CTRLA &= ~USART_RXCINTLVL_gm; }
     static void rxc_int_lo() { uart().CTRLA |= USART_RXCINTLVL_LO_gc; }
     static void rxc_int_med() { uart().CTRLA |= USART_RXCINTLVL_MED_gc; }
     static void rxc_int_hi() { uart().CTRLA |= USART_RXCINTLVL_HI_gc; }
 
+    static void txc_int_off() { uart().CTRLA &= ~USART_TXCINTLVL_gm; }
+    static void txc_int_lo() { uart().CTRLA |= USART_TXCINTLVL_LO_gc; }
+    static void txc_int_med() { uart().CTRLA |= USART_TXCINTLVL_MED_gc; }
+    static void txc_int_hi() { uart().CTRLA |= USART_TXCINTLVL_HI_gc; }
+
     static void dre_int_off() { uart().CTRLA &= ~USART_DREINTLVL_gm; }
     static void dre_int_lo() { uart().CTRLA |= USART_DREINTLVL_LO_gc; }
     static void dre_int_med() { uart().CTRLA |= USART_DREINTLVL_MED_gc; }
@@ -379,6 +284,9 @@ struct uart_t : public RX_TRAITS {
 
     static void setup() {
         port_traits::setup_pins();
+        port_traits::setup_pr();
+
+        port_traits::intmask() |= rx::traits::bit_mask;
 
         uart().CTRLA = USART_RXCINTLVL_OFF_gc | USART_TXCINTLVL_OFF_gc | USART_DREINTLVL_OFF_gc;
         uart().CTRLB = USART_RXEN_bm | USART_TXEN_bm;
@@ -393,6 +301,15 @@ struct uart_t : public RX_TRAITS {
         uart().CTRLB = 0;
     }
 
+    static void disable_tx() {
+        dre_int_off();
+        uart().CTRLB &= ~USART_TXEN_bm;
+    }
+
+    static void enable_tx() {
+        uart().CTRLB |= USART_TXEN_bm;
+    }
+
     static uint8_t write_buf(const void *d, uint8_t s) {
         if (s == 1 && tx_ring_empty() && dre()) {
             data(* (const uint8_t *) d);
@@ -436,6 +353,30 @@ struct uart_t : public RX_TRAITS {
         return res;
     }
 
+    static uint8_t write_byte(uint8_t b) {
+        if (tx_ring_empty() && dre()) {
+            data(b);
+
+            return 1;
+        }
+
+        if (tx_ring_avail() > 1) {
+            tx_ring_push(b);
+
+            while (dre() && !tx_ring_empty()) { data(tx_ring_pop()); }
+
+            if (!tx_ring_empty()) { dre_int_hi(); }
+
+            want_write = 0;
+
+            return 1;
+        } else {
+            want_write = 1;
+
+            return 0;
+        }
+    }
+
     static void on_rxc_int() {
         rx_traits::on_rx(data());
     }
@@ -457,7 +398,103 @@ struct uart_t : public RX_TRAITS {
     static inline void tx_ring_push(uint8_t b) { tx_ring.push_back(b); }
     static inline uint8_t tx_ring_avail() { return tx_ring.capacity - tx_ring.size(); }
 
+    static inline void enable_pin_ch() {
+        port_traits::intflags() = port_traits::INT_FLAGS;
+        port_traits::intctrl() |= port_traits::INT_LEVEL;
+    }
+    static inline void disable_pin_ch() {
+        port_traits::intctrl() &= ~port_traits::INT_LEVEL;
+        port_traits::intflags() = port_traits::INT_FLAGS;
+    }
 private:
     static tx_ring_t tx_ring;
     static uint8_t want_write;
 };
+
+template<typename...>
+struct uart_list;
+
+template<typename T>
+struct uart_list<T> {
+    static void setup() { T::setup(); }
+    static void enable_tx() { T::enable_tx(); }
+    static void disable_tx() { T::disable_tx(); }
+    static void rxc_int_off() { T::rxc_int_off(); }
+    static void rxc_int_hi() { T::rxc_int_hi(); }
+    static void txc_int_off() { T::txc_int_off(); }
+    static void txc_int_hi() { T::txc_int_hi(); }
+
+    static void setup_tx_pin() { T::port_traits::setup_tx(); }
+    static void tx_high() { T::tx::high(); }
+    static void tx_low() { T::tx::low(); }
+
+    static bool tx_ring_empty() { return T::tx_ring_empty(); }
+
+    static void data(uint8_t d) { T::data(d); }
+    static void write_byte(uint8_t b) { T::write_byte(b); }
+    static uint8_t write_buf(uint8_t port, const uint8_t *buf, uint8_t size) {
+        if (port == T::tx_traits::id) {
+            return T::write_buf(buf, size);
+        }
+        return 0;
+    }
+
+    static void enable_pin_ch() { T::enable_pin_ch(); }
+    static void enable_pin_ch(uint8_t id) {
+        if (id == T::rx_traits::id) {
+            T::enable_pin_ch();
+        }
+    }
+    static void disable_pin_ch() { T::disable_pin_ch(); }
+    static void disable_pin_ch(uint8_t id) {
+        if (id == T::rx_traits::id) {
+            T::disable_pin_ch();
+        }
+    }
+};
+
+template<typename T, typename... T2>
+struct uart_list<T, T2...> {
+    using L = uart_list<T2...>;
+
+    static void setup() { T::setup(); L::setup(); }
+    static void enable_tx() { T::enable_tx(); L::enable_tx(); }
+    static void disable_tx() { T::disable_tx(); L::disable_tx(); }
+    static void rxc_int_off() { T::rxc_int_off(); L::rxc_int_off(); }
+    static void txc_int_off() { T::txc_int_off(); L::txc_int_off(); }
+    static void rxc_int_hi() { T::rxc_int_hi(); L::rxc_int_hi(); }
+    static void txc_int_hi() { T::txc_int_hi(); L::txc_int_hi(); }
+
+    static void setup_tx_pin() { T::port_traits::setup_tx(); L::setup_tx_pin(); }
+    static void tx_high() { T::tx::high(); L::tx_high(); }
+    static void tx_low() { T::tx::low(); L::tx_low(); }
+
+    static bool tx_ring_empty() { return T::tx_ring_empty(); }
+
+    static void data(uint8_t d) { T::data(d); L::data(d); }
+    static void write_byte(uint8_t b) { T::write_byte(b); L::write_byte(b); }
+    static uint8_t write_buf(uint8_t port, const uint8_t *buf, uint8_t size) {
+        if (port == T::tx_traits::id) {
+            return T::write_buf(buf, size);
+        } else {
+            return L::write_buf(port, buf, size);
+        }
+    }
+
+    static void enable_pin_ch() { T::enable_pin_ch(); L::enable_pin_ch(); }
+    static void enable_pin_ch(uint8_t id) {
+        if (id == T::rx_traits::id) {
+            T::enable_pin_ch();
+        } else {
+            L::enable_pin_ch(id);
+        }
+    }
+    static void disable_pin_ch() { T::disable_pin_ch(); L::disable_pin_ch(); }
+    static void disable_pin_ch(uint8_t id) {
+        if (id == T::rx_traits::id) {
+            T::disable_pin_ch();
+        } else {
+            L::disable_pin_ch(id);
+        }
+    }
+};
diff --git a/firmware/src/ui.h b/firmware/src/ui.h
index 484d442..c4a91e9 100644
--- a/firmware/src/ui.h
+++ b/firmware/src/ui.h
@@ -80,12 +80,44 @@ inline void tx_usb_blink() { tx_blink_state[USB_LED_ID].start(); }
 inline void rx_usb_active() { rx_blink_state[USB_LED_ID].active(); }
 inline void tx_usb_active() { tx_blink_state[USB_LED_ID].active(); }
 
+inline void rx_error(uint8_t port) { rx_blink_state[port].error(); }
+
 inline void tx_blink() {
     for (uint8_t i = 0; i < MIDI_PORTS; ++i) {
         tx_blink_state[i].start();
     }
 }
 
+inline void tx_active() {
+    for (uint8_t i = 0; i < MIDI_PORTS; ++i) {
+        tx_blink_state[i].active();
+    }
+}
+
+inline void rx_data(bool active, uint8_t port) {
+    if (active) {
+        rx_active(port);
+    } else {
+        rx_blink(port);
+    }
+}
+
+inline void tx_data(bool active, uint8_t port) {
+    if (active) {
+        tx_active(port);
+    } else {
+        tx_blink(port);
+    }
+}
+
+inline void tx_data(bool active) {
+    if (active) {
+        tx_active();
+    } else {
+        tx_blink();
+    }
+}
+
 inline void usb_midi_enable() {
     usb_midi_enabled = true;
 
diff --git a/firmware/src/version.h b/firmware/src/version.h
index 5bf0d01..6bbf365 100644
--- a/firmware/src/version.h
+++ b/firmware/src/version.h
@@ -3,7 +3,7 @@
 
 #include <string.h>
 
-#define FW_VERSION "2022.07.15"
+#define FW_VERSION "2022.08.10Ex"
 
 struct version_t {
     enum {