From 4872319cb2b2d940bd766efe11f620a194b8fcad Mon Sep 17 00:00:00 2001 From: Akram <47830962+arkamnite@users.noreply.github.com> Date: Fri, 7 May 2021 00:05:16 +0100 Subject: [PATCH 01/33] Still in progress, sorry guys --- cs132/part3.md | 44 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/cs132/part3.md b/cs132/part3.md index b99ce2b2..f482c079 100644 --- a/cs132/part3.md +++ b/cs132/part3.md @@ -24,4 +24,46 @@ Before diving into assembler, we need to be familiar with the **key components o The instruction cycle takes place over **several CPU clock cycles**- the same clock cycles we saw in **sequential logic circuits**. The FDE cycle relies on several CPU components interacting with one another. ### FDE Components -There are several +There are several components that make up the FDE cycle: +- ALU +- CU +- **Program Counter** (PC): this tracks the **memory address** of the **next instruction** for execution +- **Instruction Register** (IR): contains the **most recent instruction** fetched +- **Memory Address Register** (MAR): contains the address of the _region_ of memory for read/write purposes +- **Memory Data Register** (MDR): contains **fetched data** from memory or **data ready to be written** to memory + +> Remember that the **Control Unit** is connected to all components + +A typical instruction cycle may look something like this: +| Fetch | Decode | Execute | +|-------|--------|---------| +| |