From 4872319cb2b2d940bd766efe11f620a194b8fcad Mon Sep 17 00:00:00 2001
From: Akram <47830962+arkamnite@users.noreply.github.com>
Date: Fri, 7 May 2021 00:05:16 +0100
Subject: [PATCH 01/33] Still in progress, sorry guys
---
cs132/part3.md | 44 +++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/cs132/part3.md b/cs132/part3.md
index b99ce2b2..f482c079 100644
--- a/cs132/part3.md
+++ b/cs132/part3.md
@@ -24,4 +24,46 @@ Before diving into assembler, we need to be familiar with the **key components o
The instruction cycle takes place over **several CPU clock cycles**- the same clock cycles we saw in **sequential logic circuits**. The FDE cycle relies on several CPU components interacting with one another.
### FDE Components
-There are several
+There are several components that make up the FDE cycle:
+- ALU
+- CU
+- **Program Counter** (PC): this tracks the **memory address** of the **next instruction** for execution
+- **Instruction Register** (IR): contains the **most recent instruction** fetched
+- **Memory Address Register** (MAR): contains the address of the _region_ of memory for read/write purposes
+- **Memory Data Register** (MDR): contains **fetched data** from memory or **data ready to be written** to memory
+
+> Remember that the **Control Unit** is connected to all components
+
+A typical instruction cycle may look something like this:
+| Fetch | Decode | Execute |
+|-------|--------|---------|
+|
- Instruction Received from memory location in PC
- Retrieved instruction stored in IR
- PC incremented to point to next instruction in memory
| - Opcode retrieved / instruction decoded
- Read effective address to establish opcode type
| - CU signals functional CPU components
- Can result in changes to data registers, such as the PC etc.
- PC incremented to point to next instruction in memory
|
+
+## Registers
+
+Now that we have the FDE cycle established, we need **registers** to help store intermediate information- this can either be in the form of memory or system flags. The Motorola 68008 will be used to give context to each type of register:
+
+> You can think of a register as a parallel set of bits which can be toggled on or off.
+
+#### Data registers
+- These are useful for storing **frequently used values** or **intermediate results** of calculations.
+- You typically **only need one** register **on chip**- however, the advantage of having many registers is that **fewer references to external memory are needed**.
+
+> The 68008 has 32 bit data registers. This is a _long_ register; 16 bits form a _word_, and 8 bits form a _byte_.
+
+#### Status registers
+- These have various status bits that are set or reset by the **ALU**.
+- They are a _set of flags_:
+ - Half are for the **system** (CU)
+ - The **conditional control register** is a **subset of flags**
+
+| ⬅ System byte ➡ | ⬅ User byte ➡ |
+|-------------|-----------|
+| 8 bits | Several bits will make up the CCR |
+
+> The CCR is made up of several bits representing statuses such as _extend, negative, zero, overflow, carry_. If you wanted to check the status of the computer in a program, you could use bitwise **AND** against a bitmask (the string of bits you want toggled) and seeing if the final result is the flag you wanted to see.
+
+#### Address reguster
+- These are used as **pointer registers** in the calculation of operand addresses.
+- Operations on these addresses **do not alter the CCR**.
+- The **ALU** has the capacity to incur changes in status (operations on non-addresses
From a939b72b396819239b937c565d8b9cf4ad5b035e Mon Sep 17 00:00:00 2001
From: Akram <47830962+arkamnite@users.noreply.github.com>
Date: Fri, 7 May 2021 15:09:16 +0100
Subject: [PATCH 02/33] Finished part 3
---
cs132/part3.md | 309 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 307 insertions(+), 2 deletions(-)
diff --git a/cs132/part3.md b/cs132/part3.md
index f482c079..88f97a63 100644
--- a/cs132/part3.md
+++ b/cs132/part3.md
@@ -35,6 +35,194 @@ There are several components that make up the FDE cycle:
> Remember that the **Control Unit** is connected to all components
A typical instruction cycle may look something like this:
+
+| Fetch | Decode | Execute |
+|-------|--------|---------|
+| - Instruction Received from memory location in PC
- Retrieved instruction stored in IR
- PC incremented to point to next instruction in memory
| - Opcode retrieved / instruction decoded
- Read effective address to establish opcode type
| - CU signals functional CPU components
- Can result in changes to data registers, such as the PC etc.
- PC incremented to point to next instruction in memory
|
+
+## Registers
+
+Now that we have the FDE cycle established, we need **registers** to help store intermediate information- this can either be in the form of memory or system flags. The Motorola 68008 will be used to give context to each type of register:
+
+> You can think of a register as a parallel set of bits which can be toggled on or off.
+
+#### Data registers
+- These are useful for storing **frequently used values** or **intermediate results** of calculations.
+- You typically **only need one** register **on chip**- however, the advantage of having many registers is that **fewer references to external memory are needed**.
+
+> The 68008 has 32 bit data registers. This is a _long_ register; 16 bits form a _word_, and 8 bits form a _byte_.
+
+#### Status registers
+- These have various status bits that are set or reset by the **ALU**.
+- They are a _set of flags_:
+ - Half are for the **system** (CU)
+ - The **conditional control register** is a **subset of flags**
+
+| ⬅ System byte ➡ | ⬅ User byte ➡ |
+|-------------|-----------|
+| 8 bits | Several bits will make up the CCR |
+
+> The CCR is made up of several bits representing statuses such as _extend, negative, zero, overflow, carry_. If you wanted to check the status of the computer in a program, you could use bitwise **AND** against a bitmask (the string of bits you want toggled) and seeing if the final result is the flag you wanted to see.
+
+#### Address register
+- These are used as **pointer registers** in the calculation of operand addresses.
+- Operations on these addresses **do not alter the CCR**.
+- The **ALU** has the capacity to incur changes in status (through operations on non-addresses).
+
+#### Stack pointer
+- This is an **address register** that points to the **next free location**; it can hold **subroutine return addresses**.
+
+> The 68008 has pointer registers `A0-A6` whilst `A7` is used as a system stack pointer.
+
+#### Program counter
+We are already familiar with what the PC does- it is a **32 bit** register on the 68008 that keeps track of the address at which the next instruction will be found.
+
+> If you were writing a software emulator, think of the memory as an array of strings (each string is an opcode). The PC would be an integer; your code would access `memory[PC]` to find out which opcode to pull from the memory and decode. Therefore, by incrementing the PC (an 8-bit, 16-bit, or 32-bit integer in your code) you can increment through the memory array. You can sometimes increment the PC by multiple amounts.
+> Generally speaking, if you were to be writing an emulator for any CPU, you _could_ represent each register as an n-bit unsigned integer as you can toggle bits and perform bitwise operations, including bitshifts, on each integer variable. You would typically want to implement memory as a simple array of m-bit integers, where m is the word length of your CPU.
+
+## Register Transfer Language
+
+> RTL is used to describe the operations of the microprocessor as it is executing program instructions.
+> It is also a way of making sure we access the correct parts of the microprocessor- **do not confuse it with assembler instructions**.
+
+| Example RTL | Meaning |
+|-------------|---------|
+| `[MAR] ⬅ [PC]` | _Transfer_ the contents of the PC **to** the MAR |
+| `[MS(12345)]` | The _contents_ of memory _location_ 12345 in the _main store_ |
+
+### Example: Instruction fetching
+Given a series of instructions in words, we can find a way to represent this in RTL. Consider the following example:
+
+| Plain words | RTL equivalent |
+|-------------|----------------|
+| Contents of PC transferred to MAR address buffers | `[MAR] ⬅ [PC]` |
+| Increment the PC | `[PC] ⬅ [PC] + 1` |
+| Load MBR from external memory, and set $$R / \bar W$$ to Read | `[MBR] ⬅ [MS([MAR])]`; $$R / \bar W$$ to Read |
+| Transfer opcode to IR from MBR | `[IR] ⬅ [MBR]` |
+| Decode the instruction | `CU ⬅ [IR(opcode)]` |
+
+If you wanted to add a constant byte to a register (take `D0` from the 68008), you would engage the ALU and then transfer this into a register:
+```
+{ continue previous cycle }
+[MBR] ⬅ [MS([MAR])]
+ALU ⬅ [MBR] + D0
+[DO] ⬅ ALU
+```
+As you can see, RTL describes how we can specifically set values in registers and interact with components in a standardised language.
+
+## Assembly Language
+
+> Assembly language saves us from machine code by using **mnemonics**.
+> We can provide **memory locations** and **constants**, as well as **symbolic names**.
+> These features are not afforded to us by RTL!
+
+Assembly language typically takes the following form:
+
+| Label | Opcode | Operand | Comment |
+|-------|--------|---------|---------|
+| `START:` | `move.b` | `#5, D0` | load `D0` with `5` |
+
+### Assembly Language Conventions
+
+There are several conventions of Assembly language to keep in mind:
+| Number Symbol | Meaning |
+|---------|-------------|
+| `#` | A constant value, in base 10. **This is not an address.** |
+| `$` | A **hex** value |
+| `%` | A **binary** value |
+
+| Directives | Definition | Convention | Example |
+|------------|------------|------------|---------|
+| Label names | You can assign labels to represent bytes or instructions | Label or name followed by `:` | `ANS: DS.B 1` will leave 1 byte of memory empty and name it ANS |
+| Defining storage (`DS`) | Instruct the assembler to reserve some memory | `DS.{data type} {amount}` | `DS.B 1` will leave 1 byte of memory free. See data types further on. |
+| Origin (`ORG`) | Tells the assembler where in memory to start putting the instructions or data | `ORG` followed by value | `ORG $4B0` starts the program at hex `4B0` |
+
+If you want to string together an assembler instruction, you typically write them in the form
+`operation.datatype` `source,` `destination`
+
+### Data types and assembler instructions
+
+Previously, we saw how the `DS` directive requires a data type and then an amount of data to set aside; Assembler language defines three types of data type:
+- **8 bits / byte**: `.b`
+- **2 bytes / word**: `.w`
+- **4 bytes / long word**: `.l`
+
+> You can typically omit the data type and `.` if you are working with a **word**.
+
+## Instruction set aspects
+
+Generally speaking, there are two aspects to a CPU instruction set:
+- **Instructions** which tell the processor which operations to perform
+ - Data movement: this is similar to what we have already seen with RTL
+ - Arithmetic instructions: keep in mind whether your CPU can operate on fractional numbers
+ - Logical instructions
+ - Branch instructions
+ - System control instructions
+- **Addressing modes** tell the processor which ways it can access data or memory locations, or how they may be calculated by the CPU.
+
+> Addressing modes can provide data, specify where it is, and how to go find it.
+> You may describe direct addresses, or relative addresses where you compare one address to another to find it.
+
+#### Logical instructions
+- We can often use **bitmasks** to achieve our goals in conjunction with **bitwise operations**.
+- **Shift operations** are fundamental; for example, you can multiply by 2 using left shift operations.
+- Other operations such as rotations also exist.
+
+#### Branch instructions
+These are crucial for **control flow statements**; we typically branch based on **conditions set in the CCR**.
+
+#### Subroutines
+Subroutines (`JSR`; jump, `RTS`; return) let you use the **same code repeatedly**. You will **push and pop the stack** to return to the PC.
+
+## Addressing modes
+As mentioned earlier, there are several ways for the CPU to access memory; you should be familiar with the following, and they are found on many CPUs (not just the 68008):
+
+| Address type | Definition | Example |
+|--------------|------------|---------|
+| Direct address | Explicitly specifying two registers in the same command | `move D3, D2` |
+| Immediate address | The **operand** forms part of the instruction and **remains constant** | `move.b #$42, D5` |
+| Absolute address | This **specifies the destination location explicitly** | `move.l D2, $7FFF0` which moves the long value held in D2 to address `$7FFF0` |
+| Relative address | These all **relate to the program counter** to write **position independent code** | |
+
+> Indirect addressing is never on the exam; however, this is where we add offsets, increments, or indexed addressing to access memory or data.
+> For example,---
+layout: 132/CS132
+slides: true
+layout: notes
+math: true
+title: Assembler
+---
+# Assembler
+
+## Microprocessor Fundamentals
+
+Before diving into assembler, we need to be familiar with the **key components of all CPUs**. No matter how complex a CPU is, they always have the two following components.
+
+- **Arithmetic Logic Unit** (ALU): this performs **math and logic**
+- **Control Unit** (CU): this decodes program **instructions** and handles **logistics** for execution
+
+> The CPU will constantly perform the following instruction cycle (the **fetch-decode-execute cycle**):
+> - Retrieve instructions from memory
+> - Decode to form recognisable operations
+> - Execute to impact the current state
+
+### Learn the fetch-decode-execute cycle. Think of it every time you look at a CPU, or a series of instructions. Think about which of the components (the CU or the ALU) are operating and when.
+
+The instruction cycle takes place over **several CPU clock cycles**- the same clock cycles we saw in **sequential logic circuits**. The FDE cycle relies on several CPU components interacting with one another.
+
+### FDE Components
+There are several components that make up the FDE cycle:
+- ALU
+- CU
+- **Program Counter** (PC): this tracks the **memory address** of the **next instruction** for execution
+- **Instruction Register** (IR): contains the **most recent instruction** fetched
+- **Memory Address Register** (MAR): contains the address of the _region_ of memory for read/write purposes
+- **Memory Data Register** (MDR): contains **fetched data** from memory or **data ready to be written** to memory
+
+> Remember that the **Control Unit** is connected to all components
+
+A typical instruction cycle may look something like this:
+
| Fetch | Decode | Execute |
|-------|--------|---------|
| - Instruction Received from memory location in PC
- Retrieved instruction stored in IR
- PC incremented to point to next instruction in memory
| - Opcode retrieved / instruction decoded
- Read effective address to establish opcode type
| - CU signals functional CPU components
- Can result in changes to data registers, such as the PC etc.
- PC incremented to point to next instruction in memory
|
@@ -63,7 +251,124 @@ Now that we have the FDE cycle established, we need **registers** to help store
> The CCR is made up of several bits representing statuses such as _extend, negative, zero, overflow, carry_. If you wanted to check the status of the computer in a program, you could use bitwise **AND** against a bitmask (the string of bits you want toggled) and seeing if the final result is the flag you wanted to see.
-#### Address reguster
+#### Address register
- These are used as **pointer registers** in the calculation of operand addresses.
- Operations on these addresses **do not alter the CCR**.
-- The **ALU** has the capacity to incur changes in status (operations on non-addresses
+- The **ALU** has the capacity to incur changes in status (through operations on non-addresses).
+
+#### Stack pointer
+- This is an **address register** that points to the **next free location**; it can hold **subroutine return addresses**.
+
+> The 68008 has pointer registers `A0-A6` whilst `A7` is used as a system stack pointer.
+
+#### Program counter
+We are already familiar with what the PC does- it is a **32 bit** register on the 68008 that keeps track of the address at which the next instruction will be found.
+
+> If you were writing a software emulator, think of the memory as an array of strings (each string is an opcode). The PC would be an integer; your code would access `memory[PC]` to find out which opcode to pull from the memory and decode. Therefore, by incrementing the PC (an 8-bit, 16-bit, or 32-bit integer in your code) you can increment through the memory array. You can sometimes increment the PC by multiple amounts.
+> Generally speaking, if you were to be writing an emulator for any CPU, you _could_ represent each register as an n-bit unsigned integer as you can toggle bits and perform bitwise operations, including bitshifts, on each integer variable. You would typically want to implement memory as a simple array of m-bit integers, where m is the word length of your CPU.
+
+## Register Transfer Language
+
+> RTL is used to describe the operations of the microprocessor as it is executing program instructions.
+> It is also a way of making sure we access the correct parts of the microprocessor- **do not confuse it with assembler instructions**.
+
+| Example RTL | Meaning |
+|-------------|---------|
+| `[MAR] ⬅ [PC]` | _Transfer_ the contents of the PC **to** the MAR |
+| `[MS(12345)]` | The _contents_ of memory _location_ 12345 in the _main store_ |
+
+### Example: Instruction fetching
+Given a series of instructions in words, we can find a way to represent this in RTL. Consider the following example:
+
+| Plain words | RTL equivalent |
+|-------------|----------------|
+| Contents of PC transferred to MAR address buffers | `[MAR] ⬅ [PC]` |
+| Increment the PC | `[PC] ⬅ [PC] + 1` |
+| Load MBR from external memory, and set $$R / \bar W$$ to Read | `[MBR] ⬅ [MS([MAR])]`; $$R / \bar W$$ to Read |
+| Transfer opcode to IR from MBR | `[IR] ⬅ [MBR]` |
+| Decode the instruction | `CU ⬅ [IR(opcode)]` |
+
+If you wanted to add a constant byte to a register (take `D0` from the 68008), you would engage the ALU and then transfer this into a register:
+```
+{ continue previous cycle }
+[MBR] ⬅ [MS([MAR])]
+ALU ⬅ [MBR] + D0
+[DO] ⬅ ALU
+```
+As you can see, RTL describes how we can specifically set values in registers and interact with components in a standardised language.
+
+## Assembly Language
+
+> Assembly language saves us from machine code by using **mnemonics**.
+> We can provide **memory locations** and **constants**, as well as **symbolic names**.
+> These features are not afforded to us by RTL!
+
+Assembly language typically takes the following form:
+
+| Label | Opcode | Operand | Comment |
+|-------|--------|---------|---------|
+| `START:` | `move.b` | `#5, D0` | load `D0` with `5` |
+
+### Assembly Language Conventions
+
+There are several conventions of Assembly language to keep in mind:
+| Number Symbol | Meaning |
+|---------|-------------|
+| `#` | A constant value, in base 10. **This is not an address.** |
+| `$` | A **hex** value |
+| `%` | A **binary** value |
+
+| Directives | Definition | Convention | Example |
+|------------|------------|------------|---------|
+| Label names | You can assign labels to represent bytes or instructions | Label or name followed by `:` | `ANS: DS.B 1` will leave 1 byte of memory empty and name it ANS |
+| Defining storage (`DS`) | Instruct the assembler to reserve some memory | `DS.{data type} {amount}` | `DS.B 1` will leave 1 byte of memory free. See data types further on. |
+| Origin (`ORG`) | Tells the assembler where in memory to start putting the instructions or data | `ORG` followed by value | `ORG $4B0` starts the program at hex `4B0` |
+
+If you want to string together an assembler instruction, you typically write them in the form
+`operation.datatype` `source,` `destination`
+
+### Data types and assembler instructions
+
+Previously, we saw how the `DS` directive requires a data type and then an amount of data to set aside; Assembler language defines three types of data type:
+- **8 bits / byte**: `.b`
+- **2 bytes / word**: `.w`
+- **4 bytes / long word**: `.l`
+
+> You can typically omit the data type and `.` if you are working with a **word**.
+
+## Instruction set aspects
+
+Generally speaking, there are two aspects to a CPU instruction set:
+- **Instructions** which tell the processor which operations to perform
+ - Data movement: this is similar to what we have already seen with RTL
+ - Arithmetic instructions: keep in mind whether your CPU can operate on fractional numbers
+ - Logical instructions
+ - Branch instructions
+ - System control instructions
+- **Addressing modes** tell the processor which ways it can access data or memory locations, or how they may be calculated by the CPU.
+
+> Addressing modes can provide data, specify where it is, and how to go find it.
+> You may describe direct addresses, or relative addresses where you compare one address to another to find it.
+
+#### Logical instructions
+- We can often use **bitmasks** to achieve our goals in conjunction with **bitwise operations**.
+- **Shift operations** are fundamental; for example, you can multiply by 2 using left shift operations.
+- Other operations such as rotations also exist.
+
+#### Branch instructions
+These are crucial for **control flow statements**; we typically branch based on **conditions set in the CCR**.
+
+#### Subroutines
+Subroutines (`JSR`; jump, `RTS`; return) let you use the **same code repeatedly**. You will **push and pop the stack** to return to the PC.
+
+## Addressing modes
+As mentioned earlier, there are several ways for the CPU to access memory; you should be familiar with the following, and they are found on many CPUs (not just the 68008):
+
+| Address type | Definition | Example |
+|--------------|------------|---------|
+| Direct address | Explicitly specifying two registers in the same command | `move D3, D2` |
+| Immediate address | The **operand** forms part of the instruction and **remains constant** | `move.b #$42, D5` |
+| Absolute address | This **specifies the destination location explicitly** | `move.l D2, $7FFF0` which moves the long value held in D2 to address `$7FFF0` |
+| Relative address | These all **relate to the program counter** to write **position independent code** | |
+
+> Indirect addressing is never on the exam; however, this is where we add offsets, increments, or indexed addressing to access memory or data.
From 12d3d3e3b15032c9fe035edfbf294c1eefc63d6e Mon Sep 17 00:00:00 2001
From: Akram <47830962+arkamnite@users.noreply.github.com>
Date: Fri, 7 May 2021 17:59:40 +0100
Subject: [PATCH 03/33] Added hotlink for topic 3
---
cs132/index.md | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/cs132/index.md b/cs132/index.md
index a1ae0421..e0427847 100755
--- a/cs132/index.md
+++ b/cs132/index.md
@@ -28,7 +28,7 @@ These notes will likely take the same/similar form to the CS118 notes. The prima
1. [x] [Data representation](part1.html)
2. [x] [Digital logic](part2.html)
-3. [ ] Assembler
+3. [x] [Assembler](part3.html)
4. [ ] Memory systems
5. [ ] I/O mechanisms
-6. [ ] Processor architecture
\ No newline at end of file
+6. [ ] Processor architecture
From 0103c580dacee6f82158af41041dcf619c3bcc59 Mon Sep 17 00:00:00 2001
From: Akram <47830962+arkamnite@users.noreply.github.com>
Date: Fri, 7 May 2021 18:19:21 +0100
Subject: [PATCH 04/33] Fixed the duplicate issue
---
cs132/part3.md | 187 -------------------------------------------------
1 file changed, 187 deletions(-)
diff --git a/cs132/part3.md b/cs132/part3.md
index 88f97a63..8df195b9 100644
--- a/cs132/part3.md
+++ b/cs132/part3.md
@@ -185,190 +185,3 @@ As mentioned earlier, there are several ways for the CPU to access memory; you s
| Relative address | These all **relate to the program counter** to write **position independent code** | |
> Indirect addressing is never on the exam; however, this is where we add offsets, increments, or indexed addressing to access memory or data.
-> For example,---
-layout: 132/CS132
-slides: true
-layout: notes
-math: true
-title: Assembler
----
-# Assembler
-
-## Microprocessor Fundamentals
-
-Before diving into assembler, we need to be familiar with the **key components of all CPUs**. No matter how complex a CPU is, they always have the two following components.
-
-- **Arithmetic Logic Unit** (ALU): this performs **math and logic**
-- **Control Unit** (CU): this decodes program **instructions** and handles **logistics** for execution
-
-> The CPU will constantly perform the following instruction cycle (the **fetch-decode-execute cycle**):
-> - Retrieve instructions from memory
-> - Decode to form recognisable operations
-> - Execute to impact the current state
-
-### Learn the fetch-decode-execute cycle. Think of it every time you look at a CPU, or a series of instructions. Think about which of the components (the CU or the ALU) are operating and when.
-
-The instruction cycle takes place over **several CPU clock cycles**- the same clock cycles we saw in **sequential logic circuits**. The FDE cycle relies on several CPU components interacting with one another.
-
-### FDE Components
-There are several components that make up the FDE cycle:
-- ALU
-- CU
-- **Program Counter** (PC): this tracks the **memory address** of the **next instruction** for execution
-- **Instruction Register** (IR): contains the **most recent instruction** fetched
-- **Memory Address Register** (MAR): contains the address of the _region_ of memory for read/write purposes
-- **Memory Data Register** (MDR): contains **fetched data** from memory or **data ready to be written** to memory
-
-> Remember that the **Control Unit** is connected to all components
-
-A typical instruction cycle may look something like this:
-
-| Fetch | Decode | Execute |
-|-------|--------|---------|
-| - Instruction Received from memory location in PC
- Retrieved instruction stored in IR
- PC incremented to point to next instruction in memory
| - Opcode retrieved / instruction decoded
- Read effective address to establish opcode type
| - CU signals functional CPU components
- Can result in changes to data registers, such as the PC etc.
- PC incremented to point to next instruction in memory
|
-
-## Registers
-
-Now that we have the FDE cycle established, we need **registers** to help store intermediate information- this can either be in the form of memory or system flags. The Motorola 68008 will be used to give context to each type of register:
-
-> You can think of a register as a parallel set of bits which can be toggled on or off.
-
-#### Data registers
-- These are useful for storing **frequently used values** or **intermediate results** of calculations.
-- You typically **only need one** register **on chip**- however, the advantage of having many registers is that **fewer references to external memory are needed**.
-
-> The 68008 has 32 bit data registers. This is a _long_ register; 16 bits form a _word_, and 8 bits form a _byte_.
-
-#### Status registers
-- These have various status bits that are set or reset by the **ALU**.
-- They are a _set of flags_:
- - Half are for the **system** (CU)
- - The **conditional control register** is a **subset of flags**
-
-| ⬅ System byte ➡ | ⬅ User byte ➡ |
-|-------------|-----------|
-| 8 bits | Several bits will make up the CCR |
-
-> The CCR is made up of several bits representing statuses such as _extend, negative, zero, overflow, carry_. If you wanted to check the status of the computer in a program, you could use bitwise **AND** against a bitmask (the string of bits you want toggled) and seeing if the final result is the flag you wanted to see.
-
-#### Address register
-- These are used as **pointer registers** in the calculation of operand addresses.
-- Operations on these addresses **do not alter the CCR**.
-- The **ALU** has the capacity to incur changes in status (through operations on non-addresses).
-
-#### Stack pointer
-- This is an **address register** that points to the **next free location**; it can hold **subroutine return addresses**.
-
-> The 68008 has pointer registers `A0-A6` whilst `A7` is used as a system stack pointer.
-
-#### Program counter
-We are already familiar with what the PC does- it is a **32 bit** register on the 68008 that keeps track of the address at which the next instruction will be found.
-
-> If you were writing a software emulator, think of the memory as an array of strings (each string is an opcode). The PC would be an integer; your code would access `memory[PC]` to find out which opcode to pull from the memory and decode. Therefore, by incrementing the PC (an 8-bit, 16-bit, or 32-bit integer in your code) you can increment through the memory array. You can sometimes increment the PC by multiple amounts.
-> Generally speaking, if you were to be writing an emulator for any CPU, you _could_ represent each register as an n-bit unsigned integer as you can toggle bits and perform bitwise operations, including bitshifts, on each integer variable. You would typically want to implement memory as a simple array of m-bit integers, where m is the word length of your CPU.
-
-## Register Transfer Language
-
-> RTL is used to describe the operations of the microprocessor as it is executing program instructions.
-> It is also a way of making sure we access the correct parts of the microprocessor- **do not confuse it with assembler instructions**.
-
-| Example RTL | Meaning |
-|-------------|---------|
-| `[MAR] ⬅ [PC]` | _Transfer_ the contents of the PC **to** the MAR |
-| `[MS(12345)]` | The _contents_ of memory _location_ 12345 in the _main store_ |
-
-### Example: Instruction fetching
-Given a series of instructions in words, we can find a way to represent this in RTL. Consider the following example:
-
-| Plain words | RTL equivalent |
-|-------------|----------------|
-| Contents of PC transferred to MAR address buffers | `[MAR] ⬅ [PC]` |
-| Increment the PC | `[PC] ⬅ [PC] + 1` |
-| Load MBR from external memory, and set $$R / \bar W$$ to Read | `[MBR] ⬅ [MS([MAR])]`; $$R / \bar W$$ to Read |
-| Transfer opcode to IR from MBR | `[IR] ⬅ [MBR]` |
-| Decode the instruction | `CU ⬅ [IR(opcode)]` |
-
-If you wanted to add a constant byte to a register (take `D0` from the 68008), you would engage the ALU and then transfer this into a register:
-```
-{ continue previous cycle }
-[MBR] ⬅ [MS([MAR])]
-ALU ⬅ [MBR] + D0
-[DO] ⬅ ALU
-```
-As you can see, RTL describes how we can specifically set values in registers and interact with components in a standardised language.
-
-## Assembly Language
-
-> Assembly language saves us from machine code by using **mnemonics**.
-> We can provide **memory locations** and **constants**, as well as **symbolic names**.
-> These features are not afforded to us by RTL!
-
-Assembly language typically takes the following form:
-
-| Label | Opcode | Operand | Comment |
-|-------|--------|---------|---------|
-| `START:` | `move.b` | `#5, D0` | load `D0` with `5` |
-
-### Assembly Language Conventions
-
-There are several conventions of Assembly language to keep in mind:
-| Number Symbol | Meaning |
-|---------|-------------|
-| `#` | A constant value, in base 10. **This is not an address.** |
-| `$` | A **hex** value |
-| `%` | A **binary** value |
-
-| Directives | Definition | Convention | Example |
-|------------|------------|------------|---------|
-| Label names | You can assign labels to represent bytes or instructions | Label or name followed by `:` | `ANS: DS.B 1` will leave 1 byte of memory empty and name it ANS |
-| Defining storage (`DS`) | Instruct the assembler to reserve some memory | `DS.{data type} {amount}` | `DS.B 1` will leave 1 byte of memory free. See data types further on. |
-| Origin (`ORG`) | Tells the assembler where in memory to start putting the instructions or data | `ORG` followed by value | `ORG $4B0` starts the program at hex `4B0` |
-
-If you want to string together an assembler instruction, you typically write them in the form
-`operation.datatype` `source,` `destination`
-
-### Data types and assembler instructions
-
-Previously, we saw how the `DS` directive requires a data type and then an amount of data to set aside; Assembler language defines three types of data type:
-- **8 bits / byte**: `.b`
-- **2 bytes / word**: `.w`
-- **4 bytes / long word**: `.l`
-
-> You can typically omit the data type and `.` if you are working with a **word**.
-
-## Instruction set aspects
-
-Generally speaking, there are two aspects to a CPU instruction set:
-- **Instructions** which tell the processor which operations to perform
- - Data movement: this is similar to what we have already seen with RTL
- - Arithmetic instructions: keep in mind whether your CPU can operate on fractional numbers
- - Logical instructions
- - Branch instructions
- - System control instructions
-- **Addressing modes** tell the processor which ways it can access data or memory locations, or how they may be calculated by the CPU.
-
-> Addressing modes can provide data, specify where it is, and how to go find it.
-> You may describe direct addresses, or relative addresses where you compare one address to another to find it.
-
-#### Logical instructions
-- We can often use **bitmasks** to achieve our goals in conjunction with **bitwise operations**.
-- **Shift operations** are fundamental; for example, you can multiply by 2 using left shift operations.
-- Other operations such as rotations also exist.
-
-#### Branch instructions
-These are crucial for **control flow statements**; we typically branch based on **conditions set in the CCR**.
-
-#### Subroutines
-Subroutines (`JSR`; jump, `RTS`; return) let you use the **same code repeatedly**. You will **push and pop the stack** to return to the PC.
-
-## Addressing modes
-As mentioned earlier, there are several ways for the CPU to access memory; you should be familiar with the following, and they are found on many CPUs (not just the 68008):
-
-| Address type | Definition | Example |
-|--------------|------------|---------|
-| Direct address | Explicitly specifying two registers in the same command | `move D3, D2` |
-| Immediate address | The **operand** forms part of the instruction and **remains constant** | `move.b #$42, D5` |
-| Absolute address | This **specifies the destination location explicitly** | `move.l D2, $7FFF0` which moves the long value held in D2 to address `$7FFF0` |
-| Relative address | These all **relate to the program counter** to write **position independent code** | |
-
-> Indirect addressing is never on the exam; however, this is where we add offsets, increments, or indexed addressing to access memory or data.
From dc0ce6a1518799e1ce9ae53641124115cca1df55 Mon Sep 17 00:00:00 2001
From: Akram <47830962+arkamnite@users.noreply.github.com>
Date: Fri, 7 May 2021 18:21:27 +0100
Subject: [PATCH 05/33] Tried fixing table
---
cs132/part3.md | 1 +
1 file changed, 1 insertion(+)
diff --git a/cs132/part3.md b/cs132/part3.md
index 8df195b9..1a840484 100644
--- a/cs132/part3.md
+++ b/cs132/part3.md
@@ -131,6 +131,7 @@ There are several conventions of Assembly language to keep in mind:
| `$` | A **hex** value |
| `%` | A **binary** value |
+
| Directives | Definition | Convention | Example |
|------------|------------|------------|---------|
| Label names | You can assign labels to represent bytes or instructions | Label or name followed by `:` | `ANS: DS.B 1` will leave 1 byte of memory empty and name it ANS |
From 9700d1a52a9971c30470a6cec47d4bdf38718505 Mon Sep 17 00:00:00 2001
From: Akram <47830962+arkamnite@users.noreply.github.com>
Date: Fri, 7 May 2021 18:52:26 +0100
Subject: [PATCH 06/33] Added part4
---
cs132/part4.md | 62 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
create mode 100644 cs132/part4.md
diff --git a/cs132/part4.md b/cs132/part4.md
new file mode 100644
index 00000000..e6921d05
--- /dev/null
+++ b/cs132/part4.md
@@ -0,0 +1,62 @@
+---
+layout: 132/CS132
+slides: true
+layout: notes
+math: true
+title: Memory Systems
+---
+
+# Memory Systems
+## Memory hierarchy
+When deciding on a memory technology, you must consider the following factors:
+- Frequency of access
+- Access time
+- Capacity required
+- Financial cost
+
+> The **designer's dilemma** is the conflict that is caused by choosing between low cost, high capacity storage or high cost, low capacity storage.
+> Ideally, we would want our storage access to be frequent, quick, and spatially efficient- the balance of these three leads to the cost of the storage.
+
+We know that roughly **90%** of memory accesses are within +-2KB of the previous program counter position. Therefore, we should only choose expensive memory **when we need it**, which is due to **spatial locality**.
+
+**Temporal locality** refers to the likelihood that a particular memory location will be referenced in the future.
+
+## Cache Memory
+- Cache is **kept small to limit cost**; it is also **transparent to the programmer**. However, this does allow _some_ control over what is stored in it.
+- A cache access is known as a **'cache hit'**.
+- Cache speed is incredibly important- moving down the memory hierarchy will take orders of magnitude more time for similar memory hits.
+
+> **Moore's Law** is focused on the transistor count within integrated circuits. It states that this count doubles roughly every two years.
+> Currently, single core frewuency is tailing off; this has lead the industry to focus on multicore performance instead.
+> Comparitively, memory access speed is improving much more slowly; access time and capacity can become a huge bottleneck when it comes to creating performant systems.
+
+> Cache concepts are not included in these notes as they are not fully examined, and also do not feature in the revision videos.
+
+## Memory Cell Organisation
+Now that we're familiar with different parts of the memory hierarchy, it's crucial that we understand how this memory is actually constructed (down to the metal almost).
+
+### Semiconductor Memory (main store)
+Semiconductor memory is the most common form of main store memory, otherwise known as **RAM**. It can be broken up into several groups:
+- **Static RAM** (SRAM)
+ - SRAM uses a **flip-flop** as storage element for each bit.
+- **Dynamic RAM** (DRAM)
+ - For each bit, the **presence or absence of charge** in a capacitor to determine a `1` or `0`.
+ - The capacitor charge **leaks away over time**, which requires **periodic refreshing**.
+ - DRAM is typically cheaper than SRAM which is why we accommodate for the higher overhead.
+
+> Refreshing DRAM incurs a **constant overhead**, which means that it **does not increase per bit**.
+
+Both **SRAM and DRAM are volatile** memory storage- therefore, power must continuously be applied. However, the similarities end there and it is crucial to recognise the differences between the two memory cells.
+
+> Always ask yourself about the cost of these memory technologies- it is the reason we have decided to use semiconductor memory as our main store.
+
+| SRAM cells | DRAM cells |
+|------------|------------|
+| Provides **better read/write times** | Generally simpler and more compact, which allows for **greater memory cell density** |
+| **Cache memory**, both on and off chip, is implemented as SRAM | Cheaper to produce than equivalent SRAM memory, and hence is used for **main memory** |
+
+DRAM can be organised even further:
+- Synchronous DRAM (SDRAM)
+- Rambus DRAM (RDRAM)
+- Double Data Rate Synchronous (DDR SDRAM)
+- Cache DRAM (CDRAM)
From 38c8381aa561b8b80a6a1adc56df144dd5cf31a9 Mon Sep 17 00:00:00 2001
From: Akram <47830962+arkamnite@users.noreply.github.com>
Date: Fri, 7 May 2021 18:53:06 +0100
Subject: [PATCH 07/33] Add files via upload
---
cs132/4-1.png | Bin 0 -> 73319 bytes
1 file changed, 0 insertions(+), 0 deletions(-)
create mode 100644 cs132/4-1.png
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