From 4c52f518adaa21bff8253614d61db71d26a04189 Mon Sep 17 00:00:00 2001 From: Maxime Chevalier-Boisvert Date: Sat, 30 Sep 2023 18:09:31 -0400 Subject: [PATCH] Add pow_f32 opcode to VM --- vm/src/asm.rs | 1 + vm/src/vm.rs | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/vm/src/asm.rs b/vm/src/asm.rs index c257f62a..c26f2161 100644 --- a/vm/src/asm.rs +++ b/vm/src/asm.rs @@ -1081,6 +1081,7 @@ impl Assembler "asin_f32" => self.code.push_op(Op::asin_f32), "acos_f32" => self.code.push_op(Op::acos_f32), "atan_f32" => self.code.push_op(Op::atan_f32), + "pow_f32" => self.code.push_op(Op::pow_f32), "sqrt_f32" => self.code.push_op(Op::sqrt_f32), "eq_f32" => self.code.push_op(Op::eq_f32), diff --git a/vm/src/vm.rs b/vm/src/vm.rs index 05ca07cd..a48d79b6 100644 --- a/vm/src/vm.rs +++ b/vm/src/vm.rs @@ -163,6 +163,7 @@ pub enum Op asin_f32, acos_f32, atan_f32, + pow_f32, sqrt_f32, // 32-bit floating-point comparison instructions @@ -1211,6 +1212,13 @@ impl VM self.push(v0.atan()); } + // Should return NaN for invalid inputs + Op::pow_f32 => { + let v1 = self.pop().as_f32(); + let v0 = self.pop().as_f32(); + self.push(v0.powf(v1)); + } + // Should return NaN for invalid inputs Op::sqrt_f32 => { let v0 = self.pop().as_f32();