From d3ce626ec37eb5524035fc32f683021b397dfaa6 Mon Sep 17 00:00:00 2001 From: Jagadeesh Banisetti Date: Tue, 10 Sep 2019 11:07:36 +0530 Subject: [PATCH] dp14rxss: Added multi instance support. The current dp14rxss driver implementation will fail to compile for multi instances of dp14rx subsystems with different configurations. This patch fixes the same. Signed-off-by: Jagadeesh Banisetti Acked-for-series: Vishal Sagar --- .../drivers/dp14rxss/data/dp14rxss.tcl | 125 +++++++++++++--- .../dp14rxss/src/hdcp1x/xdprxss_hdcp1x.h | 2 +- .../dp14rxss/src/hdcp22/xdprxss_hdcp22.h | 18 --- .../drivers/dp14rxss/src/xdprxss.c | 138 ++++++++++-------- .../drivers/dp14rxss/src/xdprxss.h | 61 ++++---- .../drivers/dp14rxss/src/xdprxss_dbg.c | 13 +- .../drivers/dp14rxss/src/xdprxss_g.c | 49 ++++--- .../drivers/dp14rxss/src/xdprxss_intr.c | 6 +- .../drivers/dp14rxss/src/xdprxss_selftest.c | 4 +- 9 files changed, 258 insertions(+), 158 deletions(-) diff --git a/XilinxProcessorIPLib/drivers/dp14rxss/data/dp14rxss.tcl b/XilinxProcessorIPLib/drivers/dp14rxss/data/dp14rxss.tcl index f9d6d725533..122091aa61c 100755 --- a/XilinxProcessorIPLib/drivers/dp14rxss/data/dp14rxss.tcl +++ b/XilinxProcessorIPLib/drivers/dp14rxss/data/dp14rxss.tcl @@ -51,8 +51,8 @@ proc hier_ip_define_config_file {drv_handle file_name drv_string args} { array set sub_core_params {} set sub_core_params(displayport) "BASEADDR S_AXI_ACLK LANE_COUNT LINK_RATE MAX_BITS_PER_COLOR QUAD_PIXEL_ENABLE DUAL_PIXEL_ENABLE YCRCB_ENABLE YONLY_ENABLE GT_DATAWIDTH SECONDARY_SUPPORT AUDIO_CHANNELS MST_ENABLE NUMBER_OF_MST_STREAMS PROTOCOL_SELECTION FLOW_DIRECTION" set sub_core_params(axi_iic) "BASEADDR TEN_BIT_ADR GPO_WIDTH" - set sub_core_params(hdcp) "BASEADDR S_AXI_FREQUENCY IS_RX IS_HDMI" - set sub_core_params(axi_timer) "BASEADDR CLOCK_FREQ_HZ" + set sub_core_params(hdcp) "BASEADDR" + set sub_core_params(axi_timer) "BASEADDR" set sub_core_params(hdcp22_rx_dp) "BASEADDR" set total_subcores [array size sub_core_params] @@ -67,11 +67,22 @@ proc hier_ip_define_config_file {drv_handle file_name drv_string args} { set periphs_g [::hsi::utils::get_common_driver_ips $drv_handle] + array set sub_core_inst { + displayport 1 + axi_iic 1 + hdcp 1 + axi_timer 1 + hdcp22_rx_dp 1 + } + foreach periph_g $periphs_g { ::hsi::current_hw_instance $periph_g; set child_cells_g [::hsi::get_cells] + puts $config_file "\n/*" + puts $config_file "* List of Sub-cores included from the subsystem" + puts $config_file "*/" foreach child_cell_g $child_cells_g { set child_cell_vlnv [::common::get_property VLNV $child_cell_g] set vlnv_arr [split $child_cell_vlnv :] @@ -94,6 +105,40 @@ proc hier_ip_define_config_file {drv_handle file_name drv_string args} { } if { $is_slave != 0 } { puts -nonewline $config_file "#define [string toupper $final_child_cell_instance_name_present_g]\t1\n" + + # create dictionary for ip name and it's instance names "ip_name {inst1_name inst2_name}" + dict lappend ss_ip_list $ip_name $child_cell_name_g + } + } + } + + puts $config_file "\n/*" + puts $config_file "* List of Sub-cores excluded from the subsystem" + puts $config_file "*/" + + foreach sub_core [lsort [array names sub_core_inst]] { + if {[dict exists $ss_ip_list $sub_core]} { + set max_instances $sub_core_inst($sub_core) + #check if core can have multiple instances + #It is possible that not all instances are used in the design + if {$max_instances > 1} { + set ip_instances [dict get $ss_ip_list $sub_core] + set avail_instances [llength $ip_instances] + + #check if available instances are less than MAX + #if yes, mark the missing instance + #if all instances are present then skip the core + if {$avail_instances < $max_instances} { + set final_child_cell_instance_name_g "XPAR_${periph_g}_${strval}_PRESENT" + puts -nonewline $config_file "#define [string toupper $final_child_cell_instance_name_g] 0\n" + } + } + } else { + set count 0 + while {$count<$sub_core_inst($sub_core)} { + set final_child_cell_instance_name_g "XPAR_${periph_g}_${sub_core}_${count}_PRESENT" + puts -nonewline $config_file "#define [string toupper $final_child_cell_instance_name_g] 0\n" + incr count } } } @@ -119,22 +164,22 @@ proc hier_ip_define_config_file {drv_handle file_name drv_string args} { } ::hsi::current_hw_instance $periph - set child_cells [::hsi::get_cells] + set child_cells_g [::hsi::get_cells] puts $config_file ",\n" - foreach child_cell $child_cells { - set child_cell_vlnv [::common::get_property VLNV $child_cell] + #This is to get the dictionary of included subcores. + set ss_ip_list [dict create] + foreach child_cell_g $child_cells_g { + set child_cell_vlnv [::common::get_property VLNV $child_cell_g] + set child_cell_name_g [common::get_property NAME $child_cell_g] set vlnv_arr [split $child_cell_vlnv :] lassign $vlnv_arr ip_vendor ip_library ip_name ip_version - set ip_type [common::get_property IP_TYPE $child_cell] - set child_cell_name [common::get_property NAME $child_cell] - set final_child_cell_instance_name XPAR_${child_cell_name}_DEVICE_ID - set final_child_cell_instance_name_present XPAR_${child_cell_name}_PRESENT + set ip_type_g [common::get_property IP_TYPE $child_cell_g] - if { [string compare -nocase "BUS" $ip_type] != 0 } { - set interfaces [hsi::get_intf_pins -of_objects $child_cell] + if {[string compare -nocase "BUS" $ip_type_g] != 0} { + set interfaces [hsi::get_intf_pins -of_objects $child_cell_g] set is_slave 0 foreach interface $interfaces { set intf_type [common::get_property TYPE $interface] @@ -142,24 +187,57 @@ proc hier_ip_define_config_file {drv_handle file_name drv_string args} { set is_slave 1 } } + if {$is_slave != 0} { + # create dictionary for ip name and it's instance names "ip_name {inst1_name inst2_name}" + dict lappend ss_ip_list $ip_name $child_cell_name_g + } + } + } - if { $is_slave != 0 } { - set comma ",\n" + #Check for each subcore if it is included or excluded + foreach sub_core [lsort [array names sub_core_inst]] { + set max_instances $sub_core_inst($sub_core) + + if {[dict exists $ss_ip_list $sub_core]} { + #subcore include + set ip_instances [dict get $ss_ip_list $sub_core] + set ip_inst_name [lindex $ip_instances 0] + set final_child_cell_instance_name_present "XPAR_${ip_inst_name}_PRESENT" + set final_child_cell_instance_name "XPAR_${ip_inst_name}_DEVICE_ID" + + set comma ",\n" + puts $config_file "\t\t\{" + puts -nonewline $config_file [format "\t\t\t%s" [string toupper $final_child_cell_instance_name_present]] + puts $config_file "," + puts $config_file "\t\t\t\{" + puts -nonewline $config_file [format "\t\t\t\t%s" [string toupper $final_child_cell_instance_name]] + set params_str $sub_core_params($sub_core) + set params_arr [split $params_str " " ] + + foreach param $params_arr { + set final_child_cell_param_name XPAR_${ip_inst_name}_$param + puts $config_file "," + puts -nonewline $config_file [format "\t\t\t\t%s" [string toupper $final_child_cell_param_name]] + } + puts $config_file "\n\t\t\t\}" + if { $brace < $total_subcores - 1 } { + puts $config_file "\t\t\}," + incr brace + } else { + puts $config_file "\t\t\}" + } + } else { + #subcore excluded + set count 0 + set comma ",\n" + while {$count<$max_instances} { + set final_child_cell_instance_name_present "XPAR_${periph}_${sub_core}_${count}_PRESENT" puts $config_file "\t\t\{" puts -nonewline $config_file [format "\t\t\t%s" [string toupper $final_child_cell_instance_name_present]] puts $config_file "," puts $config_file "\t\t\t\{" - puts -nonewline $config_file [format "\t\t\t\t%s" [string toupper $final_child_cell_instance_name]] - - set params_str $sub_core_params($ip_name) - set params_arr [split $params_str " " ] - - foreach param $params_arr { - set final_child_cell_param_name XPAR_${child_cell_name}_$param - puts $config_file "," - puts -nonewline $config_file [format "\t\t\t\t%s" [string toupper $final_child_cell_param_name]] - } + puts -nonewline $config_file "\t\t\t\t0" puts $config_file "\n\t\t\t\}" if { $brace < $total_subcores - 1 } { puts $config_file "\t\t\}," @@ -167,6 +245,7 @@ proc hier_ip_define_config_file {drv_handle file_name drv_string args} { } else { puts $config_file "\t\t\}" } + incr count } } } diff --git a/XilinxProcessorIPLib/drivers/dp14rxss/src/hdcp1x/xdprxss_hdcp1x.h b/XilinxProcessorIPLib/drivers/dp14rxss/src/hdcp1x/xdprxss_hdcp1x.h index bc1361919d3..541ad463d6f 100644 --- a/XilinxProcessorIPLib/drivers/dp14rxss/src/hdcp1x/xdprxss_hdcp1x.h +++ b/XilinxProcessorIPLib/drivers/dp14rxss/src/hdcp1x/xdprxss_hdcp1x.h @@ -53,7 +53,7 @@ extern "C" { /***************************** Include Files *********************************/ #include "xparameters.h" -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) #include "xhdcp1x.h" #include "xtmrctr.h" #endif diff --git a/XilinxProcessorIPLib/drivers/dp14rxss/src/hdcp22/xdprxss_hdcp22.h b/XilinxProcessorIPLib/drivers/dp14rxss/src/hdcp22/xdprxss_hdcp22.h index c84f1f2960c..7087bc4ca2b 100644 --- a/XilinxProcessorIPLib/drivers/dp14rxss/src/hdcp22/xdprxss_hdcp22.h +++ b/XilinxProcessorIPLib/drivers/dp14rxss/src/hdcp22/xdprxss_hdcp22.h @@ -58,24 +58,6 @@ extern "C" { #define XDPRXSS_HDCP22_MAX_QUEUE_SIZE 16 /**************************** Type Definitions *******************************/ -/** -* This typedef contains configuration information for the HDCP22 core. -*/ -typedef struct { - u16 DeviceId; /**< Device ID of the sub-core */ - UINTPTR AbsAddr; /**< Absolute Base Address of the Sub-cores*/ -} XDpRxSs_Hdcp22_Config; - -/** - * Sub-Core Configuration Table - */ -typedef struct -{ - u16 IsPresent; /**< Flag to indicate if sub-core is present in - the design*/ - XDpRxSs_Hdcp22_Config Hdcp22Config; /**< HDCP22 core configuration */ -} XDpRxSs_Hdcp22SubCore; - /** * These constants specify the HDCP22 Events */ diff --git a/XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss.c b/XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss.c index 731032ae6bb..be1304eed15 100644 --- a/XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss.c +++ b/XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss.c @@ -88,11 +88,11 @@ extern u32 MCDP6000_IC_Rev; typedef struct { XDp DpInst; XIic IicInst; -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) XHdcp1x Hdcp1xInst; #endif -#if (((XPAR_DPRXSS_0_HDCP_ENABLE > 0) || \ - (XPAR_XHDCP22_RX_NUM_INSTANCES > 0)) \ +#if (((XPAR_XHDCP_NUM_INSTANCES > 0) || \ + (XPAR_XHDCP22_RX_NUM_INSTANCES > 0)) \ && (XPAR_XTMRCTR_NUM_INSTANCES > 0)) XTmrCtr TmrCtrInst; #endif @@ -110,7 +110,7 @@ static void StubTp2Callback(void *InstancePtr); static void StubUnplugCallback(void *InstancePtr); static void StubAccessLaneSetCallback(void *InstancePtr); -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) static int DpRxSs_HdcpStartTimer(void *InstancePtr, u16 TimeoutInMs); static int DpRxSs_HdcpStopTimer(void *InstancePtr); static int DpRxSs_HdcpBusyDelay(void *InstancePtr, u16 DelayInMs); @@ -118,13 +118,13 @@ static void DpRxSs_TimerCallback(void *InstancePtr, u8 TmrCtrNumber); static u32 DpRxSs_ConvertUsToTicks(u32 TimeoutInUs, u32 ClkFreq); #endif -#if (((XPAR_DPRXSS_0_HDCP_ENABLE > 0) || \ - (XPAR_XHDCP22_RX_NUM_INSTANCES > 0)) \ +#if (((XPAR_XHDCP_NUM_INSTANCES > 0) || \ + (XPAR_XHDCP22_RX_NUM_INSTANCES > 0)) \ && (XPAR_XTMRCTR_NUM_INSTANCES > 0)) static void DpRxSs_TimeOutCallback(void *InstancePtr, u8 TmrCtrNumber); #endif -#if ((XPAR_DPRXSS_0_HDCP_ENABLE > 0) || (XPAR_XHDCP22_RX_NUM_INSTANCES > 0)) +#if ((XPAR_XHDCP_NUM_INSTANCES > 0) || (XPAR_XHDCP22_RX_NUM_INSTANCES > 0)) static int XDpRxSs_HdcpReset(XDpRxSs *InstancePtr); #endif @@ -187,8 +187,8 @@ XDpRxSs_SubCores DpRxSsSubCores[XPAR_XDPRXSS_NUM_INSTANCES]; u32 XDpRxSs_CfgInitialize(XDpRxSs *InstancePtr, XDpRxSs_Config *CfgPtr, UINTPTR EffectiveAddr) { -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) - XHdcp1x_Config Hdcp1xConfig; +#if (XPAR_XHDCP_NUM_INSTANCES > 0) + XHdcp1x_Config *Hdcp1xConfig; #endif XIic_Config IicConfig; XDp_Config DpConfig; @@ -333,7 +333,7 @@ u32 XDpRxSs_CfgInitialize(XDpRxSs *InstancePtr, XDpRxSs_Config *CfgPtr, DpRxSs_PopulateDpRxPorts(InstancePtr); } -#if (((XPAR_DPRXSS_0_HDCP_ENABLE > 0) || \ +#if (((XPAR_XHDCP_NUM_INSTANCES > 0) || \ (XPAR_XHDCP22_RX_NUM_INSTANCES > 0)) \ && (XPAR_XTMRCTR_NUM_INSTANCES > 0)) /* Check for Timer Counter availability */ @@ -372,37 +372,39 @@ u32 XDpRxSs_CfgInitialize(XDpRxSs *InstancePtr, XDpRxSs_Config *CfgPtr, /* Set the reset value to Timer Counter zero */ XTmrCtr_SetResetValue(InstancePtr->TmrCtrPtr, 0, XDPRXSS_TMRCTR_RST_VAL); -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) - /* Initialize the HDCP timer functions */ - XHdcp1x_SetTimerStart(InstancePtr->Hdcp1xPtr, - &DpRxSs_HdcpStartTimer); - XHdcp1x_SetTimerStop(InstancePtr->Hdcp1xPtr, - &DpRxSs_HdcpStopTimer); - XHdcp1x_SetTimerDelay(InstancePtr->Hdcp1xPtr, - &DpRxSs_HdcpBusyDelay); -#endif /*XPAR_DPRXSS_0_HDCP_ENABLE*/ +#if (XPAR_XHDCP_NUM_INSTANCES > 0) + if (InstancePtr->Hdcp1xPtr != NULL) { + /* Initialize the HDCP timer functions */ + XHdcp1x_SetTimerStart(InstancePtr->Hdcp1xPtr, + &DpRxSs_HdcpStartTimer); + XHdcp1x_SetTimerStop(InstancePtr->Hdcp1xPtr, + &DpRxSs_HdcpStopTimer); + XHdcp1x_SetTimerDelay(InstancePtr->Hdcp1xPtr, + &DpRxSs_HdcpBusyDelay); + } +#endif } #endif -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) /* Check for HDCP availability */ if ((InstancePtr->Hdcp1xPtr != NULL) && (InstancePtr->Config.HdcpEnable)) { xdbg_printf(XDBG_DEBUG_GENERAL,"SS INFO: Initializing HDCP IP " "\n\r"); - /* Calculate absolute base address of HDCP sub-core */ - InstancePtr->Config.Hdcp1xSubCore.Hdcp1xConfig.BaseAddress += - InstancePtr->Config.BaseAddress; - (void)memcpy((void *)&(Hdcp1xConfig), - (const void *)&CfgPtr->Hdcp1xSubCore.Hdcp1xConfig, - sizeof(XHdcp1x_Config)); + Hdcp1xConfig = XHdcp1x_LookupConfig( + InstancePtr->Config.Hdcp1xSubCore.Hdcp1xConfig.DeviceId); + if (!ConfigPtr) { + return XST_DEVICE_NOT_FOUND; + } - /* HDCP config initialize */ - Hdcp1xConfig.BaseAddress += InstancePtr->Config.BaseAddress; + /* Calculate absolute base address of HDCP sub-core */ + Hdcp1xConfig->BaseAddress += InstancePtr->Config.BaseAddress; + /* HDCP1x config initialize */ Status = XHdcp1x_CfgInitialize(InstancePtr->Hdcp1xPtr, - &Hdcp1xConfig, (void *)InstancePtr->DpPtr, - Hdcp1xConfig.BaseAddress); + Hdcp1xConfig, (void *)InstancePtr->DpPtr, + Hdcp1xConfig->BaseAddress); if (Status != XST_SUCCESS) { xdbg_printf(XDBG_DEBUG_GENERAL,"SS ERR:: HDCP " "initialization failed\n\r"); @@ -434,12 +436,12 @@ u32 XDpRxSs_CfgInitialize(XDpRxSs *InstancePtr, XDpRxSs_Config *CfgPtr, } #endif -#if ((XPAR_DPRXSS_0_HDCP_ENABLE > 0) || (XPAR_XHDCP22_RX_NUM_INSTANCES > 0)) +#if ((XPAR_XHDCP_NUM_INSTANCES > 0) || (XPAR_XHDCP22_RX_NUM_INSTANCES > 0)) /* Default value */ InstancePtr->HdcpIsReady = FALSE; #endif -#if ((XPAR_DPRXSS_0_HDCP_ENABLE > 0) && (XPAR_XHDCP22_RX_NUM_INSTANCES > 0)) +#if ((XPAR_XHDCP_NUM_INSTANCES > 0) && (XPAR_XHDCP22_RX_NUM_INSTANCES > 0)) /* * Set default HDCP protocol. * Setting HDCP1x as default if both HDCP1x @@ -460,8 +462,15 @@ u32 XDpRxSs_CfgInitialize(XDpRxSs *InstancePtr, XDpRxSs_Config *CfgPtr, "protocol\n\r"); return XST_FAILURE; } + } else if (InstancePtr->Hdcp22Ptr && + InstancePtr->Hdcp22Lc128Ptr && + InstancePtr->Hdcp22PrivateKeyPtr) { + InstancePtr->HdcpIsReady = TRUE; + + /* Set default HDCP content protection scheme */ + XDpRxSs_HdcpSetProtocol(InstancePtr, XDPRXSS_HDCP_22); } -#elif (XPAR_DPRXSS_0_HDCP_ENABLE > 0) +#elif (XPAR_XHDCP_NUM_INSTANCES > 0) /* * HDCP1X. * HDCP is ready when only the HDCP 1.4 core is @@ -516,13 +525,13 @@ void XDpRxSs_Reset(XDpRxSs *InstancePtr) /* Verify argument. */ Xil_AssertVoid(InstancePtr != NULL); -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) /* Reset HDCP interface */ if ((InstancePtr->Hdcp1xPtr) && (InstancePtr->Config.HdcpEnable)) { XHdcp1x_Reset(InstancePtr->Hdcp1xPtr); } #endif -#if (((XPAR_DPRXSS_0_HDCP_ENABLE > 0) || \ +#if (((XPAR_XHDCP_NUM_INSTANCES > 0) || \ (XPAR_XHDCP22_RX_NUM_INSTANCES > 0)) \ && (XPAR_XTMRCTR_NUM_INSTANCES > 0)) /* Reset Timer Counter zero */ @@ -824,7 +833,7 @@ u32 XDpRxSs_HandleDownReq(XDpRxSs *InstancePtr) return Status; } -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) || (XPAR_XHDCP22_RX_NUM_INSTANCES > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) || (XPAR_XHDCP22_RX_NUM_INSTANCES > 0) /*****************************************************************************/ /** * @@ -848,17 +857,19 @@ u32 XDpRxSs_HdcpEnable(XDpRxSs *InstancePtr) /* Verify arguments.*/ Xil_AssertNonvoid(InstancePtr); -#if (XPAR_DPTXSS_0_HDCP_ENABLE > 0) - Xil_AssertNonvoid(InstancePtr->Config.HdcpEnable); +#if (XPAR_XHDCP_NUM_INSTANCES > 0) + if (InstancePtr->Hdcp1xPtr) + Xil_AssertNonvoid(InstancePtr->Config.HdcpEnable); #endif #if (XPAR_XHDCP22_RX_NUM_INSTANCES > 0) - Xil_AssertNonvoid(InstancePtr->Config.Hdcp22Enable); + if (InstancePtr->Hdcp22Ptr) + Xil_AssertNonvoid(InstancePtr->Config.Hdcp22Enable); #endif switch (InstancePtr->HdcpProtocol) { /* Disable HDCP 1.4 and HDCP 2.2 */ case XDPRXSS_HDCP_NONE : -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) if (InstancePtr->Hdcp1xPtr) { Status1 = XHdcp1x_Disable( InstancePtr->Hdcp1xPtr); @@ -877,7 +888,7 @@ u32 XDpRxSs_HdcpEnable(XDpRxSs *InstancePtr) /* Enable HDCP 1.4 and disable HDCP 2.2 */ case XDPRXSS_HDCP_14 : -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) if (InstancePtr->Hdcp1xPtr) { Status1 = XHdcp1x_Enable( InstancePtr->Hdcp1xPtr); @@ -901,7 +912,7 @@ u32 XDpRxSs_HdcpEnable(XDpRxSs *InstancePtr) /* Enable HDCP 2.2 and disable HDCP 1.4 */ case XDPRXSS_HDCP_22 : -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) if (InstancePtr->Hdcp1xPtr) { Status1 = XHdcp1x_Disable( InstancePtr->Hdcp1xPtr); @@ -951,11 +962,13 @@ u32 XDpRxSs_HdcpDisable(XDpRxSs *InstancePtr) /* Verify arguments.*/ Xil_AssertNonvoid(InstancePtr); -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) - Xil_AssertNonvoid(InstancePtr->Config.HdcpEnable); +#if (XPAR_XHDCP_NUM_INSTANCES > 0) + if (InstancePtr->Hdcp1xPtr) + Xil_AssertNonvoid(InstancePtr->Config.HdcpEnable); #endif #if (XPAR_XHDCP22_RX_NUM_INSTANCES > 0) - Xil_AssertNonvoid(InstancePtr->Config.Hdcp22Enable); + if (InstancePtr->Hdcp22Ptr) + Xil_AssertNonvoid(InstancePtr->Config.Hdcp22Enable); #endif /* Set protocol to NONE then reset/disable HDCP 1X and 2.2 */ InstancePtr->HdcpProtocol = XDPRXSS_HDCP_NONE; @@ -965,7 +978,7 @@ u32 XDpRxSs_HdcpDisable(XDpRxSs *InstancePtr) } #endif -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) /*****************************************************************************/ /** * @@ -1029,7 +1042,7 @@ u32 XDpRxSs_SetPhysicalState(XDpRxSs *InstancePtr, u32 PhyState) } #endif -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) || (XPAR_XHDCP22_RX_NUM_INSTANCES > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) || (XPAR_XHDCP22_RX_NUM_INSTANCES > 0) /*****************************************************************************/ /** * @@ -1054,17 +1067,19 @@ u32 XDpRxSs_SetLane(XDpRxSs *InstancePtr, u32 Lane) /* Verify arguments. */ Xil_AssertNonvoid(InstancePtr); -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) - Xil_AssertNonvoid(InstancePtr->Config.HdcpEnable); +#if (XPAR_XHDCP_NUM_INSTANCES > 0) + if (InstancePtr->Hdcp1xPtr) + Xil_AssertNonvoid(InstancePtr->Config.HdcpEnable); #endif #if (XPAR_XHDCP22_RX_NUM_INSTANCES > 0) - Xil_AssertNonvoid(InstancePtr->Config.Hdcp22Enable); + if (InstancePtr->Hdcp22Ptr) + Xil_AssertNonvoid(InstancePtr->Config.Hdcp22Enable); #endif Xil_AssertNonvoid((Lane == XDPRXSS_LANE_COUNT_SET_1) || (Lane == XDPRXSS_LANE_COUNT_SET_2) || (Lane == XDPRXSS_LANE_COUNT_SET_4)); -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) if (InstancePtr->Hdcp1xPtr) { /* Set lanes into the HDCP interface */ Status = XHdcp1x_SetLaneCount(InstancePtr->Hdcp1xPtr, Lane); @@ -1086,7 +1101,7 @@ u32 XDpRxSs_SetLane(XDpRxSs *InstancePtr, u32 Lane) } #endif -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) /*****************************************************************************/ /** * @@ -1336,7 +1351,7 @@ static void DpRxSs_TimeOutCallback(void *InstancePtr, u8 TmrCtrNumber) } #endif -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) /*****************************************************************************/ /** * @@ -1583,15 +1598,15 @@ static void DpRxSs_GetIncludedSubCores(XDpRxSs *InstancePtr) (&DpRxSsSubCores[ InstancePtr->Config.DeviceId].IicInst) : NULL); -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) /* Assign instance of HDCP core */ InstancePtr->Hdcp1xPtr = ((InstancePtr->Config.Hdcp1xSubCore.IsPresent) ? (&DpRxSsSubCores[InstancePtr->Config.DeviceId].Hdcp1xInst) : NULL); #endif -#if (((XPAR_DPRXSS_0_HDCP_ENABLE > 0) || \ - (XPAR_XHDCP22_RX_NUM_INSTANCES > 0)) \ +#if (((XPAR_XHDCP_NUM_INSTANCES > 0) || \ + (XPAR_XHDCP22_RX_NUM_INSTANCES > 0)) \ && (XPAR_XTMRCTR_NUM_INSTANCES > 0)) /* Assign instance of Timer Counter core */ InstancePtr->TmrCtrPtr = @@ -1599,11 +1614,12 @@ static void DpRxSs_GetIncludedSubCores(XDpRxSs *InstancePtr) (&DpRxSsSubCores[InstancePtr->Config.DeviceId].TmrCtrInst) : NULL); #endif -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) - InstancePtr->Hdcp1xPtr->Hdcp1xRef = (void *)InstancePtr->TmrCtrPtr; +#if (XPAR_XHDCP_NUM_INSTANCES > 0) + if (InstancePtr->Hdcp1xPtr != NULL) + InstancePtr->Hdcp1xPtr->Hdcp1xRef = + (void *)InstancePtr->TmrCtrPtr; #endif - #if (XPAR_XHDCP22_RX_NUM_INSTANCES > 0) /*Assign Instance of HDCP22 core*/ InstancePtr->Hdcp22Ptr = @@ -1973,7 +1989,7 @@ void XDpRxSs_McDp6000_init(void *InstancePtr, u32 I2CAddress) } -#if ((XPAR_DPRXSS_0_HDCP_ENABLE > 0) || (XPAR_XHDCP22_RX_NUM_INSTANCES > 0)) +#if ((XPAR_XHDCP_NUM_INSTANCES > 0) || (XPAR_XHDCP22_RX_NUM_INSTANCES > 0)) /*****************************************************************************/ /** * @@ -1996,7 +2012,7 @@ static int XDpRxSs_HdcpReset(XDpRxSs *InstancePtr) int Status = XST_SUCCESS; -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) /* HDCP 1.4 */ /* Resetting HDCP 1.4 causes the state machine to be enabled, therefore * disable must be called immediately after reset is called diff --git a/XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss.h b/XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss.h index 5e32ddb8e12..51bbc2987ab 100644 --- a/XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss.h +++ b/XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss.h @@ -203,7 +203,7 @@ typedef enum { XDPRXSS_HANDLER_DP_CRC_TEST_EVENT, /**< CRC test start event * interrupt type for * DisplayPort core */ -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) XDPRXSS_HANDLER_HDCP_RPTR_TDSA_EVENT, /**< Repeater Trigger * Downstream AUTH event * interrupt type for @@ -295,29 +295,43 @@ typedef struct { * information */ } XDpRxSs_IicSubCore; -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) +/** +* This typedef contains configuration information for the +* DpRxSs subcore instances. +*/ +typedef struct { + u16 DeviceId; /**< Device ID of the sub-core */ + UINTPTR AbsAddr; /**< Absolute Base Address of the Sub-cores*/ +} XDpRxSs_SubCoreConfig; + /** * High-Bandwidth Content Protection (HDCP) Sub-core structure. */ typedef struct { u16 IsPresent; /**< Flag to hold the presence of HDCP core. */ - XHdcp1x_Config Hdcp1xConfig; /**< HDCP core configuration - * information */ + XDpRxSs_SubCoreConfig Hdcp1xConfig; /**< HDCP core configuration + information */ } XDpRxSs_Hdcp1xSubCore; -#endif -#if (((XPAR_DPRXSS_0_HDCP_ENABLE > 0) || (XPAR_XHDCP22_RX_NUM_INSTANCES > 0))\ - && (XPAR_XTMRCTR_NUM_INSTANCES > 0)) /** * Timer Counter Sub-core structure. */ typedef struct { u16 IsPresent; /**< Flag to hold the presence of Timer * Counter core */ - XTmrCtr_Config TmrCtrConfig; /**< Timer Counter core + XDpRxSs_SubCoreConfig TmrCtrConfig; /**< Timer Counter core * configuration information */ } XDpRxSs_TmrCtrSubCore; -#endif + +/** + * Sub-Core Configuration Table + */ +typedef struct +{ + u16 IsPresent; /**< Flag to indicate if sub-core is present in + the design*/ + XDpRxSs_SubCoreConfig Hdcp22Config; /**< HDCP22 core configuration */ +} XDpRxSs_Hdcp22SubCore; /** * This typedef contains configuration information for the DisplayPort @@ -347,19 +361,12 @@ typedef struct { * by this core instance. */ u8 ColorFormat; /**< Type of color format supported by this * core instance. */ - XDpRxSs_DpSubCore DpSubCore; /**< DisplayPort Configuration */ -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) - XDpRxSs_Hdcp1xSubCore Hdcp1xSubCore; /**< HDCP Configuration */ -#endif -#if (XPAR_XHDCP22_RX_NUM_INSTANCES > 0) - XDpRxSs_Hdcp22SubCore Hdcp22SubCore; -#endif XDpRxSs_IicSubCore IicSubCore; /**< IIC Configuration */ -#if (((XPAR_DPRXSS_0_HDCP_ENABLE > 0) || (XPAR_XHDCP22_RX_NUM_INSTANCES > 0))\ - && (XPAR_XTMRCTR_NUM_INSTANCES > 0)) XDpRxSs_TmrCtrSubCore TmrCtrSubCore; /**< Timer Counter * Configuration */ -#endif + XDpRxSs_DpSubCore DpSubCore; /**< DisplayPort Configuration */ + XDpRxSs_Hdcp1xSubCore Hdcp1xSubCore; /**< HDCP Configuration */ + XDpRxSs_Hdcp22SubCore Hdcp22SubCore; } XDpRxSs_Config; /*****************************************************************************/ @@ -385,10 +392,10 @@ typedef struct { /* Sub-core instances */ XDp *DpPtr; /**< DisplayPort sub-core instance */ XIic *IicPtr; /**< IIC sub-core instance */ -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) XHdcp1x *Hdcp1xPtr; /**< HDCP sub-core instance */ #endif -#if (((XPAR_DPRXSS_0_HDCP_ENABLE > 0) || \ +#if (((XPAR_XHDCP_NUM_INSTANCES > 0) || \ (XPAR_XHDCP22_RX_NUM_INSTANCES > 0)) \ && (XPAR_XTMRCTR_NUM_INSTANCES > 0)) XTmrCtr *TmrCtrPtr; /**< Timer Counter sub-core instance */ @@ -443,7 +450,7 @@ typedef struct { u8 link_up_trigger; u8 no_video_trigger; XDpRxSs_HdcpProtocol HdcpProtocol; /**< HDCP protocol selected */ -#if ((XPAR_DPRXSS_0_HDCP_ENABLE > 0) || (XPAR_XHDCP22_RX_NUM_INSTANCES > 0)) +#if ((XPAR_XHDCP_NUM_INSTANCES > 0) || (XPAR_XHDCP22_RX_NUM_INSTANCES > 0)) u8 HdcpIsReady; /**< HDCP ready flag */ #endif #if (XPAR_XHDCP22_RX_NUM_INSTANCES > 0) @@ -591,7 +598,7 @@ typedef struct { #define XDpRxSs_WaitUs(InstancePtr, MicroSeconds) \ XDp_WaitUs((InstancePtr)->DpPtr, MicroSeconds) -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) #define XDpRxSs_Printf XHdcp1x_Printf /**< Debug printf */ #define XDpRxSs_LogMsg XHdcp1x_LogMsg /**< Debug log message */ #endif @@ -613,7 +620,7 @@ u32 XDpRxSs_CheckLinkStatus(XDpRxSs *InstancePtr); u32 XDpRxSs_HandleDownReq(XDpRxSs *InstancePtr); void XDpRxSs_SetUserPixelWidth(XDpRxSs *InstancePtr, u8 UserPixelWidth); -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) || (XPAR_XHDCP22_RX_NUM_INSTANCES > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) || (XPAR_XHDCP22_RX_NUM_INSTANCES > 0) int XDpRxSs_HdcpSetProtocol(XDpRxSs *InstancePtr, XDpRxSs_HdcpProtocol Protocol); /* Optional HDCP related functions */ @@ -623,7 +630,7 @@ u32 XDpRxSs_SetLane(XDpRxSs *InstancePtr, u32 Lane); void XDpRxSs_StartTimer(XDpRxSs *InstancePtr); void XDpRxSs_StopTimer(XDpRxSs *InstancePtr); #endif -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) /* Optional HDCP related functions */ u32 XDpRxSs_Poll(XDpRxSs *InstancePtr); u32 XDpRxSs_SetPhysicalState(XDpRxSs *InstancePtr, u32 PhyState); @@ -646,10 +653,10 @@ void XDpRxSs_ReportHdcpInfo(XDpRxSs *InstancePtr); u32 XDpRxSs_SelfTest(XDpRxSs *InstancePtr); /* Interrupt functions in xdprxss_intr.c */ -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) void XDpRxSs_HdcpIntrHandler(void *InstancePtr); #endif -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) || (XPAR_XHDCP22_RX_NUM_INSTANCES > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) || (XPAR_XHDCP22_RX_NUM_INSTANCES > 0) void XDpRxSs_TmrCtrIntrHandler(void *InstancePtr); #endif void XDpRxSs_DpIntrHandler(void *InstancePtr); diff --git a/XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss_dbg.c b/XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss_dbg.c index a71737ec58e..b27ac02f04b 100644 --- a/XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss_dbg.c +++ b/XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss_dbg.c @@ -90,12 +90,12 @@ void XDpRxSs_ReportCoreInfo(XDpRxSs *InstancePtr) xil_printf("\n\rDisplayPort RX Subsystem info:\n\r"); /* Report all the included cores in the subsystem instance */ -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) if (InstancePtr->Hdcp1xPtr) { xil_printf("High-Bandwidth Content protection (HDCP):Yes\n\r"); } #endif -#if (((XPAR_DPRXSS_0_HDCP_ENABLE > 0) || \ +#if (((XPAR_XHDCP_NUM_INSTANCES > 0) || \ (XPAR_XHDCP22_RX_NUM_INSTANCES > 0)) \ && (XPAR_XTMRCTR_NUM_INSTANCES > 0)) if (InstancePtr->TmrCtrPtr) { @@ -296,10 +296,11 @@ void XDpRxSs_ReportHdcpInfo(XDpRxSs *InstancePtr) /* Verify argument. */ Xil_AssertVoid(InstancePtr != NULL); -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) - XHdcp1x_Info(InstancePtr->Hdcp1xPtr); -#else - xil_printf("HDCP is not supported in this design.\n\r"); +#if (XPAR_XHDCP_NUM_INSTANCES > 0) + if (InstancePtr->Hdcp1xPtr) + XHdcp1x_Info(InstancePtr->Hdcp1xPtr); + else #endif + xil_printf("HDCP is not supported in this design.\n\r"); } /** @} */ diff --git a/XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss_g.c b/XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss_g.c index 430926072bb..7fab7bea81a 100644 --- a/XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss_g.c +++ b/XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss_g.c @@ -39,11 +39,20 @@ * The configuration table for devices */ + +/* +* List of Sub-cores included from the subsystem +*/ #define XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_DP_PRESENT 1 +#define XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_DP_RX_HDCP_PRESENT 1 #define XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_DP_RX_HDCP22_PRESENT 1 #define XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_IIC_PRESENT 1 #define XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_TIMER_PRESENT 1 +/* +* List of Sub-cores excluded from the subsystem +*/ + XDpRxSs_Config XDpRxSs_ConfigTable[] = { @@ -60,6 +69,22 @@ XDpRxSs_Config XDpRxSs_ConfigTable[] = XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_NUM_STREAMS, XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_COLOR_FORMAT, + { + XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_IIC_PRESENT, + { + XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_IIC_DEVICE_ID, + XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_IIC_BASEADDR, + XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_IIC_TEN_BIT_ADR, + XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_IIC_GPO_WIDTH + } + }, + { + XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_TIMER_PRESENT, + { + XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_TIMER_DEVICE_ID, + XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_TIMER_BASEADDR + } + }, { XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_DP_PRESENT, { @@ -83,28 +108,18 @@ XDpRxSs_Config XDpRxSs_ConfigTable[] = } }, { - XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_DP_RX_HDCP22_PRESENT, + XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_DP_RX_HDCP_PRESENT, { - XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_DP_RX_HDCP22_DEVICE_ID, - XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_DP_RX_HDCP22_BASEADDR + XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_DP_RX_HDCP_DEVICE_ID, + XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_DP_RX_HDCP_BASEADDR } }, { - XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_IIC_PRESENT, - { - XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_IIC_DEVICE_ID, - XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_IIC_BASEADDR, - XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_IIC_TEN_BIT_ADR, - XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_IIC_GPO_WIDTH - } - }, - { - XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_TIMER_PRESENT, + XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_DP_RX_HDCP22_PRESENT, { - XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_TIMER_DEVICE_ID, - XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_TIMER_BASEADDR, - XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_TIMER_CLOCK_FREQ_HZ + XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_DP_RX_HDCP22_DEVICE_ID, + XPAR_DP_RX_HIER_0_V_DP_RXSS1_0_DP_RX_HDCP22_BASEADDR } - }, + } } }; diff --git a/XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss_intr.c b/XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss_intr.c index cc74712af54..1fde8debd6a 100644 --- a/XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss_intr.c +++ b/XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss_intr.c @@ -104,7 +104,7 @@ void XDpRxSs_DpIntrHandler(void *InstancePtr) XDp_InterruptHandler(XDpRxSsPtr->DpPtr); } -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) /*****************************************************************************/ /** * @@ -163,7 +163,7 @@ void XDpRxSs_Hdcp22LicFailHandler(void *InstancePtr) } #endif -#if (((XPAR_DPRXSS_0_HDCP_ENABLE > 0) || \ +#if (((XPAR_XHDCP_NUM_INSTANCES > 0) || \ (XPAR_XHDCP22_RX_NUM_INSTANCES > 0)) \ && (XPAR_XTMRCTR_NUM_INSTANCES > 0)) /*****************************************************************************/ @@ -502,7 +502,7 @@ u32 XDpRxSs_SetCallBack(XDpRxSs *InstancePtr, u32 HandlerType, Status = XST_SUCCESS; break; -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) case XDPRXSS_HANDLER_HDCP_RPTR_TDSA_EVENT: XHdcp1x_SetCallBack(InstancePtr->Hdcp1xPtr, XHDCP1X_RPTR_HDLR_TRIG_DOWNSTREAM_AUTH, diff --git a/XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss_selftest.c b/XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss_selftest.c index 764d9693dff..77212e2b40d 100644 --- a/XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss_selftest.c +++ b/XilinxProcessorIPLib/drivers/dp14rxss/src/xdprxss_selftest.c @@ -99,7 +99,7 @@ u32 XDpRxSs_SelfTest(XDpRxSs *InstancePtr) } } -#if (XPAR_DPRXSS_0_HDCP_ENABLE > 0) +#if (XPAR_XHDCP_NUM_INSTANCES > 0) if ((InstancePtr->Hdcp1xPtr) && (InstancePtr->Config.HdcpEnable)) { Status = XHdcp1x_SelfTest(InstancePtr->Hdcp1xPtr); if (Status != XST_SUCCESS) { @@ -110,7 +110,7 @@ u32 XDpRxSs_SelfTest(XDpRxSs *InstancePtr) } #endif -#if (((XPAR_DPRXSS_0_HDCP_ENABLE > 0) || \ +#if (((XPAR_XHDCP_NUM_INSTANCES > 0) || \ (XPAR_XHDCP22_RX_NUM_INSTANCES > 0)) \ && (XPAR_XTMRCTR_NUM_INSTANCES > 0)) if (InstancePtr->TmrCtrPtr) {