Merge branch 'dev' into main

microdynamics-cpu · Jan 21, 2022 · ab8396d · ab8396d
2 parents 2fcde70 + 45afe5b
commit ab8396d
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Showing 44 changed files with 266 additions and 298 deletions.
diff --git a/rtl/tc_l2/src/main/scala/axi4/AXI4Bridge.scala b/rtl/tc_l2/src/main/scala/axi4/AXI4Bridge.scala
@@ -1,12 +1,9 @@
-package sim
+package treecorel2
 
 import chisel3._
 import chisel3.util._
 
-import treecorel2._
-import treecorel2.common.AXI4Config
-
-class AXI4Bridge extends Module with AXI4Config {
+class AXI4Bridge extends Module with InstConfig {
   val io = IO(new Bundle {
     val socEn = Input(Bool())
     val runEn = Output(Bool())
@@ -25,10 +22,9 @@ class AXI4Bridge extends Module with AXI4Config {
   arbiter.io.rHdShk   := io.axi.r.fire()
 
   protected val wMask     = arbiter.io.dxchg.wmask
-  protected val byteSize  = wMask(7) + wMask(6) + wMask(5) + wMask(4) + wMask(3) + wMask(2) + wMask(1) + wMask(0)
   protected val socARSize = arbiter.io.dxchg.rsize
   protected val socAWSize = MuxLookup(
-    byteSize,
+    PopCount(wMask),
     0.U,
     Array(
       8.U -> 3.U,

diff --git a/rtl/tc_l2/src/main/scala/axi4/Arbiter.scala b/rtl/tc_l2/src/main/scala/axi4/Arbiter.scala
@@ -1,24 +1,21 @@
-package sim
+package treecorel2
 
 import chisel3._
 import chisel3.util._
 
-import treecorel2.DXCHGIO
-import treecorel2.common.AXI4Config
-
 object Arbiter {
 // FSM var for read/write
   val eumIDLE :: eumStandby :: eumIDLE2 :: eumAW :: eumW :: eumB :: eumAR :: eumR :: Nil = Enum(8)
 }
 
-class Arbiter extends Module with AXI4Config {
+class Arbiter extends Module with InstConfig {
   val io = IO(new Bundle {
     val awHdShk  = Input(Bool())
     val wHdShk   = Input(Bool())
     val bHdShk   = Input(Bool())
     val arHdShk  = Input(Bool())
     val rHdShk   = Input(Bool())
-    val axirdata = Input(UInt(64.W))
+    val axirdata = Input(UInt(XLen.W))
     val dxchg    = Flipped(new DXCHGIO)
     val state    = Output(UInt(3.W))
     val runEn    = Output(Bool())
@@ -30,13 +27,13 @@ class Arbiter extends Module with AXI4Config {
 
   protected val valid    = RegInit(false.B)
   protected val ren      = RegInit(false.B)
-  protected val raddr    = RegInit(0.U(64.W))
-  protected val rdata    = RegInit(0.U(64.W))
+  protected val raddr    = RegInit(0.U(XLen.W))
+  protected val rdata    = RegInit(0.U(XLen.W))
   protected val rsize    = RegInit(0.U(3.W))
   protected val wen      = RegInit(false.B)
-  protected val waddr    = RegInit(0.U(64.W))
-  protected val wdata    = RegInit(0.U(64.W))
-  protected val wmask    = RegInit(0.U(8.W))
+  protected val waddr    = RegInit(0.U(XLen.W))
+  protected val wdata    = RegInit(0.U(XLen.W))
+  protected val wmask    = RegInit(0.U(MaskLen.W))
   protected val stateReg = RegInit(Arbiter.eumIDLE)
   io.state       := stateReg
   io.dxchg.rdata := rdata

diff --git a/rtl/tc_l2/src/main/scala/axi4/Crossbar.scala b/rtl/tc_l2/src/main/scala/axi4/Crossbar.scala
@@ -3,8 +3,6 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.InstConfig
-
 class Crossbar extends Module with InstConfig {
   val io = IO(new Bundle {
     val socEn = Input(Bool())
@@ -14,7 +12,7 @@ class Crossbar extends Module with InstConfig {
   })
 
   protected val globalEn = RegInit(false.B)
-  protected val inst     = RegInit(0.U(32.W))
+  protected val inst     = RegInit(0.U(InstLen.W))
   protected val rdInst   = Mux(io.core.fetch.addr(2).asBool(), io.dxchg.rdata(63, 32), io.dxchg.rdata(31, 0))
 
   io.core.globalEn   := Mux(io.runEn, globalEn, false.B)
@@ -37,25 +35,25 @@ class Crossbar extends Module with InstConfig {
       when(io.runEn) {
         globalEn := false.B
         stateReg := eumInst
-        inst     := 0x13.U
+        inst     := NOPInst
       }
     }
   }
 
   // because the difftest's logic addr is 0x000000
-  protected val instSize  = Mux(io.socEn, InstSoCRSize, InstDiffRSize)
-  protected val baseAddr  = Mux(io.socEn, SoCStartBaseAddr, SoCStartBaseAddr)
-  protected val instAddr  = io.core.fetch.addr - baseAddr
-  protected val loadAddr  = io.core.ld.addr - baseAddr
-  protected val storeAddr = io.core.sd.addr - baseAddr
-  protected val maEn      = io.core.ld.en || io.core.sd.en
+  protected val instSize = Mux(io.socEn, InstSoCRSize, InstDiffRSize)
+  protected val baseAddr = Mux(io.socEn, SoCStartBaseAddr, SoCStartBaseAddr)
+  protected val instAddr = io.core.fetch.addr - baseAddr
+  protected val ldAddr   = io.core.ld.addr - baseAddr
+  protected val sdAddr   = io.core.sd.addr - baseAddr
+  protected val maEn     = io.core.ld.en || io.core.sd.en
 
   // prepare the data exchange io signals
   io.dxchg.ren   := ((stateReg === eumInst) || (stateReg === eumMem && maEn))
-  io.dxchg.raddr := Mux(stateReg === eumInst, instAddr, loadAddr)
+  io.dxchg.raddr := Mux(stateReg === eumInst, instAddr, ldAddr)
   io.dxchg.rsize := Mux(stateReg === eumMem && io.core.ld.en, io.core.ld.size, instSize)
   io.dxchg.wen   := stateReg === eumMem && io.core.sd.en
-  io.dxchg.waddr := storeAddr
+  io.dxchg.waddr := sdAddr
   io.dxchg.wdata := io.core.sd.data
   io.dxchg.wmask := io.core.sd.mask
 }
diff --git a/rtl/tc_l2/src/main/scala/common/AXI4Config.scala b/rtl/tc_l2/src/main/scala/common/AXI4Config.scala
@@ -1,6 +1,18 @@
-package treecorel2.common
+package treecorel2
 
 import chisel3._
 import chisel3.util._
 
-trait AXI4Config extends InstConfig {}
+trait AXI4Config extends IOConfig {
+  val AxiProtLen   = 3
+  val AxiIdLen     = 4
+  val AxiUserLen   = 1
+  val AxiSizeLen   = 3 // NOTE: or 2?
+  val AxiLen       = 8
+  val AxiStrb      = 8
+  val AxiBurstLen  = 2
+  val AxiCacheLen  = 4
+  val AxiQosLen    = 4
+  val AxiRegionLen = 4
+  val AxiRespLen   = 2
+}
diff --git a/rtl/tc_l2/src/main/scala/common/ConstVal.scala b/rtl/tc_l2/src/main/scala/common/ConstVal.scala
diff --git a/rtl/tc_l2/src/main/scala/common/InstConfig.scala b/rtl/tc_l2/src/main/scala/common/InstConfig.scala
@@ -1,13 +1,30 @@
-package treecorel2.common
+package treecorel2
 
 import chisel3._
 import chisel3.util._
 
-trait InstConfig {
-  val SoCEna            = false
-  val XLen              = 64
-  val InstLen           = 32
-  val RegfileNum        = 32
+trait IOConfig {
+  val XLen       = 64
+  val InstLen    = 32
+  val RegfileLen = 5
+  val RegfileNum = 1 << RegfileLen
+  val ISALen     = 6
+  // mem
+  val MaskLen = 8
+  val LDSize  = 3
+  // branch prediction
+  val GHRLen    = 5
+  val PHTSize   = 1 << GHRLen
+  val BTBIdxLen = 5
+  val BTBPcLen  = XLen - BTBIdxLen
+  val BTBTgtLen = XLen
+  val BTBSize   = 1 << BTBIdxLen
+}
+
+trait InstConfig extends IOConfig {
+  val SoCEna   = true
+  val CacheEna = false
+
   val FlashStartAddr    = "h0000000030000000".U(XLen.W)
   val SimStartAddr      = "h0000000080000000".U(XLen.W)
   val DiffStartBaseAddr = "h0000000080000000".U(XLen.W)
@@ -17,8 +34,8 @@ trait InstConfig {
   val InstSoCRSize      = 2.U
   val InstDiffRSize     = 3.U
   val DiffRWSize        = 3.U
-  val CacheEna          = false
 
+  val NOPInst = 0x13.U
   // inst type
   // nop is equal to [addi x0, x0, 0], so the oper is same as 'addi' inst
   val InstTypeLen = 3
@@ -95,14 +112,6 @@ trait InstConfig {
   val instFENCE_I = 59.U(InstValLen.W)
   val instCUST    = 60.U(InstValLen.W)
 
-  // branch prediction
-  val GHRLen    = 5
-  val PHTSize   = 1 << GHRLen
-  val BTBIdxLen = 5
-  val BTBPcLen  = XLen - BTBIdxLen
-  val BTBTgtLen = XLen
-  val BTBSize   = 1 << BTBIdxLen
-
   // cache
   val NWay          = 4
   val NBank         = 4
@@ -131,4 +140,8 @@ trait InstConfig {
   val medelegAddr  = 0x302.U(CSRAddrLen.W)
   val timeCause    = "h8000_0000_0000_0007".U(XLen.W)
   val ecallCause   = "h0000_0000_0000_000b".U(XLen.W)
+
+  // special inst
+  val customInst = "h0000007b".U(InstLen.W)
+  val haltInst   = "h0000006b".U(InstLen.W)
 }
diff --git a/rtl/tc_l2/src/main/scala/core/Processor.scala b/rtl/tc_l2/src/main/scala/core/Processor.scala
@@ -1,10 +1,9 @@
-package sim
+package treecorel2
 
 import chisel3._
 import chisel3.util._
 
 import difftest._
-import treecorel2._
 
 class Processor extends Module {
   val io = IO(new Bundle {

diff --git a/rtl/tc_l2/src/main/scala/core/StallControl.scala b/rtl/tc_l2/src/main/scala/core/StallControl.scala
@@ -0,0 +1,23 @@
+package treecorel2
+
+import chisel3._
+import chisel3.util._
+
+class StallControl extends Module with InstConfig {
+  val io = IO(new Bundle {
+    val globalEn = Input(Bool())
+    val stall    = Input(Bool())
+    val st1      = Output(Bool())
+    val st2      = Output(Bool())
+    val st3      = Output(Bool())
+  })
+
+  protected val (tickCnt, cntWrap) = Counter(io.globalEn && io.stall, 3)
+  protected val cyc1               = io.stall && (tickCnt === 0.U)
+  protected val cyc2               = io.stall && (tickCnt === 1.U)
+  protected val cyc3               = io.stall && (tickCnt === 2.U)
+
+  io.st1 := cyc1
+  io.st2 := cyc2
+  io.st3 := cyc3
+}
diff --git a/rtl/tc_l2/src/main/scala/core/TreeCoreL2.scala b/rtl/tc_l2/src/main/scala/core/TreeCoreL2.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import difftest._
 
-class TreeCoreL2 extends Module {
+class TreeCoreL2 extends Module with InstConfig {
   val io = IO(new Bundle {
     val globalEn = Input(Bool())
     val socEn    = Input(Bool())
@@ -43,31 +43,29 @@ class TreeCoreL2 extends Module {
   exu.io.nxtPC <> ifu.io.nxtPC
   exu.io.mtip  <> mau.io.mtip
 
-  // stall
-  protected val isStall            = exu.io.stall
-  protected val (tickCnt, cntWrap) = Counter(io.globalEn && isStall, 3)
-  protected val cyc1               = isStall && (tickCnt === 0.U)
-  protected val cyc2               = isStall && (tickCnt === 1.U)
-  protected val cyc3               = isStall && (tickCnt === 2.U)
+  // stall control
+  protected val stallCtrl = Module(new StallControl)
+  stallCtrl.io.globalEn := io.globalEn
+  stallCtrl.io.stall    := exu.io.stall
 
-  ifu.io.stall    := cyc1
-  idu.io.stall    := cyc1
+  ifu.io.stall    := stallCtrl.io.st1
+  idu.io.stall    := stallCtrl.io.st1
   ifu.io.globalEn := io.globalEn
   idu.io.globalEn := io.globalEn
-  exu.io.globalEn := Mux(cyc1 || cyc2, false.B, io.globalEn)
-  mau.io.globalEn := Mux(cyc1 || cyc2, false.B, io.globalEn)
-  wbu.io.globalEn := Mux(cyc1 || cyc2, false.B, io.globalEn)
-  idu.io.wbdata   := Mux(cyc1 || cyc2, 0.U.asTypeOf(new WBDATAIO), wbu.io.wbdata)
-  ifu.io.nxtPC    := Mux(cyc1, exu.io.nxtPC, 0.U.asTypeOf(new NXTPCIO))
+  exu.io.globalEn := Mux(stallCtrl.io.st1 || stallCtrl.io.st2, false.B, io.globalEn)
+  mau.io.globalEn := Mux(stallCtrl.io.st1 || stallCtrl.io.st2, false.B, io.globalEn)
+  wbu.io.globalEn := Mux(stallCtrl.io.st1 || stallCtrl.io.st2, false.B, io.globalEn)
+  idu.io.wbdata   := Mux(stallCtrl.io.st1 || stallCtrl.io.st2, 0.U.asTypeOf(new WBDATAIO), wbu.io.wbdata)
+  ifu.io.nxtPC    := Mux(stallCtrl.io.st1, exu.io.nxtPC, 0.U.asTypeOf(new NXTPCIO))
 
   // special judge
-  protected val lsStall   = RegEnable(cyc1, false.B, io.globalEn) || RegEnable(cyc2, false.B, io.globalEn)
-  protected val ldDataReg = RegInit(0.U(64.W))
+  protected val lsStall   = RegEnable(stallCtrl.io.st1, false.B, io.globalEn) || RegEnable(stallCtrl.io.st2, false.B, io.globalEn)
+  protected val ldDataReg = RegInit(0.U(XLen.W))
 
   when(io.globalEn) {
-    when(cyc1) {
+    when(stallCtrl.io.st1) {
       ldDataReg := io.ld.data
-    }.elsewhen(cyc3) {
+    }.elsewhen(stallCtrl.io.st3) {
       ldDataReg := 0.U
     }
   }

diff --git a/rtl/tc_l2/src/main/scala/core/exec/ACU.scala b/rtl/tc_l2/src/main/scala/core/exec/ACU.scala
@@ -3,7 +3,7 @@
 // import chisel3._
 // import chisel3.util._
 
-// import treecorel2.common.ConstVal
+// import treecorel2.ConstVal
 
 // class AGU extends Module {
 //   val io = IO(new Bundle {

diff --git a/rtl/tc_l2/src/main/scala/core/exec/ALU.scala b/rtl/tc_l2/src/main/scala/core/exec/ALU.scala
@@ -3,8 +3,6 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.InstConfig
-
 class ALU extends Module with InstConfig {
   val io = IO(new Bundle {
     val isa  = Input(UInt(InstValLen.W))

diff --git a/rtl/tc_l2/src/main/scala/core/exec/BEU.scala b/rtl/tc_l2/src/main/scala/core/exec/BEU.scala
@@ -3,8 +3,6 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.InstConfig
-
 class BEU extends Module with InstConfig {
   val io = IO(new Bundle {
     val isa        = Input(UInt(InstValLen.W))

diff --git a/rtl/tc_l2/src/main/scala/core/exec/CSRReg.scala b/rtl/tc_l2/src/main/scala/core/exec/CSRReg.scala
@@ -4,8 +4,6 @@ import chisel3._
 import chisel3.util._
 import difftest._
 
-import treecorel2.common.InstConfig
-
 class CSRReg extends Module with InstConfig {
   val io = IO(new Bundle {
     val globalEn   = Input(Bool())
@@ -43,11 +41,10 @@ class CSRReg extends Module with InstConfig {
     )
   )
 
-  protected val mretVis  = io.inst === instMRET
-  protected val ecallVis = io.inst === instECALL
-  protected val zimm     = ZeroExt(io.inst(19, 15), XLen)
-  protected val addr     = io.inst(31, 20)
-
+  protected val zimm        = ZeroExt(io.inst(19, 15), XLen)
+  protected val addr        = io.inst(31, 20)
+  protected val mretVis     = io.inst === instMRET
+  protected val ecallVis    = io.inst === instECALL
   protected val mhartidVis  = addr === mhartidAddr
   protected val mstatusVis  = addr === mstatusAddr
   protected val mieVis      = addr === mieAddr

diff --git a/rtl/tc_l2/src/main/scala/core/exec/EXU.scala b/rtl/tc_l2/src/main/scala/core/exec/EXU.scala
@@ -3,8 +3,6 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.InstConfig
-
 class EXU extends Module with InstConfig {
   val io = IO(new Bundle {
     val globalEn   = Input(Bool())
@@ -78,7 +76,7 @@ class EXU extends Module with InstConfig {
   protected val ecallEn    = csrReg.io.ecallEn
   csrReg.io.globalEn := io.globalEn
   csrReg.io.pc       := pc
-  csrReg.io.inst     := Mux(valid, inst, 0x13.U)
+  csrReg.io.inst     := Mux(valid, inst, NOPInst)
   csrReg.io.src      := src1
   csrReg.io.mtip     := io.mtip