From bbbe64043cf431c2d2e4fe68c8c2d8bbeffcc36d Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Sun, 27 Jan 2019 02:30:56 +0100 Subject: [PATCH] Fix assignments (IO Standard 2.5->3.3V LVTTL) --- mist/msx_mist.qsf | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/mist/msx_mist.qsf b/mist/msx_mist.qsf index 1151991..a6868fc 100644 --- a/mist/msx_mist.qsf +++ b/mist/msx_mist.qsf @@ -63,7 +63,7 @@ set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS ON set_global_assignment -name IGNORE_LCELL_BUFFERS ON set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name FITTER_EFFORT "AUTO FIT" set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4.0 set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0 set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION" @@ -184,7 +184,7 @@ set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:build_id_verilog.tcl" set_global_assignment -name ENABLE_SIGNALTAP OFF -set_global_assignment -name USE_SIGNALTAP_FILE output_files/joy.stp +set_global_assignment -name USE_SIGNALTAP_FILE output_files/keyb.stp set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON @@ -263,17 +263,9 @@ set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[14] set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[15] set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to SDRAM_CLK set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to SPI_SCK -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CONF_DATA0 set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED -set_global_assignment -name SYSTEMVERILOG_FILE MSX.sv -set_global_assignment -name VERILOG_FILE sd_card.v -set_global_assignment -name VERILOG_FILE mist_io.v -set_global_assignment -name VERILOG_FILE osd.v -set_global_assignment -name SYSTEMVERILOG_FILE rgb2ypbpr.sv -set_global_assignment -name VHDL_FILE dac.vhd -set_global_assignment -name QIP_FILE pll.qip -set_global_assignment -name QIP_FILE ../esemsx3/emsx.qip set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON @@ -281,6 +273,17 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON -set_global_assignment -name SIGNALTAP_FILE output_files/joy.stp set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL +set_global_assignment -name SYSTEMVERILOG_FILE MSX.sv +set_global_assignment -name VERILOG_FILE sd_card.v +set_global_assignment -name VERILOG_FILE osd.v +set_global_assignment -name SYSTEMVERILOG_FILE rgb2ypbpr.sv +set_global_assignment -name VHDL_FILE dac.vhd +set_global_assignment -name VERILOG_FILE user_io.v +set_global_assignment -name QIP_FILE pll.qip +set_global_assignment -name QIP_FILE ../esemsx3/emsx.qip +set_global_assignment -name SIGNALTAP_FILE output_files/joy.stp +set_global_assignment -name SIGNALTAP_FILE output_files/keyb.stp +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM* +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA* set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file