From ee455b6c6eae3c8044cec5fa7c1109931130ec1d Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Tue, 18 Sep 2018 16:59:48 -0700 Subject: [PATCH] Updating submodules. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * edid-decode changed from b2da151 to 5eeb151 * 5eeb151 - edid-decode: replace AdobeYCC/RGB by opYCC/RGB * litedram changed from 7a5ac75 to ea1ac4d * ea1ac4d - s6ddrphy: Pass missing nranks parameter. * e5696ad - frontend/ecc: add enable csr * e6ef89a - frontend/axi: optimize burst2beat timings * 6941285 - frontend/ecc: split Write/Read path and add buffer to improve timings * 041817d - frontend/ecc: use csr instead of signal for control * b145b0c - frontend/axi: fix write response implementation * d23dbf6 - phy: add nranks to all phys * 461b076 - frontend/ecc: add ecc adapter * c84b587 - frontend: add initial ecc code (still need to be integrated) * a8d2672 - phy/s7ddrphy_halfrate_bl8: don't generate dqs pre/post-amble, needs simulation * 5719d71 - phy/s7ddrphy_halfrate_bl8: fix cs_n * 36fa324 - core/multiplexer: fix regression (introduced by multirank support) * 42d0e5b - core/multiplexer: add more information on odt fixme * 919b756 - phy/model: pass nranks to Interface * f5c7b61 - multirank: set default nranks to 1 if not specified * f3d403f - s7ddrphy: fix typo (reset_n --> cs_n) * 37f1dec - multirank: one cs_n/cke/odt/clk per rank * 3e17d18 - phy: add halfrate_bl8 variant for s7ddrphy * 412e9a5 - Merge pull request #38 from enjoy-digital/multirank |\ | * 8ddc6c7 - drive odt of all ranks, fixes and test non regression with 1 rank | * d4f434d - dfii: send command to all ranks | * b1c2739 - initial multirank support (nbankmachines = nranks * (2**bankbits)) * | d9c2430 - Merge pull request #36 from JohnSully/timing_1 |\ \ | |/ |/| | * efd7a47 - Fix failing timing <> * | cc481be - examples: add sdram_rank_nb and user_ports_id_width |/ * 849b1f6 - frontend/axi: generate rlast signal * 1fa73e4 - test: update * 7b61b68 - sdram_init: min value for wr is 5 * 1652ab9 - examples/litedram_gen: fix address width of axi ports (addressing in bytes not words) * 1e64b7f - examples/litedram_gen: expose resp signals to user * 700f76c - frontend/axi: add resp signals * 47fed1b - frontend/axi: add last limitation * de69867 - examples/litedram_gen: expose last signals to user * e8bd782 - examples/litedram_gen: expose burst signals to user * e1598ce - phy/s7ddrphy: fix BL8 assert * ebba39d - README: update * e528e92 - phy/s7ddrphy: add assertion to avoid generating 1:2 controller with DDR3 (needs BL8 support in the PHY) * 6017e7a - phy/s7ddrphy: fix dqs_sys_latency for DDR2 * 7b42739 - phy/s7ddrphy: simplify cmd/dat phases computation and remove restrictions. * 6148618 - phy/s7ddrphy: use dict in get_cl_cw function * 5e4dca9 - add examples with standalone cores for arty and genesys2 * dce4ede - README: update * f6797a1 - test/test_axi: add burst wrap test and fix code * 47988d8 - frontend/axi: remove alignment limitation since we are in fact supporting unaligned transfers as described in the specification. * 6cc42c6 - frontend/axi: add wrap burst support * 9c729ae - core: replace adr with addr on native interface (closer to AXI and allow some simplifications) * 0506708 - core/controller: remove simulation workaround * bc8a9ce - README: update * 6f7ae84 - frontend/axi: increase default depth of buffers to improve performance * ed7eef1 - phy/s7ddrphy: fix preamble/posamble latency when with_odelay (-1 since dqs clk is not shifted) * c37d3af - frontend/bist: only keep random datas (we can generate random addresses with control) * b1e734b - frontend/bist: only use cdc on registers if needed (ie not in sys clock domain) * 92c8513 - frontend/axi: add buffer to accept command before converting burst to beats * c15c474 - test/test_axi: split reads/writes generators * 95cb7cd - test: rename read/write generators to handlers * d5d6737 - frontend/axi: fix read id * 10229d1 - test/test_axi: improve test_axi2native * 295f016 - frontend/axi: add features/limitations * 6a46ea3 - test/test_bist: add generator test, remove async test * 7677a85 - core/bankmachine: expose cmd_buffer_buffered param and small cleanup * liteeth changed from 24b0d2b to 3d86844 * 3d86844 - core/mac/sram: fix code refactoring * 5106bcd - core/mac/sram: simplify last_be code * ce72e34 - core/mac: pass endianness and use if for last_be gen/check * 94af3d6 - README: update and rename example_designs to examples * litepcie changed from a97a691 to 3e8de2d * 3e8de2d - phy/s7pciephy: remove clock constraints from phy * 6f2d97a - README: update and rename example_designs to example * litesata changed from 002cd25 to fb72044 * fb72044 - README: update and rename example_designs to examples * litescope changed from f26e36e to 686db4f * 686db4f - Merge pull request #12 from xobs/default-length |\ | * 4f8b9a3 - analyzer-driver: use default depth from config |/ * 7c1c62e - README: update and rename example_designs to examples * 3567b68 - dump/vcd: fix code generation * 182b683 - core: change cd parameter to clock_domain (keep retro compatibility for now) * liteusb changed from e841c56 to 0a9110f * 0a9110f - README: update and rename example_designs to examples * litevideo changed from 7b4240f to 13d85a1 * 13d85a1 - README: update * litex changed from 7a14b75c to 537b0e90 * 537b0e90 - Merge pull request #101 from cr1901/icestorm-migen-pull |\ | * 5c83c881 - Pull in b2740d9 from Migen. nextpnr now default, write out build scripts on dry run. * | 9c6f76f1 - bios/sdram: mode sdhw() * | a44bedd5 - bios/sdram: add missing #ifdef * | 0e68daeb - targets: self.pll_sys --> pll_sys * | 1468b9f3 - bios/sdram: show all read scans when failing. * | 07e4c183 - cpu/lm32: re-enable multiplier/divider in minimal variant (does not seem to work correctly on hardware otherwise) * | df3f003e - soc_sdram: update with litedram |/ * bebc667d - Merge pull request #99 from cr1901/mk-copy-main-ram |\ | * bd70ba27 - Add COPY_TO_MAIN_RAM generated Makefile variable to distinguish systems with/without main_ram region. * | 69716852 - Merge pull request #100 from cr1901/tinyprog-fix |\ \ | * | c812321a - lattice/programmer: Use --program-image option with tinyprog if address is given. | |/ * | 12a89447 - soc_sdram: revert vivado l2 cache workaround (still seems to cause issues on some cases...) * | 2b786065 - targets: pass endianness to LiteEThMAC, tftp working with RISC-V, still need to fix txlen * | 26963d62 - libnet/microudp: (WIP) fix endianness issues * | d9d0320d - Merge pull request #98 from jfng/fix_typo |\ \ | * | 22c01313 - fix typo and unused include |/ / * | fb24ac0e - cpu/minerva: add workaround on import until code is released * | 9cfae4df - setup.py: create litex_sim exec to ease simulation * | 8f377307 - add Minerva support * | 1944289e - litex_server: update pcie and remove bar_size parameter |/ * c5a2d6f3 - Merge pull request #96 from cr1901/tinyfpga_bx |\ | * 29492624 - build/platforms: Add TinyFPGA BX board and programmer. * | 3cb754da - Merge pull request #95 from cr1901/lm32-lite |\ \ | * | ed507d61 - Add lm32 "lite" variant, remove mult/div from "minimal" and update compiler flags accordingly. | |/ * | 28cd2da2 - README: update |/ * 05c7b9da - Merge pull request #94 from cr1901/nextpnr * 7af89efc - lattice/icestorm: Add nextpnr pnr as alternate pnr tool. * migen changed from 0.6.dev-162-ga6082d5 to 0.6.dev-168-gca0df1c * ca0df1c - build.platforms: add ice40_up5k_b_evn platform. * b2740d9 - build.lattice.icestorm: write build script even on dry run. * 2a7e33e - Emit `default_nettype none. * cff127d - build/platforms: Add TinyFPGA BX board and programmer. * 97e2651 - kasli: set USERID and USR_ACCESS * 58894fb - lattice/icestorm: Add nextpnr as alternate pnr tool. (#124) Full submodule status -- 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD) a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD) ea1ac4d6d72ecb9a65fb884857db8ba6851f3230 litedram (heads/s6-rank-fix) 3d868449e9c38a00524cff8ed2bf5dec2fc0d858 liteeth (remotes/origin/HEAD) 3e8de2d1ef347a1fdfbd01601b1bbdc4558dd90a litepcie (remotes/origin/HEAD) fb72044dabd121b4643a936b21ca3bf3aed75499 litesata (remotes/origin/HEAD) 686db4f3cd71bade8dd777d112e66797662f5bad litescope (remotes/origin/HEAD) 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD) 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD) 537b0e9058e6a5b77f434f46f3a56849c82064bd litex (remotes/origin/HEAD) ca0df1c148950213ff0551a8ec7c188a5910906e migen (0.6.dev-168-gca0df1c) --- third_party/edid-decode | 2 +- third_party/litedram | 2 +- third_party/liteeth | 2 +- third_party/litepcie | 2 +- third_party/litesata | 2 +- third_party/litescope | 2 +- third_party/liteusb | 2 +- third_party/litevideo | 2 +- third_party/litex | 2 +- third_party/migen | 2 +- 10 files changed, 10 insertions(+), 10 deletions(-) diff --git a/third_party/edid-decode b/third_party/edid-decode index b2da1516d..5eeb151a7 160000 --- a/third_party/edid-decode +++ b/third_party/edid-decode @@ -1 +1 @@ -Subproject commit b2da1516df3cc2756bfe8d1fa06d7bf2562ba1f4 +Subproject commit 5eeb151a748788666534d6ea3da07f90400d24c2 diff --git a/third_party/litedram b/third_party/litedram index 7a5ac75e2..ea1ac4d6d 160000 --- a/third_party/litedram +++ b/third_party/litedram @@ -1 +1 @@ -Subproject commit 7a5ac75e2295dcf15f83df966244f30154a8f662 +Subproject commit ea1ac4d6d72ecb9a65fb884857db8ba6851f3230 diff --git a/third_party/liteeth b/third_party/liteeth index 24b0d2b8c..3d868449e 160000 --- a/third_party/liteeth +++ b/third_party/liteeth @@ -1 +1 @@ -Subproject commit 24b0d2b8c2cfcf96a8c6cb56ec01af9a56952aad +Subproject commit 3d868449e9c38a00524cff8ed2bf5dec2fc0d858 diff --git a/third_party/litepcie b/third_party/litepcie index a97a6910c..3e8de2d1e 160000 --- a/third_party/litepcie +++ b/third_party/litepcie @@ -1 +1 @@ -Subproject commit a97a6910cbebfb4c068a178139df7b9a9c72168f +Subproject commit 3e8de2d1ef347a1fdfbd01601b1bbdc4558dd90a diff --git a/third_party/litesata b/third_party/litesata index 002cd25e7..fb72044da 160000 --- a/third_party/litesata +++ b/third_party/litesata @@ -1 +1 @@ -Subproject commit 002cd25e7fd2a60b4dcf1ce829731b9cf5c2f744 +Subproject commit fb72044dabd121b4643a936b21ca3bf3aed75499 diff --git a/third_party/litescope b/third_party/litescope index f26e36ef2..686db4f3c 160000 --- a/third_party/litescope +++ b/third_party/litescope @@ -1 +1 @@ -Subproject commit f26e36ef23170002af8ab1461ba39209e531b6cb +Subproject commit 686db4f3cd71bade8dd777d112e66797662f5bad diff --git a/third_party/liteusb b/third_party/liteusb index e841c5646..0a9110f90 160000 --- a/third_party/liteusb +++ b/third_party/liteusb @@ -1 +1 @@ -Subproject commit e841c5646c17ecbf07642c69c16c6c7c45e55475 +Subproject commit 0a9110f901182a1233cc4e64b6e39175f6784621 diff --git a/third_party/litevideo b/third_party/litevideo index 7b4240f9b..13d85a1fe 160000 --- a/third_party/litevideo +++ b/third_party/litevideo @@ -1 +1 @@ -Subproject commit 7b4240f9b3d6b7e69e5fe9dbaf50e117bd0ca704 +Subproject commit 13d85a1fe360678bebd57c55f1b35988c655ae95 diff --git a/third_party/litex b/third_party/litex index 7a14b75cd..537b0e905 160000 --- a/third_party/litex +++ b/third_party/litex @@ -1 +1 @@ -Subproject commit 7a14b75cd676e9328063abc1fcdc6fcd4fc6c5ef +Subproject commit 537b0e9058e6a5b77f434f46f3a56849c82064bd diff --git a/third_party/migen b/third_party/migen index a6082d56c..ca0df1c14 160000 --- a/third_party/migen +++ b/third_party/migen @@ -1 +1 @@ -Subproject commit a6082d56ccc615229bd3b5205f5b7207c14dca01 +Subproject commit ca0df1c148950213ff0551a8ec7c188a5910906e