diff --git a/lib/src/synthesizers/systemverilog.dart b/lib/src/synthesizers/systemverilog.dart
index b61719cfd..47062c85a 100644
--- a/lib/src/synthesizers/systemverilog.dart
+++ b/lib/src/synthesizers/systemverilog.dart
@@ -854,8 +854,6 @@ class _SynthLogic {
 
   /// Finds the best name from the collection of [Logic]s.
   String _findName(Uniquifier uniquifier) {
-    assert(!isFloatingConstant, 'Should not be using floating constants.');
-
     // check for const
     if (_constLogic != null) {
       if (!_constNameDisallowed) {
diff --git a/test/logic_name_test.dart b/test/logic_name_test.dart
index 5d027e6b7..298dee049 100644
--- a/test/logic_name_test.dart
+++ b/test/logic_name_test.dart
@@ -74,6 +74,18 @@ class BusSubsetNaming extends Module {
   }
 }
 
+class DrivenOutputModule extends Module {
+  Logic get x => output('x');
+  DrivenOutputModule(Logic? toDrive) {
+    final a = addInput('a', Logic());
+    addOutput('x');
+
+    final internal = toDrive ?? Logic(name: 'internal');
+
+    x <= mux(a, internal, a);
+  }
+}
+
 void main() {
   test(
       'GIVEN logic name is valid '
@@ -148,4 +160,24 @@ void main() {
       expect(sv, contains('c = b[3]'));
     });
   });
+
+  group('floating signals', () {
+    test('unconnected floating', () async {
+      final mod = DrivenOutputModule(null);
+      await mod.build();
+      final sv = mod.generateSynth();
+
+      // shouldn't add a Z in there if left floating
+      expect(!sv.contains('z'), true);
+    });
+
+    test('driven to z', () async {
+      final mod = DrivenOutputModule(Const('z'));
+      await mod.build();
+      final sv = mod.generateSynth();
+
+      // should add a Z if it's explicitly added
+      expect(sv, contains('z'));
+    });
+  });
 }