From 942d8b213e2556eff12a3d409bcd0a2d93533e65 Mon Sep 17 00:00:00 2001 From: Michael McLoughlin Date: Sun, 8 Jan 2023 11:12:48 -0800 Subject: [PATCH 1/3] import from #349 --- internal/opcodesextra/instructions.go | 1 + internal/opcodesextra/vnni.go | 364 ++++++++++++++++++++++++++ 2 files changed, 365 insertions(+) create mode 100644 internal/opcodesextra/vnni.go diff --git a/internal/opcodesextra/instructions.go b/internal/opcodesextra/instructions.go index 9935662c..f2888ac8 100644 --- a/internal/opcodesextra/instructions.go +++ b/internal/opcodesextra/instructions.go @@ -8,6 +8,7 @@ var sets = [][]*inst.Instruction{ movlqzx, gfni, vaes, + vnni, } // Instructions returns a list of extras to add to the instructions database. diff --git a/internal/opcodesextra/vnni.go b/internal/opcodesextra/vnni.go new file mode 100644 index 00000000..a7a78759 --- /dev/null +++ b/internal/opcodesextra/vnni.go @@ -0,0 +1,364 @@ +package opcodesextra + +import "github.com/mmcloughlin/avo/internal/inst" + +// vnni is the "Vector Neural Network Instructions" instruction set. +var vnni = []*inst.Instruction{ + // Reference: https://github.com/golang/go/blob/go1.19.3/src/cmd/internal/obj/x86/avx_optabs.go#L3056-L3075 + // + // {as: AVPDPBUSD, ytab: _yvblendmpd, prefix: Pavx, op: opBytes{ + // avxEscape | evex128 | evex66 | evex0F38 | evexW0, evexN16 | evexBcstN4 | evexZeroingEnabled, 0x50, + // avxEscape | evex256 | evex66 | evex0F38 | evexW0, evexN32 | evexBcstN4 | evexZeroingEnabled, 0x50, + // avxEscape | evex512 | evex66 | evex0F38 | evexW0, evexN64 | evexBcstN4 | evexZeroingEnabled, 0x50, + // }}, + // {as: AVPDPBUSDS, ytab: _yvblendmpd, prefix: Pavx, op: opBytes{ + // avxEscape | evex128 | evex66 | evex0F38 | evexW0, evexN16 | evexBcstN4 | evexZeroingEnabled, 0x51, + // avxEscape | evex256 | evex66 | evex0F38 | evexW0, evexN32 | evexBcstN4 | evexZeroingEnabled, 0x51, + // avxEscape | evex512 | evex66 | evex0F38 | evexW0, evexN64 | evexBcstN4 | evexZeroingEnabled, 0x51, + // }}, + // {as: AVPDPWSSD, ytab: _yvblendmpd, prefix: Pavx, op: opBytes{ + // avxEscape | evex128 | evex66 | evex0F38 | evexW0, evexN16 | evexBcstN4 | evexZeroingEnabled, 0x52, + // avxEscape | evex256 | evex66 | evex0F38 | evexW0, evexN32 | evexBcstN4 | evexZeroingEnabled, 0x52, + // avxEscape | evex512 | evex66 | evex0F38 | evexW0, evexN64 | evexBcstN4 | evexZeroingEnabled, 0x52, + // }}, + // {as: AVPDPWSSDS, ytab: _yvblendmpd, prefix: Pavx, op: opBytes{ + // avxEscape | evex128 | evex66 | evex0F38 | evexW0, evexN16 | evexBcstN4 | evexZeroingEnabled, 0x53, + // avxEscape | evex256 | evex66 | evex0F38 | evexW0, evexN32 | evexBcstN4 | evexZeroingEnabled, 0x53, + // avxEscape | evex512 | evex66 | evex0F38 | evexW0, evexN64 | evexBcstN4 | evexZeroingEnabled, 0x53, + // }}, + // + // **NOTE** The Golang assembler does not support the VEX encoded "AVX-VNNI" forms of these instructions + + { + Opcode: "VPDPBUSD", + Summary: "Multiply and Add Unsigned and Signed Bytes", + Forms: vnniForms, + }, + { + Opcode: "VPDPBUSDS", + Summary: "Multiply and Add Unsigned and Signed Bytes with Saturation", + Forms: vnniForms, + }, + { + Opcode: "VPDPWSSD", + Summary: "Multiply and Add Signed Word Integers", + Forms: vnniForms, + }, + { + Opcode: "VPDPWSSDS", + Summary: "Multiply and Add Signed Word Integers with Saturation", + Forms: vnniForms, + }, +} + +// VPDPBUSD, VPDPBUSDS, VPDPWSSD and VPDPWSSDS forms. +// +// See: https://www.felixcloutier.com/x86/vpdpbusd +// https://www.felixcloutier.com/x86/vpdpbusds +// https://www.felixcloutier.com/x86/vpdpwssd +// https://www.felixcloutier.com/x86/vpdpwssds +// +// Reference: https://github.com/golang/go/blob/go1.19.3/src/cmd/internal/obj/x86/avx_optabs.go#L148-L155 +// +// var _yvblendmpd = []ytab{ +// {zcase: Zevex_rm_v_r, zoffset: 0, args: argList{YxmEvex, YxrEvex, YxrEvex}}, +// {zcase: Zevex_rm_v_k_r, zoffset: 3, args: argList{YxmEvex, YxrEvex, Yknot0, YxrEvex}}, +// {zcase: Zevex_rm_v_r, zoffset: 0, args: argList{YymEvex, YyrEvex, YyrEvex}}, +// {zcase: Zevex_rm_v_k_r, zoffset: 3, args: argList{YymEvex, YyrEvex, Yknot0, YyrEvex}}, +// {zcase: Zevex_rm_v_r, zoffset: 0, args: argList{Yzm, Yzr, Yzr}}, +// {zcase: Zevex_rm_v_k_r, zoffset: 3, args: argList{Yzm, Yzr, Yknot0, Yzr}}, +// } + +var vnniForms = inst.Forms{ + // EVEX.128.66.0F38.W0 50 /r VPDPBUSD xmm1{k1}{z}, xmm2, xmm3/m128/m32bcst AVX512VNNI AVX512VL + // EVEX.128.66.0F38.W0 51 /r VPDPBUSDS xmm1{k1}{z}, xmm2, xmm3/m128/m32bcst AVX512VNNI AVX512VL + // EVEX.128.66.0F38.W0 52 /r VPDPWSSD xmm1{k1}{z}, xmm2, xmm3/m128/m32bcst AVX512VNNI AVX512VL + // EVEX.128.66.0F38.W0 53 /r VPDPWSSDS xmm1{k1}{z}, xmm2, xmm3/m128/m32bcst AVX512VNNI AVX512VL + // EVEX.256.66.0F38.W0 50 /r VPDPBUSD ymm1{k1}{z}, ymm2, ymm3/m256/m32bcst AVX512VNNI AVX512VL + // EVEX.256.66.0F38.W0 51 /r VPDPBUSDS ymm1{k1}{z}, ymm2, ymm3/m256/m32bcst AVX512VNNI AVX512VL + // EVEX.256.66.0F38.W0 52 /r VPDPWSSD ymm1{k1}{z}, ymm2, ymm3/m256/m32bcst AVX512VNNI AVX512VL + // EVEX.256.66.0F38.W0 53 /r VPDPWSSDS ymm1{k1}{z}, ymm2, ymm3/m256/m32bcst AVX512VNNI AVX512VL + // EVEX.512.66.0F38.W0 50 /r VPDPBUSD zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst AVX512VNNI + // EVEX.512.66.0F38.W0 51 /r VPDPBUSDS zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst AVX512VNNI + // EVEX.512.66.0F38.W0 52 /r VPDPWSSD zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst AVX512VNNI + // EVEX.512.66.0F38.W0 53 /r VPDPWSSDS zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst AVX512VNNI + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "m128", Action: inst.R}, + {Type: "xmm", Action: inst.R}, + {Type: "k", Action: inst.R}, + {Type: "xmm", Action: inst.RW}, + }, + EncodingType: inst.EncodingTypeEVEX, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "m128", Action: inst.R}, + {Type: "xmm", Action: inst.R}, + {Type: "k", Action: inst.R}, + {Type: "xmm", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + Zeroing: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "m128", Action: inst.R}, + {Type: "xmm", Action: inst.R}, + {Type: "xmm", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "m256", Action: inst.R}, + {Type: "ymm", Action: inst.R}, + {Type: "k", Action: inst.R}, + {Type: "ymm", Action: inst.RW}, + }, + EncodingType: inst.EncodingTypeEVEX, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "m256", Action: inst.R}, + {Type: "ymm", Action: inst.R}, + {Type: "k", Action: inst.R}, + {Type: "ymm", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + Zeroing: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "m256", Action: inst.R}, + {Type: "ymm", Action: inst.R}, + {Type: "ymm", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "m32", Action: inst.R}, + {Type: "xmm", Action: inst.R}, + {Type: "k", Action: inst.R}, + {Type: "xmm", Action: inst.RW}, + }, + EncodingType: inst.EncodingTypeEVEX, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "m32", Action: inst.R}, + {Type: "xmm", Action: inst.R}, + {Type: "k", Action: inst.R}, + {Type: "xmm", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "m32", Action: inst.R}, + {Type: "xmm", Action: inst.R}, + {Type: "xmm", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "m32", Action: inst.R}, + {Type: "ymm", Action: inst.R}, + {Type: "k", Action: inst.R}, + {Type: "ymm", Action: inst.RW}, + }, + EncodingType: inst.EncodingTypeEVEX, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "m32", Action: inst.R}, + {Type: "ymm", Action: inst.R}, + {Type: "k", Action: inst.R}, + {Type: "ymm", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "m32", Action: inst.R}, + {Type: "ymm", Action: inst.R}, + {Type: "ymm", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "xmm", Action: inst.R}, + {Type: "xmm", Action: inst.R}, + {Type: "k", Action: inst.R}, + {Type: "xmm", Action: inst.RW}, + }, + EncodingType: inst.EncodingTypeEVEX, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "xmm", Action: inst.R}, + {Type: "xmm", Action: inst.R}, + {Type: "k", Action: inst.R}, + {Type: "xmm", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + Zeroing: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "xmm", Action: inst.R}, + {Type: "xmm", Action: inst.R}, + {Type: "xmm", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "ymm", Action: inst.R}, + {Type: "ymm", Action: inst.R}, + {Type: "k", Action: inst.R}, + {Type: "ymm", Action: inst.RW}, + }, + EncodingType: inst.EncodingTypeEVEX, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "ymm", Action: inst.R}, + {Type: "ymm", Action: inst.R}, + {Type: "k", Action: inst.R}, + {Type: "ymm", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + Zeroing: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "ymm", Action: inst.R}, + {Type: "ymm", Action: inst.R}, + {Type: "ymm", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "m512", Action: inst.R}, + {Type: "zmm", Action: inst.R}, + {Type: "k", Action: inst.R}, + {Type: "zmm", Action: inst.RW}, + }, + EncodingType: inst.EncodingTypeEVEX, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "m512", Action: inst.R}, + {Type: "zmm", Action: inst.R}, + {Type: "k", Action: inst.R}, + {Type: "zmm", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + Zeroing: true, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "m512", Action: inst.R}, + {Type: "zmm", Action: inst.R}, + {Type: "zmm", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "m32", Action: inst.R}, + {Type: "zmm", Action: inst.R}, + {Type: "k", Action: inst.R}, + {Type: "zmm", Action: inst.RW}, + }, + EncodingType: inst.EncodingTypeEVEX, + Broadcast: true, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "m32", Action: inst.R}, + {Type: "zmm", Action: inst.R}, + {Type: "k", Action: inst.R}, + {Type: "zmm", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "m32", Action: inst.R}, + {Type: "zmm", Action: inst.R}, + {Type: "zmm", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + Broadcast: true, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "zmm", Action: inst.R}, + {Type: "zmm", Action: inst.R}, + {Type: "k", Action: inst.R}, + {Type: "zmm", Action: inst.RW}, + }, + EncodingType: inst.EncodingTypeEVEX, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "zmm", Action: inst.R}, + {Type: "zmm", Action: inst.R}, + {Type: "k", Action: inst.R}, + {Type: "zmm", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + Zeroing: true, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []inst.Operand{ + {Type: "zmm", Action: inst.R}, + {Type: "zmm", Action: inst.R}, + {Type: "zmm", Action: inst.W}, + }, + EncodingType: inst.EncodingTypeEVEX, + }, +} From 40772e7a9be499559c0909a6912e388431dd3de3 Mon Sep 17 00:00:00 2001 From: Michael McLoughlin Date: Sun, 8 Jan 2023 11:20:27 -0800 Subject: [PATCH 2/3] tweaks --- internal/opcodesextra/vnni.go | 60 +++++++++++++++++------------------ 1 file changed, 29 insertions(+), 31 deletions(-) diff --git a/internal/opcodesextra/vnni.go b/internal/opcodesextra/vnni.go index a7a78759..418b7404 100644 --- a/internal/opcodesextra/vnni.go +++ b/internal/opcodesextra/vnni.go @@ -6,57 +6,56 @@ import "github.com/mmcloughlin/avo/internal/inst" var vnni = []*inst.Instruction{ // Reference: https://github.com/golang/go/blob/go1.19.3/src/cmd/internal/obj/x86/avx_optabs.go#L3056-L3075 // - // {as: AVPDPBUSD, ytab: _yvblendmpd, prefix: Pavx, op: opBytes{ - // avxEscape | evex128 | evex66 | evex0F38 | evexW0, evexN16 | evexBcstN4 | evexZeroingEnabled, 0x50, - // avxEscape | evex256 | evex66 | evex0F38 | evexW0, evexN32 | evexBcstN4 | evexZeroingEnabled, 0x50, - // avxEscape | evex512 | evex66 | evex0F38 | evexW0, evexN64 | evexBcstN4 | evexZeroingEnabled, 0x50, - // }}, - // {as: AVPDPBUSDS, ytab: _yvblendmpd, prefix: Pavx, op: opBytes{ - // avxEscape | evex128 | evex66 | evex0F38 | evexW0, evexN16 | evexBcstN4 | evexZeroingEnabled, 0x51, - // avxEscape | evex256 | evex66 | evex0F38 | evexW0, evexN32 | evexBcstN4 | evexZeroingEnabled, 0x51, - // avxEscape | evex512 | evex66 | evex0F38 | evexW0, evexN64 | evexBcstN4 | evexZeroingEnabled, 0x51, - // }}, - // {as: AVPDPWSSD, ytab: _yvblendmpd, prefix: Pavx, op: opBytes{ - // avxEscape | evex128 | evex66 | evex0F38 | evexW0, evexN16 | evexBcstN4 | evexZeroingEnabled, 0x52, - // avxEscape | evex256 | evex66 | evex0F38 | evexW0, evexN32 | evexBcstN4 | evexZeroingEnabled, 0x52, - // avxEscape | evex512 | evex66 | evex0F38 | evexW0, evexN64 | evexBcstN4 | evexZeroingEnabled, 0x52, - // }}, - // {as: AVPDPWSSDS, ytab: _yvblendmpd, prefix: Pavx, op: opBytes{ - // avxEscape | evex128 | evex66 | evex0F38 | evexW0, evexN16 | evexBcstN4 | evexZeroingEnabled, 0x53, - // avxEscape | evex256 | evex66 | evex0F38 | evexW0, evexN32 | evexBcstN4 | evexZeroingEnabled, 0x53, - // avxEscape | evex512 | evex66 | evex0F38 | evexW0, evexN64 | evexBcstN4 | evexZeroingEnabled, 0x53, - // }}, + // {as: AVPDPBUSD, ytab: _yvblendmpd, prefix: Pavx, op: opBytes{ + // avxEscape | evex128 | evex66 | evex0F38 | evexW0, evexN16 | evexBcstN4 | evexZeroingEnabled, 0x50, + // avxEscape | evex256 | evex66 | evex0F38 | evexW0, evexN32 | evexBcstN4 | evexZeroingEnabled, 0x50, + // avxEscape | evex512 | evex66 | evex0F38 | evexW0, evexN64 | evexBcstN4 | evexZeroingEnabled, 0x50, + // }}, + // {as: AVPDPBUSDS, ytab: _yvblendmpd, prefix: Pavx, op: opBytes{ + // avxEscape | evex128 | evex66 | evex0F38 | evexW0, evexN16 | evexBcstN4 | evexZeroingEnabled, 0x51, + // avxEscape | evex256 | evex66 | evex0F38 | evexW0, evexN32 | evexBcstN4 | evexZeroingEnabled, 0x51, + // avxEscape | evex512 | evex66 | evex0F38 | evexW0, evexN64 | evexBcstN4 | evexZeroingEnabled, 0x51, + // }}, + // {as: AVPDPWSSD, ytab: _yvblendmpd, prefix: Pavx, op: opBytes{ + // avxEscape | evex128 | evex66 | evex0F38 | evexW0, evexN16 | evexBcstN4 | evexZeroingEnabled, 0x52, + // avxEscape | evex256 | evex66 | evex0F38 | evexW0, evexN32 | evexBcstN4 | evexZeroingEnabled, 0x52, + // avxEscape | evex512 | evex66 | evex0F38 | evexW0, evexN64 | evexBcstN4 | evexZeroingEnabled, 0x52, + // }}, + // {as: AVPDPWSSDS, ytab: _yvblendmpd, prefix: Pavx, op: opBytes{ + // avxEscape | evex128 | evex66 | evex0F38 | evexW0, evexN16 | evexBcstN4 | evexZeroingEnabled, 0x53, + // avxEscape | evex256 | evex66 | evex0F38 | evexW0, evexN32 | evexBcstN4 | evexZeroingEnabled, 0x53, + // avxEscape | evex512 | evex66 | evex0F38 | evexW0, evexN64 | evexBcstN4 | evexZeroingEnabled, 0x53, + // }}, // - // **NOTE** The Golang assembler does not support the VEX encoded "AVX-VNNI" forms of these instructions - + // Note the Go assembler does not support the VEX encoded "AVX-VNNI" forms of these instructions. { Opcode: "VPDPBUSD", Summary: "Multiply and Add Unsigned and Signed Bytes", - Forms: vnniForms, + Forms: vnniforms, }, { Opcode: "VPDPBUSDS", Summary: "Multiply and Add Unsigned and Signed Bytes with Saturation", - Forms: vnniForms, + Forms: vnniforms, }, { Opcode: "VPDPWSSD", Summary: "Multiply and Add Signed Word Integers", - Forms: vnniForms, + Forms: vnniforms, }, { Opcode: "VPDPWSSDS", Summary: "Multiply and Add Signed Word Integers with Saturation", - Forms: vnniForms, + Forms: vnniforms, }, } // VPDPBUSD, VPDPBUSDS, VPDPWSSD and VPDPWSSDS forms. // // See: https://www.felixcloutier.com/x86/vpdpbusd -// https://www.felixcloutier.com/x86/vpdpbusds -// https://www.felixcloutier.com/x86/vpdpwssd -// https://www.felixcloutier.com/x86/vpdpwssds +// See: https://www.felixcloutier.com/x86/vpdpbusds +// See: https://www.felixcloutier.com/x86/vpdpwssd +// See: https://www.felixcloutier.com/x86/vpdpwssds // // Reference: https://github.com/golang/go/blob/go1.19.3/src/cmd/internal/obj/x86/avx_optabs.go#L148-L155 // @@ -68,8 +67,7 @@ var vnni = []*inst.Instruction{ // {zcase: Zevex_rm_v_r, zoffset: 0, args: argList{Yzm, Yzr, Yzr}}, // {zcase: Zevex_rm_v_k_r, zoffset: 3, args: argList{Yzm, Yzr, Yknot0, Yzr}}, // } - -var vnniForms = inst.Forms{ +var vnniforms = inst.Forms{ // EVEX.128.66.0F38.W0 50 /r VPDPBUSD xmm1{k1}{z}, xmm2, xmm3/m128/m32bcst AVX512VNNI AVX512VL // EVEX.128.66.0F38.W0 51 /r VPDPBUSDS xmm1{k1}{z}, xmm2, xmm3/m128/m32bcst AVX512VNNI AVX512VL // EVEX.128.66.0F38.W0 52 /r VPDPWSSD xmm1{k1}{z}, xmm2, xmm3/m128/m32bcst AVX512VNNI AVX512VL From 90ee5b277abfdd6a9ff1339d0f71ae2a740f66b6 Mon Sep 17 00:00:00 2001 From: Michael McLoughlin Date: Sun, 8 Jan 2023 11:31:34 -0800 Subject: [PATCH 3/3] simplify the masking/zeroing/bcst forms --- build/zinstructions.go | 520 +++++++++++++++ build/zinstructions_test.go | 16 + internal/inst/ztable.go | 1140 +++++++++++++++++++++++++++++++++ internal/opcodesextra/vnni.go | 271 +------- x86/zctors.go | 236 +++++++ x86/zctors_test.go | 372 +++++++++++ x86/zoptab.go | 610 +++++++++++------- 7 files changed, 2674 insertions(+), 491 deletions(-) diff --git a/build/zinstructions.go b/build/zinstructions.go index 28dedb5c..84086fb9 100644 --- a/build/zinstructions.go +++ b/build/zinstructions.go @@ -59922,6 +59922,526 @@ func (c *Context) VPCONFLICTQ_Z(mxyz, k, xyz operand.Op) { // Operates on the global context. func VPCONFLICTQ_Z(mxyz, k, xyz operand.Op) { ctx.VPCONFLICTQ_Z(mxyz, k, xyz) } +// VPDPBUSD: Multiply and Add Unsigned and Signed Bytes. +// +// Forms: +// +// VPDPBUSD m128 xmm k xmm +// VPDPBUSD m128 xmm xmm +// VPDPBUSD m256 ymm k ymm +// VPDPBUSD m256 ymm ymm +// VPDPBUSD xmm xmm k xmm +// VPDPBUSD xmm xmm xmm +// VPDPBUSD ymm ymm k ymm +// VPDPBUSD ymm ymm ymm +// VPDPBUSD m512 zmm k zmm +// VPDPBUSD m512 zmm zmm +// VPDPBUSD zmm zmm k zmm +// VPDPBUSD zmm zmm zmm +// +// Construct and append a VPDPBUSD instruction to the active function. +func (c *Context) VPDPBUSD(ops ...operand.Op) { + c.addinstruction(x86.VPDPBUSD(ops...)) +} + +// VPDPBUSD: Multiply and Add Unsigned and Signed Bytes. +// +// Forms: +// +// VPDPBUSD m128 xmm k xmm +// VPDPBUSD m128 xmm xmm +// VPDPBUSD m256 ymm k ymm +// VPDPBUSD m256 ymm ymm +// VPDPBUSD xmm xmm k xmm +// VPDPBUSD xmm xmm xmm +// VPDPBUSD ymm ymm k ymm +// VPDPBUSD ymm ymm ymm +// VPDPBUSD m512 zmm k zmm +// VPDPBUSD m512 zmm zmm +// VPDPBUSD zmm zmm k zmm +// VPDPBUSD zmm zmm zmm +// +// Construct and append a VPDPBUSD instruction to the active function. +// Operates on the global context. +func VPDPBUSD(ops ...operand.Op) { ctx.VPDPBUSD(ops...) } + +// VPDPBUSDS: Multiply and Add Unsigned and Signed Bytes with Saturation. +// +// Forms: +// +// VPDPBUSDS m128 xmm k xmm +// VPDPBUSDS m128 xmm xmm +// VPDPBUSDS m256 ymm k ymm +// VPDPBUSDS m256 ymm ymm +// VPDPBUSDS xmm xmm k xmm +// VPDPBUSDS xmm xmm xmm +// VPDPBUSDS ymm ymm k ymm +// VPDPBUSDS ymm ymm ymm +// VPDPBUSDS m512 zmm k zmm +// VPDPBUSDS m512 zmm zmm +// VPDPBUSDS zmm zmm k zmm +// VPDPBUSDS zmm zmm zmm +// +// Construct and append a VPDPBUSDS instruction to the active function. +func (c *Context) VPDPBUSDS(ops ...operand.Op) { + c.addinstruction(x86.VPDPBUSDS(ops...)) +} + +// VPDPBUSDS: Multiply and Add Unsigned and Signed Bytes with Saturation. +// +// Forms: +// +// VPDPBUSDS m128 xmm k xmm +// VPDPBUSDS m128 xmm xmm +// VPDPBUSDS m256 ymm k ymm +// VPDPBUSDS m256 ymm ymm +// VPDPBUSDS xmm xmm k xmm +// VPDPBUSDS xmm xmm xmm +// VPDPBUSDS ymm ymm k ymm +// VPDPBUSDS ymm ymm ymm +// VPDPBUSDS m512 zmm k zmm +// VPDPBUSDS m512 zmm zmm +// VPDPBUSDS zmm zmm k zmm +// VPDPBUSDS zmm zmm zmm +// +// Construct and append a VPDPBUSDS instruction to the active function. +// Operates on the global context. +func VPDPBUSDS(ops ...operand.Op) { ctx.VPDPBUSDS(ops...) } + +// VPDPBUSDS_BCST: Multiply and Add Unsigned and Signed Bytes with Saturation (Broadcast). +// +// Forms: +// +// VPDPBUSDS.BCST m32 xmm k xmm +// VPDPBUSDS.BCST m32 xmm xmm +// VPDPBUSDS.BCST m32 ymm k ymm +// VPDPBUSDS.BCST m32 ymm ymm +// VPDPBUSDS.BCST m32 zmm k zmm +// VPDPBUSDS.BCST m32 zmm zmm +// +// Construct and append a VPDPBUSDS.BCST instruction to the active function. +func (c *Context) VPDPBUSDS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPDPBUSDS_BCST(ops...)) +} + +// VPDPBUSDS_BCST: Multiply and Add Unsigned and Signed Bytes with Saturation (Broadcast). +// +// Forms: +// +// VPDPBUSDS.BCST m32 xmm k xmm +// VPDPBUSDS.BCST m32 xmm xmm +// VPDPBUSDS.BCST m32 ymm k ymm +// VPDPBUSDS.BCST m32 ymm ymm +// VPDPBUSDS.BCST m32 zmm k zmm +// VPDPBUSDS.BCST m32 zmm zmm +// +// Construct and append a VPDPBUSDS.BCST instruction to the active function. +// Operates on the global context. +func VPDPBUSDS_BCST(ops ...operand.Op) { ctx.VPDPBUSDS_BCST(ops...) } + +// VPDPBUSDS_BCST_Z: Multiply and Add Unsigned and Signed Bytes with Saturation (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPDPBUSDS.BCST.Z m32 xmm k xmm +// VPDPBUSDS.BCST.Z m32 ymm k ymm +// VPDPBUSDS.BCST.Z m32 zmm k zmm +// +// Construct and append a VPDPBUSDS.BCST.Z instruction to the active function. +func (c *Context) VPDPBUSDS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPDPBUSDS_BCST_Z(m, xyz, k, xyz1)) +} + +// VPDPBUSDS_BCST_Z: Multiply and Add Unsigned and Signed Bytes with Saturation (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPDPBUSDS.BCST.Z m32 xmm k xmm +// VPDPBUSDS.BCST.Z m32 ymm k ymm +// VPDPBUSDS.BCST.Z m32 zmm k zmm +// +// Construct and append a VPDPBUSDS.BCST.Z instruction to the active function. +// Operates on the global context. +func VPDPBUSDS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPDPBUSDS_BCST_Z(m, xyz, k, xyz1) } + +// VPDPBUSDS_Z: Multiply and Add Unsigned and Signed Bytes with Saturation (Zeroing Masking). +// +// Forms: +// +// VPDPBUSDS.Z m128 xmm k xmm +// VPDPBUSDS.Z m256 ymm k ymm +// VPDPBUSDS.Z xmm xmm k xmm +// VPDPBUSDS.Z ymm ymm k ymm +// VPDPBUSDS.Z m512 zmm k zmm +// VPDPBUSDS.Z zmm zmm k zmm +// +// Construct and append a VPDPBUSDS.Z instruction to the active function. +func (c *Context) VPDPBUSDS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPDPBUSDS_Z(mxyz, xyz, k, xyz1)) +} + +// VPDPBUSDS_Z: Multiply and Add Unsigned and Signed Bytes with Saturation (Zeroing Masking). +// +// Forms: +// +// VPDPBUSDS.Z m128 xmm k xmm +// VPDPBUSDS.Z m256 ymm k ymm +// VPDPBUSDS.Z xmm xmm k xmm +// VPDPBUSDS.Z ymm ymm k ymm +// VPDPBUSDS.Z m512 zmm k zmm +// VPDPBUSDS.Z zmm zmm k zmm +// +// Construct and append a VPDPBUSDS.Z instruction to the active function. +// Operates on the global context. +func VPDPBUSDS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPDPBUSDS_Z(mxyz, xyz, k, xyz1) } + +// VPDPBUSD_BCST: Multiply and Add Unsigned and Signed Bytes (Broadcast). +// +// Forms: +// +// VPDPBUSD.BCST m32 xmm k xmm +// VPDPBUSD.BCST m32 xmm xmm +// VPDPBUSD.BCST m32 ymm k ymm +// VPDPBUSD.BCST m32 ymm ymm +// VPDPBUSD.BCST m32 zmm k zmm +// VPDPBUSD.BCST m32 zmm zmm +// +// Construct and append a VPDPBUSD.BCST instruction to the active function. +func (c *Context) VPDPBUSD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPDPBUSD_BCST(ops...)) +} + +// VPDPBUSD_BCST: Multiply and Add Unsigned and Signed Bytes (Broadcast). +// +// Forms: +// +// VPDPBUSD.BCST m32 xmm k xmm +// VPDPBUSD.BCST m32 xmm xmm +// VPDPBUSD.BCST m32 ymm k ymm +// VPDPBUSD.BCST m32 ymm ymm +// VPDPBUSD.BCST m32 zmm k zmm +// VPDPBUSD.BCST m32 zmm zmm +// +// Construct and append a VPDPBUSD.BCST instruction to the active function. +// Operates on the global context. +func VPDPBUSD_BCST(ops ...operand.Op) { ctx.VPDPBUSD_BCST(ops...) } + +// VPDPBUSD_BCST_Z: Multiply and Add Unsigned and Signed Bytes (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPDPBUSD.BCST.Z m32 xmm k xmm +// VPDPBUSD.BCST.Z m32 ymm k ymm +// VPDPBUSD.BCST.Z m32 zmm k zmm +// +// Construct and append a VPDPBUSD.BCST.Z instruction to the active function. +func (c *Context) VPDPBUSD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPDPBUSD_BCST_Z(m, xyz, k, xyz1)) +} + +// VPDPBUSD_BCST_Z: Multiply and Add Unsigned and Signed Bytes (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPDPBUSD.BCST.Z m32 xmm k xmm +// VPDPBUSD.BCST.Z m32 ymm k ymm +// VPDPBUSD.BCST.Z m32 zmm k zmm +// +// Construct and append a VPDPBUSD.BCST.Z instruction to the active function. +// Operates on the global context. +func VPDPBUSD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPDPBUSD_BCST_Z(m, xyz, k, xyz1) } + +// VPDPBUSD_Z: Multiply and Add Unsigned and Signed Bytes (Zeroing Masking). +// +// Forms: +// +// VPDPBUSD.Z m128 xmm k xmm +// VPDPBUSD.Z m256 ymm k ymm +// VPDPBUSD.Z xmm xmm k xmm +// VPDPBUSD.Z ymm ymm k ymm +// VPDPBUSD.Z m512 zmm k zmm +// VPDPBUSD.Z zmm zmm k zmm +// +// Construct and append a VPDPBUSD.Z instruction to the active function. +func (c *Context) VPDPBUSD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPDPBUSD_Z(mxyz, xyz, k, xyz1)) +} + +// VPDPBUSD_Z: Multiply and Add Unsigned and Signed Bytes (Zeroing Masking). +// +// Forms: +// +// VPDPBUSD.Z m128 xmm k xmm +// VPDPBUSD.Z m256 ymm k ymm +// VPDPBUSD.Z xmm xmm k xmm +// VPDPBUSD.Z ymm ymm k ymm +// VPDPBUSD.Z m512 zmm k zmm +// VPDPBUSD.Z zmm zmm k zmm +// +// Construct and append a VPDPBUSD.Z instruction to the active function. +// Operates on the global context. +func VPDPBUSD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPDPBUSD_Z(mxyz, xyz, k, xyz1) } + +// VPDPWSSD: Multiply and Add Signed Word Integers. +// +// Forms: +// +// VPDPWSSD m128 xmm k xmm +// VPDPWSSD m128 xmm xmm +// VPDPWSSD m256 ymm k ymm +// VPDPWSSD m256 ymm ymm +// VPDPWSSD xmm xmm k xmm +// VPDPWSSD xmm xmm xmm +// VPDPWSSD ymm ymm k ymm +// VPDPWSSD ymm ymm ymm +// VPDPWSSD m512 zmm k zmm +// VPDPWSSD m512 zmm zmm +// VPDPWSSD zmm zmm k zmm +// VPDPWSSD zmm zmm zmm +// +// Construct and append a VPDPWSSD instruction to the active function. +func (c *Context) VPDPWSSD(ops ...operand.Op) { + c.addinstruction(x86.VPDPWSSD(ops...)) +} + +// VPDPWSSD: Multiply and Add Signed Word Integers. +// +// Forms: +// +// VPDPWSSD m128 xmm k xmm +// VPDPWSSD m128 xmm xmm +// VPDPWSSD m256 ymm k ymm +// VPDPWSSD m256 ymm ymm +// VPDPWSSD xmm xmm k xmm +// VPDPWSSD xmm xmm xmm +// VPDPWSSD ymm ymm k ymm +// VPDPWSSD ymm ymm ymm +// VPDPWSSD m512 zmm k zmm +// VPDPWSSD m512 zmm zmm +// VPDPWSSD zmm zmm k zmm +// VPDPWSSD zmm zmm zmm +// +// Construct and append a VPDPWSSD instruction to the active function. +// Operates on the global context. +func VPDPWSSD(ops ...operand.Op) { ctx.VPDPWSSD(ops...) } + +// VPDPWSSDS: Multiply and Add Signed Word Integers with Saturation. +// +// Forms: +// +// VPDPWSSDS m128 xmm k xmm +// VPDPWSSDS m128 xmm xmm +// VPDPWSSDS m256 ymm k ymm +// VPDPWSSDS m256 ymm ymm +// VPDPWSSDS xmm xmm k xmm +// VPDPWSSDS xmm xmm xmm +// VPDPWSSDS ymm ymm k ymm +// VPDPWSSDS ymm ymm ymm +// VPDPWSSDS m512 zmm k zmm +// VPDPWSSDS m512 zmm zmm +// VPDPWSSDS zmm zmm k zmm +// VPDPWSSDS zmm zmm zmm +// +// Construct and append a VPDPWSSDS instruction to the active function. +func (c *Context) VPDPWSSDS(ops ...operand.Op) { + c.addinstruction(x86.VPDPWSSDS(ops...)) +} + +// VPDPWSSDS: Multiply and Add Signed Word Integers with Saturation. +// +// Forms: +// +// VPDPWSSDS m128 xmm k xmm +// VPDPWSSDS m128 xmm xmm +// VPDPWSSDS m256 ymm k ymm +// VPDPWSSDS m256 ymm ymm +// VPDPWSSDS xmm xmm k xmm +// VPDPWSSDS xmm xmm xmm +// VPDPWSSDS ymm ymm k ymm +// VPDPWSSDS ymm ymm ymm +// VPDPWSSDS m512 zmm k zmm +// VPDPWSSDS m512 zmm zmm +// VPDPWSSDS zmm zmm k zmm +// VPDPWSSDS zmm zmm zmm +// +// Construct and append a VPDPWSSDS instruction to the active function. +// Operates on the global context. +func VPDPWSSDS(ops ...operand.Op) { ctx.VPDPWSSDS(ops...) } + +// VPDPWSSDS_BCST: Multiply and Add Signed Word Integers with Saturation (Broadcast). +// +// Forms: +// +// VPDPWSSDS.BCST m32 xmm k xmm +// VPDPWSSDS.BCST m32 xmm xmm +// VPDPWSSDS.BCST m32 ymm k ymm +// VPDPWSSDS.BCST m32 ymm ymm +// VPDPWSSDS.BCST m32 zmm k zmm +// VPDPWSSDS.BCST m32 zmm zmm +// +// Construct and append a VPDPWSSDS.BCST instruction to the active function. +func (c *Context) VPDPWSSDS_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPDPWSSDS_BCST(ops...)) +} + +// VPDPWSSDS_BCST: Multiply and Add Signed Word Integers with Saturation (Broadcast). +// +// Forms: +// +// VPDPWSSDS.BCST m32 xmm k xmm +// VPDPWSSDS.BCST m32 xmm xmm +// VPDPWSSDS.BCST m32 ymm k ymm +// VPDPWSSDS.BCST m32 ymm ymm +// VPDPWSSDS.BCST m32 zmm k zmm +// VPDPWSSDS.BCST m32 zmm zmm +// +// Construct and append a VPDPWSSDS.BCST instruction to the active function. +// Operates on the global context. +func VPDPWSSDS_BCST(ops ...operand.Op) { ctx.VPDPWSSDS_BCST(ops...) } + +// VPDPWSSDS_BCST_Z: Multiply and Add Signed Word Integers with Saturation (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPDPWSSDS.BCST.Z m32 xmm k xmm +// VPDPWSSDS.BCST.Z m32 ymm k ymm +// VPDPWSSDS.BCST.Z m32 zmm k zmm +// +// Construct and append a VPDPWSSDS.BCST.Z instruction to the active function. +func (c *Context) VPDPWSSDS_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPDPWSSDS_BCST_Z(m, xyz, k, xyz1)) +} + +// VPDPWSSDS_BCST_Z: Multiply and Add Signed Word Integers with Saturation (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPDPWSSDS.BCST.Z m32 xmm k xmm +// VPDPWSSDS.BCST.Z m32 ymm k ymm +// VPDPWSSDS.BCST.Z m32 zmm k zmm +// +// Construct and append a VPDPWSSDS.BCST.Z instruction to the active function. +// Operates on the global context. +func VPDPWSSDS_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPDPWSSDS_BCST_Z(m, xyz, k, xyz1) } + +// VPDPWSSDS_Z: Multiply and Add Signed Word Integers with Saturation (Zeroing Masking). +// +// Forms: +// +// VPDPWSSDS.Z m128 xmm k xmm +// VPDPWSSDS.Z m256 ymm k ymm +// VPDPWSSDS.Z xmm xmm k xmm +// VPDPWSSDS.Z ymm ymm k ymm +// VPDPWSSDS.Z m512 zmm k zmm +// VPDPWSSDS.Z zmm zmm k zmm +// +// Construct and append a VPDPWSSDS.Z instruction to the active function. +func (c *Context) VPDPWSSDS_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPDPWSSDS_Z(mxyz, xyz, k, xyz1)) +} + +// VPDPWSSDS_Z: Multiply and Add Signed Word Integers with Saturation (Zeroing Masking). +// +// Forms: +// +// VPDPWSSDS.Z m128 xmm k xmm +// VPDPWSSDS.Z m256 ymm k ymm +// VPDPWSSDS.Z xmm xmm k xmm +// VPDPWSSDS.Z ymm ymm k ymm +// VPDPWSSDS.Z m512 zmm k zmm +// VPDPWSSDS.Z zmm zmm k zmm +// +// Construct and append a VPDPWSSDS.Z instruction to the active function. +// Operates on the global context. +func VPDPWSSDS_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPDPWSSDS_Z(mxyz, xyz, k, xyz1) } + +// VPDPWSSD_BCST: Multiply and Add Signed Word Integers (Broadcast). +// +// Forms: +// +// VPDPWSSD.BCST m32 xmm k xmm +// VPDPWSSD.BCST m32 xmm xmm +// VPDPWSSD.BCST m32 ymm k ymm +// VPDPWSSD.BCST m32 ymm ymm +// VPDPWSSD.BCST m32 zmm k zmm +// VPDPWSSD.BCST m32 zmm zmm +// +// Construct and append a VPDPWSSD.BCST instruction to the active function. +func (c *Context) VPDPWSSD_BCST(ops ...operand.Op) { + c.addinstruction(x86.VPDPWSSD_BCST(ops...)) +} + +// VPDPWSSD_BCST: Multiply and Add Signed Word Integers (Broadcast). +// +// Forms: +// +// VPDPWSSD.BCST m32 xmm k xmm +// VPDPWSSD.BCST m32 xmm xmm +// VPDPWSSD.BCST m32 ymm k ymm +// VPDPWSSD.BCST m32 ymm ymm +// VPDPWSSD.BCST m32 zmm k zmm +// VPDPWSSD.BCST m32 zmm zmm +// +// Construct and append a VPDPWSSD.BCST instruction to the active function. +// Operates on the global context. +func VPDPWSSD_BCST(ops ...operand.Op) { ctx.VPDPWSSD_BCST(ops...) } + +// VPDPWSSD_BCST_Z: Multiply and Add Signed Word Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPDPWSSD.BCST.Z m32 xmm k xmm +// VPDPWSSD.BCST.Z m32 ymm k ymm +// VPDPWSSD.BCST.Z m32 zmm k zmm +// +// Construct and append a VPDPWSSD.BCST.Z instruction to the active function. +func (c *Context) VPDPWSSD_BCST_Z(m, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPDPWSSD_BCST_Z(m, xyz, k, xyz1)) +} + +// VPDPWSSD_BCST_Z: Multiply and Add Signed Word Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPDPWSSD.BCST.Z m32 xmm k xmm +// VPDPWSSD.BCST.Z m32 ymm k ymm +// VPDPWSSD.BCST.Z m32 zmm k zmm +// +// Construct and append a VPDPWSSD.BCST.Z instruction to the active function. +// Operates on the global context. +func VPDPWSSD_BCST_Z(m, xyz, k, xyz1 operand.Op) { ctx.VPDPWSSD_BCST_Z(m, xyz, k, xyz1) } + +// VPDPWSSD_Z: Multiply and Add Signed Word Integers (Zeroing Masking). +// +// Forms: +// +// VPDPWSSD.Z m128 xmm k xmm +// VPDPWSSD.Z m256 ymm k ymm +// VPDPWSSD.Z xmm xmm k xmm +// VPDPWSSD.Z ymm ymm k ymm +// VPDPWSSD.Z m512 zmm k zmm +// VPDPWSSD.Z zmm zmm k zmm +// +// Construct and append a VPDPWSSD.Z instruction to the active function. +func (c *Context) VPDPWSSD_Z(mxyz, xyz, k, xyz1 operand.Op) { + c.addinstruction(x86.VPDPWSSD_Z(mxyz, xyz, k, xyz1)) +} + +// VPDPWSSD_Z: Multiply and Add Signed Word Integers (Zeroing Masking). +// +// Forms: +// +// VPDPWSSD.Z m128 xmm k xmm +// VPDPWSSD.Z m256 ymm k ymm +// VPDPWSSD.Z xmm xmm k xmm +// VPDPWSSD.Z ymm ymm k ymm +// VPDPWSSD.Z m512 zmm k zmm +// VPDPWSSD.Z zmm zmm k zmm +// +// Construct and append a VPDPWSSD.Z instruction to the active function. +// Operates on the global context. +func VPDPWSSD_Z(mxyz, xyz, k, xyz1 operand.Op) { ctx.VPDPWSSD_Z(mxyz, xyz, k, xyz1) } + // VPERM2F128: Permute Floating-Point Values. // // Forms: diff --git a/build/zinstructions_test.go b/build/zinstructions_test.go index db18d2a9..88a8dc84 100644 --- a/build/zinstructions_test.go +++ b/build/zinstructions_test.go @@ -2396,6 +2396,22 @@ func TestContextInstructions(t *testing.T) { ctx.VPCONFLICTQ_BCST(opm64, opk, opxmm) ctx.VPCONFLICTQ_BCST_Z(opm64, opk, opxmm) ctx.VPCONFLICTQ_Z(opm128, opk, opxmm) + ctx.VPDPBUSD(opm128, opxmm, opk, opxmm) + ctx.VPDPBUSDS(opm128, opxmm, opk, opxmm) + ctx.VPDPBUSDS_BCST(opm32, opxmm, opk, opxmm) + ctx.VPDPBUSDS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPDPBUSDS_Z(opm128, opxmm, opk, opxmm) + ctx.VPDPBUSD_BCST(opm32, opxmm, opk, opxmm) + ctx.VPDPBUSD_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPDPBUSD_Z(opm128, opxmm, opk, opxmm) + ctx.VPDPWSSD(opm128, opxmm, opk, opxmm) + ctx.VPDPWSSDS(opm128, opxmm, opk, opxmm) + ctx.VPDPWSSDS_BCST(opm32, opxmm, opk, opxmm) + ctx.VPDPWSSDS_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPDPWSSDS_Z(opm128, opxmm, opk, opxmm) + ctx.VPDPWSSD_BCST(opm32, opxmm, opk, opxmm) + ctx.VPDPWSSD_BCST_Z(opm32, opxmm, opk, opxmm) + ctx.VPDPWSSD_Z(opm128, opxmm, opk, opxmm) ctx.VPERM2F128(opimm8, opm256, opymm, opymm) ctx.VPERM2I128(opimm8, opm256, opymm, opymm) ctx.VPERMB(opm128, opxmm, opk, opxmm) diff --git a/internal/inst/ztable.go b/internal/inst/ztable.go index 1a16b28f..4bd143b0 100644 --- a/internal/inst/ztable.go +++ b/internal/inst/ztable.go @@ -70818,6 +70818,1146 @@ var Instructions = []Instruction{ }, }, }, + { + Opcode: "VPDPBUSD", + Summary: "Multiply and Add Unsigned and Signed Bytes", + Forms: []Form{ + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPDPBUSDS", + Summary: "Multiply and Add Unsigned and Signed Bytes with Saturation", + Forms: []Form{ + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPDPWSSD", + Summary: "Multiply and Add Signed Word Integers", + Forms: []Form{ + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, + { + Opcode: "VPDPWSSDS", + Summary: "Multiply and Add Signed Word Integers with Saturation", + Forms: []Form{ + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m128", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m256", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x1}, + {Type: "xmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VL", "AVX512VNNI"}, + Operands: []Operand{ + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x1}, + {Type: "ymm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + Broadcast: true, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "m32", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Broadcast: true, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "m512", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "k", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + Zeroing: true, + }, + { + ISA: []string{"AVX512VNNI"}, + Operands: []Operand{ + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x1}, + {Type: "zmm", Action: 0x3}, + }, + EncodingType: 0x4, + }, + }, + }, { Opcode: "VPERM2F128", Summary: "Permute Floating-Point Values", diff --git a/internal/opcodesextra/vnni.go b/internal/opcodesextra/vnni.go index 418b7404..9cb75662 100644 --- a/internal/opcodesextra/vnni.go +++ b/internal/opcodesextra/vnni.go @@ -72,291 +72,66 @@ var vnniforms = inst.Forms{ // EVEX.128.66.0F38.W0 51 /r VPDPBUSDS xmm1{k1}{z}, xmm2, xmm3/m128/m32bcst AVX512VNNI AVX512VL // EVEX.128.66.0F38.W0 52 /r VPDPWSSD xmm1{k1}{z}, xmm2, xmm3/m128/m32bcst AVX512VNNI AVX512VL // EVEX.128.66.0F38.W0 53 /r VPDPWSSDS xmm1{k1}{z}, xmm2, xmm3/m128/m32bcst AVX512VNNI AVX512VL - // EVEX.256.66.0F38.W0 50 /r VPDPBUSD ymm1{k1}{z}, ymm2, ymm3/m256/m32bcst AVX512VNNI AVX512VL - // EVEX.256.66.0F38.W0 51 /r VPDPBUSDS ymm1{k1}{z}, ymm2, ymm3/m256/m32bcst AVX512VNNI AVX512VL - // EVEX.256.66.0F38.W0 52 /r VPDPWSSD ymm1{k1}{z}, ymm2, ymm3/m256/m32bcst AVX512VNNI AVX512VL - // EVEX.256.66.0F38.W0 53 /r VPDPWSSDS ymm1{k1}{z}, ymm2, ymm3/m256/m32bcst AVX512VNNI AVX512VL - // EVEX.512.66.0F38.W0 50 /r VPDPBUSD zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst AVX512VNNI - // EVEX.512.66.0F38.W0 51 /r VPDPBUSDS zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst AVX512VNNI - // EVEX.512.66.0F38.W0 52 /r VPDPWSSD zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst AVX512VNNI - // EVEX.512.66.0F38.W0 53 /r VPDPWSSDS zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst AVX512VNNI - { - ISA: []string{"AVX512VL", "AVX512VNNI"}, - Operands: []inst.Operand{ - {Type: "m128", Action: inst.R}, - {Type: "xmm", Action: inst.R}, - {Type: "k", Action: inst.R}, - {Type: "xmm", Action: inst.RW}, - }, - EncodingType: inst.EncodingTypeEVEX, - }, - { - ISA: []string{"AVX512VL", "AVX512VNNI"}, - Operands: []inst.Operand{ - {Type: "m128", Action: inst.R}, - {Type: "xmm", Action: inst.R}, - {Type: "k", Action: inst.R}, - {Type: "xmm", Action: inst.W}, - }, - EncodingType: inst.EncodingTypeEVEX, - Zeroing: true, - }, - { - ISA: []string{"AVX512VL", "AVX512VNNI"}, - Operands: []inst.Operand{ - {Type: "m128", Action: inst.R}, - {Type: "xmm", Action: inst.R}, - {Type: "xmm", Action: inst.W}, - }, - EncodingType: inst.EncodingTypeEVEX, - }, - { - ISA: []string{"AVX512VL", "AVX512VNNI"}, - Operands: []inst.Operand{ - {Type: "m256", Action: inst.R}, - {Type: "ymm", Action: inst.R}, - {Type: "k", Action: inst.R}, - {Type: "ymm", Action: inst.RW}, - }, - EncodingType: inst.EncodingTypeEVEX, - }, - { - ISA: []string{"AVX512VL", "AVX512VNNI"}, - Operands: []inst.Operand{ - {Type: "m256", Action: inst.R}, - {Type: "ymm", Action: inst.R}, - {Type: "k", Action: inst.R}, - {Type: "ymm", Action: inst.W}, - }, - EncodingType: inst.EncodingTypeEVEX, - Zeroing: true, - }, - { - ISA: []string{"AVX512VL", "AVX512VNNI"}, - Operands: []inst.Operand{ - {Type: "m256", Action: inst.R}, - {Type: "ymm", Action: inst.R}, - {Type: "ymm", Action: inst.W}, - }, - EncodingType: inst.EncodingTypeEVEX, - }, - { - ISA: []string{"AVX512VL", "AVX512VNNI"}, - Operands: []inst.Operand{ - {Type: "m32", Action: inst.R}, - {Type: "xmm", Action: inst.R}, - {Type: "k", Action: inst.R}, - {Type: "xmm", Action: inst.RW}, - }, - EncodingType: inst.EncodingTypeEVEX, - Broadcast: true, - }, - { - ISA: []string{"AVX512VL", "AVX512VNNI"}, - Operands: []inst.Operand{ - {Type: "m32", Action: inst.R}, - {Type: "xmm", Action: inst.R}, - {Type: "k", Action: inst.R}, - {Type: "xmm", Action: inst.W}, - }, - EncodingType: inst.EncodingTypeEVEX, - Zeroing: true, - Broadcast: true, - }, - { - ISA: []string{"AVX512VL", "AVX512VNNI"}, - Operands: []inst.Operand{ - {Type: "m32", Action: inst.R}, - {Type: "xmm", Action: inst.R}, - {Type: "xmm", Action: inst.W}, - }, - EncodingType: inst.EncodingTypeEVEX, - Broadcast: true, - }, - { - ISA: []string{"AVX512VL", "AVX512VNNI"}, - Operands: []inst.Operand{ - {Type: "m32", Action: inst.R}, - {Type: "ymm", Action: inst.R}, - {Type: "k", Action: inst.R}, - {Type: "ymm", Action: inst.RW}, - }, - EncodingType: inst.EncodingTypeEVEX, - Broadcast: true, - }, - { - ISA: []string{"AVX512VL", "AVX512VNNI"}, - Operands: []inst.Operand{ - {Type: "m32", Action: inst.R}, - {Type: "ymm", Action: inst.R}, - {Type: "k", Action: inst.R}, - {Type: "ymm", Action: inst.W}, - }, - EncodingType: inst.EncodingTypeEVEX, - Zeroing: true, - Broadcast: true, - }, { - ISA: []string{"AVX512VL", "AVX512VNNI"}, - Operands: []inst.Operand{ - {Type: "m32", Action: inst.R}, - {Type: "ymm", Action: inst.R}, - {Type: "ymm", Action: inst.W}, - }, - EncodingType: inst.EncodingTypeEVEX, - Broadcast: true, - }, - { - ISA: []string{"AVX512VL", "AVX512VNNI"}, Operands: []inst.Operand{ {Type: "xmm", Action: inst.R}, {Type: "xmm", Action: inst.R}, - {Type: "k", Action: inst.R}, - {Type: "xmm", Action: inst.RW}, + {Type: "xmm{k}{z}", Action: inst.RW}, }, EncodingType: inst.EncodingTypeEVEX, + ISA: []string{"AVX512VL", "AVX512VNNI"}, }, { - ISA: []string{"AVX512VL", "AVX512VNNI"}, Operands: []inst.Operand{ + {Type: "m128/m32bcst", Action: inst.R}, {Type: "xmm", Action: inst.R}, - {Type: "xmm", Action: inst.R}, - {Type: "k", Action: inst.R}, - {Type: "xmm", Action: inst.W}, - }, - EncodingType: inst.EncodingTypeEVEX, - Zeroing: true, - }, - { - ISA: []string{"AVX512VL", "AVX512VNNI"}, - Operands: []inst.Operand{ - {Type: "xmm", Action: inst.R}, - {Type: "xmm", Action: inst.R}, - {Type: "xmm", Action: inst.W}, - }, - EncodingType: inst.EncodingTypeEVEX, - }, - { - ISA: []string{"AVX512VL", "AVX512VNNI"}, - Operands: []inst.Operand{ - {Type: "ymm", Action: inst.R}, - {Type: "ymm", Action: inst.R}, - {Type: "k", Action: inst.R}, - {Type: "ymm", Action: inst.RW}, + {Type: "xmm{k}{z}", Action: inst.RW}, }, EncodingType: inst.EncodingTypeEVEX, + ISA: []string{"AVX512VL", "AVX512VNNI"}, }, + // EVEX.256.66.0F38.W0 50 /r VPDPBUSD ymm1{k1}{z}, ymm2, ymm3/m256/m32bcst AVX512VNNI AVX512VL + // EVEX.256.66.0F38.W0 51 /r VPDPBUSDS ymm1{k1}{z}, ymm2, ymm3/m256/m32bcst AVX512VNNI AVX512VL + // EVEX.256.66.0F38.W0 52 /r VPDPWSSD ymm1{k1}{z}, ymm2, ymm3/m256/m32bcst AVX512VNNI AVX512VL + // EVEX.256.66.0F38.W0 53 /r VPDPWSSDS ymm1{k1}{z}, ymm2, ymm3/m256/m32bcst AVX512VNNI AVX512VL { - ISA: []string{"AVX512VL", "AVX512VNNI"}, Operands: []inst.Operand{ {Type: "ymm", Action: inst.R}, {Type: "ymm", Action: inst.R}, - {Type: "k", Action: inst.R}, - {Type: "ymm", Action: inst.W}, + {Type: "ymm{k}{z}", Action: inst.RW}, }, EncodingType: inst.EncodingTypeEVEX, - Zeroing: true, + ISA: []string{"AVX512VL", "AVX512VNNI"}, }, { - ISA: []string{"AVX512VL", "AVX512VNNI"}, Operands: []inst.Operand{ + {Type: "m256/m32bcst", Action: inst.R}, {Type: "ymm", Action: inst.R}, - {Type: "ymm", Action: inst.R}, - {Type: "ymm", Action: inst.W}, - }, - EncodingType: inst.EncodingTypeEVEX, - }, - { - ISA: []string{"AVX512VNNI"}, - Operands: []inst.Operand{ - {Type: "m512", Action: inst.R}, - {Type: "zmm", Action: inst.R}, - {Type: "k", Action: inst.R}, - {Type: "zmm", Action: inst.RW}, - }, - EncodingType: inst.EncodingTypeEVEX, - }, - { - ISA: []string{"AVX512VNNI"}, - Operands: []inst.Operand{ - {Type: "m512", Action: inst.R}, - {Type: "zmm", Action: inst.R}, - {Type: "k", Action: inst.R}, - {Type: "zmm", Action: inst.W}, - }, - EncodingType: inst.EncodingTypeEVEX, - Zeroing: true, - }, - { - ISA: []string{"AVX512VNNI"}, - Operands: []inst.Operand{ - {Type: "m512", Action: inst.R}, - {Type: "zmm", Action: inst.R}, - {Type: "zmm", Action: inst.W}, - }, - EncodingType: inst.EncodingTypeEVEX, - }, - { - ISA: []string{"AVX512VNNI"}, - Operands: []inst.Operand{ - {Type: "m32", Action: inst.R}, - {Type: "zmm", Action: inst.R}, - {Type: "k", Action: inst.R}, - {Type: "zmm", Action: inst.RW}, - }, - EncodingType: inst.EncodingTypeEVEX, - Broadcast: true, - }, - { - ISA: []string{"AVX512VNNI"}, - Operands: []inst.Operand{ - {Type: "m32", Action: inst.R}, - {Type: "zmm", Action: inst.R}, - {Type: "k", Action: inst.R}, - {Type: "zmm", Action: inst.W}, - }, - EncodingType: inst.EncodingTypeEVEX, - Zeroing: true, - Broadcast: true, - }, - { - ISA: []string{"AVX512VNNI"}, - Operands: []inst.Operand{ - {Type: "m32", Action: inst.R}, - {Type: "zmm", Action: inst.R}, - {Type: "zmm", Action: inst.W}, - }, - EncodingType: inst.EncodingTypeEVEX, - Broadcast: true, - }, - { - ISA: []string{"AVX512VNNI"}, - Operands: []inst.Operand{ - {Type: "zmm", Action: inst.R}, - {Type: "zmm", Action: inst.R}, - {Type: "k", Action: inst.R}, - {Type: "zmm", Action: inst.RW}, + {Type: "ymm{k}{z}", Action: inst.RW}, }, EncodingType: inst.EncodingTypeEVEX, + ISA: []string{"AVX512VL", "AVX512VNNI"}, }, + // EVEX.512.66.0F38.W0 50 /r VPDPBUSD zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst AVX512VNNI + // EVEX.512.66.0F38.W0 51 /r VPDPBUSDS zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst AVX512VNNI + // EVEX.512.66.0F38.W0 52 /r VPDPWSSD zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst AVX512VNNI + // EVEX.512.66.0F38.W0 53 /r VPDPWSSDS zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst AVX512VNNI { - ISA: []string{"AVX512VNNI"}, Operands: []inst.Operand{ {Type: "zmm", Action: inst.R}, {Type: "zmm", Action: inst.R}, - {Type: "k", Action: inst.R}, - {Type: "zmm", Action: inst.W}, + {Type: "zmm{k}{z}", Action: inst.RW}, }, EncodingType: inst.EncodingTypeEVEX, - Zeroing: true, + ISA: []string{"AVX512VNNI"}, }, { - ISA: []string{"AVX512VNNI"}, Operands: []inst.Operand{ + {Type: "m512/m32bcst", Action: inst.R}, {Type: "zmm", Action: inst.R}, - {Type: "zmm", Action: inst.R}, - {Type: "zmm", Action: inst.W}, + {Type: "zmm{k}{z}", Action: inst.RW}, }, EncodingType: inst.EncodingTypeEVEX, + ISA: []string{"AVX512VNNI"}, }, } diff --git a/x86/zctors.go b/x86/zctors.go index c8cdc3f0..832f1990 100644 --- a/x86/zctors.go +++ b/x86/zctors.go @@ -26447,6 +26447,242 @@ func VPCONFLICTQ_Z(mxyz, k, xyz operand.Op) (*intrep.Instruction, error) { return build(opcVPCONFLICTQ.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, k, xyz}) } +// VPDPBUSD: Multiply and Add Unsigned and Signed Bytes. +// +// Forms: +// +// VPDPBUSD m128 xmm k xmm +// VPDPBUSD m128 xmm xmm +// VPDPBUSD m256 ymm k ymm +// VPDPBUSD m256 ymm ymm +// VPDPBUSD xmm xmm k xmm +// VPDPBUSD xmm xmm xmm +// VPDPBUSD ymm ymm k ymm +// VPDPBUSD ymm ymm ymm +// VPDPBUSD m512 zmm k zmm +// VPDPBUSD m512 zmm zmm +// VPDPBUSD zmm zmm k zmm +// VPDPBUSD zmm zmm zmm +func VPDPBUSD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPDPBUSD.Forms(), sffxs{}, ops) +} + +// VPDPBUSDS: Multiply and Add Unsigned and Signed Bytes with Saturation. +// +// Forms: +// +// VPDPBUSDS m128 xmm k xmm +// VPDPBUSDS m128 xmm xmm +// VPDPBUSDS m256 ymm k ymm +// VPDPBUSDS m256 ymm ymm +// VPDPBUSDS xmm xmm k xmm +// VPDPBUSDS xmm xmm xmm +// VPDPBUSDS ymm ymm k ymm +// VPDPBUSDS ymm ymm ymm +// VPDPBUSDS m512 zmm k zmm +// VPDPBUSDS m512 zmm zmm +// VPDPBUSDS zmm zmm k zmm +// VPDPBUSDS zmm zmm zmm +func VPDPBUSDS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPDPBUSDS.Forms(), sffxs{}, ops) +} + +// VPDPBUSDS_BCST: Multiply and Add Unsigned and Signed Bytes with Saturation (Broadcast). +// +// Forms: +// +// VPDPBUSDS.BCST m32 xmm k xmm +// VPDPBUSDS.BCST m32 xmm xmm +// VPDPBUSDS.BCST m32 ymm k ymm +// VPDPBUSDS.BCST m32 ymm ymm +// VPDPBUSDS.BCST m32 zmm k zmm +// VPDPBUSDS.BCST m32 zmm zmm +func VPDPBUSDS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPDPBUSDS.Forms(), sffxs{sffxBCST}, ops) +} + +// VPDPBUSDS_BCST_Z: Multiply and Add Unsigned and Signed Bytes with Saturation (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPDPBUSDS.BCST.Z m32 xmm k xmm +// VPDPBUSDS.BCST.Z m32 ymm k ymm +// VPDPBUSDS.BCST.Z m32 zmm k zmm +func VPDPBUSDS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPDPBUSDS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VPDPBUSDS_Z: Multiply and Add Unsigned and Signed Bytes with Saturation (Zeroing Masking). +// +// Forms: +// +// VPDPBUSDS.Z m128 xmm k xmm +// VPDPBUSDS.Z m256 ymm k ymm +// VPDPBUSDS.Z xmm xmm k xmm +// VPDPBUSDS.Z ymm ymm k ymm +// VPDPBUSDS.Z m512 zmm k zmm +// VPDPBUSDS.Z zmm zmm k zmm +func VPDPBUSDS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPDPBUSDS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPDPBUSD_BCST: Multiply and Add Unsigned and Signed Bytes (Broadcast). +// +// Forms: +// +// VPDPBUSD.BCST m32 xmm k xmm +// VPDPBUSD.BCST m32 xmm xmm +// VPDPBUSD.BCST m32 ymm k ymm +// VPDPBUSD.BCST m32 ymm ymm +// VPDPBUSD.BCST m32 zmm k zmm +// VPDPBUSD.BCST m32 zmm zmm +func VPDPBUSD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPDPBUSD.Forms(), sffxs{sffxBCST}, ops) +} + +// VPDPBUSD_BCST_Z: Multiply and Add Unsigned and Signed Bytes (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPDPBUSD.BCST.Z m32 xmm k xmm +// VPDPBUSD.BCST.Z m32 ymm k ymm +// VPDPBUSD.BCST.Z m32 zmm k zmm +func VPDPBUSD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPDPBUSD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VPDPBUSD_Z: Multiply and Add Unsigned and Signed Bytes (Zeroing Masking). +// +// Forms: +// +// VPDPBUSD.Z m128 xmm k xmm +// VPDPBUSD.Z m256 ymm k ymm +// VPDPBUSD.Z xmm xmm k xmm +// VPDPBUSD.Z ymm ymm k ymm +// VPDPBUSD.Z m512 zmm k zmm +// VPDPBUSD.Z zmm zmm k zmm +func VPDPBUSD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPDPBUSD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPDPWSSD: Multiply and Add Signed Word Integers. +// +// Forms: +// +// VPDPWSSD m128 xmm k xmm +// VPDPWSSD m128 xmm xmm +// VPDPWSSD m256 ymm k ymm +// VPDPWSSD m256 ymm ymm +// VPDPWSSD xmm xmm k xmm +// VPDPWSSD xmm xmm xmm +// VPDPWSSD ymm ymm k ymm +// VPDPWSSD ymm ymm ymm +// VPDPWSSD m512 zmm k zmm +// VPDPWSSD m512 zmm zmm +// VPDPWSSD zmm zmm k zmm +// VPDPWSSD zmm zmm zmm +func VPDPWSSD(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPDPWSSD.Forms(), sffxs{}, ops) +} + +// VPDPWSSDS: Multiply and Add Signed Word Integers with Saturation. +// +// Forms: +// +// VPDPWSSDS m128 xmm k xmm +// VPDPWSSDS m128 xmm xmm +// VPDPWSSDS m256 ymm k ymm +// VPDPWSSDS m256 ymm ymm +// VPDPWSSDS xmm xmm k xmm +// VPDPWSSDS xmm xmm xmm +// VPDPWSSDS ymm ymm k ymm +// VPDPWSSDS ymm ymm ymm +// VPDPWSSDS m512 zmm k zmm +// VPDPWSSDS m512 zmm zmm +// VPDPWSSDS zmm zmm k zmm +// VPDPWSSDS zmm zmm zmm +func VPDPWSSDS(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPDPWSSDS.Forms(), sffxs{}, ops) +} + +// VPDPWSSDS_BCST: Multiply and Add Signed Word Integers with Saturation (Broadcast). +// +// Forms: +// +// VPDPWSSDS.BCST m32 xmm k xmm +// VPDPWSSDS.BCST m32 xmm xmm +// VPDPWSSDS.BCST m32 ymm k ymm +// VPDPWSSDS.BCST m32 ymm ymm +// VPDPWSSDS.BCST m32 zmm k zmm +// VPDPWSSDS.BCST m32 zmm zmm +func VPDPWSSDS_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPDPWSSDS.Forms(), sffxs{sffxBCST}, ops) +} + +// VPDPWSSDS_BCST_Z: Multiply and Add Signed Word Integers with Saturation (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPDPWSSDS.BCST.Z m32 xmm k xmm +// VPDPWSSDS.BCST.Z m32 ymm k ymm +// VPDPWSSDS.BCST.Z m32 zmm k zmm +func VPDPWSSDS_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPDPWSSDS.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VPDPWSSDS_Z: Multiply and Add Signed Word Integers with Saturation (Zeroing Masking). +// +// Forms: +// +// VPDPWSSDS.Z m128 xmm k xmm +// VPDPWSSDS.Z m256 ymm k ymm +// VPDPWSSDS.Z xmm xmm k xmm +// VPDPWSSDS.Z ymm ymm k ymm +// VPDPWSSDS.Z m512 zmm k zmm +// VPDPWSSDS.Z zmm zmm k zmm +func VPDPWSSDS_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPDPWSSDS.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + +// VPDPWSSD_BCST: Multiply and Add Signed Word Integers (Broadcast). +// +// Forms: +// +// VPDPWSSD.BCST m32 xmm k xmm +// VPDPWSSD.BCST m32 xmm xmm +// VPDPWSSD.BCST m32 ymm k ymm +// VPDPWSSD.BCST m32 ymm ymm +// VPDPWSSD.BCST m32 zmm k zmm +// VPDPWSSD.BCST m32 zmm zmm +func VPDPWSSD_BCST(ops ...operand.Op) (*intrep.Instruction, error) { + return build(opcVPDPWSSD.Forms(), sffxs{sffxBCST}, ops) +} + +// VPDPWSSD_BCST_Z: Multiply and Add Signed Word Integers (Broadcast, Zeroing Masking). +// +// Forms: +// +// VPDPWSSD.BCST.Z m32 xmm k xmm +// VPDPWSSD.BCST.Z m32 ymm k ymm +// VPDPWSSD.BCST.Z m32 zmm k zmm +func VPDPWSSD_BCST_Z(m, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPDPWSSD.Forms(), sffxs{sffxBCST, sffxZ}, []operand.Op{m, xyz, k, xyz1}) +} + +// VPDPWSSD_Z: Multiply and Add Signed Word Integers (Zeroing Masking). +// +// Forms: +// +// VPDPWSSD.Z m128 xmm k xmm +// VPDPWSSD.Z m256 ymm k ymm +// VPDPWSSD.Z xmm xmm k xmm +// VPDPWSSD.Z ymm ymm k ymm +// VPDPWSSD.Z m512 zmm k zmm +// VPDPWSSD.Z zmm zmm k zmm +func VPDPWSSD_Z(mxyz, xyz, k, xyz1 operand.Op) (*intrep.Instruction, error) { + return build(opcVPDPWSSD.Forms(), sffxs{sffxZ}, []operand.Op{mxyz, xyz, k, xyz1}) +} + // VPERM2F128: Permute Floating-Point Values. // // Forms: diff --git a/x86/zctors_test.go b/x86/zctors_test.go index 2c323e1f..95c91c35 100644 --- a/x86/zctors_test.go +++ b/x86/zctors_test.go @@ -30233,6 +30233,378 @@ func TestVPCONFLICTQ_ZValidFormsNoError(t *testing.T) { } } +func TestVPDPBUSDValidFormsNoError(t *testing.T) { + if _, err := VPDPBUSD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPDPBUSDSValidFormsNoError(t *testing.T) { + if _, err := VPDPBUSDS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSDS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSDS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSDS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSDS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSDS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSDS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSDS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSDS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSDS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSDS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSDS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPDPBUSDS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPDPBUSDS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSDS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSDS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSDS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSDS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSDS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPDPBUSDS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPDPBUSDS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSDS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSDS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPDPBUSDS_ZValidFormsNoError(t *testing.T) { + if _, err := VPDPBUSDS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSDS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSDS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSDS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSDS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSDS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPDPBUSD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPDPBUSD_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSD_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSD_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSD_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSD_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSD_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPDPBUSD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPDPBUSD_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSD_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSD_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPDPBUSD_ZValidFormsNoError(t *testing.T) { + if _, err := VPDPBUSD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPBUSD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPDPWSSDValidFormsNoError(t *testing.T) { + if _, err := VPDPWSSD(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSD(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSD(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSD(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSD(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSD(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSD(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSD(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSD(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSD(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSD(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSD(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPDPWSSDSValidFormsNoError(t *testing.T) { + if _, err := VPDPWSSDS(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSDS(opm128, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSDS(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSDS(opm256, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSDS(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSDS(opxmm, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSDS(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSDS(opymm, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSDS(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSDS(opm512, opzmm, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSDS(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSDS(opzmm, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPDPWSSDS_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPDPWSSDS_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSDS_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSDS_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSDS_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSDS_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSDS_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPDPWSSDS_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPDPWSSDS_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSDS_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSDS_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPDPWSSDS_ZValidFormsNoError(t *testing.T) { + if _, err := VPDPWSSDS_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSDS_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSDS_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSDS_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSDS_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSDS_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPDPWSSD_BCSTValidFormsNoError(t *testing.T) { + if _, err := VPDPWSSD_BCST(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSD_BCST(opm32, opxmm, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSD_BCST(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSD_BCST(opm32, opymm, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSD_BCST(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSD_BCST(opm32, opzmm, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPDPWSSD_BCST_ZValidFormsNoError(t *testing.T) { + if _, err := VPDPWSSD_BCST_Z(opm32, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSD_BCST_Z(opm32, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSD_BCST_Z(opm32, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + +func TestVPDPWSSD_ZValidFormsNoError(t *testing.T) { + if _, err := VPDPWSSD_Z(opm128, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSD_Z(opm256, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSD_Z(opxmm, opxmm, opk, opxmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSD_Z(opymm, opymm, opk, opymm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSD_Z(opm512, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } + if _, err := VPDPWSSD_Z(opzmm, opzmm, opk, opzmm); err != nil { + t.Fatal(err) + } +} + func TestVPERM2F128ValidFormsNoError(t *testing.T) { if _, err := VPERM2F128(opimm8, opm256, opymm, opymm); err != nil { t.Fatal(err) diff --git a/x86/zoptab.go b/x86/zoptab.go index a7380272..b8edbd83 100644 --- a/x86/zoptab.go +++ b/x86/zoptab.go @@ -315,6 +315,8 @@ const ( isasAVX512CD_AVX512VL isasAVX512CD isasAVX_PCLMULQDQ + isasAVX512VL_AVX512VNNI + isasAVX512VNNI isasAVX512VBMI_AVX512VL isasAVX512VBMI isasAVX512IFMA_AVX512VL @@ -379,6 +381,8 @@ var isaslisttable = [][]string{ {"AVX512CD", "AVX512VL"}, {"AVX512CD"}, {"AVX", "PCLMULQDQ"}, + {"AVX512VL", "AVX512VNNI"}, + {"AVX512VNNI"}, {"AVX512VBMI", "AVX512VL"}, {"AVX512VBMI"}, {"AVX512IFMA", "AVX512VL"}, @@ -1399,6 +1403,10 @@ const ( opcVPCOMPRESSQ opcVPCONFLICTD opcVPCONFLICTQ + opcVPDPBUSD + opcVPDPBUSDS + opcVPDPWSSD + opcVPDPWSSDS opcVPERM2F128 opcVPERM2I128 opcVPERMB @@ -2695,6 +2703,10 @@ var opcstringtable = []string{ "VPCOMPRESSQ", "VPCONFLICTD", "VPCONFLICTQ", + "VPDPBUSD", + "VPDPBUSDS", + "VPDPWSSD", + "VPDPWSSDS", "VPERM2F128", "VPERM2I128", "VPERMB", @@ -9861,6 +9873,114 @@ var forms = []form{ {opcVPCONFLICTQ, sffxsclsNIL, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, {opcVPCONFLICTQ, sffxsclsZ, 0, isasAVX512CD, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, {opcVPCONFLICTQ, sffxsclsNIL, 0, isasAVX512CD, 2, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionW}}}, + {opcVPDPBUSD, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsZ, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsZ, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsBCST, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsBCST_Z, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsBCST, 0, isasAVX512VL_AVX512VNNI, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsBCST, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsBCST_Z, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsBCST, 0, isasAVX512VL_AVX512VNNI, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsZ, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsZ, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsBCST, 0, isasAVX512VNNI, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsBCST_Z, 0, isasAVX512VNNI, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsBCST, 0, isasAVX512VNNI, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsNIL, 0, isasAVX512VNNI, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsZ, 0, isasAVX512VNNI, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsNIL, 0, isasAVX512VNNI, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsNIL, 0, isasAVX512VNNI, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsZ, 0, isasAVX512VNNI, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPBUSD, sffxsclsNIL, 0, isasAVX512VNNI, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsZ, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsZ, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsBCST, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsBCST_Z, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsBCST, 0, isasAVX512VL_AVX512VNNI, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsBCST, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsBCST_Z, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsBCST, 0, isasAVX512VL_AVX512VNNI, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsZ, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsZ, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsBCST, 0, isasAVX512VNNI, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsBCST_Z, 0, isasAVX512VNNI, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsBCST, 0, isasAVX512VNNI, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsNIL, 0, isasAVX512VNNI, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsZ, 0, isasAVX512VNNI, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsNIL, 0, isasAVX512VNNI, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsNIL, 0, isasAVX512VNNI, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsZ, 0, isasAVX512VNNI, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPBUSDS, sffxsclsNIL, 0, isasAVX512VNNI, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsZ, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsZ, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsBCST, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsBCST_Z, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsBCST, 0, isasAVX512VL_AVX512VNNI, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsBCST, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsBCST_Z, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsBCST, 0, isasAVX512VL_AVX512VNNI, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsZ, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsZ, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsBCST, 0, isasAVX512VNNI, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsBCST_Z, 0, isasAVX512VNNI, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsBCST, 0, isasAVX512VNNI, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsNIL, 0, isasAVX512VNNI, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsZ, 0, isasAVX512VNNI, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsNIL, 0, isasAVX512VNNI, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsNIL, 0, isasAVX512VNNI, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsZ, 0, isasAVX512VNNI, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPWSSD, sffxsclsNIL, 0, isasAVX512VNNI, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsZ, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 3, oprnds{{uint8(oprndtypeM128), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsZ, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 3, oprnds{{uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsBCST, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsBCST_Z, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsBCST, 0, isasAVX512VL_AVX512VNNI, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsBCST, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsBCST_Z, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsBCST, 0, isasAVX512VL_AVX512VNNI, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsZ, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 3, oprnds{{uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionR}, {uint8(oprndtypeXMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsZ, 0, isasAVX512VL_AVX512VNNI, 4, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsNIL, 0, isasAVX512VL_AVX512VNNI, 3, oprnds{{uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsBCST, 0, isasAVX512VNNI, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsBCST_Z, 0, isasAVX512VNNI, 4, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsBCST, 0, isasAVX512VNNI, 3, oprnds{{uint8(oprndtypeM32), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsNIL, 0, isasAVX512VNNI, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsZ, 0, isasAVX512VNNI, 4, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsNIL, 0, isasAVX512VNNI, 3, oprnds{{uint8(oprndtypeM512), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsNIL, 0, isasAVX512VNNI, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsZ, 0, isasAVX512VNNI, 4, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeK), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, + {opcVPDPWSSDS, sffxsclsNIL, 0, isasAVX512VNNI, 3, oprnds{{uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionR}, {uint8(oprndtypeZMM), false, actionRW}}}, {opcVPERM2F128, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, {opcVPERM2F128, sffxsclsNIL, 0, isasAVX, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, {opcVPERM2I128, sffxsclsNIL, 0, isasAVX2, 4, oprnds{{uint8(oprndtypeIMM8), false, actionN}, {uint8(oprndtypeM256), false, actionR}, {uint8(oprndtypeYMM), false, actionR}, {uint8(oprndtypeYMM), false, actionW}}}, @@ -15468,89 +15588,87 @@ var opcformstable = [][]form{ forms[6814:6832], forms[6832:6859], forms[6859:6886], - forms[6886:6888], - forms[6888:6890], - forms[6890:6908], - forms[6908:6926], - forms[6926:6944], - forms[6944:6971], - forms[6971:6998], - forms[6998:7025], - forms[7025:7052], - forms[7052:7070], - forms[7070:7124], - forms[7124:7178], - forms[7178:7214], - forms[7214:7232], - forms[7232:7268], - forms[7268:7286], - forms[7286:7313], - forms[7313:7340], - forms[7340:7367], - forms[7367:7394], - forms[7394:7412], - forms[7412:7430], - forms[7430:7448], - forms[7448:7466], - forms[7466:7468], - forms[7468:7470], - forms[7470:7472], - forms[7472:7474], - forms[7474:7479], - forms[7479:7484], - forms[7484:7489], - forms[7489:7494], - forms[7494:7498], - forms[7498:7502], - forms[7502:7506], - forms[7506:7508], - forms[7508:7512], - forms[7512:7516], - forms[7516:7520], - forms[7520:7522], - forms[7522:7524], - forms[7524:7526], - forms[7526:7528], - forms[7528:7555], - forms[7555:7582], - forms[7582:7609], - forms[7609:7636], - forms[7636:7654], - forms[7654:7672], - forms[7672:7676], - forms[7676:7680], - forms[7680:7698], - forms[7698:7725], - forms[7725:7752], - forms[7752:7770], - forms[7770:7788], - forms[7788:7815], - forms[7815:7842], - forms[7842:7860], + forms[6886:6913], + forms[6913:6940], + forms[6940:6967], + forms[6967:6994], + forms[6994:6996], + forms[6996:6998], + forms[6998:7016], + forms[7016:7034], + forms[7034:7052], + forms[7052:7079], + forms[7079:7106], + forms[7106:7133], + forms[7133:7160], + forms[7160:7178], + forms[7178:7232], + forms[7232:7286], + forms[7286:7322], + forms[7322:7340], + forms[7340:7376], + forms[7376:7394], + forms[7394:7421], + forms[7421:7448], + forms[7448:7475], + forms[7475:7502], + forms[7502:7520], + forms[7520:7538], + forms[7538:7556], + forms[7556:7574], + forms[7574:7576], + forms[7576:7578], + forms[7578:7580], + forms[7580:7582], + forms[7582:7587], + forms[7587:7592], + forms[7592:7597], + forms[7597:7602], + forms[7602:7606], + forms[7606:7610], + forms[7610:7614], + forms[7614:7616], + forms[7616:7620], + forms[7620:7624], + forms[7624:7628], + forms[7628:7630], + forms[7630:7632], + forms[7632:7634], + forms[7634:7636], + forms[7636:7663], + forms[7663:7690], + forms[7690:7717], + forms[7717:7744], + forms[7744:7762], + forms[7762:7780], + forms[7780:7784], + forms[7784:7788], + forms[7788:7806], + forms[7806:7833], + forms[7833:7860], forms[7860:7878], - forms[7878:7905], - forms[7905:7932], - forms[7932:7950], + forms[7878:7896], + forms[7896:7923], + forms[7923:7950], forms[7950:7968], - forms[7968:7995], - forms[7995:8022], - forms[8022:8040], - forms[8040:8043], - forms[8043:8046], - forms[8046:8064], - forms[8064:8082], - forms[8082:8085], - forms[8085:8088], - forms[8088:8091], - forms[8091:8094], - forms[8094:8096], - forms[8096:8099], - forms[8099:8117], - forms[8117:8135], - forms[8135:8153], - forms[8153:8171], - forms[8171:8189], - forms[8189:8207], + forms[7968:7986], + forms[7986:8013], + forms[8013:8040], + forms[8040:8058], + forms[8058:8076], + forms[8076:8103], + forms[8103:8130], + forms[8130:8148], + forms[8148:8151], + forms[8151:8154], + forms[8154:8172], + forms[8172:8190], + forms[8190:8193], + forms[8193:8196], + forms[8196:8199], + forms[8199:8202], + forms[8202:8204], + forms[8204:8207], forms[8207:8225], forms[8225:8243], forms[8243:8261], @@ -15566,183 +15684,189 @@ var opcformstable = [][]form{ forms[8423:8441], forms[8441:8459], forms[8459:8477], - forms[8477:8480], - forms[8480:8498], - forms[8498:8516], - forms[8516:8534], - forms[8534:8552], - forms[8552:8570], - forms[8570:8588], + forms[8477:8495], + forms[8495:8513], + forms[8513:8531], + forms[8531:8549], + forms[8549:8567], + forms[8567:8585], + forms[8585:8588], forms[8588:8606], - forms[8606:8633], - forms[8633:8651], - forms[8651:8669], - forms[8669:8687], - forms[8687:8714], + forms[8606:8624], + forms[8624:8642], + forms[8642:8660], + forms[8660:8678], + forms[8678:8696], + forms[8696:8714], forms[8714:8741], forms[8741:8759], - forms[8759:8786], - forms[8786:8813], - forms[8813:8822], - forms[8822:8831], - forms[8831:8835], - forms[8835:8862], - forms[8862:8889], - forms[8889:8916], - forms[8916:8943], + forms[8759:8777], + forms[8777:8795], + forms[8795:8822], + forms[8822:8849], + forms[8849:8867], + forms[8867:8894], + forms[8894:8921], + forms[8921:8930], + forms[8930:8939], + forms[8939:8943], forms[8943:8970], forms[8970:8997], forms[8997:9024], forms[9024:9051], forms[9051:9078], forms[9078:9105], - forms[9105:9111], - forms[9111:9114], - forms[9114:9117], - forms[9117:9120], - forms[9120:9123], - forms[9123:9141], - forms[9141:9168], - forms[9168:9186], - forms[9186:9204], - forms[9204:9208], - forms[9208:9212], - forms[9212:9216], - forms[9216:9261], - forms[9261:9267], - forms[9267:9312], - forms[9312:9339], - forms[9339:9366], - forms[9366:9384], - forms[9384:9420], - forms[9420:9465], - forms[9465:9510], - forms[9510:9537], - forms[9537:9564], - forms[9564:9582], - forms[9582:9618], - forms[9618:9663], - forms[9663:9669], - forms[9669:9714], - forms[9714:9741], - forms[9741:9768], - forms[9768:9786], - forms[9786:9822], - forms[9822:9840], - forms[9840:9867], - forms[9867:9894], - forms[9894:9912], - forms[9912:9930], + forms[9105:9132], + forms[9132:9159], + forms[9159:9186], + forms[9186:9213], + forms[9213:9219], + forms[9219:9222], + forms[9222:9225], + forms[9225:9228], + forms[9228:9231], + forms[9231:9249], + forms[9249:9276], + forms[9276:9294], + forms[9294:9312], + forms[9312:9316], + forms[9316:9320], + forms[9320:9324], + forms[9324:9369], + forms[9369:9375], + forms[9375:9420], + forms[9420:9447], + forms[9447:9474], + forms[9474:9492], + forms[9492:9528], + forms[9528:9573], + forms[9573:9618], + forms[9618:9645], + forms[9645:9672], + forms[9672:9690], + forms[9690:9726], + forms[9726:9771], + forms[9771:9777], + forms[9777:9822], + forms[9822:9849], + forms[9849:9876], + forms[9876:9894], + forms[9894:9930], forms[9930:9948], - forms[9948:9966], - forms[9966:9984], - forms[9984:10011], - forms[10011:10038], - forms[10038:10042], - forms[10042:10054], - forms[10054:10072], - forms[10072:10090], - forms[10090:10102], - forms[10102:10114], - forms[10114:10132], - forms[10132:10150], + forms[9948:9975], + forms[9975:10002], + forms[10002:10020], + forms[10020:10038], + forms[10038:10056], + forms[10056:10074], + forms[10074:10092], + forms[10092:10119], + forms[10119:10146], + forms[10146:10150], forms[10150:10162], forms[10162:10180], - forms[10180:10207], - forms[10207:10234], - forms[10234:10252], - forms[10252:10270], - forms[10270:10297], - forms[10297:10324], - forms[10324:10342], - forms[10342:10346], - forms[10346:10373], - forms[10373:10400], - forms[10400:10430], - forms[10430:10460], - forms[10460:10469], - forms[10469:10478], - forms[10478:10505], - forms[10505:10532], - forms[10532:10538], - forms[10538:10544], - forms[10544:10556], - forms[10556:10568], + forms[10180:10198], + forms[10198:10210], + forms[10210:10222], + forms[10222:10240], + forms[10240:10258], + forms[10258:10270], + forms[10270:10288], + forms[10288:10315], + forms[10315:10342], + forms[10342:10360], + forms[10360:10378], + forms[10378:10405], + forms[10405:10432], + forms[10432:10450], + forms[10450:10454], + forms[10454:10481], + forms[10481:10508], + forms[10508:10538], + forms[10538:10568], forms[10568:10577], forms[10577:10586], - forms[10586:10590], - forms[10590:10592], - forms[10592:10619], - forms[10619:10646], + forms[10586:10613], + forms[10613:10640], + forms[10640:10646], forms[10646:10652], - forms[10652:10658], - forms[10658:10688], - forms[10688:10718], - forms[10718:10727], - forms[10727:10736], - forms[10736:10740], - forms[10740:10744], - forms[10744:10746], - forms[10746:10748], - forms[10748:10775], - forms[10775:10802], - forms[10802:10808], - forms[10808:10814], - forms[10814:10826], - forms[10826:10838], - forms[10838:10847], - forms[10847:10856], - forms[10856:10860], - forms[10860:10862], - forms[10862:10892], - forms[10892:10922], - forms[10922:10931], - forms[10931:10940], - forms[10940:10943], - forms[10943:10946], - forms[10946:10949], - forms[10949:10952], - forms[10952:10970], - forms[10970:10988], - forms[10988:11006], - forms[11006:11024], - forms[11024:11051], - forms[11051:11078], - forms[11078:11108], - forms[11108:11138], - forms[11138:11147], - forms[11147:11156], - forms[11156:11157], - forms[11157:11187], - forms[11187:11217], - forms[11217:11226], - forms[11226:11235], - forms[11235:11239], - forms[11239:11243], - forms[11243:11246], - forms[11246:11249], - forms[11249:11276], - forms[11276:11303], - forms[11303:11330], - forms[11330:11357], + forms[10652:10664], + forms[10664:10676], + forms[10676:10685], + forms[10685:10694], + forms[10694:10698], + forms[10698:10700], + forms[10700:10727], + forms[10727:10754], + forms[10754:10760], + forms[10760:10766], + forms[10766:10796], + forms[10796:10826], + forms[10826:10835], + forms[10835:10844], + forms[10844:10848], + forms[10848:10852], + forms[10852:10854], + forms[10854:10856], + forms[10856:10883], + forms[10883:10910], + forms[10910:10916], + forms[10916:10922], + forms[10922:10934], + forms[10934:10946], + forms[10946:10955], + forms[10955:10964], + forms[10964:10968], + forms[10968:10970], + forms[10970:11000], + forms[11000:11030], + forms[11030:11039], + forms[11039:11048], + forms[11048:11051], + forms[11051:11054], + forms[11054:11057], + forms[11057:11060], + forms[11060:11078], + forms[11078:11096], + forms[11096:11114], + forms[11114:11132], + forms[11132:11159], + forms[11159:11186], + forms[11186:11216], + forms[11216:11246], + forms[11246:11255], + forms[11255:11264], + forms[11264:11265], + forms[11265:11295], + forms[11295:11325], + forms[11325:11334], + forms[11334:11343], + forms[11343:11347], + forms[11347:11351], + forms[11351:11354], + forms[11354:11357], forms[11357:11384], forms[11384:11411], - forms[11411:11412], - forms[11412:11413], - forms[11413:11415], - forms[11415:11417], - forms[11417:11419], - forms[11419:11421], - forms[11421:11424], - forms[11424:11429], - forms[11429:11434], - forms[11434:11439], - forms[11439:11440], - forms[11440:11441], - forms[11441:11447], - forms[11447:11455], - forms[11455:11457], - forms[11457:11459], - forms[11459:11467], - forms[11467:11475], + forms[11411:11438], + forms[11438:11465], + forms[11465:11492], + forms[11492:11519], + forms[11519:11520], + forms[11520:11521], + forms[11521:11523], + forms[11523:11525], + forms[11525:11527], + forms[11527:11529], + forms[11529:11532], + forms[11532:11537], + forms[11537:11542], + forms[11542:11547], + forms[11547:11548], + forms[11548:11549], + forms[11549:11555], + forms[11555:11563], + forms[11563:11565], + forms[11565:11567], + forms[11567:11575], + forms[11575:11583], }