From f5983cc592c0f3364b12f164817b12f1a0b1d4cb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 16 Nov 2022 11:03:24 +0000 Subject: [PATCH] Add support for ESP32_C3 (#2471) --- .vscode/tasks.TEMPLATE.json | 12 +- CMake/Modules/ESP32_C3_GCC_options.cmake | 53 + CMake/Modules/ESP32_C3_sources.cmake | 4 + CMake/Modules/FindESP32_IDF.cmake | 15 +- CMake/binutils.ESP32.cmake | 169 ++- CMake/toolchain.riscv32-esp-elf.cmake | 7 +- CMakeLists.txt | 6 - CMakePresets.json | 54 +- CMakeUserPresets.TEMPLATE.json | 37 +- README.md | 3 + README.zh-cn.md | 3 + azure-pipelines-nightly.yml | 8 + .../build-espressif-esp32-targets.yml | 33 +- azure-pipelines.yml | 8 + .../nf_boot_message/CMakeLists.txt | 5 +- .../nf_boot_message/boot_msg.c | 6 - targets/ESP32/CMakeLists.txt | 5 + targets/ESP32/ESP32_C3/CMakeLists.txt | 10 + targets/ESP32/ESP32_C3/common/CMakeLists.txt | 4 + targets/ESP32/ESP32_C3/ffconf.h | 342 +++++ ...wm_native_System_Device_Pwm_PwmChannel.cpp | 415 ++++++ targets/ESP32/ESP32_C3/nanoCLR/nanoHAL.cpp | 8 + .../ESP32/ESP32_C3/nanoCLR/target_board.h.in | 18 + targets/ESP32/ESP32_C3/target_BlockStorage.c | 23 + targets/ESP32/ESP32_C3/target_BlockStorage.h | 12 + targets/ESP32/ESP32_C3/target_common.c | 29 + targets/ESP32/ESP32_C3/target_common.h.in | 49 + .../ESP32/ESP32_C3/target_lwip_sntp_opts.h | 8 + targets/ESP32/ESP32_C3/target_lwipopts.h | 8 + .../ESP32_C3/target_nf_dev_onewire_config.cpp | 8 + .../ESP32_C3/target_nf_dev_onewire_config.h | 10 + .../target_system_device_adc_config.cpp | 8 + .../target_system_device_dac_config.cpp | 8 + .../target_system_device_i2c_config.cpp | 8 + .../target_system_device_i2s_config.cpp | 8 + .../target_system_device_spi_config.cpp | 8 + .../target_system_devices_dac_config.cpp | 8 + .../target_system_io_ports_config.cpp | 8 + .../ESP32_C3/target_windows_storage_config.h | 8 + targets/ESP32/_IDF/esp32c3/app_main.c | 57 + .../_IDF/esp32c3/partitions_nanoclr_2mb.csv | 17 + .../_IDF/esp32c3/partitions_nanoclr_4mb.csv | 17 + targets/ESP32/_IDF/sdkconfig.default.esp32c3 | 1162 +++++++++++++++++ .../ESP32/_IDF/sdkconfig.default_rev3.esp32c3 | 1162 +++++++++++++++++ .../ESP32/_common/DeviceMapping_common.cpp | 4 + .../ESP32/_common/ESP32_C3_DeviceMapping.cpp | 85 ++ .../ESP32/_common/Target_Windows_Storage.c | 4 +- .../_common/WireProtocol_HAL_Interface.c | 13 +- targets/ESP32/_common/targetHAL.c | 8 + targets/ESP32/_include/Esp32_DeviceMapping.h | 7 +- targets/ESP32/_include/esp32_idf.h | 16 + .../_nanoCLR/System.Device.Gpio/cpu_gpio.cpp | 4 + ...i2c_native_System_Device_I2c_I2cDevice.cpp | 14 +- .../_nanoCLR/System.Device.Spi/cpu_spi.cpp | 26 +- ...ware_esp32_native_Hardware_Esp32_Sleep.cpp | 152 ++- 55 files changed, 4050 insertions(+), 134 deletions(-) create mode 100644 CMake/Modules/ESP32_C3_GCC_options.cmake create mode 100644 CMake/Modules/ESP32_C3_sources.cmake create mode 100644 targets/ESP32/ESP32_C3/CMakeLists.txt create mode 100644 targets/ESP32/ESP32_C3/common/CMakeLists.txt create mode 100644 targets/ESP32/ESP32_C3/ffconf.h create mode 100644 targets/ESP32/ESP32_C3/nanoCLR/System.Device.Pwm/sys_dev_pwm_native_System_Device_Pwm_PwmChannel.cpp create mode 100644 targets/ESP32/ESP32_C3/nanoCLR/nanoHAL.cpp create mode 100644 targets/ESP32/ESP32_C3/nanoCLR/target_board.h.in create mode 100644 targets/ESP32/ESP32_C3/target_BlockStorage.c create mode 100644 targets/ESP32/ESP32_C3/target_BlockStorage.h create mode 100644 targets/ESP32/ESP32_C3/target_common.c create mode 100644 targets/ESP32/ESP32_C3/target_common.h.in create mode 100644 targets/ESP32/ESP32_C3/target_lwip_sntp_opts.h create mode 100644 targets/ESP32/ESP32_C3/target_lwipopts.h create mode 100644 targets/ESP32/ESP32_C3/target_nf_dev_onewire_config.cpp create mode 100644 targets/ESP32/ESP32_C3/target_nf_dev_onewire_config.h create mode 100644 targets/ESP32/ESP32_C3/target_system_device_adc_config.cpp create mode 100644 targets/ESP32/ESP32_C3/target_system_device_dac_config.cpp create mode 100644 targets/ESP32/ESP32_C3/target_system_device_i2c_config.cpp create mode 100644 targets/ESP32/ESP32_C3/target_system_device_i2s_config.cpp create mode 100644 targets/ESP32/ESP32_C3/target_system_device_spi_config.cpp create mode 100644 targets/ESP32/ESP32_C3/target_system_devices_dac_config.cpp create mode 100644 targets/ESP32/ESP32_C3/target_system_io_ports_config.cpp create mode 100644 targets/ESP32/ESP32_C3/target_windows_storage_config.h create mode 100644 targets/ESP32/_IDF/esp32c3/app_main.c create mode 100644 targets/ESP32/_IDF/esp32c3/partitions_nanoclr_2mb.csv create mode 100644 targets/ESP32/_IDF/esp32c3/partitions_nanoclr_4mb.csv create mode 100644 targets/ESP32/_IDF/sdkconfig.default.esp32c3 create mode 100644 targets/ESP32/_IDF/sdkconfig.default_rev3.esp32c3 create mode 100644 targets/ESP32/_common/ESP32_C3_DeviceMapping.cpp diff --git a/.vscode/tasks.TEMPLATE.json b/.vscode/tasks.TEMPLATE.json index 3cd0a96389..7341d3cac3 100644 --- a/.vscode/tasks.TEMPLATE.json +++ b/.vscode/tasks.TEMPLATE.json @@ -16,7 +16,7 @@ "command": "install-scripts\\install-nf-tools.ps1 -TargetSeries ${input:targetSeries} -Path '${input:toolsPath}' " }, { - "label": "Flash nanoCLR to ESP32", + "label": "Flash nanoCLR to ESP32/S2", "type": "shell", "command": "python ${env:IDF_PATH}/components/esptool_py/esptool/esptool.py --chip auto --port \"${input:comPort}\" --baud 1500000 --before \"default_reset\" --after \"hard_reset\" write_flash -z --flash_mode \"dio\" --flash_freq \"keep\" --flash_size detect 0x1000 ${workspaceFolder}/build/bootloader/bootloader.bin 0x10000 ${workspaceFolder}/build/nanoCLR.bin 0x8000 ${workspaceFolder}/build/partitions_${input:esp32Partitions}.bin", "presentation": { @@ -25,6 +25,16 @@ }, "problemMatcher": [] }, + { + "label": "Flash nanoCLR to ESP32-C3", + "type": "shell", + "command": "python ${env:IDF_PATH}/components/esptool_py/esptool/esptool.py --chip auto --port \"${input:comPort}\" --baud 1500000 --before \"default_reset\" --after \"hard_reset\" write_flash -z --flash_mode \"dio\" --flash_freq \"keep\" --flash_size detect 0x0 ${workspaceFolder}/build/bootloader/bootloader.bin 0x10000 ${workspaceFolder}/build/nanoCLR.bin 0x8000 ${workspaceFolder}/build/partitions_${input:esp32Partitions}.bin", + "presentation": { + "reveal": "always", + "panel": "shared" + }, + "problemMatcher": [] + }, { "label": "Erase ESP32 flash", "type": "shell", diff --git a/CMake/Modules/ESP32_C3_GCC_options.cmake b/CMake/Modules/ESP32_C3_GCC_options.cmake new file mode 100644 index 0000000000..548fe0a151 --- /dev/null +++ b/CMake/Modules/ESP32_C3_GCC_options.cmake @@ -0,0 +1,53 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +# need to specify linker flags here +set(CMAKE_EXE_LINKER_FLAGS " -Wl,--print-memory-usage " CACHE INTERNAL "executable linker flags") + +# TARGET parameter to set the target that's setting them for +# optional EXTRA_COMPILE_OPTIONS with compile options to be added +macro(nf_set_compile_options) + + # parse arguments + cmake_parse_arguments(NFSCO "" "TARGET" "EXTRA_COMPILE_OPTIONS" ${ARGN}) + + if(NOT NFSCO_TARGET OR "${NFSCO_TARGET}" STREQUAL "") + message(FATAL_ERROR "Need to set TARGET argument when calling nf_set_compile_options()") + endif() + + # include any extra options coming from any extra args? + target_compile_options(${NFSCO_TARGET} PUBLIC ${NFSCO__EXTRA_COMPILE_OPTIONS} -Wall -Wextra -Werror -Wno-unused-parameter -Wshadow -Wimplicit-fallthrough -fshort-wchar -fno-builtin -fno-common -fno-exceptions -fcheck-new ) + + # this series has FPU + target_compile_definitions(${NFSCO_TARGET} PUBLIC -DTARGET=esp32c3 -DUSE_FPU=TRUE -DPLATFORM_ESP32) + +endmacro() + +# TARGET parameter to set the target that's setting them for +# optional EXTRA_LINK_FLAGS with link flags to be added +macro(nf_set_link_options) + + # parse arguments + cmake_parse_arguments(NFSLO "" "TARGET;EXTRA_LINK_FLAGS" "" ${ARGN}) + + if(NOT NFSLO_TARGET OR "${NFSLO_TARGET}" STREQUAL "") + message(FATAL_ERROR "Need to set TARGET argument when calling nf_set_link_options()") + endif() + + # set optimization linker flags for RELEASE and MinSizeRel + if(CMAKE_BUILD_TYPE STREQUAL "Release" OR CMAKE_BUILD_TYPE STREQUAL "MinSizeRel") + set_property(TARGET ${NFSLO_TARGET} APPEND_STRING PROPERTY LINK_FLAGS " -Os ") + endif() + + # include libraries in build + nf_include_libraries_in_build(${NFSLO_TARGET}) + + # set extra linker flags + set_property(TARGET ${NFSLO_TARGET} APPEND_STRING PROPERTY LINK_FLAGS " ${NFSLO_EXTRA_LINK_FLAGS} ") + + # set optimization flags + nf_set_optimization_options(${NFSLO_TARGET}) + +endmacro() diff --git a/CMake/Modules/ESP32_C3_sources.cmake b/CMake/Modules/ESP32_C3_sources.cmake new file mode 100644 index 0000000000..0aa4fd139b --- /dev/null +++ b/CMake/Modules/ESP32_C3_sources.cmake @@ -0,0 +1,4 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# diff --git a/CMake/Modules/FindESP32_IDF.cmake b/CMake/Modules/FindESP32_IDF.cmake index 4b0c8d39d3..5104b48252 100644 --- a/CMake/Modules/FindESP32_IDF.cmake +++ b/CMake/Modules/FindESP32_IDF.cmake @@ -12,8 +12,11 @@ list(APPEND ESP32_IDF_INCLUDE_DIRS ${CMAKE_BINARY_DIR}/config) list(APPEND ESP32_IDF_INCLUDE_DIRS ${esp32_idf_SOURCE_DIR}/components/${TARGET_SERIES_SHORT}) list(APPEND ESP32_IDF_INCLUDE_DIRS ${esp32_idf_SOURCE_DIR}/components/${TARGET_SERIES_SHORT}/include) list(APPEND ESP32_IDF_INCLUDE_DIRS ${esp32_idf_SOURCE_DIR}/components/${TARGET_SERIES_SHORT}/esp_rom/include) -list(APPEND ESP32_IDF_INCLUDE_DIRS ${esp32_idf_SOURCE_DIR}/components/xtensa/${TARGET_SERIES_SHORT}/include) +list(APPEND ESP32_IDF_INCLUDE_DIRS ${esp32_idf_SOURCE_DIR}/components/${ESP32_CPU_TYPE}/include) +list(APPEND ESP32_IDF_INCLUDE_DIRS ${esp32_idf_SOURCE_DIR}/components/${ESP32_CPU_TYPE}/${TARGET_SERIES_SHORT}/include) + list(APPEND ESP32_IDF_INCLUDE_DIRS ${esp32_idf_SOURCE_DIR}/components/driver/${TARGET_SERIES_SHORT}/include/driver) +list(APPEND ESP32_IDF_INCLUDE_DIRS ${esp32_idf_SOURCE_DIR}/components/hal/include) list(APPEND ESP32_IDF_INCLUDE_DIRS ${esp32_idf_SOURCE_DIR}/components/hal/${TARGET_SERIES_SHORT}/include) list(APPEND ESP32_IDF_INCLUDE_DIRS ${esp32_idf_SOURCE_DIR}/components/soc/${TARGET_SERIES_SHORT}/include) list(APPEND ESP32_IDF_INCLUDE_DIRS ${esp32_idf_SOURCE_DIR}/components/soc/${TARGET_SERIES_SHORT}/include/soc) @@ -49,7 +52,6 @@ list(APPEND ESP32_IDF_INCLUDE_DIRS ${esp32_idf_SOURCE_DIR}/components/sdmmc) list(APPEND ESP32_IDF_INCLUDE_DIRS ${esp32_idf_SOURCE_DIR}/components/spiffs/include) list(APPEND ESP32_IDF_INCLUDE_DIRS ${esp32_idf_SOURCE_DIR}/components/spi_flash/include) list(APPEND ESP32_IDF_INCLUDE_DIRS ${esp32_idf_SOURCE_DIR}/components/soc/include) -list(APPEND ESP32_IDF_INCLUDE_DIRS ${esp32_idf_SOURCE_DIR}/components/xtensa/include) list(APPEND ESP32_IDF_INCLUDE_DIRS ${esp32_idf_SOURCE_DIR}/components/vfs/include) list(APPEND ESP32_IDF_INCLUDE_DIRS ${esp32_idf_SOURCE_DIR}/components/wear_levelling/include) @@ -76,10 +78,5 @@ include(${TARGET_SERIES}_GCC_options) list(APPEND ESP32_IDF_INCLUDE_DIRS ${esp32_idf_SOURCE_DIR}/components/freertos/include) list(APPEND ESP32_IDF_INCLUDE_DIRS ${esp32_idf_SOURCE_DIR}/components/freertos/include/esp_additions) list(APPEND ESP32_IDF_INCLUDE_DIRS ${esp32_idf_SOURCE_DIR}/components/freertos/include/esp_additions/freertos) -list(APPEND ESP32_IDF_INCLUDE_DIRS ${esp32_idf_SOURCE_DIR}/components/freertos/port/xtensa/include) -list(APPEND ESP32_IDF_INCLUDE_DIRS ${esp32_idf_SOURCE_DIR}/components/freertos/port/xtensa/include/freertos) - - -include(FindPackageHandleStandardArgs) - -# FIND_PACKAGE_HANDLE_STANDARD_ARGS(ESP32_IDF DEFAULT_MSG ESP32_IDF_INCLUDE_DIRS ESP32_IDF_SOURCES) +list(APPEND ESP32_IDF_INCLUDE_DIRS ${esp32_idf_SOURCE_DIR}/components/freertos/port/${ESP32_CPU_TYPE}/include) +list(APPEND ESP32_IDF_INCLUDE_DIRS ${esp32_idf_SOURCE_DIR}/components/freertos/port/${ESP32_CPU_TYPE}/include/freertos) diff --git a/CMake/binutils.ESP32.cmake b/CMake/binutils.ESP32.cmake index 82ba16eb8c..1ecb8bad41 100644 --- a/CMake/binutils.ESP32.cmake +++ b/CMake/binutils.ESP32.cmake @@ -102,6 +102,54 @@ function(nf_set_linker_file target linker_file_name) endfunction() +# fixes the ESP32_C3 rom linker script for rom_temp_to_power symbol +# this is required if the CPU it's a revision <= 2 +macro(nf_fix_esp32c3_rom_file) + + if((${TARGET_SERIES_SHORT} STREQUAL "esp32c3")) + # build is for esp32c3 + + if(${ESP32_REVISION} LESS_EQUAL 2) + # need to UNcomment the rom_temp_to_power symbol + file(READ + ${esp32_idf_SOURCE_DIR}/components/esp_rom/esp32c3/ld/esp32c3.rom.ld + ESP32_C3_ROM_LD_CONTENT) + + string(REPLACE + "/* rom_temp_to_power = 0x40001ab4; */" + "rom_temp_to_power = 0x40001ab4;" + ESP32_C3_ROM_LD_NEW_CONTENT + "${ESP32_C3_ROM_LD_CONTENT}") + + file(WRITE + ${esp32_idf_SOURCE_DIR}/components/esp_rom/esp32c3/ld/esp32c3.rom.ld + "${ESP32_C3_ROM_LD_NEW_CONTENT}") + else() + # need to COMMENT the rom_temp_to_power symbol + file(READ + ${esp32_idf_SOURCE_DIR}/components/esp_rom/esp32c3/ld/esp32c3.rom.ld + ESP32_C3_ROM_LD_CONTENT) + + string(FIND "${ESP32_C3_ROM_LD_CONTENT}" "/* rom_temp_to_power = 0x40001ab4; */" ROM_TEMP_SYMBOL_INDEX) + + if(ROM_TEMP_SYMBOL_INDEX EQUAL -1) + + string(REPLACE + "rom_temp_to_power = 0x40001ab4;" + "/* rom_temp_to_power = 0x40001ab4; */" + ESP32_C3_ROM_LD_NEW_CONTENT + "${ESP32_C3_ROM_LD_CONTENT}") + + file(WRITE + ${esp32_idf_SOURCE_DIR}/components/esp_rom/esp32c3/ld/esp32c3.rom.ld + "${ESP32_C3_ROM_LD_NEW_CONTENT}") + endif() + + endif() + + endif() + +endmacro() # setting compile definitions for a target based on general build options # TARGET parameter to set the target that's setting them for @@ -135,6 +183,13 @@ function(nf_set_esp32_target_series) # store the series name for later use set(TARGET_SERIES_SHORT ${TARGET_SERIES_2} CACHE INTERNAL "ESP32 target series lower case, short version") + # set the CPU type + if(${TARGET_SERIES_SHORT} STREQUAL "esp32c3" OR ${TARGET_SERIES_SHORT} STREQUAL "esp32h2") + set(ESP32_CPU_TYPE "riscv" CACHE INTERNAL "Setting CPU type") + else() + set(ESP32_CPU_TYPE "xtensa" CACHE INTERNAL "Setting CPU type") + endif() + endfunction() # Add packages that are common to ESP32 platform builds @@ -281,7 +336,7 @@ macro(nf_add_platform_sources target) # add header files with common OS definitions and board definitions configure_file(${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in - ${CMAKE_CURRENT_BINARY_DIR}/target_common.h @ONLY) + ${CMAKE_CURRENT_BINARY_DIR}/target_common.h @ONLY) # sources common to both builds target_sources(${target}.elf PUBLIC @@ -415,65 +470,46 @@ macro(nf_setup_partition_tables_generator) # create command line for partition table generator set(gen_partition_table "python" "${ESP32_PARTITION_TABLE_UTILITY}") - if(${TARGET_SERIES_SHORT} STREQUAL "esp32") - - # partition tables for ESP32 - add_custom_command( TARGET ${NANOCLR_PROJECT_NAME}.elf POST_BUILD - COMMAND ${gen_partition_table} - --flash-size 16MB - ${CMAKE_SOURCE_DIR}/targets/ESP32/_IDF/esp32/partitions_nanoclr_16mb.csv - ${CMAKE_BINARY_DIR}/partitions_16mb.bin - COMMENT "Generate ESP32 partition table for 16MB flash" ) - - add_custom_command( TARGET ${NANOCLR_PROJECT_NAME}.elf POST_BUILD - COMMAND ${gen_partition_table} - --flash-size 8MB - ${CMAKE_SOURCE_DIR}/targets/ESP32/_IDF/esp32/partitions_nanoclr_8mb.csv - ${CMAKE_BINARY_DIR}/partitions_8mb.bin - COMMENT "Generate ESP32 partition table for 8MB flash" ) + if(${TARGET_SERIES_SHORT} STREQUAL "esp32" OR ${TARGET_SERIES_SHORT} STREQUAL "esp32c3" OR ${TARGET_SERIES_SHORT} STREQUAL "esp32s2") add_custom_command( TARGET ${NANOCLR_PROJECT_NAME}.elf POST_BUILD COMMAND ${gen_partition_table} --flash-size 4MB - ${CMAKE_SOURCE_DIR}/targets/ESP32/_IDF/esp32/partitions_nanoclr_4mb.csv + ${CMAKE_SOURCE_DIR}/targets/ESP32/_IDF/${TARGET_SERIES_SHORT}/partitions_nanoclr_4mb.csv ${CMAKE_BINARY_DIR}/partitions_4mb.bin - COMMENT "Generate Esp32 partition table for 4MB flash" ) - - add_custom_command( TARGET ${NANOCLR_PROJECT_NAME}.elf POST_BUILD - COMMAND ${gen_partition_table} - --flash-size 2MB - ${CMAKE_SOURCE_DIR}/targets/ESP32/_IDF/esp32/partitions_nanoclr_2mb.csv - ${CMAKE_BINARY_DIR}/partitions_2mb.bin - COMMENT "Generate Esp32 partition table for 2MB flash" ) + COMMENT "Generate partition table for 4MB flash" ) - elseif(${TARGET_SERIES_SHORT} STREQUAL "esp32s2") - # partition tables for ESP32-S2) + endif() - - # partition tables for ESP32 - add_custom_command( TARGET ${NANOCLR_PROJECT_NAME}.elf POST_BUILD - COMMAND ${gen_partition_table} - --flash-size 16MB - ${CMAKE_SOURCE_DIR}/targets/ESP32/_IDF/esp32/partitions_nanoclr_16mb.csv - ${CMAKE_BINARY_DIR}/partitions_16mb.bin - COMMENT "Generate ESP32 partition table for 16MB flash" ) + if(${TARGET_SERIES_SHORT} STREQUAL "esp32" OR ${TARGET_SERIES_SHORT} STREQUAL "esp32s2") add_custom_command( TARGET ${NANOCLR_PROJECT_NAME}.elf POST_BUILD COMMAND ${gen_partition_table} --flash-size 8MB - ${CMAKE_SOURCE_DIR}/targets/ESP32/_IDF/esp32/partitions_nanoclr_8mb.csv + ${CMAKE_SOURCE_DIR}/targets/ESP32/_IDF/${TARGET_SERIES_SHORT}/partitions_nanoclr_8mb.csv ${CMAKE_BINARY_DIR}/partitions_8mb.bin - COMMENT "Generate ESP32 partition table for 8MB flash" ) + COMMENT "Generate partition table for 8MB flash" ) add_custom_command( TARGET ${NANOCLR_PROJECT_NAME}.elf POST_BUILD COMMAND ${gen_partition_table} - --flash-size 4MB - ${CMAKE_SOURCE_DIR}/targets/ESP32/_IDF/esp32/partitions_nanoclr_4mb.csv - ${CMAKE_BINARY_DIR}/partitions_4mb.bin - COMMENT "Generate Esp32 partition table for 4MB flash" ) + --flash-size 16MB + ${CMAKE_SOURCE_DIR}/targets/ESP32/_IDF/${TARGET_SERIES_SHORT}/partitions_nanoclr_16mb.csv + ${CMAKE_BINARY_DIR}/partitions_16mb.bin + COMMENT "Generate partition table for 16MB flash" ) endif() + if(${TARGET_SERIES_SHORT} STREQUAL "esp32" OR ${TARGET_SERIES_SHORT} STREQUAL "esp32c3" ) + # 2MB partition table for ESP32 + + add_custom_command( TARGET ${NANOCLR_PROJECT_NAME}.elf POST_BUILD + COMMAND ${gen_partition_table} + --flash-size 2MB + ${CMAKE_SOURCE_DIR}/targets/ESP32/_IDF/esp32/partitions_nanoclr_2mb.csv + ${CMAKE_BINARY_DIR}/partitions_2mb.bin + COMMENT "Generate partition table for 2MB flash" ) + endif() + endmacro() # macro to add IDF as a library to the build and add the IDF components according to variant and options @@ -496,10 +532,6 @@ macro(nf_add_idf_as_library) message(STATUS "Fixed IDF version. Is now: ${MY_IDF_VER_FIXED}") - # add IDF app_main - target_sources(${NANOCLR_PROJECT_NAME}.elf PUBLIC - ${CMAKE_SOURCE_DIR}/targets/ESP32/_IDF/${TARGET_SERIES_SHORT}/app_main.c) - # check for SDK config from build options if(SDK_CONFIG_FILE) # got an SDK config CONFIG on the build options @@ -546,7 +578,7 @@ macro(nf_add_idf_as_library) idf::esptool_py idf::spiffs idf::fatfs - ) + ) if(HAL_USE_BLE_OPTION) list(APPEND IDF_COMPONENTS_TO_ADD bt) @@ -662,6 +694,15 @@ macro(nf_add_idf_as_library) ${SDKCONFIG_DEFAULTS_FILE} PROJECT_NAME "nanoCLR" PROJECT_VER ${BUILD_VERSION} + PROJECT_DIR ${CMAKE_SOURCE_DIR} + ) + + set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + + # add IDF app_main + add_executable( + ${NANOCLR_PROJECT_NAME}.elf + ${CMAKE_SOURCE_DIR}/targets/ESP32/_IDF/${TARGET_SERIES_SHORT}/app_main.c ) #Restore original sdkconfig back to defaults @@ -775,10 +816,15 @@ macro(nf_add_idf_as_library) SDKCONFIG_DEFAULT_CONTENTS) # find out if there is support for PSRAM - string(FIND ${SDKCONFIG_DEFAULT_CONTENTS} "CONFIG_ESP32_SPIRAM_SUPPORT=y" CONFIG_ESP32_SPIRAM_SUPPORT_POS) + set(SPIRAM_SUPPORT_PRESENT -1) + if(TARGET_SERIES_SHORT STREQUAL "esp32" OR TARGET_SERIES_SHORT STREQUAL "esp32s2") + string(FIND ${SDKCONFIG_DEFAULT_CONTENTS} "CONFIG_ESP32_SPIRAM_SUPPORT=y" SPIRAM_SUPPORT_PRESENT) + elseif(TARGET_SERIES_SHORT STREQUAL "esp32s2") + string(FIND ${SDKCONFIG_DEFAULT_CONTENTS} "CONFIG_ESP32S2_SPIRAM_SUPPORT=y" SPIRAM_SUPPORT_PRESENT) + endif() # set variable - if(${CONFIG_ESP32_SPIRAM_SUPPORT_POS} GREATER -1) + if(${SPIRAM_SUPPORT_PRESENT} GREATER -1) set(PSRAM_INFO ", support for PSRAM") message(STATUS "Support for PSRAM included") else() @@ -786,7 +832,7 @@ macro(nf_add_idf_as_library) message(STATUS "Support for PSRAM **IS NOT** included") endif() - # find out revision info + # find out revision info (ESP32) string(FIND ${SDKCONFIG_DEFAULT_CONTENTS} "CONFIG_ESP32_REV_MIN_0=y" CONFIG_ESP32_REV_MIN_0_POS) string(FIND ${SDKCONFIG_DEFAULT_CONTENTS} "CONFIG_ESP32_REV_MIN_3=y" CONFIG_ESP32_REV_MIN_3_POS) @@ -799,6 +845,29 @@ macro(nf_add_idf_as_library) message(STATUS "Building for chip revision 3") endif() + # find out revision info (ESP32-C3) + unset(ESP32_REVISION) + string(FIND ${SDKCONFIG_DEFAULT_CONTENTS} "CONFIG_ESP32C3_REV_MIN_2=y" CONFIG_ESP32C3_REV_MIN_2_POS) + string(FIND ${SDKCONFIG_DEFAULT_CONTENTS} "CONFIG_ESP32C3_REV_MIN_3=y" CONFIG_ESP32C3_REV_MIN_3_POS) + string(FIND ${SDKCONFIG_DEFAULT_CONTENTS} "CONFIG_ESP32C3_REV_MIN_4=y" CONFIG_ESP32C3_REV_MIN_4_POS) + + # set variable + if(${CONFIG_ESP32C3_REV_MIN_2_POS} GREATER -1) + set(REVISION_INFO ", chip rev. >= 2") + message(STATUS "Building for chip revision >= 2") + set(ESP32_REVISION "2" CACHE STRING "ESP32 revision") + elseif(${CONFIG_ESP32C3_REV_MIN_3_POS} GREATER -1) + set(REVISION_INFO ", chip rev. >= 3") + message(STATUS "Building for chip revision >= 3") + set(ESP32_REVISION "3" CACHE STRING "ESP32 revision") + elseif(${CONFIG_ESP32C3_REV_MIN_4_POS} GREATER -1) + set(REVISION_INFO ", chip rev. 4") + message(STATUS "Building for chip revision 4") + set(ESP32_REVISION "4" CACHE STRING "ESP32 revision") + endif() + + nf_fix_esp32c3_rom_file() + # find out if there is support for BLE string(FIND ${SDKCONFIG_DEFAULT_CONTENTS} "CONFIG_BT_ENABLED=y" CONFIG_BT_ENABLED_POS) diff --git a/CMake/toolchain.riscv32-esp-elf.cmake b/CMake/toolchain.riscv32-esp-elf.cmake index ad0701aa55..0a7cf87da5 100644 --- a/CMake/toolchain.riscv32-esp-elf.cmake +++ b/CMake/toolchain.riscv32-esp-elf.cmake @@ -8,9 +8,6 @@ include(CMakeForceCompiler) # the name of the operating system for which CMake is to build set(CMAKE_SYSTEM_NAME Generic) -# name of the CPU CMake is building for -set(CMAKE_SYSTEM_PROCESSOR riscv32-esp) - # macro to setup compilers macro(nf_set_compiler_var var name) find_program( @@ -47,8 +44,8 @@ find_program( riscv32-esp-elf-size CMAKE_FIND_ROOT_PATH_BOTH) -set(CMAKE_C_FLAGS "-mlongcalls -Wno-frame-address" CACHE STRING "C Compiler Base Flags") -set(CMAKE_CXX_FLAGS "-mlongcalls -Wno-frame-address" CACHE STRING "C++ Compiler Base Flags") +set(CMAKE_C_FLAGS " -march=rv32imc -Wno-frame-address" CACHE STRING "C Compiler Base Flags") +set(CMAKE_CXX_FLAGS " -march=rv32imc -Wno-frame-address" CACHE STRING "C++ Compiler Base Flags") # root paths to search on the filesystem for cross-compiling get_filename_component(CMAKE_FIND_ROOT_PATH ${CMAKE_C_COMPILER} DIRECTORY CACHE) diff --git a/CMakeLists.txt b/CMakeLists.txt index c635ca6c18..9df4e80961 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -855,12 +855,6 @@ elseif(RTOS_ESP32_CHECK) endif() endif() - # need to add this here to keep IDF build system happy - add_executable( - ${NANOCLR_PROJECT_NAME}.elf - ${CMAKE_SOURCE_DIR}/targets/ESP32/_IDF/dummy.c - ) - # add common directory for ESP32 add_subdirectory(${CMAKE_SOURCE_DIR}/targets/ESP32) diff --git a/CMakePresets.json b/CMakePresets.json index 53a793c84c..6ec6cdb8f4 100644 --- a/CMakePresets.json +++ b/CMakePresets.json @@ -96,6 +96,39 @@ "ESP32_SPIRAM_FOR_IDF_ALLOCATION": "256 * 1024" } }, + { + "name": "xtensa-esp32c3-preset", + "description": "Preset for ESP32-C3 series", + "hidden": true, + "cacheVariables": { + "CMAKE_TOOLCHAIN_FILE": { + "type": "FILEPATH", + "value": "${sourceDir}/CMake/toolchain.riscv32-esp-elf.cmake" + }, + "NF_TARGET_HAS_NANOBOOTER": "OFF", + "RTOS": "ESP32", + "TARGET_SERIES": "ESP32_C3", + "TARGET_BOARD": "ESP32_C3", + "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", + "SUPPORT_ANY_BASE_CONVERSION": "ON", + "API_System.Net": "ON", + "API_System.Math": "ON", + "API_System.Device.Adc": "ON", + "API_System.Device.Dac": "OFF", + "API_System.Device.Gpio": "ON", + "API_System.Device.I2c": "ON", + "API_System.Device.I2s": "OFF", + "API_System.Device.Spi": "ON", + "API_System.Device.Pwm": "ON", + "API_System.Device.Wifi": "ON", + "API_System.IO.Ports": "ON", + "API_Hardware.Esp32": "ON", + "API_nanoFramework.Hardware.Esp32.Rmt": "OFF", + "API_nanoFramework.ResourceManager": "ON", + "API_nanoFramework.System.Collections": "ON", + "API_nanoFramework.System.Text": "ON" + } + }, { "name": "ORGPAL_PALTHREE_preset", "inherits": [ @@ -464,6 +497,25 @@ "TOUCHPANEL_INTERFACE": "Spi_To_TouchPanel.cpp" } }, + { + "name": "ESP32_C3_preset", + "inherits": [ + "general-preset", + "xtensa-esp32c3-preset" + ], + "hidden": true, + "cacheVariables": { + "SDK_CONFIG_FILE": "", + "NF_BUILD_RTM": "OFF", + "NF_FEATURE_DEBUGGER": "ON", + "NF_FEATURE_RTC": "ON", + "NF_FEATURE_HAS_SDCARD": "OFF", + "API_System.IO.FileSystem": "ON", + "API_Windows.Storage": "ON", + "API_nanoFramework.Device.OneWire": "OFF", + "ESP32_RESERVED_RAM_FOR_IDF_ALLOCATION": "100" + } + }, { "name": "M5Stack_preset", "inherits": [ @@ -1460,4 +1512,4 @@ } } ] -} +} \ No newline at end of file diff --git a/CMakeUserPresets.TEMPLATE.json b/CMakeUserPresets.TEMPLATE.json index 1fd257d0af..dfb99af981 100644 --- a/CMakeUserPresets.TEMPLATE.json +++ b/CMakeUserPresets.TEMPLATE.json @@ -246,6 +246,31 @@ "NF_INTEROP_ASSEMBLIES": null } }, + { + "name": "ESP32_C3_REV2", + "inherits": [ + "user-local-tools", + "user-prefs", + "ESP32_C3_preset" + ], + "cacheVariables": { + "TARGET_NAME": "${presetName}", + "NF_INTEROP_ASSEMBLIES": null + } + }, + { + "name": "ESP32_C3_REV3", + "inherits": [ + "user-local-tools", + "user-prefs", + "ESP32_C3_preset" + ], + "cacheVariables": { + "TARGET_NAME": "${presetName}", + "SDK_CONFIG_FILE": "sdkconfig.default_rev3.esp32c3", + "NF_INTEROP_ASSEMBLIES": null + } + }, { "name": "M5Stack", "inherits": [ @@ -772,6 +797,16 @@ "displayName": "ESP_WROVER_KIT", "configurePreset": "ESP_WROVER_KIT" }, + { + "name": "ESP32_C3_REV2", + "displayName": "ESP32_C3_REV2", + "configurePreset": "ESP32_C3_REV2" + }, + { + "name": "ESP32_C3_REV3", + "displayName": "ESP32_C3_REV3", + "configurePreset": "ESP32_C3_REV3" + }, { "name": "M5Stack", "displayName": "M5Stack", @@ -958,4 +993,4 @@ "configurePreset": "TI_CC1352P1_LAUNCHXL" } ] -} +} \ No newline at end of file diff --git a/README.md b/README.md index bba989d165..46dc6fc247 100644 --- a/README.md +++ b/README.md @@ -39,6 +39,8 @@ We also have a [Community Targets](https://github.com/nanoframework/nf-Community | ESP32_LILYGO | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images/raw/ESP32_LILYGO/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images/packages/detail/raw/ESP32_LILYGO/latest/) | | FEATHER_S2 | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images/raw/FEATHER_S2/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images/packages/detail/raw/FEATHER_S2/latest/) | | KALUGA_1 | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images/raw/KALUGA_1/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images/packages/detail/raw/KALUGA_1/latest/) | +| ESP32_C3_REV2 | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images/raw/ESP32_C3_REV2/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images/packages/detail/raw/ESP32_C3_REV2/latest/) | +| ESP32_C3_REV3 | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images/raw/ESP32_C3_REV3/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images/packages/detail/raw/ESP32_C3_REV3/latest/) | | ESP32_OLIMEX | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images/raw/ESP32_OLIMEX/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images/packages/detail/raw/ESP32_OLIMEX/latest/) | ### M5Stack @@ -92,6 +94,7 @@ The above .NET nanoFramework interpreter builds include support for the class li | ESP32_LILYGO | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: Wi-Fi + Ethernet | | | | | FEATHER_S2 | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | | | | | KALUGA_1 | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | | | :heavy_check_mark: | + | ESP32_C3 | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | | | | | ESP32_OLIMEX | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: Wi-Fi + Ethernet | | :heavy_check_mark: | | | M5Core | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: Wi-Fi | | :heavy_check_mark: | | | M5StickC | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: Wi-Fi | | :heavy_check_mark: | | diff --git a/README.zh-cn.md b/README.zh-cn.md index 0e309e2590..13f4c4cf15 100644 --- a/README.zh-cn.md +++ b/README.zh-cn.md @@ -38,6 +38,8 @@ | ESP32_LILYGO | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images/raw/ESP32_LILYGO/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images/packages/detail/raw/ESP32_LILYGO/latest/) | | FEATHER_S2 | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images/raw/FEATHER_S2/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images/packages/detail/raw/FEATHER_S2/latest/) | | KALUGA_1 | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images/raw/KALUGA_1/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images/packages/detail/raw/KALUGA_1/latest/) | +| ESP32_C3_REV2 | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images/raw/ESP32_C3_REV2/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images/packages/detail/raw/ESP32_C3_REV2/latest/) | +| ESP32_C3_REV3 | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images/raw/ESP32_C3_REV3/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images/packages/detail/raw/ESP32_C3_REV3/latest/) | | ESP32_OLIMEX | [![Latest Version @ Cloudsmith](https://api-prd.cloudsmith.io/v1/badges/version/net-nanoframework/nanoframework-images/raw/ESP32_OLIMEX/latest/x/?render=true)](https://cloudsmith.io/~net-nanoframework/repos/nanoframework-images/packages/detail/raw/ESP32_OLIMEX/latest/) | ### M5Stack @@ -91,6 +93,7 @@ | ESP32_LILYGO | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: Wi-Fi + Ethernet | | | | | FEATHER_S2 | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | | | | | KALUGA_1 | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | | | :heavy_check_mark: | + | ESP32_C3 | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | | | | | ESP32_OLIMEX | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: Wi-Fi + Ethernet | | :heavy_check_mark: | | | M5Core | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: Wi-Fi | | :heavy_check_mark: | | | M5StickC | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: Wi-Fi | | :heavy_check_mark: | | diff --git a/azure-pipelines-nightly.yml b/azure-pipelines-nightly.yml index 9f1c802ea1..e17bc0b952 100644 --- a/azure-pipelines-nightly.yml +++ b/azure-pipelines-nightly.yml @@ -414,6 +414,14 @@ jobs: TargetName: M5Core2 PackageName: M5Core2 + ESP32_C3_REV3: + TargetBoard: ESP32_C3 + TargetSeries: 'esp32c3' + BuildOptions: + IDF_Target: esp32c3 + TargetName: ESP32_C3_REV3 + PackageName: ESP32_C3_REV3 + variables: DOTNET_NOLOGO: true # creates a counter and assigns it to the revision variable diff --git a/azure-pipelines-templates/build-espressif-esp32-targets.yml b/azure-pipelines-templates/build-espressif-esp32-targets.yml index b31e957f59..063442e407 100644 --- a/azure-pipelines-templates/build-espressif-esp32-targets.yml +++ b/azure-pipelines-templates/build-espressif-esp32-targets.yml @@ -31,15 +31,29 @@ steps: # because of permission issues (the python script isn't allowed to write on the output folder) # we need to perform these steps by calling directly the python scripts + + # 16MB partition table it's generated for ESP32 and ESP32_S2 only - task: PythonScript@0 - condition: succeeded() + condition: >- + and( + succeeded(), + ne(variables['TargetSeries'], 'esp32c3') + ) displayName: Generate ESP32 Partition tables for 16MB flash inputs: scriptSource: 'filePath' scriptPath: '$(IDF_PATH)\components\partition_table\gen_esp32part.py' arguments: '--verify ${{ parameters.partitionsDirectory }}\partitions_nanoclr_16mb.csv ${{ parameters.repoDirectory }}\build\partitions_16mb.bin' + - task: PythonScript@0 - condition: succeeded() + condition: >- + and( + succeeded(), + or( + eq(variables['TargetSeries'], 'esp32'), + eq(variables['TargetSeries'], 'esp32s2') + ) + ) displayName: Generate ESP32 Partition tables for 8MB flash inputs: scriptSource: 'filePath' @@ -53,3 +67,18 @@ steps: scriptSource: 'filePath' scriptPath: '$(IDF_PATH)\components\partition_table\gen_esp32part.py' arguments: '--verify ${{ parameters.partitionsDirectory }}\partitions_nanoclr_4mb.csv ${{ parameters.repoDirectory }}\build\partitions_4mb.bin' + + - task: PythonScript@0 + condition: >- + and( + succeeded(), + or( + eq(variables['TargetSeries'], 'esp32'), + eq(variables['TargetSeries'], 'esp32c3') + ) + ) + displayName: Generate ESP32 Partition tables for 2MB flash + inputs: + scriptSource: 'filePath' + scriptPath: '$(IDF_PATH)\components\partition_table\gen_esp32part.py' + arguments: '--verify ${{ parameters.partitionsDirectory }}\partitions_nanoclr_2mb.csv ${{ parameters.repoDirectory }}\build\partitions_2mb.bin' diff --git a/azure-pipelines.yml b/azure-pipelines.yml index 8ee0c381e8..3f0419717c 100644 --- a/azure-pipelines.yml +++ b/azure-pipelines.yml @@ -424,6 +424,14 @@ jobs: TargetName: FEATHER_S2 PackageName: FEATHER_S2 + ESP32_C3_REV2: + TargetBoard: ESP32_C3 + TargetSeries: 'esp32c3' + BuildOptions: + IDF_Target: esp32c3 + TargetName: ESP32_C3_REV2 + PackageName: ESP32_C3_REV2 + variables: DOTNET_NOLOGO: true # creates a counter and assigns it to the revision variable diff --git a/bootloader_components/nf_boot_message/CMakeLists.txt b/bootloader_components/nf_boot_message/CMakeLists.txt index beed854475..4f42ed9cee 100644 --- a/bootloader_components/nf_boot_message/CMakeLists.txt +++ b/bootloader_components/nf_boot_message/CMakeLists.txt @@ -8,4 +8,7 @@ idf_component_register( INCLUDE_DIRS ${CMAKE_BINARY_DIR}/../targets/ESP32 ) -target_link_libraries(${COMPONENT_LIB} INTERFACE "-Wl,--wrap=bootloader_print_banner") +target_link_libraries(${COMPONENT_LIB} INTERFACE "-Wl,--whole-archive" + $ + "-Wl,--no-whole-archive" + "-Wl,--wrap=bootloader_print_banner") diff --git a/bootloader_components/nf_boot_message/boot_msg.c b/bootloader_components/nf_boot_message/boot_msg.c index 51cd9809c3..6f8eb19083 100644 --- a/bootloader_components/nf_boot_message/boot_msg.c +++ b/bootloader_components/nf_boot_message/boot_msg.c @@ -14,9 +14,3 @@ void __wrap_bootloader_print_banner(void) ESP_LOGI(TAG, ".NET nanoFramework 2nd stage bootloader ESP-IDF %s", IDF_VER_FIXED); ESP_LOGI(TAG, "build " __DATE__ " " __TIME__); } - -// need to have a main(), otherwise this won't make it into the final binary -int main(void) -{ - return 0; -} diff --git a/targets/ESP32/CMakeLists.txt b/targets/ESP32/CMakeLists.txt index 25e90e0454..e7ed034807 100644 --- a/targets/ESP32/CMakeLists.txt +++ b/targets/ESP32/CMakeLists.txt @@ -9,6 +9,11 @@ include(binutils.ESP32) # Set target series in lower case nf_set_esp32_target_series() +# checking unsupported features +if(${TARGET_SERIES_SHORT} STREQUAL "esp32c3" AND ${API_nanoFramework.Hardware.Esp32.Rmt}) + message(FATAL_ERROR "Currently RMT is not supported for ESP32-C3 builds") +endif() + # option to reserve RAM for IDF allocator option(ESP32_RESERVED_RAM_FOR_IDF_ALLOCATION "Reserved RAM for IDF allocation (in kBytes)") diff --git a/targets/ESP32/ESP32_C3/CMakeLists.txt b/targets/ESP32/ESP32_C3/CMakeLists.txt new file mode 100644 index 0000000000..2bffbbbc64 --- /dev/null +++ b/targets/ESP32/ESP32_C3/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# + +include(binutils.ESP32) + +############################## + +nf_setup_target_build() diff --git a/targets/ESP32/ESP32_C3/common/CMakeLists.txt b/targets/ESP32/ESP32_C3/common/CMakeLists.txt new file mode 100644 index 0000000000..0aa4fd139b --- /dev/null +++ b/targets/ESP32/ESP32_C3/common/CMakeLists.txt @@ -0,0 +1,4 @@ +# +# Copyright (c) .NET Foundation and Contributors +# See LICENSE file in the project root for full license information. +# diff --git a/targets/ESP32/ESP32_C3/ffconf.h b/targets/ESP32/ESP32_C3/ffconf.h new file mode 100644 index 0000000000..0dbd625ead --- /dev/null +++ b/targets/ESP32/ESP32_C3/ffconf.h @@ -0,0 +1,342 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) 2018, ChaN, all right reserved. +// See LICENSE file in the project root for full license information. +// + +// clang-format off + +#include +#include +#include + +#if (HAL_USE_SDC != TRUE) +// need this include here when not using SDCARD so it can load the one from IDF +#include +#endif + +/*---------------------------------------------------------------------------/ +/ FatFs Functional Configurations +/---------------------------------------------------------------------------*/ + +#define FFCONF_DEF 86604 /* Revision ID */ + +/*---------------------------------------------------------------------------/ +/ Function Configurations +/---------------------------------------------------------------------------*/ + +#define FF_FS_READONLY 0 +/* This option switches read-only configuration. (0:Read/Write or 1:Read-only) +/ Read-only configuration removes writing API functions, f_write(), f_sync(), +/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree() +/ and optional writing functions as well. */ + + +#define FF_FS_MINIMIZE 0 +/* This option defines minimization level to remove some basic API functions. +/ +/ 0: Basic functions are fully enabled. +/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename() +/ are removed. +/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1. +/ 3: f_lseek() function is removed in addition to 2. */ + + +#define FF_USE_STRFUNC 0 +/* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf(). +/ +/ 0: Disable string functions. +/ 1: Enable without LF-CRLF conversion. +/ 2: Enable with LF-CRLF conversion. */ + + +#define FF_USE_FIND 1 +/* This option switches filtered directory read functions, f_findfirst() and +/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */ + + +#define FF_USE_MKFS 1 +/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */ + + +#define FF_USE_FASTSEEK CONFIG_FATFS_USE_FASTSEEK +/* This option switches fast seek function. (0:Disable or 1:Enable) */ + + +#define FF_USE_EXPAND 0 +/* This option switches f_expand function. (0:Disable or 1:Enable) */ + + +#define FF_USE_CHMOD 1 +/* This option switches attribute manipulation functions, f_chmod() and f_utime(). +/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */ + + +#define FF_USE_LABEL 0 +/* This option switches volume label functions, f_getlabel() and f_setlabel(). +/ (0:Disable or 1:Enable) */ + + +#define FF_USE_FORWARD 0 +/* This option switches f_forward() function. (0:Disable or 1:Enable) */ + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/---------------------------------------------------------------------------*/ + +#define FF_CODE_PAGE CONFIG_FATFS_CODEPAGE +/* This option specifies the OEM code page to be used on the target system. +/ Incorrect code page setting can cause a file open failure. +/ +/ 437 - U.S. +/ 720 - Arabic +/ 737 - Greek +/ 771 - KBL +/ 775 - Baltic +/ 850 - Latin 1 +/ 852 - Latin 2 +/ 855 - Cyrillic +/ 857 - Turkish +/ 860 - Portuguese +/ 861 - Icelandic +/ 862 - Hebrew +/ 863 - Canadian French +/ 864 - Arabic +/ 865 - Nordic +/ 866 - Russian +/ 869 - Greek 2 +/ 932 - Japanese (DBCS) +/ 936 - Simplified Chinese (DBCS) +/ 949 - Korean (DBCS) +/ 950 - Traditional Chinese (DBCS) +/ 0 - Include all code pages above and configured by f_setcp() +*/ + + +#if defined(CONFIG_FATFS_LFN_STACK) +#define FF_USE_LFN 2 +#elif defined(CONFIG_FATFS_LFN_HEAP) +#define FF_USE_LFN 3 +#else /* CONFIG_FATFS_LFN_NONE */ +#define FF_USE_LFN 0 +#endif + +#ifdef CONFIG_FATFS_MAX_LFN +#define FF_MAX_LFN CONFIG_FATFS_MAX_LFN +#endif + +/* The FF_USE_LFN switches the support for LFN (long file name). +/ +/ 0: Disable LFN. FF_MAX_LFN has no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ To enable the LFN, ffunicode.c needs to be added to the project. The LFN function +/ requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and +/ additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled. +/ The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can +/ be in range of 12 to 255. It is recommended to be set 255 to fully support LFN +/ specification. +/ When use stack for the working buffer, take care on stack overflow. When use heap +/ memory for the working buffer, memory management functions, ff_memalloc() and +/ ff_memfree() in ffsystem.c, need to be added to the project. */ + + +#ifdef CONFIG_FATFS_API_ENCODING_UTF_8 +#define FF_LFN_UNICODE 2 +#elif defined(CONFIG_FATFS_API_ENCODING_UTF_16) +#define FF_LFN_UNICODE 1 +#else /* CONFIG_FATFS_API_ENCODING_ANSI_OEM */ +#define FF_LFN_UNICODE 0 +#endif +/* This option switches the character encoding on the API when LFN is enabled. +/ +/ 0: ANSI/OEM in current CP (TCHAR = char) +/ 1: Unicode in UTF-16 (TCHAR = WCHAR) +/ 2: Unicode in UTF-8 (TCHAR = char) +/ 3: Unicode in UTF-32 (TCHAR = DWORD) +/ +/ Also behavior of string I/O functions will be affected by this option. +/ When LFN is not enabled, this option has no effect. */ + + +#define FF_LFN_BUF 255 +#define FF_SFN_BUF 12 +/* This set of options defines size of file name members in the FILINFO structure +/ which is used to read out directory items. These values should be suffcient for +/ the file names to read. The maximum possible length of the read file name depends +/ on character encoding. When LFN is not enabled, these options have no effect. */ + + +#define FF_STRF_ENCODE 3 +/* When FF_LFN_UNICODE >= 1 with LFN enabled, string I/O functions, f_gets(), +/ f_putc(), f_puts and f_printf() convert the character encoding in it. +/ This option selects assumption of character encoding ON THE FILE to be +/ read/written via those functions. +/ +/ 0: ANSI/OEM in current CP +/ 1: Unicode in UTF-16LE +/ 2: Unicode in UTF-16BE +/ 3: Unicode in UTF-8 +*/ + + +#define FF_FS_RPATH 2 +/* This option configures support for relative path. +/ +/ 0: Disable relative path and remove related functions. +/ 1: Enable relative path. f_chdir() and f_chdrive() are available. +/ 2: f_getcwd() function is available in addition to 1. +*/ + + +/*---------------------------------------------------------------------------/ +/ Drive/Volume Configurations +/---------------------------------------------------------------------------*/ + +#define FF_VOLUMES 3 +/* Number of volumes (logical drives) to be used. (1-10) */ + + +#define FF_STR_VOLUME_ID 1 +#define FF_VOLUME_STRS "D", "E", "F" +/* FF_STR_VOLUME_ID switches support for volume ID in arbitrary strings. +/ When FF_STR_VOLUME_ID is set to 1 or 2, arbitrary strings can be used as drive +/ number in the path name. FF_VOLUME_STRS defines the volume ID strings for each +/ logical drives. Number of items must not be less than FF_VOLUMES. Valid +/ characters for the volume ID strings are A-Z, a-z and 0-9, however, they are +/ compared in case-insensitive. If FF_STR_VOLUME_ID >= 1 and FF_VOLUME_STRS is +/ not defined, a user defined volume string table needs to be defined as: +/ +/ const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb",... +*/ + + +#define FF_MULTI_PARTITION 1 +/* This option switches support for multiple volumes on the physical drive. +/ By default (0), each logical drive number is bound to the same physical drive +/ number and only an FAT volume found on the physical drive will be mounted. +/ When this function is enabled (1), each logical drive number can be bound to +/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk() +/ funciton will be available. */ + +/* SD card sector size */ +#define FF_SS_SDCARD 512 +/* wear_levelling library sector size */ +#define FF_SS_WL CONFIG_WL_SECTOR_SIZE + +#define FF_MIN_SS MIN(FF_SS_SDCARD, FF_SS_WL) +#define FF_MAX_SS MAX(FF_SS_SDCARD, FF_SS_WL) +/* This set of options configures the range of sector size to be supported. (512, +/ 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and +/ harddisk. But a larger value may be required for on-board flash memory and some +/ type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured +/ for variable sector size mode and disk_ioctl() function needs to implement +/ GET_SECTOR_SIZE command. */ + + +#define FF_USE_TRIM 0 +/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable) +/ To enable Trim function, also CTRL_TRIM command should be implemented to the +/ disk_ioctl() function. */ + + +#define FF_FS_NOFSINFO 0 +/* If you need to know correct free space on the FAT32 volume, set bit 0 of this +/ option, and f_getfree() function at first time after volume mount will force +/ a full FAT scan. Bit 1 controls the use of last allocated cluster number. +/ +/ bit0=0: Use free cluster count in the FSINFO if available. +/ bit0=1: Do not trust free cluster count in the FSINFO. +/ bit1=0: Use last allocated cluster number in the FSINFO if available. +/ bit1=1: Do not trust last allocated cluster number in the FSINFO. +*/ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/---------------------------------------------------------------------------*/ + +#define FF_FS_TINY (!CONFIG_FATFS_PER_FILE_CACHE) +/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny) +/ At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes. +/ Instead of private sector buffer eliminated from the file object, common sector +/ buffer in the filesystem object (FATFS) is used for the file data transfer. */ + + +#define FF_FS_EXFAT 0 +/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable) +/ To enable exFAT, also LFN needs to be enabled. (FF_USE_LFN >= 1) +/ Note that enabling exFAT discards ANSI C (C89) compatibility. */ + + +#define FF_FS_NORTC 0 +#define FF_NORTC_MON 1 +#define FF_NORTC_MDAY 1 +#define FF_NORTC_YEAR 2018 +/* The option FF_FS_NORTC switches timestamp functiton. If the system does not have +/ any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable +/ the timestamp function. Every object modified by FatFs will have a fixed timestamp +/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time. +/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be +/ added to the project to read current time form real-time clock. FF_NORTC_MON, +/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect. +/ These options have no effect at read-only configuration (FF_FS_READONLY = 1). */ + + +#define FF_FS_LOCK CONFIG_FATFS_FS_LOCK +/* The option FF_FS_LOCK switches file lock function to control duplicated file open +/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY +/ is 1. +/ +/ 0: Disable file lock function. To avoid volume corruption, application program +/ should avoid illegal open, remove and rename to the open objects. +/ >0: Enable file lock function. The value defines how many files/sub-directories +/ can be opened simultaneously under file lock control. Note that the file +/ lock control is independent of re-entrancy. */ + + +#define FF_FS_REENTRANT 1 +#define FF_FS_TIMEOUT (CONFIG_FATFS_TIMEOUT_MS / portTICK_PERIOD_MS) +#define FF_SYNC_t SemaphoreHandle_t +/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs +/ module itself. Note that regardless of this option, file access to different +/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs() +/ and f_fdisk() function, are always not re-entrant. Only file/directory access +/ to the same volume is under control of this function. +/ +/ 0: Disable re-entrancy. FF_FS_TIMEOUT and FF_SYNC_t have no effect. +/ 1: Enable re-entrancy. Also user provided synchronization handlers, +/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj() +/ function, must be added to the project. Samples are available in +/ option/syscall.c. +/ +/ The FF_FS_TIMEOUT defines timeout period in unit of time tick. +/ The FF_SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*, +/ SemaphoreHandle_t and etc. A header file for O/S definitions needs to be +/ included somewhere in the scope of ff.h. */ + +#include +#include "freertos/FreeRTOS.h" +#include "freertos/semphr.h" + +/* Some memory allocation functions are declared here in addition to ff.h, so that + they can be used also by external code when LFN feature is disabled. + */ +void* ff_memalloc (unsigned msize); +void ff_memfree(void*); + + +/*--- End of configuration options ---*/ + +/* Redefine names of disk IO functions to prevent name collisions */ +#define disk_initialize ff_disk_initialize +#define disk_status ff_disk_status +#define disk_read ff_disk_read +#define disk_write ff_disk_write +#define disk_ioctl ff_disk_ioctl + +// clang-format on diff --git a/targets/ESP32/ESP32_C3/nanoCLR/System.Device.Pwm/sys_dev_pwm_native_System_Device_Pwm_PwmChannel.cpp b/targets/ESP32/ESP32_C3/nanoCLR/System.Device.Pwm/sys_dev_pwm_native_System_Device_Pwm_PwmChannel.cpp new file mode 100644 index 0000000000..1ac27069fa --- /dev/null +++ b/targets/ESP32/ESP32_C3/nanoCLR/System.Device.Pwm/sys_dev_pwm_native_System_Device_Pwm_PwmChannel.cpp @@ -0,0 +1,415 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include "sys_dev_pwm_native.h" +#include +#include "Esp32_DeviceMapping.h" + +// Used to map a PWM channel number to a pin number for High and low speed channels +static char HighSpeedPinMap[8] = {255, 255, 255, 255, 255, 255, 255, 255}; +static char LowSpeedPinMap[8] = {255, 255, 255, 255, 255, 255, 255, 255}; +// Pin functions from PWM1 to PWM16 +static int PwmMapping[16] = { + 262400, + 262656, + 262912, + 263168, + 263424, + 263680, + 263936, + 264192, + 264448, + 264704, + 264960, + 265216, + 265472, + 265728, + 265984, + 266240}; + +#define GetSpeedMode(timer) (ledc_mode_t)((timer > 3) ? LEDC_LOW_SPEED_MODE : LEDC_HIGH_SPEED_MODE) +#define IDF_ERROR(result) \ + if (result != ESP_OK) \ + { \ + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); \ + } + +namespace sys_dev_pwm_native_System_Device_Pwm_PwmChannelHelpers +{ +uint32_t PwmController_Timer_resolution[8]; + +int GetChannel(int pin, int timerId, bool create); +uint32_t CalculateDuty(int timerId, uint32_t dutyCycle, PwmPulsePolarity polarity); +HRESULT ConfigureAndStart(CLR_RT_HeapBlock *pThis, bool create, bool noStart); +} // namespace sys_dev_pwm_native_System_Device_Pwm_PwmChannelHelpers + +using namespace sys_dev_pwm_native_System_Device_Pwm_PwmChannelHelpers; + +// +// Look up Pin number to find channel, if create true and not present then add pin +// return channel number or -1 if error +// +int sys_dev_pwm_native_System_Device_Pwm_PwmChannelHelpers::GetChannel(int pin, int timerId, bool create) +{ + int channel = -1; // Return if not found + + // Select map depending if high or low speed timers + char *pMap = (timerId > 3) ? LowSpeedPinMap : HighSpeedPinMap; + char *pMap2 = pMap; + + // look for pin in map + for (int index = 0; index < 8; index++, pMap++) + { + if (*pMap == pin) + { + channel = index; + break; + } + } + + if (create && channel == -1) + { + // if pin/channel not found then allocate one + for (int index = 0; index < 8; index++, pMap2++) + { + if (*pMap2 == 255) + { + channel = index; + *pMap2 = pin; + break; + } + } + } + + return channel; +} + +// +// Work out the duty Cycle for the current duty resolution and polarity +// +uint32_t sys_dev_pwm_native_System_Device_Pwm_PwmChannelHelpers::CalculateDuty( + int timerId, + uint32_t dutyCycle, + PwmPulsePolarity polarity) +{ + // if polarity Active low then reverse duty cycle + if (polarity == PwmPulsePolarity::PwmPulsePolarity_ActiveLow) + { + dutyCycle = 10000 - dutyCycle; + } + + // Return a duty cycle in the range of the current timer duty resolution + uint32_t calculatedDuty = PwmController_Timer_resolution[timerId] * dutyCycle / 10000; + return calculatedDuty; +} + +HRESULT sys_dev_pwm_native_System_Device_Pwm_PwmChannelHelpers::ConfigureAndStart( + CLR_RT_HeapBlock *pThis, + bool create, + bool noStart) +{ + int32_t timerId; + int32_t pinNumber; + uint32_t dutyCycle; + + PwmPulsePolarity polarity; + + ledc_mode_t mode; + ledc_channel_t channel; + ledc_timer_t timer_sel; + ledc_channel_config_t ledc_conf; + + NANOCLR_HEADER(); + + // Retrieves the needed parameters from private class properties or method parameters + timerId = pThis[Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::FIELD___pwmTimer].NumericByRef().s4; + pinNumber = pThis[Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::FIELD___pinNumber].NumericByRef().s4; + dutyCycle = pThis[Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::FIELD___dutyCycle].NumericByRef().u4; + polarity = (PwmPulsePolarity)(pThis[Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::FIELD___polarity] + .NumericByRef() + .u4); + + // Configure channel + mode = GetSpeedMode(timerId); + channel = (ledc_channel_t)GetChannel(pinNumber, timerId, create); + + if (channel == -1) + { + // Unable to create a new channel, all channels used up ? + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + } + + timer_sel = (ledc_timer_t)(timerId & 0x03); + + // Work out the duty Cycle for the current duty resolution + dutyCycle = CalculateDuty(timerId, dutyCycle, polarity); + + ledc_conf = {pinNumber, mode, channel, LEDC_INTR_DISABLE, timer_sel, dutyCycle, 0}; + + // Configure Channel which will also start it + IDF_ERROR(ledc_channel_config(&ledc_conf)); + + // Because it is started from the configure we optionally stop it and set idle level based on polarity + if (noStart) + { + ledc_stop(mode, channel, polarity); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::NativeInit___VOID(CLR_RT_StackFrame &stack) +{ + int32_t pinNumber; + + NANOCLR_HEADER(); + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // Check pin number is a valid for output + pinNumber = pThis[FIELD___pinNumber].NumericByRef().s4; + + if (!GPIO_IS_VALID_OUTPUT_GPIO(pinNumber)) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // Create a new entry in channel table and configure channel which will also start channel + NANOCLR_CHECK_HRESULT(ConfigureAndStart(pThis, true, true)); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::NativeSetDesiredFrequency___VOID__I4( + CLR_RT_StackFrame &stack) +{ + int32_t timerId; + int32_t desiredFrequency; + int32_t optimumDutyResolution; + uint32_t precision; + uint64_t divParam; + esp_err_t result; + + ledc_timer_t timer; + ledc_mode_t mode; + ledc_timer_bit_t duty_res; + ledc_timer_config_t timer_conf; + + NANOCLR_HEADER(); + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties ( 0 - 7 ) + timerId = pThis[FIELD___pwmTimer].NumericByRef().s4; + desiredFrequency = stack.Arg1().NumericByRef().s4; + + // parameter check + if (desiredFrequency < 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + timer = (ledc_timer_t)(timerId & 0x03); + mode = (timerId <= 4) ? LEDC_HIGH_SPEED_MODE : LEDC_LOW_SPEED_MODE; + + // Work out the optimal duty resolution based on current frequency, default to 1 if not found + // Working from 15 bit duty resolution down until we have a valid divisor + optimumDutyResolution = 1; + + for (int dutyResolution = 15; dutyResolution > 0; dutyResolution--) + { + precision = (0x1 << dutyResolution); // 2**depth + + divParam = ((uint64_t)LEDC_APB_CLK_HZ << 8) / desiredFrequency / precision; + + if (divParam > 256) + { + optimumDutyResolution = dutyResolution; + break; + } + } + + duty_res = (ledc_timer_bit_t)optimumDutyResolution; + + // Save resolution for working out values for percent duty cycle + PwmController_Timer_resolution[timerId] = (0x1 << optimumDutyResolution); + + timer_conf = {mode, duty_res, timer, (uint32_t)desiredFrequency, LEDC_AUTO_CLK}; + + result = ledc_timer_config(&timer_conf); + if (result != ESP_OK) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // store the frequency + pThis[FIELD___frequency].NumericByRef().s4 = desiredFrequency; + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::NativeSetActiveDutyCyclePercentage___VOID__R8( + CLR_RT_StackFrame &stack) +{ + int32_t timerId; + int32_t pinNumber; + uint32_t dutyCycle; + + ledc_channel_t channel; + + PwmPulsePolarity polarity; + ledc_mode_t speed_mode; + + NANOCLR_HEADER(); + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties or method parameters + timerId = pThis[FIELD___pwmTimer].NumericByRef().s4; + pinNumber = pThis[FIELD___pinNumber].NumericByRef().s4; + polarity = (PwmPulsePolarity)(pThis[FIELD___polarity].NumericByRef().u4); + + // parameter check + if (stack.Arg1().NumericByRef().r8 < 0 || stack.Arg1().NumericByRef().r8 > 1.0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // retrieve percentage as 0 to 10000 (0% to 100%) + dutyCycle = (uint32_t)(stack.Arg1().NumericByRef().r8 * CONST_DutyCycleFactor); + + // Get channel number used for this pinNumber + // FIXME check result + channel = (ledc_channel_t)GetChannel(pinNumber, timerId, false); + + // Get speed mode based on Timer used + speed_mode = GetSpeedMode(timerId); + + // Work out the duty Cycle for the current duty resolution + dutyCycle = CalculateDuty(timerId, dutyCycle, polarity); + + // Update duty on channel + IDF_ERROR(ledc_set_duty(speed_mode, channel, dutyCycle)); + + // Activate duty on channel + IDF_ERROR(ledc_update_duty(speed_mode, channel)); + + // store the new duty cycle + pThis[FIELD___dutyCycle].NumericByRef().u4 = dutyCycle; + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::NativeStart___VOID(CLR_RT_StackFrame &stack) +{ + NANOCLR_HEADER(); + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // Call configure to start PWM channel + NANOCLR_CHECK_HRESULT(ConfigureAndStart(pThis, false, false)); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::NativeStop___VOID(CLR_RT_StackFrame &stack) +{ + int32_t timerId; + int32_t pinNumber; + int32_t polarity; + + ledc_mode_t speed_mode; + ledc_channel_t channel; + + NANOCLR_HEADER(); + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties or method parameters + timerId = pThis[FIELD___pwmTimer].NumericByRef().s4; + pinNumber = pThis[FIELD___pinNumber].NumericByRef().s4; + polarity = pThis[FIELD___polarity].NumericByRef().s4; + + speed_mode = GetSpeedMode(timerId); + + // FIX ME check result + channel = (ledc_channel_t)GetChannel(pinNumber, timerId, false); + + ledc_stop(speed_mode, channel, (uint32_t)polarity); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::DisposeNative___VOID(CLR_RT_StackFrame &stack) +{ + int32_t timerId; + int32_t pinNumber; + char *pMap; + + NANOCLR_HEADER(); + + CLR_RT_HeapBlock *pThis = stack.This(); + FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties or method parameters + timerId = pThis[FIELD___pwmTimer].NumericByRef().s4; + pinNumber = pThis[FIELD___pinNumber].NumericByRef().s4; + + // Remove pin from pin/channel Map + pMap = (timerId > 3) ? LowSpeedPinMap : HighSpeedPinMap; + + for (int index = 0; index < 8; index++, pMap++) + { + if (*pMap == pinNumber) + { + *pMap = 255; + break; + } + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_pwm_native_System_Device_Pwm_PwmChannel::GetChannel___STATIC__I4__I4__I4( + CLR_RT_StackFrame &stack) +{ + int32_t pinSetup; + + NANOCLR_HEADER(); + + int pin = stack.Arg0().NumericByRef().s4; + int timerId = stack.Arg1().NumericByRef().s4; + int pwm = 0; + + // Check if the combination is ok and set the result + for (pwm = timerId * 2; pwm < timerId * 2 + 2; pwm++) + { + pinSetup = (int32_t)Esp32_GetMappedDevicePinsWithFunction(PwmMapping[pwm]); + + if (pinSetup == pin) + { + // The channel is actually the pin number + stack.SetResult_I4(pin); + break; + } + } + + if (pwm == timerId * 2 + 2) + { + stack.SetResult_I4(-1); + } + + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/targets/ESP32/ESP32_C3/nanoCLR/nanoHAL.cpp b/targets/ESP32/ESP32_C3/nanoCLR/nanoHAL.cpp new file mode 100644 index 0000000000..e754dd5f80 --- /dev/null +++ b/targets/ESP32/ESP32_C3/nanoCLR/nanoHAL.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/targets/ESP32/ESP32_C3/nanoCLR/target_board.h.in b/targets/ESP32/ESP32_C3/nanoCLR/target_board.h.in new file mode 100644 index 0000000000..4d14660a1b --- /dev/null +++ b/targets/ESP32/ESP32_C3/nanoCLR/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef TARGET_BOARD_NANOCLR_H +#define TARGET_BOARD_NANOCLR_H + +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @TARGET_BOARD@ built with ESP-IDF @IDF_VER@" + +#endif // TARGET_BOARD_NANOCLR_H diff --git a/targets/ESP32/ESP32_C3/target_BlockStorage.c b/targets/ESP32/ESP32_C3/target_BlockStorage.c new file mode 100644 index 0000000000..708823cdb7 --- /dev/null +++ b/targets/ESP32/ESP32_C3/target_BlockStorage.c @@ -0,0 +1,23 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice ESP32Flash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + // add device AND request initialization + // required to setup flash partitions memory mapping + BlockStorageList_AddDevice( + (BlockStorageDevice *)&Device_BlockStorage, + &ESP32Flash_BlockStorageInterface, + &Device_BlockStorageConfig, + true); +} diff --git a/targets/ESP32/ESP32_C3/target_BlockStorage.h b/targets/ESP32/ESP32_C3/target_BlockStorage.h new file mode 100644 index 0000000000..658820a8f3 --- /dev/null +++ b/targets/ESP32/ESP32_C3/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef TARGETPAL_BLOCKSTORAGE_H +#define TARGETPAL_BLOCKSTORAGE_H + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif // TARGETPAL_BLOCKSTORAGE_H diff --git a/targets/ESP32/ESP32_C3/target_common.c b/targets/ESP32/ESP32_C3/target_common.c new file mode 100644 index 0000000000..0ca5bb663b --- /dev/null +++ b/targets/ESP32/ESP32_C3/target_common.c @@ -0,0 +1,29 @@ +// +// Copyright (c) .NET Foundation and Contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include "target_common.h" + +#include + +HAL_SYSTEM_CONFIG HalSystemConfig = { + {true}, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, // ConvertCOM_DebugHandle(1), + 0, // ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + {RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size}, + {FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size}}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; + +void FixUpHalSystemConfig() +{ + HalSystemConfig.FLASH1.Size = g_rom_flashchip.chip_size; +} diff --git a/targets/ESP32/ESP32_C3/target_common.h.in b/targets/ESP32/ESP32_C3/target_common.h.in new file mode 100644 index 0000000000..6794119b58 --- /dev/null +++ b/targets/ESP32/ESP32_C3/target_common.h.in @@ -0,0 +1,49 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef TARGET_COMMON_H +#define TARGET_COMMON_H + +#include + +/////////////////////////////////////////////////////////////////////// +// RAM start address and size is filled @ HeapLocation() during boot // +/////////////////////////////////////////////////////////////////////// + +// RAM base address +#define RAM1_MEMORY_StartAddress (0x0) +// RAM size +#define RAM1_MEMORY_Size (0x0) + +///////////////////////////////////////////////////////////////////////////////// +// FLASH start address and size is filled @ FixUpHalSystemConfig() during boot // +///////////////////////////////////////////////////////////////////////////////// + +// FLASH base address +#define FLASH1_MEMORY_StartAddress (0x0) +// FLASH size +#define FLASH1_MEMORY_Size (0x0) + +///////////////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////// +#define TARGETNAMESTRING "@TARGET_NAME@" +#define PLATFORMNAMESTRING "ESP32" +////////////////////////////////////////////// + +///////////////////////////////////// +#define PLATFORM_HAS_RNG TRUE +///////////////////////////////////// + +///////////////////////////////////// +// #define EVENTS_HEART_BEAT +///////////////////////////////////// + +#endif // TARGET_COMMON_H diff --git a/targets/ESP32/ESP32_C3/target_lwip_sntp_opts.h b/targets/ESP32/ESP32_C3/target_lwip_sntp_opts.h new file mode 100644 index 0000000000..c4d09f1f1a --- /dev/null +++ b/targets/ESP32/ESP32_C3/target_lwip_sntp_opts.h @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T OVERRIDE ANY lwIP SNTP OPTIONS // +////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/ESP32/ESP32_C3/target_lwipopts.h b/targets/ESP32/ESP32_C3/target_lwipopts.h new file mode 100644 index 0000000000..ca1a0b4465 --- /dev/null +++ b/targets/ESP32/ESP32_C3/target_lwipopts.h @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +///////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T OVERRIDE ANY lwIP OPTIONS // +///////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/ESP32/ESP32_C3/target_nf_dev_onewire_config.cpp b/targets/ESP32/ESP32_C3/target_nf_dev_onewire_config.cpp new file mode 100644 index 0000000000..949567e829 --- /dev/null +++ b/targets/ESP32/ESP32_C3/target_nf_dev_onewire_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/ESP32/ESP32_C3/target_nf_dev_onewire_config.h b/targets/ESP32/ESP32_C3/target_nf_dev_onewire_config.h new file mode 100644 index 0000000000..167ba490d6 --- /dev/null +++ b/targets/ESP32/ESP32_C3/target_nf_dev_onewire_config.h @@ -0,0 +1,10 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +// use UART 2 for the 1-wire interface +#define NF_ONEWIRE_ESP32_UART_NUM UART_NUM_2 +// use GPIO port 16 for RX and 17 for TX +#define NF_ONEWIRE_ESP32_UART_RX_PIN UART_NUM_2_RXD_DIRECT_GPIO_NUM +#define NF_ONEWIRE_ESP32_UART_TX_PIN UART_NUM_2_TXD_DIRECT_GPIO_NUM diff --git a/targets/ESP32/ESP32_C3/target_system_device_adc_config.cpp b/targets/ESP32/ESP32_C3/target_system_device_adc_config.cpp new file mode 100644 index 0000000000..949567e829 --- /dev/null +++ b/targets/ESP32/ESP32_C3/target_system_device_adc_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/ESP32/ESP32_C3/target_system_device_dac_config.cpp b/targets/ESP32/ESP32_C3/target_system_device_dac_config.cpp new file mode 100644 index 0000000000..949567e829 --- /dev/null +++ b/targets/ESP32/ESP32_C3/target_system_device_dac_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/ESP32/ESP32_C3/target_system_device_i2c_config.cpp b/targets/ESP32/ESP32_C3/target_system_device_i2c_config.cpp new file mode 100644 index 0000000000..949567e829 --- /dev/null +++ b/targets/ESP32/ESP32_C3/target_system_device_i2c_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/ESP32/ESP32_C3/target_system_device_i2s_config.cpp b/targets/ESP32/ESP32_C3/target_system_device_i2s_config.cpp new file mode 100644 index 0000000000..949567e829 --- /dev/null +++ b/targets/ESP32/ESP32_C3/target_system_device_i2s_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/ESP32/ESP32_C3/target_system_device_spi_config.cpp b/targets/ESP32/ESP32_C3/target_system_device_spi_config.cpp new file mode 100644 index 0000000000..949567e829 --- /dev/null +++ b/targets/ESP32/ESP32_C3/target_system_device_spi_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/ESP32/ESP32_C3/target_system_devices_dac_config.cpp b/targets/ESP32/ESP32_C3/target_system_devices_dac_config.cpp new file mode 100644 index 0000000000..949567e829 --- /dev/null +++ b/targets/ESP32/ESP32_C3/target_system_devices_dac_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/ESP32/ESP32_C3/target_system_io_ports_config.cpp b/targets/ESP32/ESP32_C3/target_system_io_ports_config.cpp new file mode 100644 index 0000000000..949567e829 --- /dev/null +++ b/targets/ESP32/ESP32_C3/target_system_io_ports_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/ESP32/ESP32_C3/target_windows_storage_config.h b/targets/ESP32/ESP32_C3/target_windows_storage_config.h new file mode 100644 index 0000000000..949567e829 --- /dev/null +++ b/targets/ESP32/ESP32_C3/target_windows_storage_config.h @@ -0,0 +1,8 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/ESP32/_IDF/esp32c3/app_main.c b/targets/ESP32/_IDF/esp32c3/app_main.c new file mode 100644 index 0000000000..de37f30e2e --- /dev/null +++ b/targets/ESP32/_IDF/esp32c3/app_main.c @@ -0,0 +1,57 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include +#include + +extern void CLRStartupThread(void const *argument); +TaskHandle_t ReceiverTask; + +void receiver_task(void *pvParameter) +{ + (void)pvParameter; + + ReceiverThread(0); + + vTaskDelete(NULL); +} + +// Main task start point +void main_task(void *pvParameter) +{ + (void)pvParameter; + + // CLR settings to launch CLR thread + CLR_SETTINGS clrSettings; + (void)memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.EnterDebuggerLoopAfterExit = true; + + CLRStartupThread(&clrSettings); + + vTaskDelete(NULL); +} + +// App_main +// Called from Esp32 IDF start up code before scheduler starts +void app_main() +{ + // Switch off logging so as not to interfere with WireProtocol over Uart0 + esp_log_level_set("*", ESP_LOG_NONE); + + ESP_ERROR_CHECK(nvs_flash_init()); + + // start receiver task + xTaskCreate(&receiver_task, "ReceiverThread", 3072, NULL, 5, &ReceiverTask); + + // start the CLR main task + xTaskCreate(&main_task, "main_task", 15000, NULL, 5, NULL); +} diff --git a/targets/ESP32/_IDF/esp32c3/partitions_nanoclr_2mb.csv b/targets/ESP32/_IDF/esp32c3/partitions_nanoclr_2mb.csv new file mode 100644 index 0000000000..7940191288 --- /dev/null +++ b/targets/ESP32/_IDF/esp32c3/partitions_nanoclr_2mb.csv @@ -0,0 +1,17 @@ +################################################ +# ESP-IDF Partition Table for .NET nanoFramework +# Name, Type, SubType, Offset, Size, +############################################################################################################################### +# if you change the partitions here, make sure to update the BlockRegions array in the device BlockStorage configuration file # +############################################################################################################################### +nvs, data, nvs, 0x9000, 0x6000, +phy_init, data, phy, 0xf000, 0x1000, +# Factory area for nanoCLR - 1664k +factory, app, factory, 0x10000, 0x1A0000, +# Deployment area for Managed code 2240k +deploy, data, 0x84, 0x1B0000, 0x40000, +# Config data for Network, Wireless, certificates, user data 64k +config, data, spiffs, 0x1F0000, 0x10000, +################################# +# total size has to be 0x200000 # +################################# diff --git a/targets/ESP32/_IDF/esp32c3/partitions_nanoclr_4mb.csv b/targets/ESP32/_IDF/esp32c3/partitions_nanoclr_4mb.csv new file mode 100644 index 0000000000..3e58204a79 --- /dev/null +++ b/targets/ESP32/_IDF/esp32c3/partitions_nanoclr_4mb.csv @@ -0,0 +1,17 @@ +################################################ +# ESP-IDF Partition Table for .NET nanoFramework +# Name, Type, SubType, Offset, Size, +############################################################################################################################### +# if you change the partitions here, make sure to update the BlockRegions array in the device BlockStorage configuration file # +############################################################################################################################### +nvs, data, nvs, 0x9000, 0x6000, +phy_init, data, phy, 0xf000, 0x1000, +# Factory area for nanoCLR - 1664k +factory, app, factory, 0x10000, 0x1A0000, +# Deployment area for Managed code 1984k +deploy, data, 0x84, 0x1B0000, 0x1F0000, +# Config data for Network, Wireless, certificates, user data 256k +config, data, spiffs, 0x3C0000, 0x40000, +################################# +# total size has to be 0x400000 # +################################# diff --git a/targets/ESP32/_IDF/sdkconfig.default.esp32c3 b/targets/ESP32/_IDF/sdkconfig.default.esp32c3 new file mode 100644 index 0000000000..a5b3f87f7e --- /dev/null +++ b/targets/ESP32/_IDF/sdkconfig.default.esp32c3 @@ -0,0 +1,1162 @@ +# +# Automatically generated file. DO NOT EDIT. +# Espressif IoT Development Framework (ESP-IDF) Project Configuration +# +CONFIG_IDF_CMAKE=y +CONFIG_IDF_TARGET_ARCH_RISCV=y +CONFIG_IDF_TARGET="esp32c3" +CONFIG_IDF_TARGET_ESP32C3=y +CONFIG_IDF_FIRMWARE_CHIP_ID=0x0005 + +# +# SDK tool configuration +# +CONFIG_SDK_TOOLPREFIX="riscv32-esp-elf-" +# CONFIG_SDK_TOOLCHAIN_SUPPORTS_TIME_WIDE_64_BITS is not set +# end of SDK tool configuration + +# +# Build type +# +CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y +# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set +CONFIG_APP_BUILD_GENERATE_BINARIES=y +CONFIG_APP_BUILD_BOOTLOADER=y +CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y +# end of Build type + +# +# Application manager +# +CONFIG_APP_COMPILE_TIME_DATE=y +# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set +# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set +# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set +CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16 +# end of Application manager + +# +# Bootloader config +# +CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x1000 +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG=y +CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set +CONFIG_BOOTLOADER_LOG_LEVEL_INFO=y +# CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE is not set +CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y +# CONFIG_BOOTLOADER_FACTORY_RESET is not set +# CONFIG_BOOTLOADER_APP_TEST is not set +CONFIG_BOOTLOADER_WDT_ENABLE=y +# CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set +CONFIG_BOOTLOADER_WDT_TIME_MS=9000 +# CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set +CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0 +# CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set +# end of Bootloader config + +# +# Security features +# +CONFIG_SECURE_BOOT_SUPPORTS_RSA=y +CONFIG_SECURE_TARGET_HAS_SECURE_ROM_DL_MODE=y +# CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set +# CONFIG_SECURE_BOOT is not set +# CONFIG_SECURE_FLASH_ENC_ENABLED is not set +# CONFIG_SECURE_BOOT_ALLOW_JTAG is not set +# end of Security features + +# +# Serial flasher config +# +CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200 +# CONFIG_ESPTOOLPY_NO_STUB is not set +# CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set +# CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set +CONFIG_ESPTOOLPY_FLASHMODE_DIO=y +# CONFIG_ESPTOOLPY_FLASHMODE_DOUT is not set +CONFIG_ESPTOOLPY_FLASHMODE="dio" +CONFIG_ESPTOOLPY_FLASHFREQ_80M=y +# CONFIG_ESPTOOLPY_FLASHFREQ_40M is not set +# CONFIG_ESPTOOLPY_FLASHFREQ_26M is not set +# CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set +CONFIG_ESPTOOLPY_FLASHFREQ="80m" +# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y +# CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE="2MB" +CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y +CONFIG_ESPTOOLPY_BEFORE_RESET=y +# CONFIG_ESPTOOLPY_BEFORE_NORESET is not set +CONFIG_ESPTOOLPY_BEFORE="default_reset" +CONFIG_ESPTOOLPY_AFTER_RESET=y +# CONFIG_ESPTOOLPY_AFTER_NORESET is not set +CONFIG_ESPTOOLPY_AFTER="hard_reset" +# CONFIG_ESPTOOLPY_MONITOR_BAUD_CONSOLE is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_9600B is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_57600B is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_230400B is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_921600B=y +# CONFIG_ESPTOOLPY_MONITOR_BAUD_2MB is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER is not set +CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER_VAL=115200 +CONFIG_ESPTOOLPY_MONITOR_BAUD=921600 +# end of Serial flasher config + +# +# Partition Table +# +CONFIG_PARTITION_TABLE_SINGLE_APP=y +# CONFIG_PARTITION_TABLE_TWO_OTA is not set +CONFIG_PARTITION_TABLE_CUSTOM=y +# default to 4mb partition table for nanoCLR +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="targets/ESP32/_IDF/${TARGET_SERIES_SHORT}/partitions_nanoclr_4mb.csv" +# CONFIG_PARTITION_TABLE_FILENAME is not set +CONFIG_PARTITION_TABLE_OFFSET=0x8000 +CONFIG_PARTITION_TABLE_MD5=y +# end of Partition Table + +# +# Compiler options +# +# CONFIG_COMPILER_OPTIMIZATION_DEFAULT=y +CONFIG_COMPILER_OPTIMIZATION_SIZE=y +# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE=y +# CONFIG_COMPILER_CXX_EXCEPTIONS is not set +# CONFIG_COMPILER_CXX_RTTI is not set +CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y +# CONFIG_COMPILER_STACK_CHECK_MODE_NORM is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_STRONG is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set +# CONFIG_COMPILER_WARN_WRITE_STRINGS is not set +# CONFIG_COMPILER_DISABLE_GCC8_WARNINGS is not set +# CONFIG_COMPILER_DUMP_RTL_FILES is not set +# end of Compiler options + +# +# Component config +# + +# +# Application Level Tracing +# +# CONFIG_APPTRACE_DEST_TRAX is not set +CONFIG_APPTRACE_DEST_NONE=y +CONFIG_APPTRACE_LOCK_ENABLE=y +# end of Application Level Tracing + +# +# ESP-ASIO +# +# CONFIG_ASIO_SSL_SUPPORT is not set +# end of ESP-ASIO + +CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_EFF=0 +CONFIG_BTDM_CTRL_PCM_ROLE_EFF=0 +CONFIG_BTDM_CTRL_PCM_POLAR_EFF=0 +CONFIG_BTDM_CTRL_BLE_MAX_CONN_EFF=0 +CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN_EFF=0 +CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF=0 +CONFIG_BTDM_CTRL_PINNED_TO_CORE=0 +CONFIG_BTDM_BLE_SLEEP_CLOCK_ACCURACY_INDEX_EFF=1 +CONFIG_BT_CTRL_MODE_EFF=1 +CONFIG_BT_CTRL_BLE_MAX_ACT=10 +CONFIG_BT_CTRL_BLE_MAX_ACT_EFF=10 +CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB=0 +CONFIG_BT_CTRL_PINNED_TO_CORE=0 +CONFIG_BT_CTRL_HCI_TL=1 +CONFIG_BT_CTRL_ADV_DUP_FILT_MAX=30 +CONFIG_BT_CTRL_HW_CCA_EFF=0 +CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_EFF=0 +CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_SUPP=y +CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_NUM=100 +CONFIG_BT_CTRL_BLE_ADV_REPORT_DISCARD_THRSHOLD=20 +CONFIG_BT_CTRL_BLE_SCAN_DUPL=y +CONFIG_BT_CTRL_SCAN_DUPL_TYPE=0 +CONFIG_BT_CTRL_SCAN_DUPL_CACHE_SIZE=100 +CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_EFF=0 +CONFIG_BT_CTRL_SLEEP_MODE_EFF=0 +CONFIG_BT_CTRL_SLEEP_CLOCK_EFF=0 +CONFIG_BT_CTRL_HCI_TL_EFF=1 +CONFIG_BT_RESERVE_DRAM=0 +CONFIG_BT_NIMBLE_USE_ESP_TIMER=y + +# +# CoAP Configuration +# +CONFIG_COAP_MBEDTLS_PSK=y +# CONFIG_COAP_MBEDTLS_PKI is not set +# CONFIG_COAP_MBEDTLS_DEBUG is not set +CONFIG_COAP_LOG_DEFAULT_LEVEL=0 +# end of CoAP Configuration + +# +# Driver configurations +# + +# +# ADC configuration +# +# CONFIG_ADC_FORCE_XPD_FSM is not set +CONFIG_ADC_DISABLE_DAC=y +# end of ADC configuration + +# +# SPI configuration +# +# CONFIG_SPI_MASTER_IN_IRAM is not set +CONFIG_SPI_MASTER_ISR_IN_IRAM=y +# CONFIG_SPI_SLAVE_IN_IRAM is not set +CONFIG_SPI_SLAVE_ISR_IN_IRAM=y +# end of SPI configuration + +# +# TWAI configuration +# +# CONFIG_TWAI_ISR_IN_IRAM is not set +# end of TWAI configuration + +# +# UART configuration +# +CONFIG_UART_ISR_IN_IRAM=y +# end of UART configuration +# end of Driver configurations + +# +# eFuse Bit Manager +# +# CONFIG_EFUSE_CUSTOM_TABLE is not set +# CONFIG_EFUSE_VIRTUAL is not set +CONFIG_EFUSE_MAX_BLK_LEN=256 +# end of eFuse Bit Manager + +# +# SPI RAM config +# +CONFIG_SPIRAM_BOOT_INIT=y +CONFIG_SPIRAM_IGNORE_NOTFOUND=y +CONFIG_SPIRAM_USE_MEMMAP=n +CONFIG_SPIRAM_USE_CAPS_ALLOC=n +CONFIG_SPIRAM_USE_MALLOC=y +CONFIG_SPIRAM_TYPE_AUTO=y +CONFIG_SPIRAM_TYPE_ESPPSRAM32=n +CONFIG_SPIRAM_TYPE_ESPPSRAM64=n +CONFIG_SPIRAM_SIZE=-1 +CONFIG_SPIRAM_SPEED_40M=y +# CONFIG_SPIRAM_MEMTEST is not set +CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=16384 +CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP=y +CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL=32768 +CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=n +CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=n + +# +# ESP-TLS +# +CONFIG_ESP_TLS_USING_MBEDTLS=y +CONFIG_ESP_TLS_USE_DS_PERIPHERAL=y +# CONFIG_ESP_TLS_SERVER is not set +# CONFIG_ESP_TLS_PSK_VERIFICATION is not set +# CONFIG_ESP_TLS_INSECURE is not set +# end of ESP-TLS + + +# +# ESP32C3-Specific +# +CONFIG_ESP32C3_DEFAULT_CPU_FREQ_160=y +CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ=160 +# CONFIG_ESP32C3_REV_MIN_0 is not set +# CONFIG_ESP32C3_REV_MIN_1 is not set +CONFIG_ESP32C3_REV_MIN_2=y +#CONFIG_ESP32C3_REV_MIN_3 is not set +# CONFIG_ESP32C3_REV_MIN_4 is not set +CONFIG_ESP32C3_REV_MIN=2 +CONFIG_ESP32C3_DEBUG_OCDAWARE=y +CONFIG_ESP32C3_BROWNOUT_DET=y +CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_7=y +# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_2 is not set +CONFIG_ESP32C3_BROWNOUT_DET_LVL=7 +CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC_SYSTIMER=y +# CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC is not set +# CONFIG_ESP32C3_TIME_SYSCALL_USE_SYSTIMER is not set +# CONFIG_ESP32C3_TIME_SYSCALL_USE_NONE is not set +CONFIG_ESP32C3_RTC_CLK_SRC_INT_RC=y +# CONFIG_ESP32C3_RTC_CLK_SRC_EXT_CRYS is not set +# CONFIG_ESP32C3_RTC_CLK_SRC_EXT_OSC is not set +# CONFIG_ESP32C3_RTC_CLK_SRC_INT_8MD256 is not set +CONFIG_ESP32C3_RTC_CLK_CAL_CYCLES=1024 +# CONFIG_ESP32C3_NO_BLOBS is not set +# end of ESP32C3-Specific + +# +# Cache config +# +CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB=y +# CONFIG_ESP32S2_INSTRUCTION_CACHE_16KB is not set +# CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B is not set +CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_32B=y +CONFIG_ESP32S2_DATA_CACHE_0KB=y +# CONFIG_ESP32S2_DATA_CACHE_8KB is not set +# CONFIG_ESP32S2_DATA_CACHE_16KB is not set +# CONFIG_ESP32S2_DATA_CACHE_LINE_16B is not set +CONFIG_ESP32S2_DATA_CACHE_LINE_32B=y +# CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP is not set +# CONFIG_ESP32S2_DATA_CACHE_WRAP is not set +# end of Cache config + +CONFIG_ESP32S2_SPIRAM_SUPPORT=y +# CONFIG_ESP32S2_TRAX is not set +CONFIG_ESP32S2_TRACEMEM_RESERVE_DRAM=0x0 +# CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE is not set +CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO=y +CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES=2 +# CONFIG_ESP32S2_ULP_COPROC_ENABLED is not set +CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM=0 +CONFIG_ESP32S2_DEBUG_OCDAWARE=y +# CONFIG_ESP32S2_DEBUG_STUBS_ENABLE is not set +CONFIG_ESP32S2_BROWNOUT_DET=y +CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_7=y +# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_2 is not set +# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_1 is not set +CONFIG_ESP32S2_BROWNOUT_DET_LVL=7 +CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC_FRC1=y +# CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC is not set +# CONFIG_ESP32S2_TIME_SYSCALL_USE_FRC1 is not set +# CONFIG_ESP32S2_TIME_SYSCALL_USE_NONE is not set +CONFIG_ESP32S2_RTC_CLK_SRC_INT_RC=y +# CONFIG_ESP32S2_RTC_CLK_SRC_EXT_CRYS is not set +# CONFIG_ESP32S2_RTC_CLK_SRC_EXT_OSC is not set +# CONFIG_ESP32S2_RTC_CLK_SRC_INT_8MD256 is not set +CONFIG_ESP32S2_RTC_CLK_CAL_CYCLES=576 +# CONFIG_ESP32S2_NO_BLOBS is not set +# CONFIG_ESP32S2_KEEP_USB_ALIVE is not set +# CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM is not set +# CONFIG_ESP32S2_USE_FIXED_STATIC_RAM_SIZE is not set +# end of ESP32S2-specific + +# +# ADC-Calibration +# +# end of ADC-Calibration + +# config for XTAL freq +# adding it here, so it can be overriden by our CMake +CONFIG_ESP32_XTAL_FREQ_40=y + +# +# Common ESP-related +# +CONFIG_ESP_ERR_TO_NAME_LOOKUP=y +CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_ESP_MAIN_TASK_STACK_SIZE=3584 +CONFIG_ESP_IPC_TASK_STACK_SIZE=1024 +CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048 +CONFIG_ESP_CONSOLE_UART_DEFAULT=y +# CONFIG_ESP_CONSOLE_UART_CUSTOM is not set +# CONFIG_ESP_CONSOLE_NONE is not set +CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG is not set +CONFIG_ESP_CONSOLE_UART=y +CONFIG_ESP_CONSOLE_MULTIPLE_UART=y +CONFIG_ESP_CONSOLE_UART_NUM=0 +CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200 +CONFIG_ESP_INT_WDT=y +CONFIG_ESP_INT_WDT_TIMEOUT_MS=300 +# CONFIG_ESP_TASK_WDT is not set +# CONFIG_ESP_TASK_WDT_PANIC is not set +# CONFIG_ESP_TASK_WDT_TIMEOUT_S is not set +# CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 is not set +# CONFIG_ESP_PANIC_HANDLER_IRAM is not set +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y +# end of Common ESP-related + +# +# Ethernet +# +# Parameters configured in binutils.ESP32.CMAKE +# +CONFIG_ETH_ENABLED=y +CONFIG_ETH_USE_ESP32_EMAC=y + +CONFIG_ETH_PHY_INTERFACE_RMII=y +# CONFIG_ETH_PHY_INTERFACE_MII is not set + +#CONFIG_ETH_RMII_CLK_OUTPUT=y +#CONFIG_ETH_RMII_CLK_OUT_GPIO=17 +#CONFIG_ETH_RMII_CLK_INPUT=y +#CONFIG_ETH_RMII_CLK_IN_GPIO=n + +CONFIG_ETH_DMA_BUFFER_SIZE=512 +CONFIG_ETH_DMA_RX_BUFFER_NUM=10 +CONFIG_ETH_DMA_TX_BUFFER_NUM=10 + +# Include SPI drivers in case used in build +CONFIG_ETH_USE_SPI_ETHERNET=y +#CONFIG_ETH_SPI_ETHERNET_DM9051=y +#CONFIG_ETH_SPI_ETHERNET_W5500=y +#CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL=y +#CONFIG_ETH_USE_OPENETH=n +# end of Ethernet + +# +# Event Loop Library +# +# CONFIG_ESP_EVENT_LOOP_PROFILING is not set +CONFIG_ESP_EVENT_POST_FROM_ISR=y +CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR=y +# end of Event Loop Library + +# +# GDB Stub +# +# end of GDB Stub + +# +# ESP HTTP client +# +CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y +# CONFIG_ESP_HTTP_CLIENT_ENABLE_BASIC_AUTH is not set +# end of ESP HTTP client + +# +# HTTP Server +# +CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 +CONFIG_HTTPD_MAX_URI_LEN=512 +CONFIG_HTTPD_ERR_RESP_NO_DELAY=y +CONFIG_HTTPD_PURGE_BUF_LEN=32 +# CONFIG_HTTPD_LOG_PURGE_DATA is not set +# CONFIG_HTTPD_WS_SUPPORT is not set +# end of HTTP Server + +# +# ESP HTTPS OTA +# +# CONFIG_OTA_ALLOW_HTTP is not set +# end of ESP HTTPS OTA + +# +# ESP HTTPS server +# +# CONFIG_ESP_HTTPS_SERVER_ENABLE is not set +# end of ESP HTTPS server + +# +# ESP NETIF Adapter +# +CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120 +CONFIG_ESP_NETIF_TCPIP_LWIP=y +# CONFIG_ESP_NETIF_LOOPBACK is not set +# CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER is not set +# end of ESP NETIF Adapter + +# +# Power Management +# +CONFIG_PM_ENABLE=y +# end of Power Management + +# +# ESP System Settings +# +# CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set +CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y +# CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set +# CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set +CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE=y +CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK=y +CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y +CONFIG_ESP_SLEEP_POWER_DOWN_FLASH=y + +# +# Memory protection +# +CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=y +CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK=y +# end of Memory protection +# end of ESP System Settings + +# +# High resolution timer (esp_timer) +# +# CONFIG_ESP_TIMER_PROFILING is not set +CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y +CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y +CONFIG_ESP_TIMER_TASK_STACK_SIZE=3584 +CONFIG_ESP_TIMER_IMPL_SYSTIMER=y +# end of High resolution timer (esp_timer) + +# +# Wi-Fi +# +CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +# CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y +# CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER is not set +CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1 +CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=32 +# CONFIG_ESP32_WIFI_CSI_ENABLED is not set +CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP32_WIFI_TX_BA_WIN=6 +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +CONFIG_ESP32_WIFI_NVS_ENABLED=y +CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32 +# CONFIG_WIFI_LOG_DEFAULT_LEVEL_NONE is not set +# CONFIG_WIFI_LOG_DEFAULT_LEVEL_ERROR is not set +# CONFIG_WIFI_LOG_DEFAULT_LEVEL_WARN is not set +CONFIG_WIFI_LOG_DEFAULT_LEVEL_INFO=y +# CONFIG_WIFI_LOG_DEFAULT_LEVEL_DEBUG is not set +# CONFIG_WIFI_LOG_DEFAULT_LEVEL_VERBOSE is not set +CONFIG_ESP32_WIFI_IRAM_OPT=y +CONFIG_ESP32_WIFI_RX_IRAM_OPT=y +CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y +# CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set +# CONFIG_ESP_WIFI_FTM_ENABLE is not set +# CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE is not set +# end of Wi-Fi + +# +# PHY +# +CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y +# CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set +CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP_PHY_MAX_TX_POWER=20 +# end of PHY + +# +# Core dump +# +# CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH is not set +# CONFIG_ESP_COREDUMP_ENABLE_TO_UART is not set +CONFIG_ESP_COREDUMP_ENABLE_TO_NONE=y +# end of Core dump + +# +# FAT Filesystem support +# +# CONFIG_FATFS_CODEPAGE_DYNAMIC is not set +CONFIG_FATFS_CODEPAGE_437=y +# CONFIG_FATFS_CODEPAGE_720 is not set +# CONFIG_FATFS_CODEPAGE_737 is not set +# CONFIG_FATFS_CODEPAGE_771 is not set +# CONFIG_FATFS_CODEPAGE_775 is not set +# CONFIG_FATFS_CODEPAGE_850 is not set +# CONFIG_FATFS_CODEPAGE_852 is not set +# CONFIG_FATFS_CODEPAGE_855 is not set +# CONFIG_FATFS_CODEPAGE_857 is not set +# CONFIG_FATFS_CODEPAGE_860 is not set +# CONFIG_FATFS_CODEPAGE_861 is not set +# CONFIG_FATFS_CODEPAGE_862 is not set +# CONFIG_FATFS_CODEPAGE_863 is not set +# CONFIG_FATFS_CODEPAGE_864 is not set +# CONFIG_FATFS_CODEPAGE_865 is not set +# CONFIG_FATFS_CODEPAGE_866 is not set +# CONFIG_FATFS_CODEPAGE_869 is not set +# CONFIG_FATFS_CODEPAGE_932 is not set +# CONFIG_FATFS_CODEPAGE_936 is not set +# CONFIG_FATFS_CODEPAGE_949 is not set +# CONFIG_FATFS_CODEPAGE_950 is not set +CONFIG_FATFS_CODEPAGE=437 +# CONFIG_FATFS_LFN_NONE is not set +CONFIG_FATFS_LFN_HEAP=y +# CONFIG_FATFS_LFN_STACK is not set +CONFIG_FATFS_FS_LOCK=0 +CONFIG_FATFS_TIMEOUT_MS=10000 +CONFIG_FATFS_PER_FILE_CACHE=y +# CONFIG_FATFS_USE_FASTSEEK is not set +# end of FAT Filesystem support + +# +# Modbus configuration +# +CONFIG_FMB_COMM_MODE_TCP_EN=y +CONFIG_FMB_TCP_PORT_DEFAULT=502 +CONFIG_FMB_TCP_PORT_MAX_CONN=5 +CONFIG_FMB_TCP_CONNECTION_TOUT_SEC=20 +CONFIG_FMB_COMM_MODE_RTU_EN=y +CONFIG_FMB_COMM_MODE_ASCII_EN=y +CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND=150 +CONFIG_FMB_MASTER_DELAY_MS_CONVERT=200 +CONFIG_FMB_QUEUE_LENGTH=20 +CONFIG_FMB_PORT_TASK_STACK_SIZE=4096 +CONFIG_FMB_SERIAL_BUF_SIZE=256 +CONFIG_FMB_SERIAL_ASCII_BITS_PER_SYMB=8 +CONFIG_FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS=1000 +CONFIG_FMB_PORT_TASK_PRIO=10 +CONFIG_FMB_CONTROLLER_SLAVE_ID_SUPPORT=y +CONFIG_FMB_CONTROLLER_SLAVE_ID=0x00112233 +CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT=20 +CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE=20 +CONFIG_FMB_CONTROLLER_STACK_SIZE=4096 +CONFIG_FMB_EVENT_QUEUE_TIMEOUT=20 +CONFIG_FMB_TIMER_PORT_ENABLED=y +CONFIG_FMB_TIMER_GROUP=0 +CONFIG_FMB_TIMER_INDEX=0 +# CONFIG_FMB_TIMER_ISR_IN_IRAM is not set +# end of Modbus configuration + +# +# FreeRTOS +# +# CONFIG_FREERTOS_UNICORE is not set +CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF +CONFIG_FREERTOS_CORETIMER_0=y +# CONFIG_FREERTOS_CORETIMER_1 is not set +CONFIG_FREERTOS_OPTIMIZED_SCHEDULER=y +CONFIG_FREERTOS_HZ=100 +CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y +# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set +CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y +CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 +CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y +# CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE is not set +# CONFIG_FREERTOS_ASSERT_DISABLE is not set +CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=2304 +CONFIG_FREERTOS_ISR_STACKSIZE=1536 +# CONFIG_FREERTOS_LEGACY_HOOKS is not set +CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 +CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y +# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set +CONFIG_FREERTOS_TIMER_TASK_PRIORITY=5 +CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10 +CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 +CONFIG_FREERTOS_USE_TICKLESS_IDLE=y +# CONFIG_FREERTOS_USE_TRACE_FACILITY is not set +# CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS is not set +CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y +CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y +# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set +# CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH is not set +CONFIG_FREERTOS_DEBUG_OCDAWARE=y +# end of FreeRTOS + +# +# Heap memory debugging +# +CONFIG_HEAP_POISONING_DISABLED=y +# CONFIG_HEAP_POISONING_LIGHT is not set +# CONFIG_HEAP_POISONING_COMPREHENSIVE is not set +CONFIG_HEAP_TRACING_OFF=y +# CONFIG_HEAP_TRACING_STANDALONE is not set +# CONFIG_HEAP_TRACING_TOHOST is not set +# CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set +# end of Heap memory debugging + +# +# jsmn +# +# CONFIG_JSMN_PARENT_LINKS is not set +# CONFIG_JSMN_STRICT is not set +# end of jsmn + +# +# libsodium +# +# end of libsodium + +# +# Log output +# +# CONFIG_LOG_DEFAULT_LEVEL_NONE is not set +# CONFIG_LOG_DEFAULT_LEVEL_ERROR is not set +# CONFIG_LOG_DEFAULT_LEVEL_WARN is not set +CONFIG_LOG_DEFAULT_LEVEL_INFO=y +# CONFIG_LOG_DEFAULT_LEVEL_DEBUG is not set +# CONFIG_LOG_DEFAULT_LEVEL_VERBOSE is not set +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_LOG_COLORS=y +CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y +# CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM is not set +# end of Log output + +# +# LWIP +# +CONFIG_LWIP_LOCAL_HOSTNAME="nanodevice" +CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y +# CONFIG_LWIP_L2_TO_L3_COPY is not set +# CONFIG_LWIP_IRAM_OPTIMIZATION is not set +CONFIG_LWIP_TIMERS_ONDEMAND=y +CONFIG_LWIP_MAX_SOCKETS=16 +# CONFIG_LWIP_USE_ONLY_LWIP_SELECT is not set +CONFIG_LWIP_SO_LINGER=y +CONFIG_LWIP_SO_REUSE=y +CONFIG_LWIP_SO_REUSE_RXTOALL=y +CONFIG_LWIP_SO_RCVBUF=y +# CONFIG_LWIP_NETBUF_RECVINFO is not set +CONFIG_LWIP_IP4_FRAG=y +CONFIG_LWIP_IP6_FRAG=y +# CONFIG_LWIP_IP4_REASSEMBLY is not set +# CONFIG_LWIP_IP6_REASSEMBLY is not set +# CONFIG_LWIP_IP_FORWARD is not set +# CONFIG_LWIP_STATS is not set +# CONFIG_LWIP_ETHARP_TRUST_IP_MAC is not set +CONFIG_LWIP_ESP_GRATUITOUS_ARP=y +CONFIG_LWIP_GARP_TMR_INTERVAL=60 +CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32 +CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y +# CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set +# CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set +CONFIG_LWIP_DHCP_OPTIONS_LEN=80 + +# +# DHCP server +# +# CONFIG_LWIP_DHCPS is not set +CONFIG_LWIP_DHCPS_LEASE_UNIT=60 +CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 +# end of DHCP server + +# CONFIG_LWIP_AUTOIP is not set +# CONFIG_LWIP_IPV6 is not set +# CONFIG_LWIP_IPV6_AUTOCONFIG is not set +CONFIG_LWIP_NETIF_LOOPBACK=y +CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 + +# +# TCP +# +CONFIG_LWIP_MAX_ACTIVE_TCP=16 +CONFIG_LWIP_MAX_LISTENING_TCP=8 +CONFIG_LWIP_TCP_HIGH_SPEED_RETRANSMISSION=y +CONFIG_LWIP_TCP_MAXRTX=12 +CONFIG_LWIP_TCP_SYNMAXRTX=12 +CONFIG_LWIP_TCP_MSS=1440 +CONFIG_LWIP_TCP_TMR_INTERVAL=250 +CONFIG_LWIP_TCP_MSL=60000 +CONFIG_LWIP_TCP_SND_BUF_DEFAULT=5744 +CONFIG_LWIP_TCP_WND_DEFAULT=5744 +CONFIG_LWIP_TCP_RECVMBOX_SIZE=6 +CONFIG_LWIP_TCP_QUEUE_OOSEQ=y +# CONFIG_LWIP_TCP_SACK_OUT is not set +# CONFIG_LWIP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set +CONFIG_LWIP_TCP_OVERSIZE_MSS=y +# CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set +CONFIG_LWIP_TCP_RTO_TIME=1500 +# end of TCP + +# +# UDP +# +CONFIG_LWIP_MAX_UDP_PCBS=16 +CONFIG_LWIP_UDP_RECVMBOX_SIZE=6 +# end of UDP + +# +# Checksums +# +# CONFIG_LWIP_CHECKSUM_CHECK_IP is not set +# CONFIG_LWIP_CHECKSUM_CHECK_UDP is not set +CONFIG_LWIP_CHECKSUM_CHECK_ICMP=y +# end of Checksums + +CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0 is not set +CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x7FFFFFFF +# CONFIG_LWIP_PPP_SUPPORT is not set +CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE=3 +CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS=5 +# CONFIG_LWIP_SLIP_SUPPORT is not set + +# +# ICMP +# +CONFIG_LWIP_ICMP=y +# CONFIG_LWIP_MULTICAST_PING is not set +# CONFIG_LWIP_BROADCAST_PING is not set +# end of ICMP + +# +# LWIP RAW API +# +CONFIG_LWIP_MAX_RAW_PCBS=16 +# end of LWIP RAW API + +# +# SNTP +# +CONFIG_LWIP_DHCP_MAX_NTP_SERVERS=1 +CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000 +# end of SNTP + +CONFIG_LWIP_ESP_LWIP_ASSERT=y + +# +# Hooks +# +# CONFIG_LWIP_HOOK_TCP_ISN_NONE is not set +CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT=y +# CONFIG_LWIP_HOOK_TCP_ISN_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_ROUTE_NONE=y +# CONFIG_LWIP_HOOK_IP6_ROUTE_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_ROUTE_CUSTOM is not set +CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set +# end of Hooks + +# CONFIG_LWIP_DEBUG is not set +# end of LWIP + +# +# mbedTLS +# +# CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC is not set +CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC=y +# CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC is not set +CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=y +CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN=16384 +CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096 +CONFIG_MBEDTLS_DYNAMIC_BUFFER=y +# CONFIG_MBEDTLS_DEBUG=y + +# +# Certificate Bundle +# +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE is not set +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL is not set +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_CMN is not set +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_NONE is not set +# CONFIG_MBEDTLS_CUSTOM_CERTIFICATE_BUNDLE is not set +# end of Certificate Bundle + +CONFIG_MBEDTLS_ECP_RESTARTABLE=y +CONFIG_MBEDTLS_CMAC_C=y +CONFIG_MBEDTLS_HARDWARE_AES=y +CONFIG_MBEDTLS_AES_USE_INTERRUPT=y +CONFIG_MBEDTLS_HARDWARE_GCM=y +CONFIG_MBEDTLS_HARDWARE_MPI=y +CONFIG_MBEDTLS_HARDWARE_SHA=y +CONFIG_MBEDTLS_ROM_MD5=y +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set +CONFIG_MBEDTLS_HAVE_TIME=y +CONFIG_MBEDTLS_HAVE_TIME_DATE=y +CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y +CONFIG_MBEDTLS_SHA512_C=y +CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y +# CONFIG_MBEDTLS_TLS_SERVER_ONLY is not set +# CONFIG_MBEDTLS_TLS_CLIENT_ONLY is not set +# CONFIG_MBEDTLS_TLS_DISABLED is not set +CONFIG_MBEDTLS_TLS_SERVER=y +CONFIG_MBEDTLS_TLS_CLIENT=y +CONFIG_MBEDTLS_TLS_ENABLED=y + +# +# TLS Key Exchange Methods +# +# CONFIG_MBEDTLS_PSK_MODES is not set +CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y +# end of TLS Key Exchange Methods + +CONFIG_MBEDTLS_SSL_RENEGOTIATION=y +# CONFIG_MBEDTLS_SSL_PROTO_SSL3 is not set +CONFIG_MBEDTLS_SSL_PROTO_TLS1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y +# CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set +CONFIG_MBEDTLS_SSL_ALPN=y +# CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS is not set +CONFIG_MBEDTLS_X509_CHECK_KEY_USAGE=y +CONFIG_MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE=y +CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y + +# +# Symmetric Ciphers +# +CONFIG_MBEDTLS_AES_C=y +# CONFIG_MBEDTLS_CAMELLIA_C is not set +CONFIG_MBEDTLS_DES_C=y +CONFIG_MBEDTLS_RC4_DISABLED=y +# CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT is not set +# CONFIG_MBEDTLS_RC4_ENABLED is not set +# CONFIG_MBEDTLS_BLOWFISH_C is not set +CONFIG_MBEDTLS_XTEA_C=y +CONFIG_MBEDTLS_CCM_C=y +CONFIG_MBEDTLS_GCM_C=y +# CONFIG_MBEDTLS_NIST_KW_C is not set +# end of Symmetric Ciphers + +# CONFIG_MBEDTLS_RIPEMD160_C=y + +# +# Certificates +# +CONFIG_MBEDTLS_PEM_PARSE_C=y +# CONFIG_MBEDTLS_PEM_WRITE_C is not set +CONFIG_MBEDTLS_X509_CRL_PARSE_C=y +CONFIG_MBEDTLS_X509_CSR_PARSE_C=y +# end of Certificates + +CONFIG_MBEDTLS_ECP_C=y +CONFIG_MBEDTLS_ECDH_C=y +CONFIG_MBEDTLS_ECDSA_C=y +# CONFIG_MBEDTLS_ECJPAKE_C is not set +CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y +CONFIG_MBEDTLS_ECP_NIST_OPTIM=y +# CONFIG_MBEDTLS_POLY1305_C is not set +# CONFIG_MBEDTLS_CHACHA20_C is not set +# CONFIG_MBEDTLS_HKDF_C is not set +# CONFIG_MBEDTLS_THREADING_C is not set +# CONFIG_MBEDTLS_LARGE_KEY_SOFTWARE_MPI is not set +# CONFIG_MBEDTLS_SECURITY_RISKS is not set +# end of mbedTLS + +# +# mDNS +# +CONFIG_MDNS_MAX_SERVICES=10 +CONFIG_MDNS_TASK_PRIORITY=1 +CONFIG_MDNS_TASK_STACK_SIZE=4096 +# CONFIG_MDNS_TASK_AFFINITY_NO_AFFINITY is not set +CONFIG_MDNS_TASK_AFFINITY_CPU0=y +CONFIG_MDNS_TASK_AFFINITY=0x0 +CONFIG_MDNS_SERVICE_ADD_TIMEOUT_MS=2000 +# CONFIG_MDNS_STRICT_MODE is not set +CONFIG_MDNS_TIMER_PERIOD_MS=100 +# end of mDNS + +# +# ESP-MQTT Configurations +# +CONFIG_MQTT_PROTOCOL_311=y +CONFIG_MQTT_TRANSPORT_SSL=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y +# CONFIG_MQTT_MSG_ID_INCREMENTAL is not set +# CONFIG_MQTT_SKIP_PUBLISH_IF_DISCONNECTED is not set +# CONFIG_MQTT_REPORT_DELETED_MESSAGES is not set +# CONFIG_MQTT_USE_CUSTOM_CONFIG is not set +# CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED is not set +# CONFIG_MQTT_CUSTOM_OUTBOX is not set +# end of ESP-MQTT Configurations + +# +# Newlib +# +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set +CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y +# CONFIG_NEWLIB_NANO_FORMAT is not set +# end of Newlib + +# +# NVS +# +# end of NVS + +# +# OpenSSL +# +# CONFIG_OPENSSL_DEBUG is not set +CONFIG_OPENSSL_ERROR_STACK=y +# CONFIG_OPENSSL_ASSERT_DO_NOTHING is not set +CONFIG_OPENSSL_ASSERT_EXIT=y +# end of OpenSSL + +# +# PThreads +# +CONFIG_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_PTHREAD_STACK_MIN=768 +CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread" +# end of PThreads + +# +# SPI Flash driver +# +# CONFIG_SPI_FLASH_VERIFY_WRITE is not set +# CONFIG_SPI_FLASH_ENABLE_COUNTERS is not set +CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y +CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set +# CONFIG_SPI_FLASH_USE_LEGACY_IMPL is not set +# CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set +CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y +CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20 +CONFIG_SPI_FLASH_ERASE_YIELD_TICKS=1 +CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192 +# CONFIG_SPI_FLASH_SIZE_OVERRIDE is not set +# CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set + +# +# Auto-detect flash chips +# +CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP=y +# end of Auto-detect flash chips + +CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=y +# end of SPI Flash driver + +# +# SPIFFS Configuration +# +CONFIG_SPIFFS_MAX_PARTITIONS=3 + +# +# SPIFFS Cache Configuration +# +CONFIG_SPIFFS_CACHE=y +CONFIG_SPIFFS_CACHE_WR=y +# CONFIG_SPIFFS_CACHE_STATS is not set +# end of SPIFFS Cache Configuration + +CONFIG_SPIFFS_PAGE_CHECK=y +CONFIG_SPIFFS_GC_MAX_RUNS=10 +# CONFIG_SPIFFS_GC_STATS is not set +CONFIG_SPIFFS_PAGE_SIZE=256 +CONFIG_SPIFFS_OBJ_NAME_LEN=32 +# CONFIG_SPIFFS_FOLLOW_SYMLINKS is not set +CONFIG_SPIFFS_USE_MAGIC=y +CONFIG_SPIFFS_USE_MAGIC_LENGTH=y +CONFIG_SPIFFS_META_LENGTH=4 +CONFIG_SPIFFS_USE_MTIME=y + +# +# Debug Configuration +# +# CONFIG_SPIFFS_DBG is not set +# CONFIG_SPIFFS_API_DBG is not set +# CONFIG_SPIFFS_GC_DBG is not set +# CONFIG_SPIFFS_CACHE_DBG is not set +# CONFIG_SPIFFS_CHECK_DBG is not set +# CONFIG_SPIFFS_TEST_VISUALISATION is not set +# end of Debug Configuration +# end of SPIFFS Configuration + +# +# TCP Transport +# + +# +# Websocket +# +CONFIG_WS_TRANSPORT=y +CONFIG_WS_BUFFER_SIZE=1024 +# end of Websocket +# end of TCP Transport + +# +# TinyUSB +# +CONFIG_USB_ENABLED=y +CONFIG_USB_CDC_ENABLED=y +CONFIG_USB_DESC_CDC_STRING=".NET nanoFramework device" +CONFIG_USB_CDC_RX_BUFSIZE=64 +# setting this to WP packet size +CONFIG_USB_CDC_TX_BUFSIZE=1024 +# end of TinyUSB + +# +# Unity unit testing library +# +CONFIG_UNITY_ENABLE_FLOAT=y +CONFIG_UNITY_ENABLE_DOUBLE=y +# CONFIG_UNITY_ENABLE_COLOR is not set +CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y +# CONFIG_UNITY_ENABLE_FIXTURE is not set +# CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set +# end of Unity unit testing library + +# +# Virtual file system +# +CONFIG_VFS_SUPPORT_IO=y +CONFIG_VFS_SUPPORT_DIR=y +CONFIG_VFS_SUPPORT_SELECT=y +CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_VFS_SUPPORT_TERMIOS=y + +# +# Host File System I/O (Semihosting) +# +CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS=1 +CONFIG_VFS_SEMIHOSTFS_HOST_PATH_MAX_LEN=128 +# end of Host File System I/O (Semihosting) +# end of Virtual file system + +# +# Wear Levelling +# +# CONFIG_WL_SECTOR_SIZE_512 is not set +CONFIG_WL_SECTOR_SIZE_4096=y +CONFIG_WL_SECTOR_SIZE=4096 +# end of Wear Levelling + +# +# Wi-Fi Provisioning Manager +# +CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16 +CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30 +# end of Wi-Fi Provisioning Manager + +# +# Supplicant +# +CONFIG_WPA_MBEDTLS_CRYPTO=y +# CONFIG_WPA_WAPI_PSK is not set +# CONFIG_WPA_DEBUG_PRINT is not set +# CONFIG_WPA_TESTING_OPTIONS is not set +# CONFIG_WPA_WPS_STRICT is not set +# CONFIG_WPA_11KV_SUPPORT is not set +# end of Supplicant +# end of Component config diff --git a/targets/ESP32/_IDF/sdkconfig.default_rev3.esp32c3 b/targets/ESP32/_IDF/sdkconfig.default_rev3.esp32c3 new file mode 100644 index 0000000000..2202c09ef6 --- /dev/null +++ b/targets/ESP32/_IDF/sdkconfig.default_rev3.esp32c3 @@ -0,0 +1,1162 @@ +# +# Automatically generated file. DO NOT EDIT. +# Espressif IoT Development Framework (ESP-IDF) Project Configuration +# +CONFIG_IDF_CMAKE=y +CONFIG_IDF_TARGET_ARCH_RISCV=y +CONFIG_IDF_TARGET="esp32c3" +CONFIG_IDF_TARGET_ESP32C3=y +CONFIG_IDF_FIRMWARE_CHIP_ID=0x0005 + +# +# SDK tool configuration +# +CONFIG_SDK_TOOLPREFIX="riscv32-esp-elf-" +# CONFIG_SDK_TOOLCHAIN_SUPPORTS_TIME_WIDE_64_BITS is not set +# end of SDK tool configuration + +# +# Build type +# +CONFIG_APP_BUILD_TYPE_APP_2NDBOOT=y +# CONFIG_APP_BUILD_TYPE_ELF_RAM is not set +CONFIG_APP_BUILD_GENERATE_BINARIES=y +CONFIG_APP_BUILD_BOOTLOADER=y +CONFIG_APP_BUILD_USE_FLASH_SECTIONS=y +# end of Build type + +# +# Application manager +# +CONFIG_APP_COMPILE_TIME_DATE=y +# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set +# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set +# CONFIG_APP_PROJECT_VER_FROM_CONFIG is not set +CONFIG_APP_RETRIEVE_LEN_ELF_SHA=16 +# end of Application manager + +# +# Bootloader config +# +CONFIG_BOOTLOADER_OFFSET_IN_FLASH=0x1000 +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_DEBUG=y +CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_PERF is not set +# CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_NONE is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_ERROR is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_WARN is not set +CONFIG_BOOTLOADER_LOG_LEVEL_INFO=y +# CONFIG_BOOTLOADER_LOG_LEVEL_DEBUG is not set +# CONFIG_BOOTLOADER_LOG_LEVEL_VERBOSE is not set +CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y +# CONFIG_BOOTLOADER_FACTORY_RESET is not set +# CONFIG_BOOTLOADER_APP_TEST is not set +CONFIG_BOOTLOADER_WDT_ENABLE=y +# CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set +CONFIG_BOOTLOADER_WDT_TIME_MS=9000 +# CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ON_POWER_ON is not set +# CONFIG_BOOTLOADER_SKIP_VALIDATE_ALWAYS is not set +CONFIG_BOOTLOADER_RESERVE_RTC_SIZE=0 +# CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC is not set +# end of Bootloader config + +# +# Security features +# +CONFIG_SECURE_BOOT_SUPPORTS_RSA=y +CONFIG_SECURE_TARGET_HAS_SECURE_ROM_DL_MODE=y +# CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set +# CONFIG_SECURE_BOOT is not set +# CONFIG_SECURE_FLASH_ENC_ENABLED is not set +# CONFIG_SECURE_BOOT_ALLOW_JTAG is not set +# end of Security features + +# +# Serial flasher config +# +CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200 +# CONFIG_ESPTOOLPY_NO_STUB is not set +# CONFIG_ESPTOOLPY_FLASHMODE_QIO is not set +# CONFIG_ESPTOOLPY_FLASHMODE_QOUT is not set +CONFIG_ESPTOOLPY_FLASHMODE_DIO=y +# CONFIG_ESPTOOLPY_FLASHMODE_DOUT is not set +CONFIG_ESPTOOLPY_FLASHMODE="dio" +CONFIG_ESPTOOLPY_FLASHFREQ_80M=y +# CONFIG_ESPTOOLPY_FLASHFREQ_40M is not set +# CONFIG_ESPTOOLPY_FLASHFREQ_26M is not set +# CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set +CONFIG_ESPTOOLPY_FLASHFREQ="80m" +# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y +# CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE="2MB" +CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y +CONFIG_ESPTOOLPY_BEFORE_RESET=y +# CONFIG_ESPTOOLPY_BEFORE_NORESET is not set +CONFIG_ESPTOOLPY_BEFORE="default_reset" +CONFIG_ESPTOOLPY_AFTER_RESET=y +# CONFIG_ESPTOOLPY_AFTER_NORESET is not set +CONFIG_ESPTOOLPY_AFTER="hard_reset" +# CONFIG_ESPTOOLPY_MONITOR_BAUD_CONSOLE is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_9600B is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_57600B is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_115200B is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_230400B is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_921600B=y +# CONFIG_ESPTOOLPY_MONITOR_BAUD_2MB is not set +# CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER is not set +CONFIG_ESPTOOLPY_MONITOR_BAUD_OTHER_VAL=115200 +CONFIG_ESPTOOLPY_MONITOR_BAUD=921600 +# end of Serial flasher config + +# +# Partition Table +# +CONFIG_PARTITION_TABLE_SINGLE_APP=y +# CONFIG_PARTITION_TABLE_TWO_OTA is not set +CONFIG_PARTITION_TABLE_CUSTOM=y +# default to 4mb partition table for nanoCLR +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="targets/ESP32/_IDF/${TARGET_SERIES_SHORT}/partitions_nanoclr_4mb.csv" +# CONFIG_PARTITION_TABLE_FILENAME is not set +CONFIG_PARTITION_TABLE_OFFSET=0x8000 +CONFIG_PARTITION_TABLE_MD5=y +# end of Partition Table + +# +# Compiler options +# +# CONFIG_COMPILER_OPTIMIZATION_DEFAULT=y +CONFIG_COMPILER_OPTIMIZATION_SIZE=y +# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE=y +# CONFIG_COMPILER_CXX_EXCEPTIONS is not set +# CONFIG_COMPILER_CXX_RTTI is not set +CONFIG_COMPILER_STACK_CHECK_MODE_NONE=y +# CONFIG_COMPILER_STACK_CHECK_MODE_NORM is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_STRONG is not set +# CONFIG_COMPILER_STACK_CHECK_MODE_ALL is not set +# CONFIG_COMPILER_WARN_WRITE_STRINGS is not set +# CONFIG_COMPILER_DISABLE_GCC8_WARNINGS is not set +# CONFIG_COMPILER_DUMP_RTL_FILES is not set +# end of Compiler options + +# +# Component config +# + +# +# Application Level Tracing +# +# CONFIG_APPTRACE_DEST_TRAX is not set +CONFIG_APPTRACE_DEST_NONE=y +CONFIG_APPTRACE_LOCK_ENABLE=y +# end of Application Level Tracing + +# +# ESP-ASIO +# +# CONFIG_ASIO_SSL_SUPPORT is not set +# end of ESP-ASIO + +CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_EFF=0 +CONFIG_BTDM_CTRL_PCM_ROLE_EFF=0 +CONFIG_BTDM_CTRL_PCM_POLAR_EFF=0 +CONFIG_BTDM_CTRL_BLE_MAX_CONN_EFF=0 +CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN_EFF=0 +CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF=0 +CONFIG_BTDM_CTRL_PINNED_TO_CORE=0 +CONFIG_BTDM_BLE_SLEEP_CLOCK_ACCURACY_INDEX_EFF=1 +CONFIG_BT_CTRL_MODE_EFF=1 +CONFIG_BT_CTRL_BLE_MAX_ACT=10 +CONFIG_BT_CTRL_BLE_MAX_ACT_EFF=10 +CONFIG_BT_CTRL_BLE_STATIC_ACL_TX_BUF_NB=0 +CONFIG_BT_CTRL_PINNED_TO_CORE=0 +CONFIG_BT_CTRL_HCI_TL=1 +CONFIG_BT_CTRL_ADV_DUP_FILT_MAX=30 +CONFIG_BT_CTRL_HW_CCA_EFF=0 +CONFIG_BT_CTRL_DFT_TX_POWER_LEVEL_EFF=0 +CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_SUPP=y +CONFIG_BT_CTRL_BLE_ADV_REPORT_FLOW_CTRL_NUM=100 +CONFIG_BT_CTRL_BLE_ADV_REPORT_DISCARD_THRSHOLD=20 +CONFIG_BT_CTRL_BLE_SCAN_DUPL=y +CONFIG_BT_CTRL_SCAN_DUPL_TYPE=0 +CONFIG_BT_CTRL_SCAN_DUPL_CACHE_SIZE=100 +CONFIG_BT_CTRL_COEX_PHY_CODED_TX_RX_TLIM_EFF=0 +CONFIG_BT_CTRL_SLEEP_MODE_EFF=0 +CONFIG_BT_CTRL_SLEEP_CLOCK_EFF=0 +CONFIG_BT_CTRL_HCI_TL_EFF=1 +CONFIG_BT_RESERVE_DRAM=0 +CONFIG_BT_NIMBLE_USE_ESP_TIMER=y + +# +# CoAP Configuration +# +CONFIG_COAP_MBEDTLS_PSK=y +# CONFIG_COAP_MBEDTLS_PKI is not set +# CONFIG_COAP_MBEDTLS_DEBUG is not set +CONFIG_COAP_LOG_DEFAULT_LEVEL=0 +# end of CoAP Configuration + +# +# Driver configurations +# + +# +# ADC configuration +# +# CONFIG_ADC_FORCE_XPD_FSM is not set +CONFIG_ADC_DISABLE_DAC=y +# end of ADC configuration + +# +# SPI configuration +# +# CONFIG_SPI_MASTER_IN_IRAM is not set +CONFIG_SPI_MASTER_ISR_IN_IRAM=y +# CONFIG_SPI_SLAVE_IN_IRAM is not set +CONFIG_SPI_SLAVE_ISR_IN_IRAM=y +# end of SPI configuration + +# +# TWAI configuration +# +# CONFIG_TWAI_ISR_IN_IRAM is not set +# end of TWAI configuration + +# +# UART configuration +# +CONFIG_UART_ISR_IN_IRAM=y +# end of UART configuration +# end of Driver configurations + +# +# eFuse Bit Manager +# +# CONFIG_EFUSE_CUSTOM_TABLE is not set +# CONFIG_EFUSE_VIRTUAL is not set +CONFIG_EFUSE_MAX_BLK_LEN=256 +# end of eFuse Bit Manager + +# +# SPI RAM config +# +CONFIG_SPIRAM_BOOT_INIT=y +CONFIG_SPIRAM_IGNORE_NOTFOUND=y +CONFIG_SPIRAM_USE_MEMMAP=n +CONFIG_SPIRAM_USE_CAPS_ALLOC=n +CONFIG_SPIRAM_USE_MALLOC=y +CONFIG_SPIRAM_TYPE_AUTO=y +CONFIG_SPIRAM_TYPE_ESPPSRAM32=n +CONFIG_SPIRAM_TYPE_ESPPSRAM64=n +CONFIG_SPIRAM_SIZE=-1 +CONFIG_SPIRAM_SPEED_40M=y +# CONFIG_SPIRAM_MEMTEST is not set +CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=16384 +CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP=y +CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL=32768 +CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY=n +CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=n + +# +# ESP-TLS +# +CONFIG_ESP_TLS_USING_MBEDTLS=y +CONFIG_ESP_TLS_USE_DS_PERIPHERAL=y +# CONFIG_ESP_TLS_SERVER is not set +# CONFIG_ESP_TLS_PSK_VERIFICATION is not set +# CONFIG_ESP_TLS_INSECURE is not set +# end of ESP-TLS + + +# +# ESP32C3-Specific +# +CONFIG_ESP32C3_DEFAULT_CPU_FREQ_160=y +CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ=160 +# CONFIG_ESP32C3_REV_MIN_0 is not set +# CONFIG_ESP32C3_REV_MIN_1 is not set +# CONFIG_ESP32C3_REV_MIN_2 is not set +CONFIG_ESP32C3_REV_MIN_3=y +# CONFIG_ESP32C3_REV_MIN_4 is not set +CONFIG_ESP32C3_REV_MIN=3 +CONFIG_ESP32C3_DEBUG_OCDAWARE=y +CONFIG_ESP32C3_BROWNOUT_DET=y +CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_7=y +# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_ESP32C3_BROWNOUT_DET_LVL_SEL_2 is not set +CONFIG_ESP32C3_BROWNOUT_DET_LVL=7 +CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC_SYSTIMER=y +# CONFIG_ESP32C3_TIME_SYSCALL_USE_RTC is not set +# CONFIG_ESP32C3_TIME_SYSCALL_USE_SYSTIMER is not set +# CONFIG_ESP32C3_TIME_SYSCALL_USE_NONE is not set +CONFIG_ESP32C3_RTC_CLK_SRC_INT_RC=y +# CONFIG_ESP32C3_RTC_CLK_SRC_EXT_CRYS is not set +# CONFIG_ESP32C3_RTC_CLK_SRC_EXT_OSC is not set +# CONFIG_ESP32C3_RTC_CLK_SRC_INT_8MD256 is not set +CONFIG_ESP32C3_RTC_CLK_CAL_CYCLES=1024 +# CONFIG_ESP32C3_NO_BLOBS is not set +# end of ESP32C3-Specific + +# +# Cache config +# +CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB=y +# CONFIG_ESP32S2_INSTRUCTION_CACHE_16KB is not set +# CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B is not set +CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_32B=y +CONFIG_ESP32S2_DATA_CACHE_0KB=y +# CONFIG_ESP32S2_DATA_CACHE_8KB is not set +# CONFIG_ESP32S2_DATA_CACHE_16KB is not set +# CONFIG_ESP32S2_DATA_CACHE_LINE_16B is not set +CONFIG_ESP32S2_DATA_CACHE_LINE_32B=y +# CONFIG_ESP32S2_INSTRUCTION_CACHE_WRAP is not set +# CONFIG_ESP32S2_DATA_CACHE_WRAP is not set +# end of Cache config + +CONFIG_ESP32S2_SPIRAM_SUPPORT=y +# CONFIG_ESP32S2_TRAX is not set +CONFIG_ESP32S2_TRACEMEM_RESERVE_DRAM=0x0 +# CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE is not set +CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO=y +CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES=2 +# CONFIG_ESP32S2_ULP_COPROC_ENABLED is not set +CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM=0 +CONFIG_ESP32S2_DEBUG_OCDAWARE=y +# CONFIG_ESP32S2_DEBUG_STUBS_ENABLE is not set +CONFIG_ESP32S2_BROWNOUT_DET=y +CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_7=y +# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_2 is not set +# CONFIG_ESP32S2_BROWNOUT_DET_LVL_SEL_1 is not set +CONFIG_ESP32S2_BROWNOUT_DET_LVL=7 +CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC_FRC1=y +# CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC is not set +# CONFIG_ESP32S2_TIME_SYSCALL_USE_FRC1 is not set +# CONFIG_ESP32S2_TIME_SYSCALL_USE_NONE is not set +CONFIG_ESP32S2_RTC_CLK_SRC_INT_RC=y +# CONFIG_ESP32S2_RTC_CLK_SRC_EXT_CRYS is not set +# CONFIG_ESP32S2_RTC_CLK_SRC_EXT_OSC is not set +# CONFIG_ESP32S2_RTC_CLK_SRC_INT_8MD256 is not set +CONFIG_ESP32S2_RTC_CLK_CAL_CYCLES=576 +# CONFIG_ESP32S2_NO_BLOBS is not set +# CONFIG_ESP32S2_KEEP_USB_ALIVE is not set +# CONFIG_ESP32S2_RTCDATA_IN_FAST_MEM is not set +# CONFIG_ESP32S2_USE_FIXED_STATIC_RAM_SIZE is not set +# end of ESP32S2-specific + +# +# ADC-Calibration +# +# end of ADC-Calibration + +# config for XTAL freq +# adding it here, so it can be overriden by our CMake +CONFIG_ESP32_XTAL_FREQ_40=y + +# +# Common ESP-related +# +CONFIG_ESP_ERR_TO_NAME_LOOKUP=y +CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_ESP_MAIN_TASK_STACK_SIZE=3584 +CONFIG_ESP_IPC_TASK_STACK_SIZE=1024 +CONFIG_ESP_MINIMAL_SHARED_STACK_SIZE=2048 +CONFIG_ESP_CONSOLE_UART_DEFAULT=y +# CONFIG_ESP_CONSOLE_UART_CUSTOM is not set +# CONFIG_ESP_CONSOLE_NONE is not set +CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG is not set +CONFIG_ESP_CONSOLE_UART=y +CONFIG_ESP_CONSOLE_MULTIPLE_UART=y +CONFIG_ESP_CONSOLE_UART_NUM=0 +CONFIG_ESP_CONSOLE_UART_BAUDRATE=115200 +CONFIG_ESP_INT_WDT=y +CONFIG_ESP_INT_WDT_TIMEOUT_MS=300 +# CONFIG_ESP_TASK_WDT is not set +# CONFIG_ESP_TASK_WDT_PANIC is not set +# CONFIG_ESP_TASK_WDT_TIMEOUT_S is not set +# CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 is not set +# CONFIG_ESP_PANIC_HANDLER_IRAM is not set +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_STA=y +CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP=y +# end of Common ESP-related + +# +# Ethernet +# +# Parameters configured in binutils.ESP32.CMAKE +# +CONFIG_ETH_ENABLED=y +CONFIG_ETH_USE_ESP32_EMAC=y + +CONFIG_ETH_PHY_INTERFACE_RMII=y +# CONFIG_ETH_PHY_INTERFACE_MII is not set + +#CONFIG_ETH_RMII_CLK_OUTPUT=y +#CONFIG_ETH_RMII_CLK_OUT_GPIO=17 +#CONFIG_ETH_RMII_CLK_INPUT=y +#CONFIG_ETH_RMII_CLK_IN_GPIO=n + +CONFIG_ETH_DMA_BUFFER_SIZE=512 +CONFIG_ETH_DMA_RX_BUFFER_NUM=10 +CONFIG_ETH_DMA_TX_BUFFER_NUM=10 + +# Include SPI drivers in case used in build +CONFIG_ETH_USE_SPI_ETHERNET=y +#CONFIG_ETH_SPI_ETHERNET_DM9051=y +#CONFIG_ETH_SPI_ETHERNET_W5500=y +#CONFIG_ETH_SPI_ETHERNET_KSZ8851SNL=y +#CONFIG_ETH_USE_OPENETH=n +# end of Ethernet + +# +# Event Loop Library +# +# CONFIG_ESP_EVENT_LOOP_PROFILING is not set +CONFIG_ESP_EVENT_POST_FROM_ISR=y +CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR=y +# end of Event Loop Library + +# +# GDB Stub +# +# end of GDB Stub + +# +# ESP HTTP client +# +CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y +# CONFIG_ESP_HTTP_CLIENT_ENABLE_BASIC_AUTH is not set +# end of ESP HTTP client + +# +# HTTP Server +# +CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 +CONFIG_HTTPD_MAX_URI_LEN=512 +CONFIG_HTTPD_ERR_RESP_NO_DELAY=y +CONFIG_HTTPD_PURGE_BUF_LEN=32 +# CONFIG_HTTPD_LOG_PURGE_DATA is not set +# CONFIG_HTTPD_WS_SUPPORT is not set +# end of HTTP Server + +# +# ESP HTTPS OTA +# +# CONFIG_OTA_ALLOW_HTTP is not set +# end of ESP HTTPS OTA + +# +# ESP HTTPS server +# +# CONFIG_ESP_HTTPS_SERVER_ENABLE is not set +# end of ESP HTTPS server + +# +# ESP NETIF Adapter +# +CONFIG_ESP_NETIF_IP_LOST_TIMER_INTERVAL=120 +CONFIG_ESP_NETIF_TCPIP_LWIP=y +# CONFIG_ESP_NETIF_LOOPBACK is not set +# CONFIG_ESP_NETIF_TCPIP_ADAPTER_COMPATIBLE_LAYER is not set +# end of ESP NETIF Adapter + +# +# Power Management +# +CONFIG_PM_ENABLE=y +# end of Power Management + +# +# ESP System Settings +# +# CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is not set +CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT=y +# CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT is not set +# CONFIG_ESP_SYSTEM_PANIC_GDBSTUB is not set +CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE=y +CONFIG_ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK=y +CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP=y +CONFIG_ESP_SLEEP_POWER_DOWN_FLASH=y + +# +# Memory protection +# +CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=y +CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK=y +# end of Memory protection +# end of ESP System Settings + +# +# High resolution timer (esp_timer) +# +# CONFIG_ESP_TIMER_PROFILING is not set +CONFIG_ESP_TIME_FUNCS_USE_RTC_TIMER=y +CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER=y +CONFIG_ESP_TIMER_TASK_STACK_SIZE=3584 +CONFIG_ESP_TIMER_IMPL_SYSTIMER=y +# end of High resolution timer (esp_timer) + +# +# Wi-Fi +# +CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +# CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y +# CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER is not set +CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1 +CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=32 +# CONFIG_ESP32_WIFI_CSI_ENABLED is not set +CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP32_WIFI_TX_BA_WIN=6 +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +CONFIG_ESP32_WIFI_NVS_ENABLED=y +CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32 +# CONFIG_WIFI_LOG_DEFAULT_LEVEL_NONE is not set +# CONFIG_WIFI_LOG_DEFAULT_LEVEL_ERROR is not set +# CONFIG_WIFI_LOG_DEFAULT_LEVEL_WARN is not set +CONFIG_WIFI_LOG_DEFAULT_LEVEL_INFO=y +# CONFIG_WIFI_LOG_DEFAULT_LEVEL_DEBUG is not set +# CONFIG_WIFI_LOG_DEFAULT_LEVEL_VERBOSE is not set +CONFIG_ESP32_WIFI_IRAM_OPT=y +CONFIG_ESP32_WIFI_RX_IRAM_OPT=y +CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE=y +# CONFIG_ESP_WIFI_SLP_IRAM_OPT is not set +# CONFIG_ESP_WIFI_FTM_ENABLE is not set +# CONFIG_ESP_WIFI_STA_DISCONNECTED_PM_ENABLE is not set +# end of Wi-Fi + +# +# PHY +# +CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE=y +# CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set +CONFIG_ESP_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP_PHY_MAX_TX_POWER=20 +# end of PHY + +# +# Core dump +# +# CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH is not set +# CONFIG_ESP_COREDUMP_ENABLE_TO_UART is not set +CONFIG_ESP_COREDUMP_ENABLE_TO_NONE=y +# end of Core dump + +# +# FAT Filesystem support +# +# CONFIG_FATFS_CODEPAGE_DYNAMIC is not set +CONFIG_FATFS_CODEPAGE_437=y +# CONFIG_FATFS_CODEPAGE_720 is not set +# CONFIG_FATFS_CODEPAGE_737 is not set +# CONFIG_FATFS_CODEPAGE_771 is not set +# CONFIG_FATFS_CODEPAGE_775 is not set +# CONFIG_FATFS_CODEPAGE_850 is not set +# CONFIG_FATFS_CODEPAGE_852 is not set +# CONFIG_FATFS_CODEPAGE_855 is not set +# CONFIG_FATFS_CODEPAGE_857 is not set +# CONFIG_FATFS_CODEPAGE_860 is not set +# CONFIG_FATFS_CODEPAGE_861 is not set +# CONFIG_FATFS_CODEPAGE_862 is not set +# CONFIG_FATFS_CODEPAGE_863 is not set +# CONFIG_FATFS_CODEPAGE_864 is not set +# CONFIG_FATFS_CODEPAGE_865 is not set +# CONFIG_FATFS_CODEPAGE_866 is not set +# CONFIG_FATFS_CODEPAGE_869 is not set +# CONFIG_FATFS_CODEPAGE_932 is not set +# CONFIG_FATFS_CODEPAGE_936 is not set +# CONFIG_FATFS_CODEPAGE_949 is not set +# CONFIG_FATFS_CODEPAGE_950 is not set +CONFIG_FATFS_CODEPAGE=437 +# CONFIG_FATFS_LFN_NONE is not set +CONFIG_FATFS_LFN_HEAP=y +# CONFIG_FATFS_LFN_STACK is not set +CONFIG_FATFS_FS_LOCK=0 +CONFIG_FATFS_TIMEOUT_MS=10000 +CONFIG_FATFS_PER_FILE_CACHE=y +# CONFIG_FATFS_USE_FASTSEEK is not set +# end of FAT Filesystem support + +# +# Modbus configuration +# +CONFIG_FMB_COMM_MODE_TCP_EN=y +CONFIG_FMB_TCP_PORT_DEFAULT=502 +CONFIG_FMB_TCP_PORT_MAX_CONN=5 +CONFIG_FMB_TCP_CONNECTION_TOUT_SEC=20 +CONFIG_FMB_COMM_MODE_RTU_EN=y +CONFIG_FMB_COMM_MODE_ASCII_EN=y +CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND=150 +CONFIG_FMB_MASTER_DELAY_MS_CONVERT=200 +CONFIG_FMB_QUEUE_LENGTH=20 +CONFIG_FMB_PORT_TASK_STACK_SIZE=4096 +CONFIG_FMB_SERIAL_BUF_SIZE=256 +CONFIG_FMB_SERIAL_ASCII_BITS_PER_SYMB=8 +CONFIG_FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS=1000 +CONFIG_FMB_PORT_TASK_PRIO=10 +CONFIG_FMB_CONTROLLER_SLAVE_ID_SUPPORT=y +CONFIG_FMB_CONTROLLER_SLAVE_ID=0x00112233 +CONFIG_FMB_CONTROLLER_NOTIFY_TIMEOUT=20 +CONFIG_FMB_CONTROLLER_NOTIFY_QUEUE_SIZE=20 +CONFIG_FMB_CONTROLLER_STACK_SIZE=4096 +CONFIG_FMB_EVENT_QUEUE_TIMEOUT=20 +CONFIG_FMB_TIMER_PORT_ENABLED=y +CONFIG_FMB_TIMER_GROUP=0 +CONFIG_FMB_TIMER_INDEX=0 +# CONFIG_FMB_TIMER_ISR_IN_IRAM is not set +# end of Modbus configuration + +# +# FreeRTOS +# +# CONFIG_FREERTOS_UNICORE is not set +CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF +CONFIG_FREERTOS_CORETIMER_0=y +# CONFIG_FREERTOS_CORETIMER_1 is not set +CONFIG_FREERTOS_OPTIMIZED_SCHEDULER=y +CONFIG_FREERTOS_HZ=100 +CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y +# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set +CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y +CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 +CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y +# CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE is not set +# CONFIG_FREERTOS_ASSERT_DISABLE is not set +CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=2304 +CONFIG_FREERTOS_ISR_STACKSIZE=1536 +# CONFIG_FREERTOS_LEGACY_HOOKS is not set +CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 +CONFIG_FREERTOS_SUPPORT_STATIC_ALLOCATION=y +# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set +CONFIG_FREERTOS_TIMER_TASK_PRIORITY=5 +CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_FREERTOS_TIMER_QUEUE_LENGTH=10 +CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 +CONFIG_FREERTOS_USE_TICKLESS_IDLE=y +# CONFIG_FREERTOS_USE_TRACE_FACILITY is not set +# CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS is not set +CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y +CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y +# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set +# CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH is not set +CONFIG_FREERTOS_DEBUG_OCDAWARE=y +# end of FreeRTOS + +# +# Heap memory debugging +# +CONFIG_HEAP_POISONING_DISABLED=y +# CONFIG_HEAP_POISONING_LIGHT is not set +# CONFIG_HEAP_POISONING_COMPREHENSIVE is not set +CONFIG_HEAP_TRACING_OFF=y +# CONFIG_HEAP_TRACING_STANDALONE is not set +# CONFIG_HEAP_TRACING_TOHOST is not set +# CONFIG_HEAP_ABORT_WHEN_ALLOCATION_FAILS is not set +# end of Heap memory debugging + +# +# jsmn +# +# CONFIG_JSMN_PARENT_LINKS is not set +# CONFIG_JSMN_STRICT is not set +# end of jsmn + +# +# libsodium +# +# end of libsodium + +# +# Log output +# +# CONFIG_LOG_DEFAULT_LEVEL_NONE is not set +# CONFIG_LOG_DEFAULT_LEVEL_ERROR is not set +# CONFIG_LOG_DEFAULT_LEVEL_WARN is not set +CONFIG_LOG_DEFAULT_LEVEL_INFO=y +# CONFIG_LOG_DEFAULT_LEVEL_DEBUG is not set +# CONFIG_LOG_DEFAULT_LEVEL_VERBOSE is not set +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_LOG_COLORS=y +CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y +# CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM is not set +# end of Log output + +# +# LWIP +# +CONFIG_LWIP_LOCAL_HOSTNAME="nanodevice" +CONFIG_LWIP_DNS_SUPPORT_MDNS_QUERIES=y +# CONFIG_LWIP_L2_TO_L3_COPY is not set +# CONFIG_LWIP_IRAM_OPTIMIZATION is not set +CONFIG_LWIP_TIMERS_ONDEMAND=y +CONFIG_LWIP_MAX_SOCKETS=16 +# CONFIG_LWIP_USE_ONLY_LWIP_SELECT is not set +CONFIG_LWIP_SO_LINGER=y +CONFIG_LWIP_SO_REUSE=y +CONFIG_LWIP_SO_REUSE_RXTOALL=y +CONFIG_LWIP_SO_RCVBUF=y +# CONFIG_LWIP_NETBUF_RECVINFO is not set +CONFIG_LWIP_IP4_FRAG=y +CONFIG_LWIP_IP6_FRAG=y +# CONFIG_LWIP_IP4_REASSEMBLY is not set +# CONFIG_LWIP_IP6_REASSEMBLY is not set +# CONFIG_LWIP_IP_FORWARD is not set +# CONFIG_LWIP_STATS is not set +# CONFIG_LWIP_ETHARP_TRUST_IP_MAC is not set +CONFIG_LWIP_ESP_GRATUITOUS_ARP=y +CONFIG_LWIP_GARP_TMR_INTERVAL=60 +CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32 +CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y +# CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID is not set +# CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set +CONFIG_LWIP_DHCP_OPTIONS_LEN=80 + +# +# DHCP server +# +# CONFIG_LWIP_DHCPS is not set +CONFIG_LWIP_DHCPS_LEASE_UNIT=60 +CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 +# end of DHCP server + +# CONFIG_LWIP_AUTOIP is not set +# CONFIG_LWIP_IPV6 is not set +# CONFIG_LWIP_IPV6_AUTOCONFIG is not set +CONFIG_LWIP_NETIF_LOOPBACK=y +CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 + +# +# TCP +# +CONFIG_LWIP_MAX_ACTIVE_TCP=16 +CONFIG_LWIP_MAX_LISTENING_TCP=8 +CONFIG_LWIP_TCP_HIGH_SPEED_RETRANSMISSION=y +CONFIG_LWIP_TCP_MAXRTX=12 +CONFIG_LWIP_TCP_SYNMAXRTX=12 +CONFIG_LWIP_TCP_MSS=1440 +CONFIG_LWIP_TCP_TMR_INTERVAL=250 +CONFIG_LWIP_TCP_MSL=60000 +CONFIG_LWIP_TCP_SND_BUF_DEFAULT=5744 +CONFIG_LWIP_TCP_WND_DEFAULT=5744 +CONFIG_LWIP_TCP_RECVMBOX_SIZE=6 +CONFIG_LWIP_TCP_QUEUE_OOSEQ=y +# CONFIG_LWIP_TCP_SACK_OUT is not set +# CONFIG_LWIP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set +CONFIG_LWIP_TCP_OVERSIZE_MSS=y +# CONFIG_LWIP_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_LWIP_TCP_OVERSIZE_DISABLE is not set +CONFIG_LWIP_TCP_RTO_TIME=1500 +# end of TCP + +# +# UDP +# +CONFIG_LWIP_MAX_UDP_PCBS=16 +CONFIG_LWIP_UDP_RECVMBOX_SIZE=6 +# end of UDP + +# +# Checksums +# +# CONFIG_LWIP_CHECKSUM_CHECK_IP is not set +# CONFIG_LWIP_CHECKSUM_CHECK_UDP is not set +CONFIG_LWIP_CHECKSUM_CHECK_ICMP=y +# end of Checksums + +CONFIG_LWIP_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_LWIP_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +# CONFIG_LWIP_TCPIP_TASK_AFFINITY_CPU0 is not set +CONFIG_LWIP_TCPIP_TASK_AFFINITY=0x7FFFFFFF +# CONFIG_LWIP_PPP_SUPPORT is not set +CONFIG_LWIP_IPV6_MEMP_NUM_ND6_QUEUE=3 +CONFIG_LWIP_IPV6_ND6_NUM_NEIGHBORS=5 +# CONFIG_LWIP_SLIP_SUPPORT is not set + +# +# ICMP +# +CONFIG_LWIP_ICMP=y +# CONFIG_LWIP_MULTICAST_PING is not set +# CONFIG_LWIP_BROADCAST_PING is not set +# end of ICMP + +# +# LWIP RAW API +# +CONFIG_LWIP_MAX_RAW_PCBS=16 +# end of LWIP RAW API + +# +# SNTP +# +CONFIG_LWIP_DHCP_MAX_NTP_SERVERS=1 +CONFIG_LWIP_SNTP_UPDATE_DELAY=3600000 +# end of SNTP + +CONFIG_LWIP_ESP_LWIP_ASSERT=y + +# +# Hooks +# +# CONFIG_LWIP_HOOK_TCP_ISN_NONE is not set +CONFIG_LWIP_HOOK_TCP_ISN_DEFAULT=y +# CONFIG_LWIP_HOOK_TCP_ISN_CUSTOM is not set +CONFIG_LWIP_HOOK_IP6_ROUTE_NONE=y +# CONFIG_LWIP_HOOK_IP6_ROUTE_DEFAULT is not set +# CONFIG_LWIP_HOOK_IP6_ROUTE_CUSTOM is not set +CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_NONE=y +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_DEFAULT is not set +# CONFIG_LWIP_HOOK_NETCONN_EXT_RESOLVE_CUSTOM is not set +# end of Hooks + +# CONFIG_LWIP_DEBUG is not set +# end of LWIP + +# +# mbedTLS +# +# CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC is not set +CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC=y +# CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC is not set +CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN=y +CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN=16384 +CONFIG_MBEDTLS_SSL_OUT_CONTENT_LEN=4096 +CONFIG_MBEDTLS_DYNAMIC_BUFFER=y +# CONFIG_MBEDTLS_DEBUG=y + +# +# Certificate Bundle +# +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE is not set +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_FULL is not set +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_CMN is not set +# CONFIG_MBEDTLS_CERTIFICATE_BUNDLE_DEFAULT_NONE is not set +# CONFIG_MBEDTLS_CUSTOM_CERTIFICATE_BUNDLE is not set +# end of Certificate Bundle + +CONFIG_MBEDTLS_ECP_RESTARTABLE=y +CONFIG_MBEDTLS_CMAC_C=y +CONFIG_MBEDTLS_HARDWARE_AES=y +CONFIG_MBEDTLS_AES_USE_INTERRUPT=y +CONFIG_MBEDTLS_HARDWARE_GCM=y +CONFIG_MBEDTLS_HARDWARE_MPI=y +CONFIG_MBEDTLS_HARDWARE_SHA=y +CONFIG_MBEDTLS_ROM_MD5=y +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_SIGN is not set +# CONFIG_MBEDTLS_ATCA_HW_ECDSA_VERIFY is not set +CONFIG_MBEDTLS_HAVE_TIME=y +CONFIG_MBEDTLS_HAVE_TIME_DATE=y +CONFIG_MBEDTLS_ECDSA_DETERMINISTIC=y +CONFIG_MBEDTLS_SHA512_C=y +CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y +# CONFIG_MBEDTLS_TLS_SERVER_ONLY is not set +# CONFIG_MBEDTLS_TLS_CLIENT_ONLY is not set +# CONFIG_MBEDTLS_TLS_DISABLED is not set +CONFIG_MBEDTLS_TLS_SERVER=y +CONFIG_MBEDTLS_TLS_CLIENT=y +CONFIG_MBEDTLS_TLS_ENABLED=y + +# +# TLS Key Exchange Methods +# +# CONFIG_MBEDTLS_PSK_MODES is not set +CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y +# end of TLS Key Exchange Methods + +CONFIG_MBEDTLS_SSL_RENEGOTIATION=y +# CONFIG_MBEDTLS_SSL_PROTO_SSL3 is not set +CONFIG_MBEDTLS_SSL_PROTO_TLS1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y +# CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set +CONFIG_MBEDTLS_SSL_ALPN=y +# CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS is not set +CONFIG_MBEDTLS_X509_CHECK_KEY_USAGE=y +CONFIG_MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE=y +CONFIG_MBEDTLS_SERVER_SSL_SESSION_TICKETS=y + +# +# Symmetric Ciphers +# +CONFIG_MBEDTLS_AES_C=y +# CONFIG_MBEDTLS_CAMELLIA_C is not set +CONFIG_MBEDTLS_DES_C=y +CONFIG_MBEDTLS_RC4_DISABLED=y +# CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT is not set +# CONFIG_MBEDTLS_RC4_ENABLED is not set +# CONFIG_MBEDTLS_BLOWFISH_C is not set +CONFIG_MBEDTLS_XTEA_C=y +CONFIG_MBEDTLS_CCM_C=y +CONFIG_MBEDTLS_GCM_C=y +# CONFIG_MBEDTLS_NIST_KW_C is not set +# end of Symmetric Ciphers + +# CONFIG_MBEDTLS_RIPEMD160_C=y + +# +# Certificates +# +CONFIG_MBEDTLS_PEM_PARSE_C=y +# CONFIG_MBEDTLS_PEM_WRITE_C is not set +CONFIG_MBEDTLS_X509_CRL_PARSE_C=y +CONFIG_MBEDTLS_X509_CSR_PARSE_C=y +# end of Certificates + +CONFIG_MBEDTLS_ECP_C=y +CONFIG_MBEDTLS_ECDH_C=y +CONFIG_MBEDTLS_ECDSA_C=y +# CONFIG_MBEDTLS_ECJPAKE_C is not set +CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y +CONFIG_MBEDTLS_ECP_NIST_OPTIM=y +# CONFIG_MBEDTLS_POLY1305_C is not set +# CONFIG_MBEDTLS_CHACHA20_C is not set +# CONFIG_MBEDTLS_HKDF_C is not set +# CONFIG_MBEDTLS_THREADING_C is not set +# CONFIG_MBEDTLS_LARGE_KEY_SOFTWARE_MPI is not set +# CONFIG_MBEDTLS_SECURITY_RISKS is not set +# end of mbedTLS + +# +# mDNS +# +CONFIG_MDNS_MAX_SERVICES=10 +CONFIG_MDNS_TASK_PRIORITY=1 +CONFIG_MDNS_TASK_STACK_SIZE=4096 +# CONFIG_MDNS_TASK_AFFINITY_NO_AFFINITY is not set +CONFIG_MDNS_TASK_AFFINITY_CPU0=y +CONFIG_MDNS_TASK_AFFINITY=0x0 +CONFIG_MDNS_SERVICE_ADD_TIMEOUT_MS=2000 +# CONFIG_MDNS_STRICT_MODE is not set +CONFIG_MDNS_TIMER_PERIOD_MS=100 +# end of mDNS + +# +# ESP-MQTT Configurations +# +CONFIG_MQTT_PROTOCOL_311=y +CONFIG_MQTT_TRANSPORT_SSL=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y +# CONFIG_MQTT_MSG_ID_INCREMENTAL is not set +# CONFIG_MQTT_SKIP_PUBLISH_IF_DISCONNECTED is not set +# CONFIG_MQTT_REPORT_DELETED_MESSAGES is not set +# CONFIG_MQTT_USE_CUSTOM_CONFIG is not set +# CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED is not set +# CONFIG_MQTT_CUSTOM_OUTBOX is not set +# end of ESP-MQTT Configurations + +# +# Newlib +# +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set +CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y +# CONFIG_NEWLIB_NANO_FORMAT is not set +# end of Newlib + +# +# NVS +# +# end of NVS + +# +# OpenSSL +# +# CONFIG_OPENSSL_DEBUG is not set +CONFIG_OPENSSL_ERROR_STACK=y +# CONFIG_OPENSSL_ASSERT_DO_NOTHING is not set +CONFIG_OPENSSL_ASSERT_EXIT=y +# end of OpenSSL + +# +# PThreads +# +CONFIG_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_PTHREAD_STACK_MIN=768 +CONFIG_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_PTHREAD_TASK_NAME_DEFAULT="pthread" +# end of PThreads + +# +# SPI Flash driver +# +# CONFIG_SPI_FLASH_VERIFY_WRITE is not set +# CONFIG_SPI_FLASH_ENABLE_COUNTERS is not set +CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y +CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set +# CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set +# CONFIG_SPI_FLASH_USE_LEGACY_IMPL is not set +# CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set +CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y +CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20 +CONFIG_SPI_FLASH_ERASE_YIELD_TICKS=1 +CONFIG_SPI_FLASH_WRITE_CHUNK_SIZE=8192 +# CONFIG_SPI_FLASH_SIZE_OVERRIDE is not set +# CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED is not set + +# +# Auto-detect flash chips +# +CONFIG_SPI_FLASH_SUPPORT_ISSI_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_MXIC_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_GD_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_WINBOND_CHIP=y +CONFIG_SPI_FLASH_SUPPORT_BOYA_CHIP=y +# end of Auto-detect flash chips + +CONFIG_SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE=y +# end of SPI Flash driver + +# +# SPIFFS Configuration +# +CONFIG_SPIFFS_MAX_PARTITIONS=3 + +# +# SPIFFS Cache Configuration +# +CONFIG_SPIFFS_CACHE=y +CONFIG_SPIFFS_CACHE_WR=y +# CONFIG_SPIFFS_CACHE_STATS is not set +# end of SPIFFS Cache Configuration + +CONFIG_SPIFFS_PAGE_CHECK=y +CONFIG_SPIFFS_GC_MAX_RUNS=10 +# CONFIG_SPIFFS_GC_STATS is not set +CONFIG_SPIFFS_PAGE_SIZE=256 +CONFIG_SPIFFS_OBJ_NAME_LEN=32 +# CONFIG_SPIFFS_FOLLOW_SYMLINKS is not set +CONFIG_SPIFFS_USE_MAGIC=y +CONFIG_SPIFFS_USE_MAGIC_LENGTH=y +CONFIG_SPIFFS_META_LENGTH=4 +CONFIG_SPIFFS_USE_MTIME=y + +# +# Debug Configuration +# +# CONFIG_SPIFFS_DBG is not set +# CONFIG_SPIFFS_API_DBG is not set +# CONFIG_SPIFFS_GC_DBG is not set +# CONFIG_SPIFFS_CACHE_DBG is not set +# CONFIG_SPIFFS_CHECK_DBG is not set +# CONFIG_SPIFFS_TEST_VISUALISATION is not set +# end of Debug Configuration +# end of SPIFFS Configuration + +# +# TCP Transport +# + +# +# Websocket +# +CONFIG_WS_TRANSPORT=y +CONFIG_WS_BUFFER_SIZE=1024 +# end of Websocket +# end of TCP Transport + +# +# TinyUSB +# +CONFIG_USB_ENABLED=y +CONFIG_USB_CDC_ENABLED=y +CONFIG_USB_DESC_CDC_STRING=".NET nanoFramework device" +CONFIG_USB_CDC_RX_BUFSIZE=64 +# setting this to WP packet size +CONFIG_USB_CDC_TX_BUFSIZE=1024 +# end of TinyUSB + +# +# Unity unit testing library +# +CONFIG_UNITY_ENABLE_FLOAT=y +CONFIG_UNITY_ENABLE_DOUBLE=y +# CONFIG_UNITY_ENABLE_COLOR is not set +CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y +# CONFIG_UNITY_ENABLE_FIXTURE is not set +# CONFIG_UNITY_ENABLE_BACKTRACE_ON_FAIL is not set +# end of Unity unit testing library + +# +# Virtual file system +# +CONFIG_VFS_SUPPORT_IO=y +CONFIG_VFS_SUPPORT_DIR=y +CONFIG_VFS_SUPPORT_SELECT=y +CONFIG_VFS_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_VFS_SUPPORT_TERMIOS=y + +# +# Host File System I/O (Semihosting) +# +CONFIG_VFS_SEMIHOSTFS_MAX_MOUNT_POINTS=1 +CONFIG_VFS_SEMIHOSTFS_HOST_PATH_MAX_LEN=128 +# end of Host File System I/O (Semihosting) +# end of Virtual file system + +# +# Wear Levelling +# +# CONFIG_WL_SECTOR_SIZE_512 is not set +CONFIG_WL_SECTOR_SIZE_4096=y +CONFIG_WL_SECTOR_SIZE=4096 +# end of Wear Levelling + +# +# Wi-Fi Provisioning Manager +# +CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16 +CONFIG_WIFI_PROV_AUTOSTOP_TIMEOUT=30 +# end of Wi-Fi Provisioning Manager + +# +# Supplicant +# +CONFIG_WPA_MBEDTLS_CRYPTO=y +# CONFIG_WPA_WAPI_PSK is not set +# CONFIG_WPA_DEBUG_PRINT is not set +# CONFIG_WPA_TESTING_OPTIONS is not set +# CONFIG_WPA_WPS_STRICT is not set +# CONFIG_WPA_11KV_SUPPORT is not set +# end of Supplicant +# end of Component config diff --git a/targets/ESP32/_common/DeviceMapping_common.cpp b/targets/ESP32/_common/DeviceMapping_common.cpp index c4de68acfe..0230f0ad6f 100644 --- a/targets/ESP32/_common/DeviceMapping_common.cpp +++ b/targets/ESP32/_common/DeviceMapping_common.cpp @@ -49,8 +49,10 @@ int Esp32_GetMappedDevicePins(Esp32_MapDeviceType deviceType, int busIndex, int case DEV_TYPE_ADC: return (int)Esp32_ADC_DevicePinMap[pinIndex]; +#if !defined(CONFIG_IDF_TARGET_ESP32C3) case DEV_TYPE_DAC: return (int)Esp32_DAC_DevicePinMap[pinIndex]; +#endif case DEV_TYPE_I2S: return (int)Esp32_I2S_DevicePinMap[busIndex][pinIndex]; @@ -88,9 +90,11 @@ void Esp32_SetMappedDevicePins(Esp32_MapDeviceType deviceType, int busIndex, int Esp32_ADC_DevicePinMap[pinIndex] = ioPinNumber; break; +#if !defined(CONFIG_IDF_TARGET_ESP32C3) case DEV_TYPE_DAC: Esp32_DAC_DevicePinMap[pinIndex] = ioPinNumber; break; +#endif case DEV_TYPE_I2S: Esp32_I2S_DevicePinMap[busIndex][pinIndex] = ioPinNumber; diff --git a/targets/ESP32/_common/ESP32_C3_DeviceMapping.cpp b/targets/ESP32/_common/ESP32_C3_DeviceMapping.cpp new file mode 100644 index 0000000000..5d2fa823b5 --- /dev/null +++ b/targets/ESP32/_common/ESP32_C3_DeviceMapping.cpp @@ -0,0 +1,85 @@ +// +// Copyright (c) .NET Foundation and Contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// SPI +// 2 devices +// Map pins mosi, miso, clock +// +int8_t Esp32_SPI_DevicePinMap[MAX_SPI_DEVICES][Esp32SpiPin_Max] = { + // SPI1 - use defaults from IDF sample + {SPI_IOMUX_PIN_NUM_MOSI, SPI_IOMUX_PIN_NUM_MISO, SPI_IOMUX_PIN_NUM_CLK}, + // SPI2 - no pins assigned + {-1, -1, -1}}; + +// Serial +// 2 devices COM1,COM2 ( UART_NUM_0, UART_NUM_1 ) +// Map pins Tx, RX, RTS, CTS +// Set pins to default for UART_NUM_0 +// others assign as NONE because the default pins can be shared with serial flash and PSRAM +int8_t Esp32_SERIAL_DevicePinMap[UART_NUM_MAX][Esp32SerialPin_Max] = { + // COM 1 - pins 21, 20 + {UART_NUM_0_TXD_DIRECT_GPIO_NUM, + UART_NUM_0_RXD_DIRECT_GPIO_NUM, + UART_PIN_NO_CHANGE, + UART_PIN_NO_CHANGE}, + +#if defined(UART_NUM_2) + // COM 2 - all set to UART_PIN_NO_CHANGE + {UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE}, +#endif +}; + +// ============================================= +// I2C +// 1 devices I2C1 +// Map pins Data & Clock +int8_t Esp32_I2C_DevicePinMap[I2C_NUM_MAX][2] = { + // I2C1 - pins 18, 19, + {I2C1_DATA, I2C1_CLOCK}}; + +// ============================================= +// LED PWM +// 16 channels LED1 to LED16 or PWM1 to PWM16 +// Map pins Data & Clock +int8_t Esp32_LED_DevicePinMap[16] = { + // Channels ( non assigned ) + -1, // 1 + -1, // 2 + -1, // 3 + -1, // 4 + -1, // 5 + -1, // 6 + -1, // 7 + -1, // 8 + -1, // 9 + -1, // 10 + -1, // 11 + -1, // 12 + -1, // 13 + -1, // 14 + -1, // 15 + -1, // 16 +}; + +// We use "ADC1" for 20 logical channels +// Mapped to ESP32 controllers +// ESP32 ADC1 channels 0 - 7 +// " ADC1 channel 8 - Internal Temperature sensor (VP) +// " ADC1 channel 9 - Internal Hall Sensor (VN) +// " ADC2 channels 10 - 19 +// TODO review ADC channels for ESP32_C3 +int8_t Esp32_ADC_DevicePinMap[6] = { + // 0 1 2 3 4 5 + 0, 1, 2, 3, 4, 5}; + +// I2S +// 1 device I2S1 +// Map pins various pins. If not used, I2S_PIN_NO_CHANGE is used +int8_t Esp32_I2S_DevicePinMap[I2S_NUM_MAX][5] = { + // No pin pre configured + {I2S_PIN_NO_CHANGE, I2S_PIN_NO_CHANGE, I2S_PIN_NO_CHANGE, I2S_PIN_NO_CHANGE, I2S_PIN_NO_CHANGE}}; diff --git a/targets/ESP32/_common/Target_Windows_Storage.c b/targets/ESP32/_common/Target_Windows_Storage.c index e500f4acd4..b2224850f4 100644 --- a/targets/ESP32/_common/Target_Windows_Storage.c +++ b/targets/ESP32/_common/Target_Windows_Storage.c @@ -39,9 +39,9 @@ #include #include -static const char *TAG = "SDCard"; +#if !defined(CONFIG_IDF_TARGET_ESP32C3) && (HAL_USE_SDC == TRUE) -#if (HAL_USE_SDC == TRUE) +static const char *TAG = "SDCard"; // // Unmount SD card ( MMC/SDIO or SPI) diff --git a/targets/ESP32/_common/WireProtocol_HAL_Interface.c b/targets/ESP32/_common/WireProtocol_HAL_Interface.c index 76d1c51473..26ffad51ba 100644 --- a/targets/ESP32/_common/WireProtocol_HAL_Interface.c +++ b/targets/ESP32/_common/WireProtocol_HAL_Interface.c @@ -52,11 +52,20 @@ static uart_port_t ESP32_WP_UART = UART_NUM_0; #elif CONFIG_IDF_TARGET_ESP32S3 -// NOT IMPLEMENTED (YET) +#error "NOT IMPLEMENTED (YET)" #elif CONFIG_IDF_TARGET_ESP32C3 -// NOT IMPLEMENTED (YET) + +// WP uses UART0 +static uart_port_t ESP32_WP_UART = UART_NUM_0; + +// UART pins for ESP32-C3 +// U0RXD 20 +// U0TXD 21 + +#define ESP32_WP_RX_PIN UART_NUM_0_RXD_DIRECT_GPIO_NUM +#define ESP32_WP_TX_PIN UART_NUM_0_TXD_DIRECT_GPIO_NUM #endif diff --git a/targets/ESP32/_common/targetHAL.c b/targets/ESP32/_common/targetHAL.c index 1b0fbb666d..442a909f08 100644 --- a/targets/ESP32/_common/targetHAL.c +++ b/targets/ESP32/_common/targetHAL.c @@ -9,7 +9,11 @@ inline void HAL_AssertEx() { +#if defined(__riscv) + asm("ebreak"); +#else asm("break.n 1"); +#endif while (true) { // nop @@ -20,7 +24,11 @@ inline void HAL_AssertEx() inline void HARD_Breakpoint() { +#if defined(__riscv) + asm("ebreak"); +#else asm("break.n 1"); +#endif while (true) { // nop diff --git a/targets/ESP32/_include/Esp32_DeviceMapping.h b/targets/ESP32/_include/Esp32_DeviceMapping.h index edaded1085..0a92700063 100644 --- a/targets/ESP32/_include/Esp32_DeviceMapping.h +++ b/targets/ESP32/_include/Esp32_DeviceMapping.h @@ -55,9 +55,14 @@ extern int8_t Esp32_I2C_DevicePinMap[I2C_NUM_MAX][2]; extern int8_t Esp32_I2S_DevicePinMap[I2S_NUM_MAX][5]; extern int8_t Esp32_SERIAL_DevicePinMap[UART_NUM_MAX][Esp32SerialPin_Max]; extern int8_t Esp32_LED_DevicePinMap[16]; -extern int8_t Esp32_ADC_DevicePinMap[20]; extern int8_t Esp32_DAC_DevicePinMap[2]; +#if defined(CONFIG_IDF_TARGET_ESP32C3) +extern int8_t Esp32_ADC_DevicePinMap[6]; +#else +extern int8_t Esp32_ADC_DevicePinMap[20]; +#endif + void Esp32_DecodeAlternateFunction( uint32_t alternateFunction, Esp32_MapDeviceType &deviceType, diff --git a/targets/ESP32/_include/esp32_idf.h b/targets/ESP32/_include/esp32_idf.h index e659b3e2cc..daf46f917f 100644 --- a/targets/ESP32/_include/esp32_idf.h +++ b/targets/ESP32/_include/esp32_idf.h @@ -11,6 +11,10 @@ #include #include +#if defined(CONFIG_IDF_TARGET_ESP32C3) +#include +#endif + #include #include #include @@ -34,8 +38,18 @@ #define CONFIG_LOG_TIMESTAMP_SOURCE_RTOS 1 #endif +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wformat" +#endif + #include +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wformat" +#endif + #include #include #include @@ -43,7 +57,9 @@ #include #include #include +#if defined(CONFIG_IDF_TARGET_ESP32) || defined(CONFIG_IDF_TARGET_ESP32S2) #include +#endif #include #include #include diff --git a/targets/ESP32/_nanoCLR/System.Device.Gpio/cpu_gpio.cpp b/targets/ESP32/_nanoCLR/System.Device.Gpio/cpu_gpio.cpp index 0a6eba8a91..a2d1a01ee0 100644 --- a/targets/ESP32/_nanoCLR/System.Device.Gpio/cpu_gpio.cpp +++ b/targets/ESP32/_nanoCLR/System.Device.Gpio/cpu_gpio.cpp @@ -325,7 +325,11 @@ static void gpio_isr(void *arg) if (xHigherPriorityTaskWoken != pdFAIL) { +#if defined(CONFIG_IDF_TARGET_ESP32C3) + portYIELD_FROM_ISR(); +#else portYIELD_FROM_ISR(xHigherPriorityTaskWoken); +#endif } } else diff --git a/targets/ESP32/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp b/targets/ESP32/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp index 0eab267ba9..0a0efb4f27 100644 --- a/targets/ESP32/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp +++ b/targets/ESP32/_nanoCLR/System.Device.I2c/sys_dev_i2c_native_System_Device_I2c_I2cDevice.cpp @@ -15,7 +15,13 @@ typedef Library_sys_dev_i2c_native_System_Device_I2c_I2cConnectionSettings I2cCo typedef Library_sys_dev_i2c_native_System_Device_I2c_I2cTransferResult I2cTransferResult; typedef Library_corlib_native_System_SpanByte SpanByte; -static char Esp_I2C_Initialised_Flag[I2C_NUM_MAX] = {0, 0}; +static char Esp_I2C_Initialised_Flag[I2C_NUM_MAX] = { + 0 +#if I2C_NUM_MAX > 1 + , + 0 +#endif +}; void Esp32_I2c_UnitializeAll() { @@ -70,7 +76,11 @@ HRESULT Library_sys_dev_i2c_native_System_Device_I2c_I2cDevice::NativeInit___VOI // subtract 1 to get ESP32 bus number i2c_port_t bus = (i2c_port_t)(pConfig[I2cConnectionSettings::FIELD___busId].NumericByRef().s4 - 1); - if (bus != I2C_NUM_0 && bus != I2C_NUM_1) + if (bus != I2C_NUM_0 +#if I2C_NUM_MAX > 1 + && bus != I2C_NUM_1 +#endif + ) { NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); } diff --git a/targets/ESP32/_nanoCLR/System.Device.Spi/cpu_spi.cpp b/targets/ESP32/_nanoCLR/System.Device.Spi/cpu_spi.cpp index 0a98fddd3f..fa351358a5 100644 --- a/targets/ESP32/_nanoCLR/System.Device.Spi/cpu_spi.cpp +++ b/targets/ESP32/_nanoCLR/System.Device.Spi/cpu_spi.cpp @@ -143,10 +143,19 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &spiDev // First available bus on ESP32 is HSPI_HOST(1) // Try with DMA first +#if defined(CONFIG_IDF_TARGET_ESP32C3) + esp_err_t ret = spi_bus_initialize((spi_host_device_t)(busIndex), &bus_config, SPI_DMA_CH_AUTO); +#else esp_err_t ret = spi_bus_initialize((spi_host_device_t)(busIndex + HSPI_HOST), &bus_config, SPI_DMA_CH_AUTO); +#endif + if (ret != ESP_OK) { +#if defined(CONFIG_IDF_TARGET_ESP32C3) + ESP_LOGE(TAG, "Unable to init SPI bus %d esp_err %d", busIndex, ret); +#else ESP_LOGE(TAG, "Unable to init SPI bus %d esp_err %d", busIndex + HSPI_HOST, ret); +#endif return false; } @@ -161,10 +170,20 @@ bool CPU_SPI_Initialize(uint8_t busIndex, const SPI_DEVICE_CONFIGURATION &spiDev // Uninitialise the bus bool CPU_SPI_Uninitialize(uint8_t busIndex) { +#if defined(CONFIG_IDF_TARGET_ESP32C3) + esp_err_t ret = spi_bus_free((spi_host_device_t)(busIndex)); +#else esp_err_t ret = spi_bus_free((spi_host_device_t)(busIndex + HSPI_HOST)); +#endif + if (ret != ESP_OK) { +#if defined(CONFIG_IDF_TARGET_ESP32C3) + ESP_LOGE(TAG, "spi_bus_free bus %d esp_err %d", busIndex, ret); +#else ESP_LOGE(TAG, "spi_bus_free bus %d esp_err %d", busIndex + HSPI_HOST, ret); +#endif + return false; } @@ -214,7 +233,7 @@ spi_device_interface_config_t GetConfig(const SPI_DEVICE_CONFIGURATION &spiDevic { int csPin = spiDeviceConfig.DeviceChipSelect; uint8_t spiMode = spiDeviceConfig.Spi_Mode; - int clockHz = spiDeviceConfig.Clock_RateHz; + int32_t clockHz = spiDeviceConfig.Clock_RateHz; // if clock frequency is unset use the maximum frequency if (clockHz == 0) @@ -279,8 +298,13 @@ HRESULT CPU_SPI_Add_Device(const SPI_DEVICE_CONFIGURATION &spiDeviceConfig, uint spi_device_handle_t deviceHandle; // First available bus on ESP32 is HSPI_HOST(1) +#if defined(CONFIG_IDF_TARGET_ESP32C3) + esp_err_t ret = spi_bus_add_device((spi_host_device_t)(spiDeviceConfig.Spi_Bus), &dev_config, &deviceHandle); +#else esp_err_t ret = spi_bus_add_device((spi_host_device_t)(spiDeviceConfig.Spi_Bus + HSPI_HOST), &dev_config, &deviceHandle); +#endif + if (ret != ESP_OK) { ESP_LOGE(TAG, "Unable to init SPI device, esp_err %d", ret); diff --git a/targets/ESP32/_nanoCLR/nanoFramework.Hardware.ESP32/nanoFramework_hardware_esp32_native_Hardware_Esp32_Sleep.cpp b/targets/ESP32/_nanoCLR/nanoFramework.Hardware.ESP32/nanoFramework_hardware_esp32_native_Hardware_Esp32_Sleep.cpp index 9b4879410b..dec5882ac7 100644 --- a/targets/ESP32/_nanoCLR/nanoFramework.Hardware.ESP32/nanoFramework_hardware_esp32_native_Hardware_Esp32_Sleep.cpp +++ b/targets/ESP32/_nanoCLR/nanoFramework.Hardware.ESP32/nanoFramework_hardware_esp32_native_Hardware_Esp32_Sleep.cpp @@ -30,30 +30,44 @@ HRESULT Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32 CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); - { - uint64_t mask = (uint64_t)stack.Arg0().NumericByRef().s8; - int level = stack.Arg1().NumericByRef().s4; - // Extract pin number from mask value - gpio_num_t gpio_num = GPIO_NUM_0; - esp_err_t err = 0; - if (mask) // Only enable pin if other than Pin.None +#if SOC_PM_SUPPORT_EXT_WAKEUP + + gpio_num_t gpio_num; + esp_err_t err; + + uint64_t mask = (uint64_t)stack.Arg0().NumericByRef().s8; + int level = stack.Arg1().NumericByRef().s4; + + // Extract pin number from mask value + gpio_num = GPIO_NUM_0; + err = 0; + + if (mask) // Only enable pin if other than Pin.None + { + for (size_t i = 0; i < GPIO_NUM_MAX; i++) { - for (size_t i = 0; i < GPIO_NUM_MAX; i++) + if (mask & 0x01) { - if (mask & 0x01) - { - gpio_num = (gpio_num_t)i; - } - mask >>= 1; + gpio_num = (gpio_num_t)i; } - err = esp_sleep_enable_ext0_wakeup(gpio_num, level); + mask >>= 1; } - - // Return err to the managed application - stack.SetResult_I4((int)err); + err = esp_sleep_enable_ext0_wakeup(gpio_num, level); } + + // Return err to the managed application + stack.SetResult_I4((int)err); + NANOCLR_NOCLEANUP_NOLABEL(); + +#else + + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + NANOCLR_NOCLEANUP(); + +#endif } HRESULT Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Sleep:: @@ -61,29 +75,49 @@ HRESULT Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32 CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); - { - uint64_t mask = (uint64_t)stack.Arg0().NumericByRef().s8; - esp_sleep_ext1_wakeup_mode_t mode = (esp_sleep_ext1_wakeup_mode_t)stack.Arg1().NumericByRef().s4; - esp_err_t err = esp_sleep_enable_ext1_wakeup(mask, mode); +#if SOC_PM_SUPPORT_EXT_WAKEUP + + uint64_t mask = (uint64_t)stack.Arg0().NumericByRef().s8; + esp_sleep_ext1_wakeup_mode_t mode = (esp_sleep_ext1_wakeup_mode_t)stack.Arg1().NumericByRef().s4; + + esp_err_t err = esp_sleep_enable_ext1_wakeup(mask, mode); + + // Return err to the managed application + stack.SetResult_I4((int)err); - // Return err to the managed application - stack.SetResult_I4((int)err); - } NANOCLR_NOCLEANUP_NOLABEL(); + +#else + + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + NANOCLR_NOCLEANUP(); + +#endif } HRESULT Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Sleep:: NativeEnableWakeupByTouchPad___STATIC__nanoFrameworkHardwareEsp32EspNativeError(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); - { - esp_err_t err = esp_sleep_enable_touchpad_wakeup(); - // Return err to the managed application - stack.SetResult_I4((int)err); - } +#if SOC_PM_SUPPORT_EXT_WAKEUP + + esp_err_t err = esp_sleep_enable_touchpad_wakeup(); + + // Return err to the managed application + stack.SetResult_I4((int)err); + NANOCLR_NOCLEANUP_NOLABEL(); + +#else + + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + NANOCLR_NOCLEANUP(); + +#endif } HRESULT Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Sleep:: @@ -131,37 +165,67 @@ HRESULT Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32 NativeGetWakeupCause___STATIC__nanoFrameworkHardwareEsp32SleepWakeupCause(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); - { - esp_sleep_wakeup_cause_t cause = esp_sleep_get_wakeup_cause(); - // Return value to the managed application - stack.SetResult_I4((int32_t)cause); - } +#if SOC_PM_SUPPORT_EXT_WAKEUP + + esp_sleep_wakeup_cause_t cause = esp_sleep_get_wakeup_cause(); + + // Return value to the managed application + stack.SetResult_I4((int32_t)cause); + NANOCLR_NOCLEANUP_NOLABEL(); + +#else + + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + NANOCLR_NOCLEANUP(); + +#endif } HRESULT Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Sleep:: NativeGetWakeupGpioPin___STATIC__nanoFrameworkHardwareEsp32SleepWakeupGpioPin(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); - { - int64_t pin = (int64_t)esp_sleep_get_ext1_wakeup_status(); - // Return value to the managed application - stack.SetResult_I8(pin); - } +#if SOC_PM_SUPPORT_EXT_WAKEUP + + int64_t pin = (int64_t)esp_sleep_get_ext1_wakeup_status(); + + // Return value to the managed application + stack.SetResult_I8(pin); + NANOCLR_NOCLEANUP_NOLABEL(); + +#else + + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + NANOCLR_NOCLEANUP(); + +#endif } HRESULT Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Sleep:: NativeGetWakeupTouchpad___STATIC__nanoFrameworkHardwareEsp32SleepTouchPad(CLR_RT_StackFrame &stack) { NANOCLR_HEADER(); - { - touch_pad_t touch_pad = esp_sleep_get_touchpad_wakeup_status(); - // Return value to the managed application - stack.SetResult_I4((int)touch_pad); - } +#if SOC_PM_SUPPORT_EXT_WAKEUP + + touch_pad_t touch_pad = esp_sleep_get_touchpad_wakeup_status(); + + // Return value to the managed application + stack.SetResult_I4((int)touch_pad); + NANOCLR_NOCLEANUP_NOLABEL(); + +#else + + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + NANOCLR_NOCLEANUP(); + +#endif }