diff --git a/CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake index 5d9d8b98bd..81e7863b46 100644 --- a/CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake @@ -21,7 +21,7 @@ set(CHIBIOS_PORT_SRCS hal_lld.c hal_adc_lld.c - #hal_can_lld.c + hal_can_lld.c #hal_dac_lld.c stm32_dma.c hal_ext_lld.c @@ -56,7 +56,7 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/STM32F0xx ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/ADCv1 - #${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1 #${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DACv1 ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DMAv1 ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/EXTIv1 @@ -82,7 +82,7 @@ list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ext/ST/STM32F0xx) list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/ADCv1) -#list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1) #list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DACv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DMAv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/EXTIv1) diff --git a/CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake index 6231c6af16..f11d9526a0 100644 --- a/CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake @@ -21,7 +21,7 @@ set(CHIBIOS_PORT_SRCS hal_lld.c hal_adc_lld.c - #hal_can_lld.c + hal_can_lld.c #hal_dac_lld.c stm32_dma.c hal_ext_lld.c @@ -59,7 +59,7 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/STM32F4xx ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/ADCv2 - #${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1 #${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DACv1 ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DMAv2 ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/EXTIv1 @@ -88,7 +88,7 @@ list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ext/ST/STM32F4xx) list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/ADCv2) -#list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1) #list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DACv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DMAv2) list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/EXTIv1) diff --git a/CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake index 03288400cb..fd51bc5dcd 100644 --- a/CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake @@ -21,7 +21,7 @@ set(CHIBIOS_PORT_SRCS hal_lld.c hal_adc_lld.c - #hal_can_lld.c + hal_can_lld.c #hal_dac_lld.c stm32_dma.c hal_ext_lld.c @@ -59,7 +59,7 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/STM32F7xx ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/ADCv2 - #${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1 #${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DACv1 ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DMAv2 ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/EXTIv1 @@ -88,7 +88,7 @@ list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ext/ST/STM32F7xx) list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/ADCv2) -#list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1) #list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DACv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DMAv2) list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/EXTIv1) diff --git a/CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake index 59f6490823..880c26ef92 100644 --- a/CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake @@ -21,7 +21,7 @@ set(CHIBIOS_PORT_SRCS hal_lld.c hal_adc_lld.c - #hal_can_lld.c + hal_can_lld.c #hal_dac_lld.c stm32_dma.c hal_ext_lld.c @@ -59,7 +59,7 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/STM32H7xx ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/ADCv4 - #${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1 #${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DACv1 ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DMAv3 ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/EXTIv1 @@ -88,7 +88,7 @@ list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ext/ST/STM32H7xx) list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/ADCv4) -#list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1) #list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DACv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DMAv3) list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/EXTIv1) diff --git a/CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake b/CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake index 9eb8e7f1dd..f4ec34207f 100644 --- a/CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake +++ b/CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake @@ -21,7 +21,7 @@ set(CHIBIOS_PORT_SRCS hal_lld.c hal_adc_lld.c - #hal_can_lld.c + hal_can_lld.c #hal_dac_lld.c stm32_dma.c hal_ext_lld.c @@ -56,7 +56,7 @@ foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/STM32L0xx ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/ADCv1 - #${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1 #${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DACv1 ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DMAv1 ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/EXTIv1 @@ -82,7 +82,7 @@ list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ext/ST/STM32L0xx) list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/ADCv1) -#list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1) #list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DACv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DMAv1) list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/EXTIv1) diff --git a/CMake/Modules/FindnanoFramework.Devices.Can.cmake b/CMake/Modules/FindnanoFramework.Devices.Can.cmake new file mode 100644 index 0000000000..a52445cb53 --- /dev/null +++ b/CMake/Modules/FindnanoFramework.Devices.Can.cmake @@ -0,0 +1,40 @@ +# +# Copyright (c) 2018 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + + +# native code directory +set(BASE_PATH_FOR_THIS_MODULE "${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/nanoFramework.Devices.Can") + + +# set include directories +list(APPEND nanoFramework.Devices.Can_INCLUDE_DIRS "${BASE_PATH_FOR_THIS_MODULE}") +list(APPEND nanoFramework.Devices.Can_INCLUDE_DIRS "${TARGET_BASE_LOCATION}") + +# source files +set(nanoFramework.Devices.Can_SRCS + + nf_devices_can_native_nanoFramework_Devices_Can_CanController.cpp + nf_devices_can_native.cpp + + target_nf_devices_can_config.cpp +) + +foreach(SRC_FILE ${nanoFramework.Devices.Can_SRCS}) + set(nanoFramework.Devices.Can_SRC_FILE SRC_FILE-NOTFOUND) + find_file(nanoFramework.Devices.Can_SRC_FILE ${SRC_FILE} + PATHS + "${BASE_PATH_FOR_THIS_MODULE}" + "${TARGET_BASE_LOCATION}" + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${nanoFramework.Devices.Can_SRC_FILE}") # debug helper + list(APPEND nanoFramework.Devices.Can_SOURCES ${nanoFramework.Devices.Can_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(nanoFramework.Devices.Can DEFAULT_MSG nanoFramework.Devices.Can_INCLUDE_DIRS nanoFramework.Devices.Can_SOURCES) diff --git a/CMake/Modules/NF_NativeAssemblies.cmake b/CMake/Modules/NF_NativeAssemblies.cmake index 0d17a70482..1b598a2d3b 100644 --- a/CMake/Modules/NF_NativeAssemblies.cmake +++ b/CMake/Modules/NF_NativeAssemblies.cmake @@ -9,6 +9,7 @@ # and the namespace designation is 'Windows.Devices.Gpio' ########################################################################################### +option(API_nanoFramework.Devices.Can "option for nanoFramework.Devices.Can") option(API_nanoFramework.Devices.OneWire "option for nanoFramework.Devices.OneWire") option(API_nanoFramework.Networking.Sntp "option for nanoFramework.Networking.Sntp") option(API_nanoFramework.Runtime.Events "option for nanoFramework.Runtime.Events API") @@ -83,6 +84,12 @@ macro(ParseNativeAssemblies) PerformSettingsForApiEntry("nanoFramework.Hardware.Stm32") endif() + # nanoFramework.Devices.Can + if(API_nanoFramework.Devices.Can) + ##### API name here (doted name) + PerformSettingsForApiEntry("nanoFramework.Devices.Can") + endif() + # nanoFramework.Devices.OneWire if(API_nanoFramework.Devices.OneWire) ##### API name here (doted name) diff --git a/CMakeLists.txt b/CMakeLists.txt index 04eb33bab3..719ab91b5a 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -457,6 +457,13 @@ else() endif() +if(API_nanoFramework.Devices.Can) + set(HAL_USE_CAN_OPTION TRUE CACHE INTERNAL "HAL CAN for nanoFramework.Devices.Can") +else() + set(HAL_USE_CAN_OPTION FALSE CACHE INTERNAL "HAL CAN for nanoFramework.Devices.Can") +endif() + + ################################################################# # manage dependent APIs required for some API namespaces ################################################################# @@ -466,7 +473,8 @@ if( API_nanoFramework.Devices.OneWire OR API_System.Net OR API_Windows.Devices.Gpio OR API_Windows.Devices.SerialCommunication OR - API_Windows.Networking.Sockets) + API_Windows.Networking.Sockets OR + API_nanoFramework.Devices.Can) # these APIs requires nanoFramework.Runtime.Events set(API_nanoFramework.Runtime.Events ON CACHE INTERNAL "enable of API_nanoFramework.Runtime.Events") diff --git a/azure-pipelines.yml b/azure-pipelines.yml index ddf56402d0..a9d958e303 100644 --- a/azure-pipelines.yml +++ b/azure-pipelines.yml @@ -93,11 +93,11 @@ jobs: NeedsDFU: true ST_STM32F429I_DISCOVERY: BoardName: ST_STM32F429I_DISCOVERY - BuildOptions: -DTARGET_SERIES=STM32F4xx -DRTOS=CHIBIOS -DSUPPORT_ANY_BASE_CONVERSION=ON -DNF_FEATURE_DEBUGGER=ON -DSWO_OUTPUT=ON -DNF_FEATURE_RTC=ON -DAPI_System.Math=ON -DAPI_Hardware.Stm32=ON -DAPI_Windows.Devices.Gpio=ON -DAPI_Windows.Devices.Spi=ON -DAPI_Windows.Devices.I2c=ON -DAPI_Windows.Devices.Pwm=ON -DAPI_Windows.Devices.SerialCommunication=ON -DAPI_Windows.Devices.Adc=ON -DAPI_nanoFramework.Devices.OneWire=ON + BuildOptions: -DTARGET_SERIES=STM32F4xx -DRTOS=CHIBIOS -DSUPPORT_ANY_BASE_CONVERSION=ON -DNF_FEATURE_DEBUGGER=ON -DSWO_OUTPUT=ON -DNF_FEATURE_RTC=ON -DAPI_System.Math=ON -DAPI_Hardware.Stm32=ON -DAPI_Windows.Devices.Gpio=ON -DAPI_Windows.Devices.Spi=ON -DAPI_Windows.Devices.I2c=ON -DAPI_Windows.Devices.Pwm=ON -DAPI_Windows.Devices.SerialCommunication=ON -DAPI_Windows.Devices.Adc=ON -DAPI_nanoFramework.Devices.OneWire=ON -DAPI_nanoFramework.Devices.Can=ON NeedsDFU: false ST_STM32F4_DISCOVERY: BoardName: ST_STM32F4_DISCOVERY - BuildOptions: -DTARGET_SERIES=STM32F4xx -DRTOS=CHIBIOS -DSUPPORT_ANY_BASE_CONVERSION=ON -DNF_FEATURE_DEBUGGER=ON -DSWO_OUTPUT=ON -DNF_FEATURE_RTC=ON -DAPI_System.Math=ON -DAPI_Hardware.Stm32=ON -DAPI_Windows.Devices.Gpio=ON -DAPI_Windows.Devices.Spi=ON -DAPI_Windows.Devices.I2c=ON -DAPI_Windows.Devices.Pwm=ON -DAPI_Windows.Devices.SerialCommunication=ON -DAPI_Windows.Devices.Adc=ON -DAPI_nanoFramework.Devices.OneWire=ON + BuildOptions: -DTARGET_SERIES=STM32F4xx -DRTOS=CHIBIOS -DSUPPORT_ANY_BASE_CONVERSION=ON -DNF_FEATURE_DEBUGGER=ON -DSWO_OUTPUT=ON -DNF_FEATURE_RTC=ON -DAPI_System.Math=ON -DAPI_Hardware.Stm32=ON -DAPI_Windows.Devices.Gpio=ON -DAPI_Windows.Devices.Spi=ON -DAPI_Windows.Devices.I2c=ON -DAPI_Windows.Devices.Pwm=ON -DAPI_Windows.Devices.SerialCommunication=ON -DAPI_Windows.Devices.Adc=ON -DAPI_nanoFramework.Devices.OneWire=ON -DAPI_nanoFramework.Devices.Can=ON NeedsDFU: false ST_NUCLEO64_F091RC: BoardName: ST_NUCLEO64_F091RC @@ -109,7 +109,7 @@ jobs: NeedsDFU: false ST_STM32F769I_DISCOVERY: BoardName: ST_STM32F769I_DISCOVERY - BuildOptions: -DTARGET_SERIES=STM32F7xx -DRTOS=CHIBIOS -DSUPPORT_ANY_BASE_CONVERSION=ON -DNF_FEATURE_DEBUGGER=ON -DSWO_OUTPUT=ON -DNF_FEATURE_RTC=ON -DAPI_System.Math=ON -DAPI_Hardware.Stm32=ON -DNF_FEATURE_HAS_CONFIG_BLOCK=ON -DAPI_Windows.Devices.Gpio=ON -DAPI_Windows.Devices.Spi=ON -DAPI_Windows.Devices.I2c=ON -DAPI_Windows.Devices.Pwm=ON -DAPI_Windows.Devices.SerialCommunication=ON -DAPI_Windows.Devices.Adc=ON -DAPI_System.Net=ON -DNF_SECURITY_MBEDTLS=ON -DAPI_nanoFramework.Devices.OneWire=ON + BuildOptions: -DTARGET_SERIES=STM32F7xx -DRTOS=CHIBIOS -DSUPPORT_ANY_BASE_CONVERSION=ON -DNF_FEATURE_DEBUGGER=ON -DSWO_OUTPUT=ON -DNF_FEATURE_RTC=ON -DAPI_System.Math=ON -DAPI_Hardware.Stm32=ON -DNF_FEATURE_HAS_CONFIG_BLOCK=ON -DAPI_Windows.Devices.Gpio=ON -DAPI_Windows.Devices.Spi=ON -DAPI_Windows.Devices.I2c=ON -DAPI_Windows.Devices.Pwm=ON -DAPI_Windows.Devices.SerialCommunication=ON -DAPI_Windows.Devices.Adc=ON -DAPI_System.Net=ON -DNF_SECURITY_MBEDTLS=ON -DAPI_nanoFramework.Devices.OneWire=ON -DAPI_nanoFramework.Devices.Can=ON NeedsDFU: false variables: diff --git a/cmake-variants.TEMPLATE.json b/cmake-variants.TEMPLATE.json index b403fb28a8..fbb7ec42c6 100644 --- a/cmake-variants.TEMPLATE.json +++ b/cmake-variants.TEMPLATE.json @@ -64,6 +64,7 @@ "NF_SECURITY_OPENSSL" : "OFF-default-ON-to-add-network-security-from-OpenSSL", "NF_SECURITY_MBEDTLS" : "OFF-default-ON-to-add-network-security-from-mbedTLS", "MBEDTLS_SOURCE" : "", + "API_nanoFramework.Devices.Can" : "OFF-default-ON-to-add-this-API", "API_nanoFramework.Devices.OneWire" : "OFF-default-ON-to-add-this-API", "API_System.Math" : "OFF-default-ON-to-add-this-API", "API_System.Net" : "OFF-default-ON-to-add-this-API", diff --git a/src/PAL/Include/nanoPAL_Events.h b/src/PAL/Include/nanoPAL_Events.h index 4d2a6c472a..c09e4b8d17 100644 --- a/src/PAL/Include/nanoPAL_Events.h +++ b/src/PAL/Include/nanoPAL_Events.h @@ -19,6 +19,7 @@ #define EVENT_SERIAL 30 #define EVENT_NETWORK 40 #define EVENT_WIFI 50 +#define EVENT_CAN 60 //////////////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////// diff --git a/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/halconf.h b/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/halconf.h index 99e29ea94a..5b88194cb3 100644 --- a/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/halconf.h +++ b/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/halconf.h @@ -42,9 +42,10 @@ /** * @brief Enables the CAN subsystem. */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN FALSE -#endif +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +// #define HAL_USE_CAN FALSE +// #endif /** * @brief Enables the cryptographic subsystem. @@ -244,7 +245,7 @@ * @brief Enforces the driver to use direct callbacks rather than OSAL events. */ #if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE +#define CAN_ENFORCE_USE_CALLBACKS TRUE #endif /*===========================================================================*/ diff --git a/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/halconf.h b/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/halconf.h index aaf8013deb..0118d80587 100644 --- a/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/halconf.h +++ b/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/halconf.h @@ -42,9 +42,10 @@ /** * @brief Enables the CAN subsystem. */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN FALSE -#endif +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +// #define HAL_USE_CAN FALSE +// #endif /** * @brief Enables the cryptographic subsystem. @@ -244,7 +245,7 @@ * @brief Enforces the driver to use direct callbacks rather than OSAL events. */ #if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE +#define CAN_ENFORCE_USE_CALLBACKS TRUE #endif /*===========================================================================*/ diff --git a/targets/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/halconf.h b/targets/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/halconf.h index c2e6c8f466..40c6938507 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/halconf.h +++ b/targets/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/halconf.h @@ -42,9 +42,10 @@ /** * @brief Enables the CAN subsystem. */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN FALSE -#endif +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +// #define HAL_USE_CAN FALSE +// #endif /** * @brief Enables the cryptographic subsystem. @@ -242,7 +243,7 @@ * @brief Enforces the driver to use direct callbacks rather than OSAL events. */ #if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE +#define CAN_ENFORCE_USE_CALLBACKS TRUE #endif /*===========================================================================*/ diff --git a/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/halconf.h b/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/halconf.h index 6ac2ab3910..afdb6de483 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/halconf.h +++ b/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/halconf.h @@ -42,9 +42,10 @@ /** * @brief Enables the CAN subsystem. */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN FALSE -#endif +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +// #define HAL_USE_CAN FALSE +// #endif /** * @brief Enables the cryptographic subsystem. @@ -243,7 +244,7 @@ * @brief Enforces the driver to use direct callbacks rather than OSAL events. */ #if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE +#define CAN_ENFORCE_USE_CALLBACKS TRUE #endif /*===========================================================================*/ diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/halconf.h b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/halconf.h index 9962dbf066..0a47dfcf59 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/halconf.h +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/halconf.h @@ -42,9 +42,10 @@ /** * @brief Enables the CAN subsystem. */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN FALSE -#endif +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +// #define HAL_USE_CAN FALSE +// #endif /** * @brief Enables the cryptographic subsystem. @@ -244,7 +245,7 @@ * @brief Enforces the driver to use direct callbacks rather than OSAL events. */ #if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE +#define CAN_ENFORCE_USE_CALLBACKS TRUE #endif /*===========================================================================*/ diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/halconf_nf.h b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/halconf_nf.h index ef39df9e55..ae98eab61d 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/halconf_nf.h +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/halconf_nf.h @@ -26,4 +26,9 @@ #define HAL_USE_STM32_ONEWIRE TRUE #endif +// enables STM32 Can driver +#if !defined(HAL_USE_STM32_CAN) +#define HAL_USE_STM32_CAN TRUE +#endif + #endif // _HALCONF_NF_H_ diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf.h b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf.h index 5350b73762..4b19bca8f5 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf.h +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf.h @@ -93,8 +93,8 @@ /* * CAN driver system settings. */ -#define STM32_CAN_USE_CAN1 FALSE -#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_USE_CAN2 TRUE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 #define STM32_CAN_CAN2_IRQ_PRIORITY 11 diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_nf_devices_can_config.cpp b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_nf_devices_can_config.cpp new file mode 100644 index 0000000000..81c129781d --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_nf_devices_can_config.cpp @@ -0,0 +1,44 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_nf_devices_can_config.h" +#include + +/////////// +// CAN1 // +/////////// + +// pin configuration for CAN1 +// port for TX pin is: GPIOB +// TX pin: is GPIOB_09 +// port for RX pin is: GPIOB +// RX pin: is GPIOB_08 +// GPIO alternate pin function is 9 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in STM32F405xx/STM32F407xx datasheet) +CAN_CONFIG_PINS(1, GPIOB, GPIOB, 9, 8, 9) + +// buffer +CANRxFrame Can1_MsgBuffer[CAN1_RX_BUFFER_SIZE]; + +// initialization for CAN1 +CAN_INIT(1, CAN1_RX_BUFFER_SIZE) + +/////////// +// CAN2 // +/////////// + +// pin configuration for CAN2 +// port for TX pin is: GPIOB +// TX pin: is GPIOB_06 +// port for RX pin is: GPIOB +// RX pin: is GPIOB_05 +// GPIO alternate pin function is 9 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in STM32F405xx/STM32F407xx datasheet) +CAN_CONFIG_PINS(2, GPIOB, GPIOB, 6, 5, 9) + +// buffer +CANRxFrame Can2_MsgBuffer[CAN2_RX_BUFFER_SIZE]; + +// initialization for CAN1 +CAN_INIT(2, CAN2_RX_BUFFER_SIZE) diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_nf_devices_can_config.h b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_nf_devices_can_config.h new file mode 100644 index 0000000000..adc8ace3b2 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_nf_devices_can_config.h @@ -0,0 +1,25 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +////////// +// CAN1 // +////////// + +// enable CAN1 +#define NF_CAN_STM32_CAN_USE_CAN1 TRUE + +// buffers size +#define CAN1_RX_BUFFER_SIZE 16 + +////////// +// CAN2 // +////////// + +// enable CAN2 +#define NF_CAN_STM32_CAN_USE_CAN2 TRUE + +// buffers size +#define CAN2_RX_BUFFER_SIZE 16 diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/halconf.h b/targets/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/halconf.h index a614f38b7c..fe5555ed0a 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/halconf.h +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/halconf.h @@ -42,9 +42,10 @@ /** * @brief Enables the CAN subsystem. */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN FALSE -#endif +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +// #define HAL_USE_CAN FALSE +// #endif /** * @brief Enables the cryptographic subsystem. @@ -243,7 +244,7 @@ * @brief Enforces the driver to use direct callbacks rather than OSAL events. */ #if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE +#define CAN_ENFORCE_USE_CALLBACKS TRUE #endif /*===========================================================================*/ diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/halconf_nf.h b/targets/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/halconf_nf.h index d1dc2115b7..208e10036f 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/halconf_nf.h +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/halconf_nf.h @@ -21,5 +21,10 @@ #define HAL_USE_STM32_ONEWIRE TRUE #endif +// enables STM32 Can driver +#if !defined(HAL_USE_STM32_CAN) +#define HAL_USE_STM32_CAN TRUE +#endif + #endif // _HALCONF_NF_H_ diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/mcuconf.h b/targets/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/mcuconf.h index a4661e2f45..0dbddf192c 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/mcuconf.h +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/mcuconf.h @@ -93,8 +93,8 @@ /* * CAN driver system settings. */ -#define STM32_CAN_USE_CAN1 FALSE -#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_USE_CAN2 TRUE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 #define STM32_CAN_CAN2_IRQ_PRIORITY 11 diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_nf_devices_can_config.cpp b/targets/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_nf_devices_can_config.cpp new file mode 100644 index 0000000000..81c129781d --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_nf_devices_can_config.cpp @@ -0,0 +1,44 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_nf_devices_can_config.h" +#include + +/////////// +// CAN1 // +/////////// + +// pin configuration for CAN1 +// port for TX pin is: GPIOB +// TX pin: is GPIOB_09 +// port for RX pin is: GPIOB +// RX pin: is GPIOB_08 +// GPIO alternate pin function is 9 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in STM32F405xx/STM32F407xx datasheet) +CAN_CONFIG_PINS(1, GPIOB, GPIOB, 9, 8, 9) + +// buffer +CANRxFrame Can1_MsgBuffer[CAN1_RX_BUFFER_SIZE]; + +// initialization for CAN1 +CAN_INIT(1, CAN1_RX_BUFFER_SIZE) + +/////////// +// CAN2 // +/////////// + +// pin configuration for CAN2 +// port for TX pin is: GPIOB +// TX pin: is GPIOB_06 +// port for RX pin is: GPIOB +// RX pin: is GPIOB_05 +// GPIO alternate pin function is 9 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in STM32F405xx/STM32F407xx datasheet) +CAN_CONFIG_PINS(2, GPIOB, GPIOB, 6, 5, 9) + +// buffer +CANRxFrame Can2_MsgBuffer[CAN2_RX_BUFFER_SIZE]; + +// initialization for CAN1 +CAN_INIT(2, CAN2_RX_BUFFER_SIZE) diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_nf_devices_can_config.h b/targets/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_nf_devices_can_config.h new file mode 100644 index 0000000000..adc8ace3b2 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_nf_devices_can_config.h @@ -0,0 +1,25 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +////////// +// CAN1 // +////////// + +// enable CAN1 +#define NF_CAN_STM32_CAN_USE_CAN1 TRUE + +// buffers size +#define CAN1_RX_BUFFER_SIZE 16 + +////////// +// CAN2 // +////////// + +// enable CAN2 +#define NF_CAN_STM32_CAN_USE_CAN2 TRUE + +// buffers size +#define CAN2_RX_BUFFER_SIZE 16 diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/halconf.h b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/halconf.h index 776072cb8d..d9f5b53e7d 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/halconf.h +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/halconf.h @@ -42,9 +42,10 @@ /** * @brief Enables the CAN subsystem. */ -#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) -#define HAL_USE_CAN FALSE -#endif +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +// #define HAL_USE_CAN FALSE +// #endif /** * @brief Enables the cryptographic subsystem. @@ -243,7 +244,7 @@ * @brief Enforces the driver to use direct callbacks rather than OSAL events. */ #if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) -#define CAN_ENFORCE_USE_CALLBACKS FALSE +#define CAN_ENFORCE_USE_CALLBACKS TRUE #endif /*===========================================================================*/ diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/halconf_nf.h b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/halconf_nf.h index dbbf8eb94f..c8473fd4a5 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/halconf_nf.h +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/halconf_nf.h @@ -26,4 +26,9 @@ #define HAL_USE_STM32_ONEWIRE TRUE #endif +// enables STM32 Can driver +#if !defined(HAL_USE_STM32_CAN) +#define HAL_USE_STM32_CAN TRUE +#endif + #endif // _HALCONF_NF_H_ diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h index cffadb2567..a3e422aaea 100644 --- a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h @@ -123,8 +123,8 @@ /* * CAN driver system settings. */ -#define STM32_CAN_USE_CAN1 FALSE -#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_USE_CAN2 TRUE #define STM32_CAN_USE_CAN3 FALSE #define STM32_CAN_CAN1_IRQ_PRIORITY 11 #define STM32_CAN_CAN2_IRQ_PRIORITY 11 diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_nf_devices_can_config.cpp b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_nf_devices_can_config.cpp new file mode 100644 index 0000000000..81c129781d --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_nf_devices_can_config.cpp @@ -0,0 +1,44 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_nf_devices_can_config.h" +#include + +/////////// +// CAN1 // +/////////// + +// pin configuration for CAN1 +// port for TX pin is: GPIOB +// TX pin: is GPIOB_09 +// port for RX pin is: GPIOB +// RX pin: is GPIOB_08 +// GPIO alternate pin function is 9 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in STM32F405xx/STM32F407xx datasheet) +CAN_CONFIG_PINS(1, GPIOB, GPIOB, 9, 8, 9) + +// buffer +CANRxFrame Can1_MsgBuffer[CAN1_RX_BUFFER_SIZE]; + +// initialization for CAN1 +CAN_INIT(1, CAN1_RX_BUFFER_SIZE) + +/////////// +// CAN2 // +/////////// + +// pin configuration for CAN2 +// port for TX pin is: GPIOB +// TX pin: is GPIOB_06 +// port for RX pin is: GPIOB +// RX pin: is GPIOB_05 +// GPIO alternate pin function is 9 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in STM32F405xx/STM32F407xx datasheet) +CAN_CONFIG_PINS(2, GPIOB, GPIOB, 6, 5, 9) + +// buffer +CANRxFrame Can2_MsgBuffer[CAN2_RX_BUFFER_SIZE]; + +// initialization for CAN1 +CAN_INIT(2, CAN2_RX_BUFFER_SIZE) diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_nf_devices_can_config.h b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_nf_devices_can_config.h new file mode 100644 index 0000000000..adc8ace3b2 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_nf_devices_can_config.h @@ -0,0 +1,25 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +////////// +// CAN1 // +////////// + +// enable CAN1 +#define NF_CAN_STM32_CAN_USE_CAN1 TRUE + +// buffers size +#define CAN1_RX_BUFFER_SIZE 16 + +////////// +// CAN2 // +////////// + +// enable CAN2 +#define NF_CAN_STM32_CAN_USE_CAN2 TRUE + +// buffers size +#define CAN2_RX_BUFFER_SIZE 16 diff --git a/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Devices.Can/nf_devices_can_native.cpp b/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Devices.Can/nf_devices_can_native.cpp new file mode 100644 index 0000000000..213ffd6ab2 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Devices.Can/nf_devices_can_native.cpp @@ -0,0 +1,69 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "nf_devices_can_native.h" + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController::WriteMessage___VOID__nanoFrameworkDevicesCanCanMessage, + NULL, + NULL, + NULL, + NULL, + Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController::GetMessage___nanoFrameworkDevicesCanCanMessage, + Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController::DisposeNative___VOID, + Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController::NativeInit___VOID, + Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController::NativeUpdateCallbacks___VOID, + NULL, + Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController::GetDeviceSelector___STATIC__STRING, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Devices_Can = +{ + "nanoFramework.Devices.Can", + 0xD2E9416A, + method_lookup, + { 1, 0, 0, 1 } +}; diff --git a/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Devices.Can/nf_devices_can_native.h b/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Devices.Can/nf_devices_can_native.h new file mode 100644 index 0000000000..a39a01ab24 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Devices.Can/nf_devices_can_native.h @@ -0,0 +1,157 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#ifndef _NF_DEVICES_CAN_NATIVE_H_ +#define _NF_DEVICES_CAN_NATIVE_H_ + +#include +#include "target_nf_devices_can_config.h" +#include +#include + +struct Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController +{ + static const int FIELD_STATIC__s_eventListener = 0; + + static const int FIELD___disposed = 1; + static const int FIELD___callbacks = 2; + static const int FIELD___syncLock = 3; + static const int FIELD___controllerId = 4; + static const int FIELD___settings = 5; + static const int FIELD___message = 6; + static const int FIELD__ControllerId = 7; + + NANOCLR_NATIVE_DECLARE(WriteMessage___VOID__nanoFrameworkDevicesCanCanMessage); + NANOCLR_NATIVE_DECLARE(GetMessage___nanoFrameworkDevicesCanCanMessage); + NANOCLR_NATIVE_DECLARE(DisposeNative___VOID); + NANOCLR_NATIVE_DECLARE(NativeInit___VOID); + NANOCLR_NATIVE_DECLARE(NativeUpdateCallbacks___VOID); + NANOCLR_NATIVE_DECLARE(GetDeviceSelector___STATIC__STRING); + + //--// + +}; + +struct Library_nf_devices_can_native_nanoFramework_Devices_Can_CanControllerEventListener +{ + static const int FIELD___canControllersMap = 1; + + + //--// + +}; + +struct Library_nf_devices_can_native_nanoFramework_Devices_Can_CanControllerManager +{ + static const int FIELD_STATIC___syncLock = 1; + static const int FIELD_STATIC__s_controllersCollection = 2; + + + //--// + +}; + +struct Library_nf_devices_can_native_nanoFramework_Devices_Can_CanMessage +{ + static const int FIELD___id = 1; + static const int FIELD___identifierType = 2; + static const int FIELD___frameType = 3; + static const int FIELD___message = 4; + + + //--// + +}; + +struct Library_nf_devices_can_native_nanoFramework_Devices_Can_CanMessageEvent +{ + static const int FIELD__ControllerIndex = 3; + static const int FIELD__Event = 4; + + + //--// + +}; + +struct Library_nf_devices_can_native_nanoFramework_Devices_Can_CanSettings +{ + static const int FIELD___baudRatePrescaler = 1; + static const int FIELD___phaseSegment1 = 2; + static const int FIELD___phaseSegment2 = 3; + static const int FIELD___syncJumpWidth = 4; + + + //--// + +}; + + + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Devices_Can; + +// struct representing the CAN +struct NF_PAL_CAN +{ + CANDriver* Driver; + CANConfig Configuration; + thread_t* ReceiverThread; + + HAL_RingBuffer MsgRingBuffer; + CANRxFrame* MsgBuffer; +}; + +/////////////////////////////////////////// +// declaration of the CAN PAL strucs // +/////////////////////////////////////////// +#if STM32_CAN_USE_CAN1 + extern NF_PAL_CAN Can1_PAL; +#endif +#if STM32_CAN_USE_CAN2 + extern NF_PAL_CAN Can2_PAL; +#endif +#if STM32_CAN_USE_CAN3 + extern NF_PAL_CAN Can3_PAL; +#endif + +// the following macro defines a function that configures the GPIO pins for a STM32 CAN +// it gets called in the can_lld_start function// this is required because the CAN peripherals can use multiple GPIO configuration combinations +#define CAN_CONFIG_PINS(num, gpio_port_tx, gpio_port_rx, tx_pin, rx_pin, alternate_function) void ConfigPins_CAN##num() { \ + palSetPadMode(gpio_port_tx, tx_pin, PAL_MODE_ALTERNATE(alternate_function) | PAL_STM32_OTYPE_PUSHPULL \ + | PAL_STM32_OSPEED_HIGHEST | PAL_STM32_MODE_ALTERNATE); \ + palSetPadMode(gpio_port_rx, rx_pin, PAL_MODE_ALTERNATE(alternate_function) | PAL_STM32_OTYPE_PUSHPULL \ + | PAL_STM32_OSPEED_HIGHEST | PAL_STM32_MODE_ALTERNATE); \ +} + +/////////////////////////////////////////////////////////////////////////////////////////// +// when a CAN is defined the declarations bellow will have the real function/configuration +// in the target folder @ target_nf_devices_can_config.cpp +/////////////////////////////////////////////////////////////////////////////////////////// +void ConfigPins_CAN1(); +void ConfigPins_CAN2(); +void ConfigPins_CAN3(); + + +///////////////////////////////////// +// CAN Msg buffers // +// these live in the target folder // +///////////////////////////////////// +extern CANRxFrame Can1_MsgBuffer[]; +extern CANRxFrame Can2_MsgBuffer[]; +extern CANRxFrame Can3_MsgBuffer[]; + +// +#define CAN_INIT(num, buffer_size) void Init_Can##num() { \ + Can##num##_PAL.MsgBuffer = Can##num##_MsgBuffer; \ + Can##num##_PAL.MsgRingBuffer.Initialize( Can##num##_PAL.MsgBuffer, buffer_size); \ +} + +// when a CAN is defined the declarations bellow will have the real function/configuration +// in the target folder @ target_nf_devices_can_config.cpp +void Init_Can1(); +void Init_Can2(); +void Init_Can3(); + +#endif //_NF_DEVICES_CAN_NATIVE_H_ diff --git a/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Devices.Can/nf_devices_can_native_nanoFramework_Devices_Can_CanController.cpp b/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Devices.Can/nf_devices_can_native_nanoFramework_Devices_Can_CanController.cpp new file mode 100644 index 0000000000..c1a95dd3c5 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Devices.Can/nf_devices_can_native_nanoFramework_Devices_Can_CanController.cpp @@ -0,0 +1,456 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "nf_devices_can_native.h" + + +//////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH nanoFramework.Devices.Can.CanEvent (in managed code) !!! // +//////////////////////////////////////////////////////////////////////////////////// + +enum CanEvent +{ + CanEvent_MessageReceived = 0, + CanEvent_ErrorOccurred, +}; + +//////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH nanoFramework.Devices.Can.CanMessageIdType (in managed code) !!! // +//////////////////////////////////////////////////////////////////////////////////////////// + +enum CanMessageIdType +{ + CanMessageIdType_SID = 0, + CanMessageIdType_EID, +}; + +/////////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH nanoFramework.Devices.Can.CanMessageFrameType (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////////////// + +enum CanMessageFrameType +{ + CanMessageFrameType_Data = 0, + CanMessageFrameType_RemoteRequest, +}; + +/////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////// + +// define these types here to make it shorter and improve code readability +typedef Library_nf_devices_can_native_nanoFramework_Devices_Can_CanSettings CanSettings; +typedef Library_nf_devices_can_native_nanoFramework_Devices_Can_CanMessage ManagedCanMessage; + +static void RxMessage(CANDriver *canp, uint32_t flags) +{ + NATIVE_INTERRUPT_START + + NF_PAL_CAN* palCan; + uint8_t controllerId = 0; + CANRxFrame rxMsg; + + (void)flags; + + #if STM32_CAN_USE_CAN1 + if (canp == &CAND1) + { + palCan = &Can1_PAL; + controllerId = 1; + } + #endif + #if STM32_CAN_USE_CAN2 + if (canp == &CAND2) + { + palCan = &Can2_PAL; + controllerId = 2; + } + #endif + #if STM32_CAN_USE_CAN3 + if (canp == &CAND3) + { + palCan = &Can3_PAL; + controllerId = 3; + } + #endif + + while (canReceiveTimeout(palCan->Driver, CAN_ANY_MAILBOX, &rxMsg, TIME_IMMEDIATE) == MSG_OK) + { + // got message + + // store message in the CAN buffer + // don't care about the success of the operation, if it's full we are droping the message anyway + palCan->MsgRingBuffer.Push(rxMsg); + + // fire event for CAN message received + PostManagedEvent( EVENT_CAN, 0, controllerId, CanEvent_MessageReceived ); + } + + NATIVE_INTERRUPT_END +} + +///////////////////////////////////////////////////////// +// CAN PAL strucs delcared in nf_devices_can_native.h // +///////////////////////////////////////////////////////// +#if STM32_CAN_USE_CAN1 + NF_PAL_CAN Can1_PAL; +#endif +#if STM32_CAN_USE_CAN2 + NF_PAL_CAN Can2_PAL; +#endif +#if STM32_CAN_USE_CAN3 + NF_PAL_CAN Can3_PAL; +#endif + +HRESULT Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController::WriteMessage___VOID__nanoFrameworkDevicesCanCanMessage( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + uint32_t id; + CanMessageIdType msgIdType; + CanMessageFrameType msgFrameType; + CLR_RT_HeapBlock_Array* message; + CANTxFrame txmsg; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + CLR_RT_HeapBlock* pMessage = stack.Arg1().Dereference(); + + // get controller index + uint8_t controllerIndex = (uint8_t)(pThis[ FIELD___controllerId ].NumericByRef().s4); + + // dereference message fields + id = (uint32_t)(pMessage[ Library_nf_devices_can_native_nanoFramework_Devices_Can_CanMessage::FIELD___id ].NumericByRef().u4); + msgIdType = (CanMessageIdType)(pMessage[ Library_nf_devices_can_native_nanoFramework_Devices_Can_CanMessage::FIELD___identifierType ].NumericByRefConst().u1); + msgFrameType = (CanMessageFrameType)(pMessage[ Library_nf_devices_can_native_nanoFramework_Devices_Can_CanMessage::FIELD___frameType ].NumericByRefConst().u1); + + // get message to transmite + message = pMessage[ Library_nf_devices_can_native_nanoFramework_Devices_Can_CanMessage::FIELD___message ].DereferenceArray(); + + // message max length is 8 bytes + if(message->m_numOfElements > 8) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + + // compose the transmite packet to send + if(message != NULL) + { + // copy message to structure + memcpy(txmsg.data8, (uint8_t*)message->GetFirstElement(), message->m_numOfElements); + } + // message id according to it's type + if(msgIdType == CanMessageIdType_SID) + { + txmsg.IDE = CAN_IDE_STD; + txmsg.SID = id; + } + else + { + txmsg.IDE = CAN_IDE_EXT; + txmsg.EID = id; + } + // remote transmission request + txmsg.RTR = msgFrameType == CanMessageFrameType_Data ? CAN_RTR_DATA : CAN_RTR_REMOTE; + // data length + txmsg.DLC = message->m_numOfElements; + + switch (controllerIndex) + { + #if STM32_CAN_USE_CAN1 + case 1: + canTransmit(Can1_PAL.Driver, CAN_ANY_MAILBOX, &txmsg, TIME_MS2I(100)); + break; + #endif + #if STM32_CAN_USE_CAN2 + case 2: + canTransmit(Can2_PAL.Driver, CAN_ANY_MAILBOX, &txmsg, TIME_MS2I(100)); + break; + #endif + #if STM32_CAN_USE_CAN3 + case 3: + canTransmit(Can3_PAL.Driver, CAN_ANY_MAILBOX, &txmsg, TIME_MS2I(100)); + break; + #endif + default: + // this CAN bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController::GetMessage___nanoFrameworkDevicesCanCanMessage( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Index canMessageTypeDef; + CLR_RT_HeapBlock* canMessage = NULL; + + CANRxFrame canFrame; + NF_PAL_CAN* palCan; + uint8_t controllerIndex; + size_t messageCount = 0; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get controller index + controllerIndex = (uint8_t)(pThis[ FIELD___controllerId ].NumericByRef().s4); + + // get the PAL struct for this CAN bus + switch (controllerIndex) + { + + #if STM32_CAN_USE_CAN1 + case 1: + palCan = &Can1_PAL; + + break; + #endif + + #if STM32_CAN_USE_CAN2 + case 2: + palCan = &Can2_PAL; + + break; + #endif + + #if STM32_CAN_USE_CAN3 + case 3: + palCan = &Can3_PAL; + + break; + #endif + + default: + // this CAN bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // get next CAN frame from ring buffer + messageCount = palCan->MsgRingBuffer.Pop(&canFrame, 1); + + // find type, don't bother checking the result as the type exists for sure + g_CLR_RT_TypeSystem.FindTypeDef( "CanMessage", "nanoFramework.Devices.Can", canMessageTypeDef ); + + // create an instance of + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(stack.PushValue(), canMessageTypeDef)); + + canMessage = stack.TopValue().Dereference(); + + if(messageCount == 1) + { + // we have a message + + // get pointer to each managed field and set appropriate value + CLR_RT_HeapBlock& identifierTypeFieldRef = canMessage[ ManagedCanMessage::FIELD___identifierType ]; + CLR_RT_HeapBlock& frameTypeFieldRef = canMessage[ ManagedCanMessage::FIELD___frameType ]; + + // get message frame type + uint8_t* fr = (uint8_t*)&frameTypeFieldRef.NumericByRef().u1; + *fr = canFrame.RTR; + + // get message id type + uint8_t* idType = (uint8_t*)&identifierTypeFieldRef.NumericByRef().u1; + *idType = canFrame.IDE; + + // get message id + CLR_RT_HeapBlock& idFieldRef = canMessage[ ManagedCanMessage::FIELD___id ]; + uint32_t* id = (uint32_t*)&idFieldRef.NumericByRef().u4; + + if(canFrame.IDE == 0) + { + *id = canFrame.SID; + } + else + { + *id = canFrame.EID; + } + + // get data if any + if(canFrame.data8) + { + CLR_RT_HeapBlock& dataArrayField = canMessage[ ManagedCanMessage::FIELD___message ]; + // create an array of + NANOCLR_CHECK_HRESULT( CLR_RT_HeapBlock_Array::CreateInstance( dataArrayField, 8, g_CLR_RT_WellKnownTypes.m_UInt8 ) ); + + // get a pointer to the first object in the array + CLR_UINT8* dataBuffer = (CLR_UINT8*)(dataArrayField.DereferenceArray()->GetFirstElement()); + memcpy(dataBuffer, &canFrame.data8[0], 8); + } + } + else + { + // no more messages, return null + stack.SetResult_Object(NULL); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController::DisposeNative___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + { + + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + NF_PAL_CAN* palCan = NULL; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the managed spi connectionSettings object instance + CLR_RT_HeapBlock* pConfig = pThis[ FIELD___settings ].Dereference(); + + // get controller index + uint8_t controllerIndex = (uint8_t)(pThis[ FIELD___controllerId ].NumericByRef().s4); + + // init the PAL struct for this CAN bus and assign the respective driver + // all this occurs if not already done + switch (controllerIndex) + { + #if STM32_CAN_USE_CAN1 + case 1: + Init_Can1(); + ConfigPins_CAN1(); + Can1_PAL.Driver = &CAND1; + palCan = &Can1_PAL; + break; + #endif + #if STM32_CAN_USE_CAN2 + case 2: + Init_Can2(); + ConfigPins_CAN2(); + Can2_PAL.Driver = &CAND2; + palCan = &Can2_PAL; + break; + #endif + #if STM32_CAN_USE_CAN3 + case 3: + Init_Can3(); + ConfigPins_CAN3(); + Can3_PAL.Driver = &CAND3; + palCan = &Can3_PAL; + break; + #endif + default: + // this CAN bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // get config + palCan->Configuration = { + CAN_MCR_ABOM | CAN_MCR_AWUM | CAN_MCR_TXFP, + (uint32_t)( + CAN_BTR_SJW((uint8_t)pConfig[ CanSettings::FIELD___syncJumpWidth ].NumericByRef().u1) | + CAN_BTR_TS2((uint8_t)pConfig[ CanSettings::FIELD___phaseSegment2 ].NumericByRef().u1) | + CAN_BTR_TS1((uint8_t)pConfig[ CanSettings::FIELD___phaseSegment1 ].NumericByRef().u1) | + CAN_BTR_BRP((uint8_t)pConfig[ CanSettings::FIELD___baudRatePrescaler ].NumericByRef().u1) + ) + }; + + // start CAN + canStart(palCan->Driver, &palCan->Configuration); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController::NativeUpdateCallbacks___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NF_PAL_CAN* palCan = NULL; + bool callbacksRegistered; + uint8_t controllerIndex; + + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get controller index + controllerIndex = (uint8_t)(pThis[ FIELD___controllerId ].NumericByRef().s4); + + // flag to determine if there are any callbacks registered in managed code + callbacksRegistered = (pThis[ FIELD___callbacks ].Dereference() != NULL); + + switch (controllerIndex) + { + #if STM32_CAN_USE_CAN1 + case 1: + palCan = &Can1_PAL; + break; + #endif + #if STM32_CAN_USE_CAN2 + case 2: + palCan = &Can2_PAL; + break; + #endif + #if STM32_CAN_USE_CAN3 + case 3: + palCan = &Can3_PAL; + break; + #endif + default: + // this CAN bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // need to start CAN again + // it's safe to stop first + canStop(palCan->Driver); + + if(callbacksRegistered) + { + // there is someone listening on the managed end + palCan->Driver->rxfull_cb = RxMessage; + } + else + { + // no one listening, OK to remove + palCan->Driver->rxfull_cb = NULL; + } + + // start CAN + canStart(palCan->Driver, &palCan->Configuration); + + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController::GetDeviceSelector___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // declare the device selector string whose max size is "SPI1,SPI2,SPI3,SPI4,SPI5,SPI6," + terminator and init with the terminator + char deviceSelectorString[ 30 + 1] = { 0 }; + + #if STM32_CAN_USE_CAN1 + strcat(deviceSelectorString, "CAN1,"); + #endif + #if STM32_CAN_USE_CAN2 + strcat(deviceSelectorString, "CAN2,"); + #endif + #if STM32_CAN_USE_CAN3 + strcat(deviceSelectorString, "CAN3,"); + #endif + + // replace the last comma with a terminator + deviceSelectorString[hal_strlen_s(deviceSelectorString) - 1] = '\0'; + + // because the caller is expecting a result to be returned + // we need set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + stack.SetResult_String(deviceSelectorString); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/targets/CMSIS-OS/ChibiOS/nanoCLR/target_platform.h.in b/targets/CMSIS-OS/ChibiOS/nanoCLR/target_platform.h.in index b874964134..5fad70d5d9 100644 --- a/targets/CMSIS-OS/ChibiOS/nanoCLR/target_platform.h.in +++ b/targets/CMSIS-OS/ChibiOS/nanoCLR/target_platform.h.in @@ -44,4 +44,7 @@ // set when watchod is enabled #define HAL_USE_WDG @HAL_USE_WDG_OPTION@ +// enable CAN +#define HAL_USE_CAN @HAL_USE_CAN_OPTION@ + #endif /* _TARGET_CHIBIOS_NANOCLR_H_ */