diff --git a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h
index 2853d5c5f6..0f1d14a831 100644
--- a/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h
+++ b/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h
@@ -43,9 +43,9 @@
 #define STM32_SW                            STM32_SW_PLL
 #define STM32_PLLSRC                        STM32_PLLSRC_HSE
 #define STM32_PLLM_VALUE                    25
-#define STM32_PLLN_VALUE                    384
+#define STM32_PLLN_VALUE                    432
 #define STM32_PLLP_VALUE                    2
-#define STM32_PLLQ_VALUE                    8
+#define STM32_PLLQ_VALUE                    9
 #define STM32_PLLR_VALUE                    2
 #define STM32_HPRE                          STM32_HPRE_DIV1
 #define STM32_PPRE1                         STM32_PPRE1_DIV4
@@ -55,18 +55,18 @@
 #define STM32_MCO1SEL                       STM32_MCO1SEL_HSI
 #define STM32_MCO1PRE                       STM32_MCO1PRE_DIV1
 #define STM32_MCO2SEL                       STM32_MCO2SEL_SYSCLK
-#define STM32_MCO2PRE                       STM32_MCO2PRE_DIV1
+#define STM32_MCO2PRE                       STM32_MCO2PRE_DIV4
 #define STM32_I2SSRC                        STM32_I2SSRC_OFF
 #define STM32_PLLI2SN_VALUE                 192
-#define STM32_PLLI2SP_VALUE                 2
-#define STM32_PLLI2SQ_VALUE                 2
-#define STM32_PLLI2SR_VALUE                 2
-#define STM32_PLLI2SDIVQ_VALUE              1
+#define STM32_PLLI2SP_VALUE                 4
+#define STM32_PLLI2SQ_VALUE                 4
+#define STM32_PLLI2SR_VALUE                 4
+#define STM32_PLLI2SDIVQ_VALUE              2
 #define STM32_PLLSAIN_VALUE                 192
 #define STM32_PLLSAIP_VALUE                 4
-#define STM32_PLLSAIQ_VALUE                 3
-#define STM32_PLLSAIR_VALUE                 2
-#define STM32_PLLSAIDIVQ_VALUE              1 
+#define STM32_PLLSAIQ_VALUE                 4
+#define STM32_PLLSAIR_VALUE                 4
+#define STM32_PLLSAIDIVQ_VALUE              2 
 #define STM32_PLLSAIDIVR_VALUE              2 
 #define STM32_SAI1SEL                       STM32_SAI1SEL_SAIPLL
 #define STM32_SAI2SEL                       STM32_SAI2SEL_SAIPLL