From 547711b3da608cc7331fd5afb0b4e55cf7dfd627 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 16 Aug 2017 19:16:49 +0100 Subject: [PATCH] Work on Devices.Spi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - update code to latest version of the managed class library - move gpioPort[] to targetPAL to allow reuse - work on NativeTransfer for byte[] transfers (code improvement, add comments) Signed-off-by: José Simões --- targets/CMSIS-OS/ChibiOS/Include/targetPAL.h | 18 ++ .../CMSIS-OS/ChibiOS/nanoCLR/CMakeLists.txt | 1 + ...io_native_Windows_Devices_Gpio_GpioPin.cpp | 33 +- .../win_dev_spi_native.cpp | 9 +- .../Windows.Devices.Spi/win_dev_spi_native.h | 24 +- ..._native_Windows_Devices_Spi_SpiBusInfo.cpp | 29 +- ...i_native_Windows_Devices_Spi_SpiDevice.cpp | 298 +++++++++--------- targets/CMSIS-OS/ChibiOS/nanoCLR/targetPAL.c | 36 +++ 8 files changed, 247 insertions(+), 201 deletions(-) create mode 100644 targets/CMSIS-OS/ChibiOS/Include/targetPAL.h create mode 100644 targets/CMSIS-OS/ChibiOS/nanoCLR/targetPAL.c diff --git a/targets/CMSIS-OS/ChibiOS/Include/targetPAL.h b/targets/CMSIS-OS/ChibiOS/Include/targetPAL.h new file mode 100644 index 0000000000..271ad5e63a --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/Include/targetPAL.h @@ -0,0 +1,18 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _GPIO_PORT +#define _GPIO_PORT + +#include + + +// Contains available GPIO ports for the current board +extern stm32_gpio_t* gpioPort[]; + +//Gets the GPIO according to a pin number +#define GPIO_PORT(pin) (gpioPort[pin/16]) + +#endif diff --git a/targets/CMSIS-OS/ChibiOS/nanoCLR/CMakeLists.txt b/targets/CMSIS-OS/ChibiOS/nanoCLR/CMakeLists.txt index 2647462f98..29782139c5 100644 --- a/targets/CMSIS-OS/ChibiOS/nanoCLR/CMakeLists.txt +++ b/targets/CMSIS-OS/ChibiOS/nanoCLR/CMakeLists.txt @@ -14,6 +14,7 @@ list(APPEND TARGET_CHIBIOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/WireProto list(APPEND TARGET_CHIBIOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_MonitorCommands.c) list(APPEND TARGET_CHIBIOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/Aborts_CortexM3.cpp) list(APPEND TARGET_CHIBIOS_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/CLR_Startup_Thread.c") +list(APPEND TARGET_CHIBIOS_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetPAL.c") # append target HAL source files list(APPEND TARGET_CHIBIOS_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Time.cpp") diff --git a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioPin.cpp b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioPin.cpp index 186313b249..3c07a13eb2 100644 --- a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioPin.cpp +++ b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioPin.cpp @@ -9,6 +9,7 @@ #include #include +#include #include "win_dev_gpio_native.h" /////////////////////////////////////////////////////////////////////////////////////// @@ -40,38 +41,6 @@ enum GpioPinValue /////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////// -stm32_gpio_t* gpioPort[] = { GPIOA, GPIOB -#if STM32_HAS_GPIOC -, GPIOC -#endif -#if STM32_HAS_GPIOD -, GPIOD -#endif -#if STM32_HAS_GPIOE -, GPIOE -#endif -#if STM32_HAS_GPIOF -, GPIOF -#endif -#if STM32_HAS_GPIOG -, GPIOG -#endif -#if STM32_HAS_GPIOH -, GPIOH -#endif -#if STM32_HAS_GPIOI -, GPIOI -#endif -#if STM32_HAS_GPIOJ -, GPIOJ -#endif -#if STM32_HAS_GPIOK -, GPIOK -#endif - }; - -#define GPIO_PORT(pin) (gpioPort[pin/16]) - void IsrProcedure( GPIO_PIN pin, bool pinState, void* context ) { diff --git a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native.cpp b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native.cpp index fd1aafa801..eed103617a 100644 --- a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native.cpp +++ b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native.cpp @@ -36,8 +36,11 @@ static const CLR_RT_MethodHandler method_lookup[] = NULL, NULL, NULL, - Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer___VOID__STRING__SZARRAY_U1__SZARRAY_U1__BOOLEAN, - Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer___VOID__STRING__SZARRAY_U2__SZARRAY_U2__BOOLEAN, + NULL, + NULL, + NULL, + Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer___VOID__SZARRAY_U1__SZARRAY_U1__BOOLEAN, + Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer___VOID__SZARRAY_U2__SZARRAY_U2__BOOLEAN, Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeInit___VOID, NULL, NULL, @@ -61,6 +64,6 @@ static const CLR_RT_MethodHandler method_lookup[] = const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Spi = { "Windows.Devices.Spi", - 0xD124F515, + 0x3A9E993E, method_lookup }; diff --git a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native.h b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native.h index 143ab27e92..7d495ab05c 100644 --- a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native.h +++ b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native.h @@ -11,7 +11,13 @@ #include #include #include +#include +struct nfSPIConfig +{ + SPIConfig Configuration; + SPIDriver * Driver; +}; struct Library_win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo { @@ -31,6 +37,16 @@ struct Library_win_dev_spi_native_Windows_Devices_Spi_SpiConnectionSettings static const int FIELD___databitLength = 3; static const int FIELD___spiMode = 4; static const int FIELD___spiSharingMode = 5; + static const int FIELD___bitOrder = 6; + + + //--// + +}; + +struct Library_win_dev_spi_native_Windows_Devices_Spi_SpiController +{ + static const int FIELD_STATIC__DeviceCollection = 0; //--// @@ -45,16 +61,18 @@ struct Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice static const int FIELD___connectionSettings = 4; static const int FIELD___disposedValue = 5; - NANOCLR_NATIVE_DECLARE(NativeTransfer___VOID__STRING__SZARRAY_U1__SZARRAY_U1__BOOLEAN); - NANOCLR_NATIVE_DECLARE(NativeTransfer___VOID__STRING__SZARRAY_U2__SZARRAY_U2__BOOLEAN); + NANOCLR_NATIVE_DECLARE(NativeTransfer___VOID__SZARRAY_U1__SZARRAY_U1__BOOLEAN); + NANOCLR_NATIVE_DECLARE(NativeTransfer___VOID__SZARRAY_U2__SZARRAY_U2__BOOLEAN); NANOCLR_NATIVE_DECLARE(NativeInit___VOID); NANOCLR_NATIVE_DECLARE(DisposeNative___VOID); NANOCLR_NATIVE_DECLARE(GetDeviceSelector___STATIC__STRING); //--// + static uint16_t ComputePrescaler (uint8_t bus, int32_t requestedFrequency); + static nfSPIConfig GetConfig(int bus, CLR_RT_HeapBlock* config); }; extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Spi; -#endif //_WIN_DEV_SPI_NATIVE_H_ \ No newline at end of file +#endif //_WIN_DEV_SPI_NATIVE_H_ diff --git a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo.cpp b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo.cpp index 605ff55b43..7bec246eae 100644 --- a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo.cpp +++ b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo.cpp @@ -11,11 +11,16 @@ HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo::get_MaxClockF { NANOCLR_HEADER(); { - CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); - - signed int retVal = 48000000; - - stack.SetResult_I4( retVal ); + CLR_RT_HeapBlock* pArg = &(stack.Arg1()); + + // spiBus is an ASCII string with the bus name in format 'SPIn' + // need to grab 'n' from the string and convert to the integer value from the ASCII code + uint8_t bus = (uint8_t)pArg[0].RecoverString()[3] - 48; + + // According to STM : "At a minimum, the clock frequency should be twice the required communication frequency." + // So maximum useable frequency is CoreClock / 2. + // SPI2 or SPI3 are on APB1, so divide max frequency by four. + stack.SetResult_I4 ((bus == 2 or bus == 3) ? SystemCoreClock >>= 2 : SystemCoreClock >> 1); } NANOCLR_NOCLEANUP(); } @@ -24,11 +29,15 @@ HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo::get_MinClockF { NANOCLR_HEADER(); { - CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); - - signed int retVal = 1000000; - - stack.SetResult_I4( retVal ); + CLR_RT_HeapBlock* pArg = &(stack.Arg1()); + + // spiBus is an ASCII string with the bus name in format 'SPIn' + // need to grab 'n' from the string and convert to the integer value from the ASCII code + uint8_t bus = (uint8_t)pArg[0].RecoverString()[3] - 48; + + // Max prescaler value = 256 + // SPI2 or SPI3 are on APB1, so divide max frequency by four. + stack.SetResult_I4 ((bus == 2 or bus == 3) ? SystemCoreClock >>= 9 : SystemCoreClock >> 8); } NANOCLR_NOCLEANUP(); } diff --git a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiDevice.cpp b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiDevice.cpp index ea5536a85f..29a10ffd18 100644 --- a/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiDevice.cpp +++ b/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiDevice.cpp @@ -10,9 +10,20 @@ #include #include - +#include #include "win_dev_spi_native.h" +SPIConfig spi_cfg; + +/////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.Spi.SpiMode (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////// + +enum DataBitOrder +{ + MSB = 0, + LSB +}; /////////////////////////////////////////////////////////////////////////////////////// // !!! KEEP IN SYNC WITH Windows.Devices.Spi.SpiMode (in managed code) !!! // @@ -33,39 +44,7 @@ enum SpiModes typedef Library_win_dev_spi_native_Windows_Devices_Spi_SpiConnectionSettings SpiConnectionSettings; -stm32_gpio_t* gpioPortSpi[] = { GPIOA, GPIOB -#if STM32_HAS_GPIOC -, GPIOC -#endif -#if STM32_HAS_GPIOD -, GPIOD -#endif -#if STM32_HAS_GPIOE -, GPIOE -#endif -#if STM32_HAS_GPIOF -, GPIOF -#endif -#if STM32_HAS_GPIOG -, GPIOG -#endif -#if STM32_HAS_GPIOH -, GPIOH -#endif -#if STM32_HAS_GPIOI -, GPIOI -#endif -#if STM32_HAS_GPIOJ -, GPIOJ -#endif -#if STM32_HAS_GPIOK -, GPIOK -#endif -}; - -#define GPIO_PORT(pin) (gpioPortSpi[pin/16]) - -uint16_t ComputePrescaler (uint8_t bus, int32_t requestedFrequency) +uint16_t Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::ComputePrescaler (uint8_t bus, int32_t requestedFrequency) { uint16_t pre = 0; int32_t clock = STM32_SPII2S_MAX >> 1; // SP1, SPI4, SPI5 and SPI6 on APB2 @@ -86,169 +65,182 @@ uint16_t ComputePrescaler (uint8_t bus, int32_t requestedFrequency) return pre; } -HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer___VOID__STRING__SZARRAY_U1__SZARRAY_U1__BOOLEAN( CLR_RT_StackFrame& stack ) -{ - NANOCLR_HEADER(); - - const char * spiBus = stack.Arg0().StringText(); - uint8_t bus = (uint8_t)spiBus[3] - 48; - int wCount = stack.Arg1().DereferenceArray()->m_numOfElements; - int rCount = stack.Arg2().DereferenceArray()->m_numOfElements; - - uint8_t * wBuf = stack.Arg1().DereferenceArray()->GetFirstElement(); - uint8_t * rBuf = stack.Arg2().DereferenceArray()->GetFirstElement(); +nfSPIConfig Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::GetConfig(int bus, CLR_RT_HeapBlock* config) +{ + SPIDriver * _drv; + + int csPin = config[ SpiConnectionSettings::FIELD___csLine ].NumericByRef().s4; + uint16_t CR1 = SPI_CR1_SSI | SPI_CR1_MSTR | SPI_CR1_SPE; - SPIDriver _drv; + switch (config[ SpiConnectionSettings::FIELD___spiMode ].NumericByRef().s4) + { + case SpiModes_Mode1 : + CR1 |= SPI_CR1_CPHA; + break; + case SpiModes_Mode2 : + CR1 |= SPI_CR1_CPOL; + break; + case SpiModes_Mode3 : + CR1 |= SPI_CR1_CPHA | SPI_CR1_CPOL; + break; + default : // Default to Mode0 if invalid mode specified + break; + } + if (config[ SpiConnectionSettings::FIELD___databitLength ].NumericByRef().s4 == 16) + { + // data length is 16 bits + CR1 |= SPI_CR1_DFF; + } + CR1 |= ComputePrescaler(bus, config[ SpiConnectionSettings::FIELD___clockFrequency ].NumericByRef().s4); switch (bus) { #if STM32_SPI_USE_SPI1 - case 1 : _drv = SPID1; + case 1 : _drv = &SPID1; break; #endif #if STM32_SPI_USE_SPI2 - case 2 : _drv = SPID2; + case 2 : _drv = &SPID2; break; #endif #if STM32_SPI_USE_SPI3 - case 3 : _drv = SPID3; + case 3 : _drv = &SPID3; break; #endif #if STM32_SPI_USE_SPI4 - case 4 : _drv = SPID4; + case 4 : _drv = &SPID4; break; #endif #if STM32_SPI_USE_SPI5 - case 5 : _drv = SPID5; + case 5 : _drv = &SPID5; break; #endif #if STM32_SPI_USE_SPI6 - case 6 : _drv = SPID6; + case 6 : _drv = &SPID6; break; #endif } - spiSelect(&_drv); - if (wCount != 0 && rCount != 0) // Transmit+Receive + + nfSPIConfig cfg = { - if (stack.Arg3().NumericByRef().u1 == 1) spiExchange(&_drv,wCount, wBuf, rBuf); // Full duplex - else { - spiSend(&_drv, wCount, wBuf); - spiReceive(&_drv, rCount, rBuf); - } - } - else // Transmit only or Receive only - { - if (rCount != 0) spiReceive(&_drv, rCount, rBuf); - else spiSend(&_drv, wCount, wBuf); - } - spiUnselect(&_drv); - - NANOCLR_NOCLEANUP(); -} - -HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer___VOID__STRING__SZARRAY_U2__SZARRAY_U2__BOOLEAN( CLR_RT_StackFrame& stack ) -{ - NANOCLR_HEADER(); - - NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + NULL, + GPIO_PORT(csPin), + csPin % 16, + CR1, + 0 + }, + _drv + }; - NANOCLR_NOCLEANUP(); + return cfg; } -HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeInit___VOID( CLR_RT_StackFrame& stack ) +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer___VOID__SZARRAY_U1__SZARRAY_U1__BOOLEAN( CLR_RT_StackFrame& stack ) { NANOCLR_HEADER(); { - CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + unsigned char * writeData = NULL; + unsigned char * readData = NULL; + int writeSize = 0; + int readSize = 0; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); - // get connection settings from managed object - CLR_RT_HeapBlock* connectionSettings = pThis[ FIELD___connectionSettings ].Dereference(); FAULT_ON_NULL(connectionSettings); + // get bus index + // this is coded with a multiplication, need to perform and int division to get the number + // see the comments in the SpiDevice() constructor in managed code for details + uint8_t bus = (uint8_t)(pThis[ FIELD___deviceId ].NumericByRef().s4 / 1000); - const char* spiBus = pThis[ FIELD___spiBus ].RecoverString(); - FAULT_ON_NULL(spiBus); - - // spiBus is an ASCII string with the bus name in format 'SPIn' - // need to grab 'n' from the string and convert to the integer value from the ASCII code - uint8_t bus = (uint8_t)spiBus[3] - 48; + nfSPIConfig cfg = GetConfig(bus, pThis[ FIELD___connectionSettings ].Dereference()); - uint16_t CR1 = SPI_CR1_SSI | SPI_CR1_MSTR | SPI_CR1_SPE; + // dereference the write and read buffers from the arguments + CLR_RT_HeapBlock_Array* writeBuffer = stack.Arg1().DereferenceArray(); + if (writeBuffer != NULL) + { + // grab the pointer to the array by getting the first element of the array + writeData = writeBuffer->GetFirstElement(); - // mode - int32_t mode = connectionSettings[ SpiConnectionSettings::FIELD___spiMode ].NumericByRef().s4; + // get the size of the buffer by reading the number of elements in the HeapBlock array + writeSize = writeBuffer->m_numOfElements; + } - switch (mode) + CLR_RT_HeapBlock_Array* readBuffer = stack.Arg2().DereferenceArray(); + if (readBuffer != NULL) { - case SpiModes_Mode1 : - CR1 |= SPI_CR1_CPHA; - break; - case SpiModes_Mode2 : - CR1 |= SPI_CR1_CPOL; - break; - case SpiModes_Mode3 : - CR1 |= SPI_CR1_CPHA | SPI_CR1_CPOL; - break; - default : // Default to Mode0 if invalid mode specified - break; + // grab the pointer to the array by getting the first element of the array + readData = readBuffer->GetFirstElement(); + + // get the size of the buffer by reading the number of elements in the HeapBlock array + readSize = readBuffer->m_numOfElements; } - // Data format - int32_t dataBitLength = connectionSettings[ SpiConnectionSettings::FIELD___databitLength ].NumericByRef().s4; + // because the bus access is shared, acquire and select the appropriate bus + spiStart(cfg.Driver, &cfg.Configuration); + spiAcquireBus(cfg.Driver); + spiSelect(cfg.Driver); + + bool fullDuplex = (bool)stack.Arg3().NumericByRef().u1; - if (dataBitLength == 16) + if (writeSize != 0 && readSize != 0) { - // data length is 16 bits - CR1 |= SPI_CR1_DFF; + // Transmit+Receive + if (fullDuplex) + { + // Full duplex + spiExchange(cfg.Driver, writeSize, &writeData[0], &readData[0]); + } + else + { + spiSend(cfg.Driver, writeSize, &writeData[0]); + spiReceive(cfg.Driver, readSize, &readData[0]); + } + } + else + { + // Transmit only or Receive only + if (readSize != 0) + { + spiReceive(cfg.Driver, readSize, &readData[0]); + } + else + { + spiSend(cfg.Driver, writeSize, &writeData[0]); + } } - // Clock prescaler - int32_t clockFrequency = connectionSettings[ SpiConnectionSettings::FIELD___clockFrequency ].NumericByRef().s4; + // Release the bus + spiUnselect(cfg.Driver); + spiReleaseBus(cfg.Driver); + spiStop(cfg.Driver); + + // null pointers and vars + writeData = NULL; + readData = NULL; + writeBuffer = NULL; + readBuffer = NULL; + pThis = NULL; + } + NANOCLR_NOCLEANUP(); +} - CR1 |= ComputePrescaler(bus, clockFrequency); +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer___VOID__SZARRAY_U2__SZARRAY_U2__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); - // chip select pin - int32_t csPin = connectionSettings[ SpiConnectionSettings::FIELD___csLine ].NumericByRef().s4; + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + NANOCLR_NOCLEANUP(); +} - SPIConfig spi_cfg = - { - NULL, - GPIO_PORT(csPin), - csPin % 16, - CR1, - }; - - switch (bus) - { - #if STM32_SPI_USE_SPI1 - case 1 : spiStart(&SPID1, &spi_cfg); - break; - #endif - #if STM32_SPI_USE_SPI2 - case 2 : spiStart(&SPID2, &spi_cfg); - break; - #endif - #if STM32_SPI_USE_SPI3 - case 3 : spiStart(&SPID3, &spi_cfg); - break; - #endif - #if STM32_SPI_USE_SPI4 - case 4 : spiStart(&SPID4, &spi_cfg); - break; - #endif - #if STM32_SPI_USE_SPI5 - case 5 : spiStart(&SPID5, &spi_cfg); - break; - #endif - #if STM32_SPI_USE_SPI6 - case 6 : spiStart(&SPID6, &spi_cfg); - break; - #endif +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); - } + // nothing to do in the native init - } NANOCLR_NOCLEANUP(); } @@ -273,22 +265,22 @@ HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::GetDeviceSelec char* retVal = ""; #if STM32_SPI_USE_SPI1 - strcat(retVal,"SPI1"); + strcat(retVal,"SPI1,"); #endif #if STM32_SPI_USE_SPI2 - strcat(retVal,",SPI2"); + strcat(retVal,"SPI2,"); #endif #if STM32_SPI_USE_SPI3 - strcat(retVal,",SPI3"); + strcat(retVal,"SPI3,"); #endif #if STM32_SPI_USE_SPI4 - strcat(retVal,",SPI4"); + strcat(retVal,"SPI4,"); #endif #if STM32_SPI_USE_SPI5 - strcat(retVal,",SPI5"); + strcat(retVal,"SPI5,"); #endif #if STM32_SPI_USE_SPI6 - strcat(retVal,",SPI6"); + strcat(retVal,"SPI6"); #endif stack.SetResult_String( retVal ); diff --git a/targets/CMSIS-OS/ChibiOS/nanoCLR/targetPAL.c b/targets/CMSIS-OS/ChibiOS/nanoCLR/targetPAL.c new file mode 100644 index 0000000000..9cff098439 --- /dev/null +++ b/targets/CMSIS-OS/ChibiOS/nanoCLR/targetPAL.c @@ -0,0 +1,36 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +stm32_gpio_t* gpioPort[] = { GPIOA, GPIOB +#if STM32_HAS_GPIOC +, GPIOC +#endif +#if STM32_HAS_GPIOD +, GPIOD +#endif +#if STM32_HAS_GPIOE +, GPIOE +#endif +#if STM32_HAS_GPIOF +, GPIOF +#endif +#if STM32_HAS_GPIOG +, GPIOG +#endif +#if STM32_HAS_GPIOH +, GPIOH +#endif +#if STM32_HAS_GPIOI +, GPIOI +#endif +#if STM32_HAS_GPIOJ +, GPIOJ +#endif +#if STM32_HAS_GPIOK +, GPIOK +#endif +};