diff --git a/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_windows_devices_serialcommunication_config.cpp b/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_windows_devices_serialcommunication_config.cpp
index e7987e3518..18ef762d75 100644
--- a/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_windows_devices_serialcommunication_config.cpp
+++ b/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_windows_devices_serialcommunication_config.cpp
@@ -5,6 +5,113 @@
 
 #include "win_dev_serial_native.h"
 
+///////////
+// UART1 //
+///////////
+
+// pin configuration for UART1
+// port: GPIOA
+// TX pin: is GPIOA_9
+// RX pin: is GPIOA_10
+// GPIO alternate pin function is 7 (see "Table 12. STM32F427xx and STM32F429xx alternate function mapping" in STM32F427xx and STM32F429xx datasheet)
+UART_CONFIG_PINS(1, GPIOA, 9, 10, 7)
+
+// buffers size
+// tx buffer size: 256 bytes
+#define UART1_TX_SIZE  256
+// rx buffer size: 256 bytes
+#define UART1_RX_SIZE  256
+
+// buffers
+// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary
+// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache)
+#if defined(__GNUC__)
+__attribute__((aligned (32)))
+#endif
+uint8_t Uart1_TxBuffer[UART1_TX_SIZE];
+#if defined(__GNUC__)
+__attribute__((aligned (32)))
+#endif
+uint8_t Uart1_RxBuffer[UART1_RX_SIZE];
+
+// initialization for UART1
+UART_INIT(1, UART1_TX_SIZE, UART1_RX_SIZE)
+
+// un-initialization for UART1
+UART_UNINIT(1)
+
+
+///////////
+// UART2 //
+///////////
+
+// pin configuration for UART2
+// port: GPIOD
+// TX pin: is GPIOD_5
+// RX pin: is GPIOD_6
+// GPIO alternate pin function is 7 (see "Table 12. STM32F427xx and STM32F429xx alternate function mapping" in STM32F427xx and STM32F429xx datasheet)
+UART_CONFIG_PINS(2, GPIOD, 5, 6, 7)
+
+// buffers size
+// tx buffer size: 256 bytes
+#define UART2_TX_SIZE  256
+// rx buffer size: 256 bytes
+#define UART2_RX_SIZE  256
+
+// buffers
+// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary
+// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache)
+#if defined(__GNUC__)
+__attribute__((aligned (32)))
+#endif
+uint8_t Uart2_TxBuffer[UART2_TX_SIZE];
+#if defined(__GNUC__)
+__attribute__((aligned (32)))
+#endif
+uint8_t Uart2_RxBuffer[UART2_RX_SIZE];
+
+// initialization for UART2
+UART_INIT(2, UART2_TX_SIZE, UART2_RX_SIZE)
+
+// un-initialization for UART2
+UART_UNINIT(2)
+
+
+///////////
+// UART3 //
+///////////
+
+// pin configuration for UART3
+// port: GPIOD
+// TX pin: is GPIOD_8
+// RX pin: is GPIOD_9
+// GPIO alternate pin function is 7 (see "Table 12. STM32F427xx and STM32F429xx alternate function mapping" in STM32F427xx and STM32F429xx datasheet)
+UART_CONFIG_PINS(3, GPIOD, 8, 9, 7)
+
+// buffers size
+// tx buffer size: 256 bytes
+#define UART3_TX_SIZE  256
+// rx buffer size: 256 bytes
+#define UART3_RX_SIZE  256
+
+// buffers
+// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary
+// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache)
+#if defined(__GNUC__)
+__attribute__((aligned (32)))
+#endif
+uint8_t Uart3_TxBuffer[UART3_TX_SIZE];
+#if defined(__GNUC__)
+__attribute__((aligned (32)))
+#endif
+uint8_t Uart3_RxBuffer[UART3_RX_SIZE];
+
+// initialization for UART3
+UART_INIT(3, UART3_TX_SIZE, UART3_RX_SIZE)
+
+// un-initialization for UART3
+UART_UNINIT(3)
+
 
 ///////////
 // UART6 //