From be0ad92c75d67344a8fb308503a91576ce023bf9 Mon Sep 17 00:00:00 2001 From: Milad Fa Date: Wed, 10 Sep 2025 16:29:23 +0000 Subject: [PATCH] deps: V8: cherry-pick 2abc61361dd4 Original commit message: Fix scratch registers passed to mtvsrdd `ra` cannot be r0 as it will be interpreted as Operand(0) Change-Id: Idce58191f9d3578dc91dc4aa3872a0bf2939d8b3 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/6936113 Commit-Queue: Milad Farazmand Reviewed-by: Junliang Yan Cr-Commit-Position: refs/heads/main@{#102388} Refs: https://github.com/v8/v8/commit/2abc61361dd4452f25de96b9d1241ed9f51bd202 --- common.gypi | 2 +- deps/v8/src/codegen/ppc/macro-assembler-ppc.cc | 4 ++++ deps/v8/src/compiler/backend/ppc/code-generator-ppc.cc | 2 +- deps/v8/src/wasm/baseline/ppc/liftoff-assembler-ppc-inl.h | 2 +- 4 files changed, 7 insertions(+), 3 deletions(-) diff --git a/common.gypi b/common.gypi index 4906769afbd55b..7a68c62aae0d3a 100644 --- a/common.gypi +++ b/common.gypi @@ -38,7 +38,7 @@ # Reset this number to 0 on major V8 upgrades. # Increment by one for each non-official patch applied to deps/v8. - 'v8_embedder_string': '-node.8', + 'v8_embedder_string': '-node.9', ##### V8 defaults for Node.js ##### diff --git a/deps/v8/src/codegen/ppc/macro-assembler-ppc.cc b/deps/v8/src/codegen/ppc/macro-assembler-ppc.cc index 35e63884fa1736..eb9018b9577d45 100644 --- a/deps/v8/src/codegen/ppc/macro-assembler-ppc.cc +++ b/deps/v8/src/codegen/ppc/macro-assembler-ppc.cc @@ -3981,6 +3981,7 @@ void MacroAssembler::I64x2Mul(Simd128Register dst, Simd128Register src1, if (CpuFeatures::IsSupported(PPC_10_PLUS)) { vmulld(dst, src1, src2); } else { + DCHECK(scratch1 != r0); Register scratch_1 = scratch1; Register scratch_2 = scratch2; for (int i = 0; i < 2; i++) { @@ -4333,6 +4334,7 @@ void MacroAssembler::I8x16BitMask(Register dst, Simd128Register src, if (CpuFeatures::IsSupported(PPC_10_PLUS)) { vextractbm(dst, src); } else { + DCHECK(scratch1 != r0); mov(scratch1, Operand(0x8101820283038)); mov(scratch2, Operand(0x4048505860687078)); mtvsrdd(scratch3, scratch1, scratch2); @@ -4385,6 +4387,7 @@ void MacroAssembler::I8x16Shuffle(Simd128Register dst, Simd128Register src1, Simd128Register src2, uint64_t high, uint64_t low, Register scratch1, Register scratch2, Simd128Register scratch3) { + DCHECK(scratch2 != r0); mov(scratch1, Operand(low)); mov(scratch2, Operand(high)); mtvsrdd(scratch3, scratch2, scratch1); @@ -4673,6 +4676,7 @@ void MacroAssembler::S128Not(Simd128Register dst, Simd128Register src) { void MacroAssembler::S128Const(Simd128Register dst, uint64_t high, uint64_t low, Register scratch1, Register scratch2) { + DCHECK(scratch2 != r0); mov(scratch1, Operand(low)); mov(scratch2, Operand(high)); mtvsrdd(dst, scratch2, scratch1); diff --git a/deps/v8/src/compiler/backend/ppc/code-generator-ppc.cc b/deps/v8/src/compiler/backend/ppc/code-generator-ppc.cc index 83dfc3d560144f..c9e62e847e9540 100644 --- a/deps/v8/src/compiler/backend/ppc/code-generator-ppc.cc +++ b/deps/v8/src/compiler/backend/ppc/code-generator-ppc.cc @@ -2743,7 +2743,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( break; } case kPPC_I8x16BitMask: { - __ I8x16BitMask(i.OutputRegister(), i.InputSimd128Register(0), r0, ip, + __ I8x16BitMask(i.OutputRegister(), i.InputSimd128Register(0), ip, r0, kScratchSimd128Reg); break; } diff --git a/deps/v8/src/wasm/baseline/ppc/liftoff-assembler-ppc-inl.h b/deps/v8/src/wasm/baseline/ppc/liftoff-assembler-ppc-inl.h index 7e85d568a62e06..9f1b70a560b5f9 100644 --- a/deps/v8/src/wasm/baseline/ppc/liftoff-assembler-ppc-inl.h +++ b/deps/v8/src/wasm/baseline/ppc/liftoff-assembler-ppc-inl.h @@ -2861,7 +2861,7 @@ void LiftoffAssembler::emit_v128_anytrue(LiftoffRegister dst, void LiftoffAssembler::emit_i8x16_bitmask(LiftoffRegister dst, LiftoffRegister src) { - I8x16BitMask(dst.gp(), src.fp().toSimd(), r0, ip, kScratchSimd128Reg); + I8x16BitMask(dst.gp(), src.fp().toSimd(), ip, r0, kScratchSimd128Reg); } void LiftoffAssembler::emit_s128_const(LiftoffRegister dst,