From 1e6efe5abce3cc03028332838a4050c5b2f88147 Mon Sep 17 00:00:00 2001 From: svv232 Date: Sun, 1 Dec 2024 16:50:05 -0500 Subject: [PATCH 1/2] implementation for branch not equal instruction --- .../src/interpreters/riscv32im/interpreter.rs | 29 ++++++++++++++++--- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index 04d50853f2..462ded8981 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -2141,8 +2141,8 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction - (imm11.clone() * Env::constant(1 << 7)) // imm11 at bits 8 - (imm1_4.clone() * Env::constant(1 << 8)) // imm1_4 at bits 9-11 - (funct3 * Env::constant(1 << 11)) // funct3 at bits 11-14 - - (rs1 * Env::constant(1 << 14)) // rs1 at bits 15-20 - - (rs2 * Env::constant(1 << 19)) // rs2 at bits 20-24 + - (rs1.clone() * Env::constant(1 << 14)) // rs1 at bits 15-20 + - (rs2.clone() * Env::constant(1 << 19)) // rs2 at bits 20-24 - (imm5_10.clone() * Env::constant(1 << 24)) // imm5_10 at bits 25-30 - (imm12.clone() * Env::constant(1 << 31)), // imm12 at bits 31 ); @@ -2153,14 +2153,35 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction + (imm1_4 * Env::constant(1 << 1)) }; // extra bit is because the 0th bit in the immediate is always 0 i.e you cannot jump to an odd address - let _imm0_12 = env.sign_extend(&imm0_12, 13); + let imm0_12 = env.sign_extend(&imm0_12, 13); match instr { SBInstruction::BranchEq => { unimplemented!("BranchEq") } SBInstruction::BranchNeq => { - unimplemented!("BranchNeq") + // bne: if (x[rs1] != x[rs2]) pc += sext(offset) + let local_rs1 = env.read_register(&rs1); + let local_rs2 = env.read_register(&rs2); + + let equals = env.equal(&local_rs1, &local_rs2); + let offset = equals.clone() * Env::constant(4) + (Env::constant(1) - equals) * imm0_12; + let addr = { + let res_scratch = env.alloc_scratch(); + let overflow_scratch = env.alloc_scratch(); + let (res, _overflow) = unsafe { + env.add_witness( + &next_instruction_pointer, + &offset, + res_scratch, + overflow_scratch, + ) + }; + // FIXME: Requires a range check + res + }; + env.set_instruction_pointer(next_instruction_pointer); + env.set_next_instruction_pointer(addr); } SBInstruction::BranchLessThan => { unimplemented!("BranchLessThan") From c281b7eee2d6ee1bf62230e0affe47bb8c7b365b Mon Sep 17 00:00:00 2001 From: svv232 Date: Sun, 1 Dec 2024 17:30:17 -0500 Subject: [PATCH 2/2] fixing unused variable naming to fix CI --- o1vm/src/interpreters/riscv32im/interpreter.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/o1vm/src/interpreters/riscv32im/interpreter.rs b/o1vm/src/interpreters/riscv32im/interpreter.rs index 462ded8981..b379c5b290 100644 --- a/o1vm/src/interpreters/riscv32im/interpreter.rs +++ b/o1vm/src/interpreters/riscv32im/interpreter.rs @@ -2069,7 +2069,7 @@ pub fn interpret_sbtype(env: &mut Env, instr: SBInstruction /* fetch instruction pointer from the program state */ let instruction_pointer = env.get_instruction_pointer(); /* compute the next instruction ptr and add one, as well record raml lookup */ - let _next_instruction_pointer = env.get_next_instruction_pointer(); + let next_instruction_pointer = env.get_next_instruction_pointer(); /* read instruction from ip address */ let instruction = { let v0 = env.read_memory(&instruction_pointer);