diff --git a/edalize/edatool.py b/edalize/edatool.py index b51278b92..f53f31107 100644 --- a/edalize/edatool.py +++ b/edalize/edatool.py @@ -161,7 +161,6 @@ def __init__(self, edam=None, work_root=None, eda_api=None, verbose=True): self.hooks = edam.get("hooks", {}) self.parameters = edam.get("parameters", {}) - self.export_files = edam.get("export_files", True) self.work_root = work_root self.env = os.environ.copy() diff --git a/edalize/libero.py b/edalize/libero.py index 0155f6297..09f0cd297 100644 --- a/edalize/libero.py +++ b/edalize/libero.py @@ -130,7 +130,6 @@ def configure_main(self): "op": "{", "cl": "}", "sp": " ", - "export_files": self.export_files, } # Set preferred HDL language based on file type amount if not user defined. @@ -203,11 +202,7 @@ def syn_constraint_file_filter(self, f): } _file_type = f.file_type.split("-")[0] if _file_type in file_types: - if self.export_files: - filename = f.name.split("/")[-1] - return file_types[_file_type] + filename - else: - return f.name + return f.name return "" def pnr_constraint_file_filter(self, f): @@ -218,11 +213,7 @@ def pnr_constraint_file_filter(self, f): } _file_type = f.file_type.split("-")[0] if _file_type in file_types: - if self.export_files: - filename = f.name.split("/")[-1] - return file_types[_file_type] + filename - else: - return f.name + return f.name return "" def constraint_file_filter(self, f, type="ALL"): @@ -234,18 +225,8 @@ def constraint_file_filter(self, f, type="ALL"): "NDC": "constraint/", } _file_type = f.file_type.split("-")[0] - if _file_type in file_types: - if self.export_files: - filename = f.name.split("/")[-1] - if type == "ALL": - return file_types[_file_type] + filename - elif _file_type == type: - return file_types[_file_type] + filename - else: - if type == "ALL": - return f.name - elif _file_type == type: - return f.name + if _file_type in file_types and (type == "ALL" or type == _file_type): + return f.name return "" def build_main(self): diff --git a/edalize/templates/libero/libero-project.tcl.j2 b/edalize/templates/libero/libero-project.tcl.j2 index 2d012cfe3..e5d84fc00 100644 --- a/edalize/templates/libero/libero-project.tcl.j2 +++ b/edalize/templates/libero/libero-project.tcl.j2 @@ -4,8 +4,26 @@ puts "----------------- Creating project {{name}} ------------------------------" # Create a new project with device parameters -new_project -location {{op}}{{prj_root}}{{cl}} -name {{name}} -project_description {} -hdl {{op}}{{tool_options.hdl}}{{cl}} -family {{op}}{{tool_options.family}}{{cl}} -die {{op}}{{tool_options.die}}{{cl}} -package {{op}}{{tool_options.package}}{{cl}} {% if tool_options.speed -%} -speed {{op}}{{tool_options.speed}}{{cl}}{{sp}}{%- endif %}{% if tool_options.dievoltage -%} -die_voltage {{op}}{{tool_options.dievoltage}}{{cl}}{{sp}}{%- endif %}{% if tool_options.range -%}-part_range {{op}}{{tool_options.range}}{{cl}}{{sp}}{%- endif %}{% if tool_options.defiostd -%} -adv_options {IO_DEFT_STD:{{tool_options.defiostd}}{{cl}}{% endif %} - +new_project \ + -location {{op}}{{prj_root}}{{cl}} \ + -name {{name}} \ + -project_description {} \ + -hdl {{op}}{{tool_options.hdl}}{{cl}} \ + -family {{op}}{{tool_options.family}}{{cl}} \ + -die {{op}}{{tool_options.die}}{{cl}} \ + -package {{op}}{{tool_options.package}}{{cl}} \ +{% if tool_options.speed %} + -speed {{op}}{{tool_options.speed}}{{cl}}{{sp}} \ +{% endif %} +{% if tool_options.dievoltage %} + -die_voltage {{op}}{{tool_options.dievoltage}}{{cl}}{{sp}} \ +{% endif %} +{% if tool_options.range %} + -part_range {{op}}{{tool_options.range}}{{cl}}{{sp}} \ +{% endif %} +{% if tool_options.defiostd %} + -adv_options {IO_DEFT_STD:{{tool_options.defiostd}}{{cl}} \ +{% endif %} {% if incdirs %} # Set up the include directories @@ -13,26 +31,17 @@ set_global_include_path_order -paths "{% for incdir in incdirs %} {{incdir}} {% build_design_hierarchy {% endif %} -# Import HDL sources and constraints -{% if export_files %} -set libero_export_files 1 - +# Link HDL sources and constraints +create_links \ {% for src_file in src_files if src_file|src_file_filter%} -import_files {{src_file|src_file_filter}}{{cl}} + {{src_file|src_file_filter}}{{cl}} \ {% endfor %} -{% else %} -set libero_export_files 0 - -{% for src_file in src_files if src_file|src_file_filter%} -create_links {{src_file|src_file_filter}}{{cl}} -{% endfor %} -{% endif %} # Import HDL sources on libraries (logical_names) {% for library in library_files.items() %} {% set lib = library[0] %} {% set files = library[1] %} -import_files \ +create_links \ -library {{op}}{{lib}}{{cl}} \ {% for f in files %} -hdl_source {{op}}{{f}}{{cl}} \ @@ -67,14 +76,14 @@ puts "----------------------- Synthesize Constraints --------------------------- {% set ns = namespace(SYN=false) %}{# If synthesis constraints are present #} {% for src_file in src_files if src_file|syn_constraint_file_filter %} {% set ns.SYN=true %} -puts "File: {% if export_files %}{{prj_root}}/{% endif %}{{src_file|syn_constraint_file_filter}}" +puts "File: {{src_file|syn_constraint_file_filter}}" {% endfor %} {%- if ns.SYN %} # Configure Synthesize tool to use the project constraints organize_tool_files -tool {SYNTHESIZE} \ {% for src_file in src_files if src_file|syn_constraint_file_filter %} - -file {{op}}{% if export_files %}{{prj_root}}/{% endif %}{{src_file|syn_constraint_file_filter}}{{cl}} \ + -file {{op}}{{src_file|syn_constraint_file_filter}}{{cl}} \ {% endfor %} -module {{op}}{{toplevel}}::work{{cl}} -input_type {constraint} {% endif %} @@ -84,13 +93,13 @@ puts "----------------------- Place and Route Constraints ---------------------- {% set ns.PNR=false %} {% for src_file in src_files if src_file|pnr_constraint_file_filter %} {% set ns.PNR=true %} -puts "File: {% if export_files %}{{prj_root}}/{% endif %}{{src_file|pnr_constraint_file_filter}}" +puts "File: {{src_file|pnr_constraint_file_filter}}" {% endfor %} {% if ns.PNR %} organize_tool_files -tool {PLACEROUTE} \ {% for src_file in src_files if src_file|pnr_constraint_file_filter %} - -file {{op}}{% if export_files %}{{prj_root}}/{% endif %}{{src_file|pnr_constraint_file_filter}}{{cl}} \ + -file {{op}}{{src_file|pnr_constraint_file_filter}}{{cl}} \ {% endfor %} -module {{op}}{{toplevel}}::work{{cl}} -input_type {constraint} {% endif %} @@ -100,13 +109,13 @@ puts "----------------------- Verify Timings Constraints ----------------------- {% set ns.TIM=false %} {%- for src_file in src_files if src_file|constraint_file_filter("SDC") %} {% set ns.TIM=true %} -puts "File: {% if export_files %}{{prj_root}}/{% endif %}{{src_file|constraint_file_filter}}" +puts "File: {{src_file|constraint_file_filter}}" {% endfor %} {%- if ns.TIM %} organize_tool_files -tool {VERIFYTIMING} \ {% for src_file in src_files if src_file|constraint_file_filter("SDC") %} - -file {{op}}{% if export_files %}{{prj_root}}/{% endif %}{{src_file|constraint_file_filter}}{{cl}} \ + -file {{op}}{{src_file|constraint_file_filter}}{{cl}} \ {% endfor %} -module {{op}}{{toplevel}}::work{{cl}} -input_type {constraint} {% endif %} diff --git a/tests/test_libero/libero-test-all-project.tcl b/tests/test_libero/libero-test-all-project.tcl index 1592679b1..32ef81aa3 100644 --- a/tests/test_libero/libero-test-all-project.tcl +++ b/tests/test_libero/libero-test-all-project.tcl @@ -4,27 +4,37 @@ puts "----------------- Creating project libero-test-all ------------------------------" # Create a new project with device parameters -new_project -location {./prj} -name libero-test-all -project_description {} -hdl {VHDL} -family {PolarFire} -die {MPF300TS_ES} -package {FCG1152} -speed {-1} -die_voltage {1.0} -part_range {EXT} -adv_options {IO_DEFT_STD:LVCMOS 1.8V} +new_project \ + -location {./prj} \ + -name libero-test-all \ + -project_description {} \ + -hdl {VHDL} \ + -family {PolarFire} \ + -die {MPF300TS_ES} \ + -package {FCG1152} \ + -speed {-1} \ + -die_voltage {1.0} \ + -part_range {EXT} \ + -adv_options {IO_DEFT_STD:LVCMOS 1.8V} \ # Set up the include directories set_global_include_path_order -paths " . " build_design_hierarchy -# Import HDL sources and constraints -set libero_export_files 1 - -import_files -sdc {sdc_file} -import_files -hdl_source {sv_file.sv} -import_files -hdl_source {vlog_file.v} -import_files -hdl_source {vlog05_file.v} -import_files -hdl_source {vhdl_file.vhd} -import_files -hdl_source {vhdl2008_file} -import_files -hdl_source {another_sv_file.sv} -import_files -io_pdc {pdc_constraint_file.pdc} -import_files -fp_pdc {pdc_floorplan_constraint_file.pdc} +# Link HDL sources and constraints +create_links \ + -sdc {sdc_file} \ + -hdl_source {sv_file.sv} \ + -hdl_source {vlog_file.v} \ + -hdl_source {vlog05_file.v} \ + -hdl_source {vhdl_file.vhd} \ + -hdl_source {vhdl2008_file} \ + -hdl_source {another_sv_file.sv} \ + -io_pdc {pdc_constraint_file.pdc} \ + -fp_pdc {pdc_floorplan_constraint_file.pdc} \ # Import HDL sources on libraries (logical_names) -import_files \ +create_links \ -library {libx} \ -hdl_source {vhdl_lfile} \ @@ -49,29 +59,29 @@ puts "Configured Synthesize tool to include dirs:" puts "- ../../." puts "----------------------- Synthesize Constraints ---------------------------" -puts "File: ./prj/constraint/sdc_file" +puts "File: sdc_file" # Configure Synthesize tool to use the project constraints organize_tool_files -tool {SYNTHESIZE} \ - -file {./prj/constraint/sdc_file} \ + -file {sdc_file} \ -module {top_module::work} -input_type {constraint} # Configure Place and Route tool to use the project constraints puts "----------------------- Place and Route Constraints ----------------------" -puts "File: ./prj/constraint/sdc_file" -puts "File: ./prj/constraint/io/pdc_constraint_file.pdc" -puts "File: ./prj/constraint/fp/pdc_floorplan_constraint_file.pdc" +puts "File: sdc_file" +puts "File: pdc_constraint_file.pdc" +puts "File: pdc_floorplan_constraint_file.pdc" organize_tool_files -tool {PLACEROUTE} \ - -file {./prj/constraint/sdc_file} \ - -file {./prj/constraint/io/pdc_constraint_file.pdc} \ - -file {./prj/constraint/fp/pdc_floorplan_constraint_file.pdc} \ + -file {sdc_file} \ + -file {pdc_constraint_file.pdc} \ + -file {pdc_floorplan_constraint_file.pdc} \ -module {top_module::work} -input_type {constraint} # Configure Verify Timing tool to use the project constraints puts "----------------------- Verify Timings Constraints -----------------------" -puts "File: ./prj/constraint/sdc_file" +puts "File: sdc_file" organize_tool_files -tool {VERIFYTIMING} \ - -file {./prj/constraint/sdc_file} \ + -file {sdc_file} \ -module {top_module::work} -input_type {constraint} save_project diff --git a/tests/test_libero/libero-test-project.tcl b/tests/test_libero/libero-test-project.tcl index 615ef811f..ac72b481e 100644 --- a/tests/test_libero/libero-test-project.tcl +++ b/tests/test_libero/libero-test-project.tcl @@ -4,27 +4,34 @@ puts "----------------- Creating project libero-test ------------------------------" # Create a new project with device parameters -new_project -location {./prj} -name libero-test -project_description {} -hdl {VERILOG} -family {PolarFire} -die {MPF300TS_ES} -package {FCG1152} -part_range {IND} +new_project \ + -location {./prj} \ + -name libero-test \ + -project_description {} \ + -hdl {VERILOG} \ + -family {PolarFire} \ + -die {MPF300TS_ES} \ + -package {FCG1152} \ + -part_range {IND} \ # Set up the include directories set_global_include_path_order -paths " . " build_design_hierarchy -# Import HDL sources and constraints -set libero_export_files 1 - -import_files -sdc {sdc_file} -import_files -hdl_source {sv_file.sv} -import_files -hdl_source {vlog_file.v} -import_files -hdl_source {vlog05_file.v} -import_files -hdl_source {vhdl_file.vhd} -import_files -hdl_source {vhdl2008_file} -import_files -hdl_source {another_sv_file.sv} -import_files -io_pdc {pdc_constraint_file.pdc} -import_files -fp_pdc {pdc_floorplan_constraint_file.pdc} +# Link HDL sources and constraints +create_links \ + -sdc {sdc_file} \ + -hdl_source {sv_file.sv} \ + -hdl_source {vlog_file.v} \ + -hdl_source {vlog05_file.v} \ + -hdl_source {vhdl_file.vhd} \ + -hdl_source {vhdl2008_file} \ + -hdl_source {another_sv_file.sv} \ + -io_pdc {pdc_constraint_file.pdc} \ + -fp_pdc {pdc_floorplan_constraint_file.pdc} \ # Import HDL sources on libraries (logical_names) -import_files \ +create_links \ -library {libx} \ -hdl_source {vhdl_lfile} \ @@ -49,29 +56,29 @@ puts "Configured Synthesize tool to include dirs:" puts "- ../../." puts "----------------------- Synthesize Constraints ---------------------------" -puts "File: ./prj/constraint/sdc_file" +puts "File: sdc_file" # Configure Synthesize tool to use the project constraints organize_tool_files -tool {SYNTHESIZE} \ - -file {./prj/constraint/sdc_file} \ + -file {sdc_file} \ -module {top_module::work} -input_type {constraint} # Configure Place and Route tool to use the project constraints puts "----------------------- Place and Route Constraints ----------------------" -puts "File: ./prj/constraint/sdc_file" -puts "File: ./prj/constraint/io/pdc_constraint_file.pdc" -puts "File: ./prj/constraint/fp/pdc_floorplan_constraint_file.pdc" +puts "File: sdc_file" +puts "File: pdc_constraint_file.pdc" +puts "File: pdc_floorplan_constraint_file.pdc" organize_tool_files -tool {PLACEROUTE} \ - -file {./prj/constraint/sdc_file} \ - -file {./prj/constraint/io/pdc_constraint_file.pdc} \ - -file {./prj/constraint/fp/pdc_floorplan_constraint_file.pdc} \ + -file {sdc_file} \ + -file {pdc_constraint_file.pdc} \ + -file {pdc_floorplan_constraint_file.pdc} \ -module {top_module::work} -input_type {constraint} # Configure Verify Timing tool to use the project constraints puts "----------------------- Verify Timings Constraints -----------------------" -puts "File: ./prj/constraint/sdc_file" +puts "File: sdc_file" organize_tool_files -tool {VERIFYTIMING} \ - -file {./prj/constraint/sdc_file} \ + -file {sdc_file} \ -module {top_module::work} -input_type {constraint} save_project