From 34b78a0f1794463746f93af3b3d415a90cf6a63d Mon Sep 17 00:00:00 2001 From: Craig Blackmore Date: Thu, 31 Aug 2023 13:37:45 +0100 Subject: [PATCH] Fix Luimm5 and ls[23] typos These should be Iuimm5 and Is[23]. Signed-off-by: Craig Blackmore --- docs/source/instruction_set_extensions.rst | 66 +++++++++++----------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/docs/source/instruction_set_extensions.rst b/docs/source/instruction_set_extensions.rst index 351720f22..fbe126349 100644 --- a/docs/source/instruction_set_extensions.rst +++ b/docs/source/instruction_set_extensions.rst @@ -672,19 +672,19 @@ Bit Manipulation Encoding +--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+ | 31: 30 | 29 : 25 | 24 : 20 | 19 : 15 | 14 : 12 | 11 : 7 | 6 : 0 | | +--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+ - | **f2** | **ls3[4:0]** | **ls2[4:0]** | **rs1** | **funct3** | **rD** | **opcode** | **Mnemonic** | + | **f2** | **Is3[4:0]** | **Is2[4:0]** | **rs1** | **funct3** | **rD** | **opcode** | **Mnemonic** | +========+======================+===============+=========+============+========+============+====================================+ - | 00 | Luimm5[4:0] | Iuimm5[4:0] | src | 000 | dest | 101 1011 | **cv.extract rD, rs1, Is3, Is2** | + | 00 | Iuimm5[4:0] | Iuimm5[4:0] | src | 000 | dest | 101 1011 | **cv.extract rD, rs1, Is3, Is2** | +--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+ - | 01 | Luimm5[4:0] | Iuimm5[4:0] | src | 000 | dest | 101 1011 | **cv.extractu rD, rs1, Is3, Is2** | + | 01 | Iuimm5[4:0] | Iuimm5[4:0] | src | 000 | dest | 101 1011 | **cv.extractu rD, rs1, Is3, Is2** | +--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+ - | 10 | Luimm5[4:0] | Iuimm5[4:0] | src | 000 | dest | 101 1011 | **cv.insert rD, rs1, Is3, Is2** | + | 10 | Iuimm5[4:0] | Iuimm5[4:0] | src | 000 | dest | 101 1011 | **cv.insert rD, rs1, Is3, Is2** | +--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+ - | 00 | Luimm5[4:0] | Iuimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bclr rD, rs1, Is3, Is2** | + | 00 | Iuimm5[4:0] | Iuimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bclr rD, rs1, Is3, Is2** | +--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+ - | 01 | Luimm5[4:0] | Iuimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bset rD, rs1, Is3, Is2** | + | 01 | Iuimm5[4:0] | Iuimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bset rD, rs1, Is3, Is2** | +--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+ - | 11 | 000, Luimm2[1:0] | Iuimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bitrev rD, rs1, Is3, Is2** | + | 11 | 000, Iuimm2[1:0] | Iuimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bitrev rD, rs1, Is3, Is2** | +--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+ .. table:: Register Bit Manipulation operations encoding @@ -771,7 +771,7 @@ General ALU operations | | | | | else rD = rs1 | | | | - | | Note: If ls2 is equal to 0, | + | | Note: If Is2 is equal to 0, | | | | | | -2^(Is2-1) is equivalent to -1 while (2^(Is2-1)-1) is equivalent to 0. | +-------------------------------------------+------------------------------------------------------------------------+ @@ -781,7 +781,7 @@ General ALU operations | | | | | else rD = rs1 | | | | - | | Note: If ls2 is equal to 0, (2^(Is2-1)-1) is equivalent to 0. | + | | Note: If Is2 is equal to 0, (2^(Is2-1)-1) is equivalent to 0. | +-------------------------------------------+------------------------------------------------------------------------+ | **cv.clipr rD, rs1, rs2** | if rs1 <= -(rs2+1), rD = -(rs2+1), | | | | @@ -945,21 +945,21 @@ General ALU Encoding +--------+---------------+---------+---------+------------+--------+------------+----------------------------------+ | **f2** | **Is3[4:0]** | **rs2** | **rs1** | **funct3** | **rD** | **opcode** | | +========+===============+=========+=========+============+========+============+==================================+ - | 00 | Luimm5[4:0] | src2 | src1 | 010 | dest | 101 1011 | **cv.addN rD, rs1, rs2, Is3** | + | 00 | Iuimm5[4:0] | src2 | src1 | 010 | dest | 101 1011 | **cv.addN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+----------------------------------+ - | 01 | Luimm5[4:0] | src2 | src1 | 010 | dest | 101 1011 | **cv.adduN rD, rs1, rs2, Is3** | + | 01 | Iuimm5[4:0] | src2 | src1 | 010 | dest | 101 1011 | **cv.adduN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+----------------------------------+ - | 10 | Luimm5[4:0] | src2 | src1 | 010 | dest | 101 1011 | **cv.addRN rD, rs1, rs2, Is3** | + | 10 | Iuimm5[4:0] | src2 | src1 | 010 | dest | 101 1011 | **cv.addRN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+----------------------------------+ - | 11 | Luimm5[4:0] | src2 | src1 | 010 | dest | 101 1011 | **cv.adduRN rD, rs1, rs2, Is3** | + | 11 | Iuimm5[4:0] | src2 | src1 | 010 | dest | 101 1011 | **cv.adduRN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+----------------------------------+ - | 00 | Luimm5[4:0] | src2 | src1 | 011 | dest | 101 1011 | **cv.subN rD, rs1, rs2, Is3** | + | 00 | Iuimm5[4:0] | src2 | src1 | 011 | dest | 101 1011 | **cv.subN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+----------------------------------+ - | 01 | Luimm5[4:0] | src2 | src1 | 011 | dest | 101 1011 | **cv.subuN rD, rs1, rs2, Is3** | + | 01 | Iuimm5[4:0] | src2 | src1 | 011 | dest | 101 1011 | **cv.subuN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+----------------------------------+ - | 10 | Luimm5[4:0] | src2 | src1 | 011 | dest | 101 1011 | **cv.subRN rD, rs1, rs2, Is3** | + | 10 | Iuimm5[4:0] | src2 | src1 | 011 | dest | 101 1011 | **cv.subRN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+----------------------------------+ - | 11 | Luimm5[4:0] | src2 | src1 | 011 | dest | 101 1011 | **cv.subuRN rD, rs1, rs2, Is3** | + | 11 | Iuimm5[4:0] | src2 | src1 | 011 | dest | 101 1011 | **cv.subuRN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+----------------------------------+ .. table:: General ALU operations encoding @@ -1201,21 +1201,21 @@ Encoding +--------+---------------+---------+---------+------------+--------+------------+------------------------------------+ | **f2** | **Is3[4:0]** | **rs2** | **rs1** | **funct3** | **rD** | **opcode** | | +========+===============+=========+=========+============+========+============+====================================+ - | 00 | Luimm5[4:0] | src2 | src1 | 101 | dest | 101 1011 | **cv.muluN rD, rs1, rs2, Is3** | + | 00 | Iuimm5[4:0] | src2 | src1 | 101 | dest | 101 1011 | **cv.muluN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+------------------------------------+ - | 01 | Luimm5[4:0] | src2 | src1 | 101 | dest | 101 1011 | **cv.mulhhuN rD, rs1, rs2, Is3** | + | 01 | Iuimm5[4:0] | src2 | src1 | 101 | dest | 101 1011 | **cv.mulhhuN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+------------------------------------+ - | 00 | Luimm5[4:0] | src2 | src1 | 100 | dest | 101 1011 | **cv.mulsN rD, rs1, rs2, Is3** | + | 00 | Iuimm5[4:0] | src2 | src1 | 100 | dest | 101 1011 | **cv.mulsN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+------------------------------------+ - | 01 | Luimm5[4:0] | src2 | src1 | 100 | dest | 101 1011 | **cv.mulhhsN rD, rs1, rs2, Is3** | + | 01 | Iuimm5[4:0] | src2 | src1 | 100 | dest | 101 1011 | **cv.mulhhsN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+------------------------------------+ - | 10 | Luimm5[4:0] | src2 | src1 | 101 | dest | 101 1011 | **cv.muluRN rD, rs1, rs2, Is3** | + | 10 | Iuimm5[4:0] | src2 | src1 | 101 | dest | 101 1011 | **cv.muluRN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+------------------------------------+ - | 11 | Luimm5[4:0] | src2 | src1 | 101 | dest | 101 1011 | **cv.mulhhuRN rD, rs1, rs2, Is3** | + | 11 | Iuimm5[4:0] | src2 | src1 | 101 | dest | 101 1011 | **cv.mulhhuRN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+------------------------------------+ - | 10 | Luimm5[4:0] | src2 | src1 | 100 | dest | 101 1011 | **cv.mulsRN rD, rs1, rs2, Is3** | + | 10 | Iuimm5[4:0] | src2 | src1 | 100 | dest | 101 1011 | **cv.mulsRN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+------------------------------------+ - | 11 | Luimm5[4:0] | src2 | src1 | 100 | dest | 101 1011 | **cv.mulhhsRN rD, rs1, rs2, Is3** | + | 11 | Iuimm5[4:0] | src2 | src1 | 100 | dest | 101 1011 | **cv.mulhhsRN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+------------------------------------+ .. table:: 16-Bit Multiply-Accumulate operations @@ -1228,21 +1228,21 @@ Encoding +--------+---------------+---------+---------+------------+--------+------------+------------------------------------+ | **f2** | **Is3[4:0]** | **rs2** | **rs1** | **funct3** | **rD** | **opcode** | | +========+===============+=========+=========+============+========+============+====================================+ - | 00 | Luimm5[4:0] | src2 | src1 | 111 | dest | 101 1011 | **cv.macuN rD, rs1, rs2, Is3** | + | 00 | Iuimm5[4:0] | src2 | src1 | 111 | dest | 101 1011 | **cv.macuN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+------------------------------------+ - | 01 | Luimm5[4:0] | src2 | src1 | 111 | dest | 101 1011 | **cv.machhuN rD, rs1, rs2, Is3** | + | 01 | Iuimm5[4:0] | src2 | src1 | 111 | dest | 101 1011 | **cv.machhuN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+------------------------------------+ - | 00 | Luimm5[4:0] | src2 | src1 | 110 | dest | 101 1011 | **cv.macsN rD, rs1, rs2, Is3** | + | 00 | Iuimm5[4:0] | src2 | src1 | 110 | dest | 101 1011 | **cv.macsN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+------------------------------------+ - | 01 | Luimm5[4:0] | src2 | src1 | 110 | dest | 101 1011 | **cv.machhsN rD, rs1, rs2, Is3** | + | 01 | Iuimm5[4:0] | src2 | src1 | 110 | dest | 101 1011 | **cv.machhsN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+------------------------------------+ - | 10 | Luimm5[4:0] | src2 | src1 | 111 | dest | 101 1011 | **cv.macuRN rD, rs1, rs2, Is3** | + | 10 | Iuimm5[4:0] | src2 | src1 | 111 | dest | 101 1011 | **cv.macuRN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+------------------------------------+ - | 11 | Luimm5[4:0] | src2 | src1 | 111 | dest | 101 1011 | **cv.machhuRN rD, rs1, rs2, Is3** | + | 11 | Iuimm5[4:0] | src2 | src1 | 111 | dest | 101 1011 | **cv.machhuRN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+------------------------------------+ - | 10 | Luimm5[4:0] | src2 | src1 | 110 | dest | 101 1011 | **cv.macsRN rD, rs1, rs2, Is3** | + | 10 | Iuimm5[4:0] | src2 | src1 | 110 | dest | 101 1011 | **cv.macsRN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+------------------------------------+ - | 11 | Luimm5[4:0] | src2 | src1 | 110 | dest | 101 1011 | **cv.machhsRN rD, rs1, rs2, Is3** | + | 11 | Iuimm5[4:0] | src2 | src1 | 110 | dest | 101 1011 | **cv.machhsRN rD, rs1, rs2, Is3** | +--------+---------------+---------+---------+------------+--------+------------+------------------------------------+ .. table:: 32-Bit Multiply-Accumulate operations