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Merge from CV32E40X #486

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silabs-oysteink
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Includes CSR stall updates and an added ID stage stall for WFE which reads mstatus.tw.

silabs-oysteink and others added 8 commits August 23, 2023 09:03
1: ID stage stalls are kept as before for implicit CSR reads (mret and tablejumps). They stall on any CSR accesses in EX or WB.
2: EX stage is stalled for:
2.1: CSR instruction reading multiple CSRs (imiiplicit reads) are stalled when any CSR access is in WB
2.2: CSR instructions are stalled when any implicit CSR write is in WB
2.3: CSR instructions are stalled on a true RAW hazard with another regular CSR instruction in WB.

Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
…out stall signals being conservative i.e not factoring inn kill or halt.

Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
…k_merge-w35.23-1

Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
…X and WB sd it reads mstatus.tw.

Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
@silabs-oysteink silabs-oysteink added the Component:RTL For issues in the RTL (e.g. for files in the rtl directory) label Aug 28, 2023
@Silabs-ArjanB Silabs-ArjanB merged commit 299414b into openhwgroup:master Aug 28, 2023
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2 participants