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+# Cores TG Meeting, December 6, 2021
+
+## Attendees
+* Jérôme Quevremont (Thales)
+* Arjan Bink (Silicon Labs)
+* Oystein Knauserud (Silicon Labs)
+* Davide Schiavone (OpenHW)
+* Duncan Bees (OpenHW)
+* Jean-Luc Nagel (CSEM)
+* Pascal Gouedo (Dolphin)
+* Yoann Pruvost
+* Tariq Kurd (Huawei)
+* Ibrahim Abu Kharmeh (Huawei)
+
+## CV32E40P 'v2'
+
+Pascal gave an update on the CV32E40P status. Project Launch (PL) was presented in the TWG in November.
+
+## CV32E40X / CV32E40S
+
+Oystein gave an update on the CV32E40X / CV32E40S status. Write buffer implementation is complete. Data independent timing and dummy instruction insertion work for the CV32E40S is in progress. Formal verification is still considered a bottleneck.
+
+## CV32E41P
+
+Tariq Kurd presented the CV32E41P status. Zfinx has been implemented and Zce is almost implemented.
+
+## CVA6
+
+Jérôme Quevremont gave an update on the CVA6. 
+
+## Cores TG specific feedback from OpenHW members survey
+
+Discussed Cores TG specific feedback.
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