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Other phases will be the subject of separate proposals. Phase 1 will provide the following. - -- support for the following CORE-V instruction set extensions: - - - hardware loop; - - multiple accumulate; - - post-increment and register-indexed load/store; - - direct branches; and - - general ALU operations. - -- support for a generic CORE-V instruction set extension interface: - - - this will provide a commercial driver for future tool chain development for these extensions. - -In order to support the Software TG primary goal of developing a thriving commercial ecosystem, only a basic implementation will be provided. By basic implemention, we mean that the assembler/linker will support the instructions, the compiler will have intrinisc/builtin function support and the compiler will have patterns to generate the instructions from C code in obvious circumstances. - -However there will be no attempt to provide compiler optimization (which is a much bigger task). Software companies will rely on the majority of work still needing to be done in order to drive their businesses. - -In order to support the Software TG secondary goal of upstreaming all open source tool developments: - -- all development will be kept compliant with GNU coding standards; -- the implemenation will follow the upsrtream tool design conventions; and -- the design will remain consistent with the standard RISC-V GNU compiler tool chain. - -The finished work will be contributed and maintained upstream. - -### Nature of the development - -This project is modification of a set of existing public open source code bases maintained as projects of the Free Software Foundation (FSF). As such the processes used within OpenHW will reflect the processes of those upstream projects. - -These code bases are very large: - -- GCC: 6.2MLOC -- binutils and GDB: 3.9MLOC -- newlib or GlibC: 0.9MLOC / 1.3MLOC - -The code bases include substantial regression test suites, and success with these test suites is a pre-requisite of upstream acceptance of any patch. The GCC test suite is the largest of these, which in its standard configuration comprises around 100,000 C tests and 50,000 C++ tests. - -Until CORE-V is accepted upstream, code will be developed in narrow mirrors of upstream repositories, featuring a single development branch based on upstream top of tree. This will be used as the basis of the patches to be submitted for upstreaming. - -Once CORE-V is accepted upstream, code will be developed exclusively in upstream FSF repositories and the narrow mirrors will be removed. - -### Summary timeline - -- Preliminary Project Launch (PPL, this document): early October 2020 - - - includes project plan - -- Project Launch (PL): end October 2020 -- First release (hardware loop support): end October 2020 -- Upstreaming of first release: objective is to include in GCC 11.1 in Q2/2021 - - - patch must be submitted by GCC stage 3 gate in early November 2020 - - requires cooperation from RISC-V GCC maintainers - - otherwise will be delayed to GCC 12.1 in Q2/2022. - -- Subsequent releases to support further instruction set extensions will be timed according to available resource. - -## OpenHW members/participants committed to participate in this project - -All OpenHW group members are invited to contributed expertise to this project. At present we are aware of: - -1. Embecosm -2. To be checked: Thales (phase 2) - -## Project Manager and technical lead - -- Jessica Mills, Embecosm, supported by Jeremy Bennett, Embecosm - -This is a much lighter role than a traditional project manager, since the requirements are fully defined through the hardware design process. The primary roles will be: -- tracking and reporting status to OpenHW Software TG and Technical WG -- identifying and resolving issues related to the outcome. - -Jessica Mills is currently project managing the CORE-V GCC development effort -within Embecosm, work she co-presented at OSDForum in September 2020. - -## Project documents - -The following project documents will be created: -- Preliminary Project Proposal (this document) - - - including an initial project plan - - including an initial risk register - -- Project Proposal, an updated version of this document - - - separate detailed project plan - - separate risk register - -## Virtual customer - -It is proposed that the OpenHW Group Hardware TG act as a "virtual customer" to exercise the compiler as it is developed. - -While the tool chain will have been thoroughly tested, it will benefit from the OpenHW Group Hardware TG being able to use if with their reference applications. - -## Summary of requirements - -The requirements are captured in the [OpenHW Group CV32E40P User Manual](https://core-v-docs-verif-strat.readthedocs.io/projects/cv32e40p_um/en/latest/). - -## Explanation of why OpenHW should do this project - -A processor is only useful with a robust, up-to-date, proven compiler tool chain. CORE-V, being a strict RISC-V derivative can use a standard RISC-V compiler tool chain, but in these circumstances will not be able to take advantage of any of the extended ISA features of the CORE-V processors. - -This project will provide a baseline tool chain allowing these extensions to be used, albeit without optimization, from the CORE-V tool chain. - -## Industry landscape - -Description of competing, alternative, or related efforts in the industry - -### Related efforts to be described - -The upstream GNU tool chain projects already support standard RISC-V. It is reasonably standard, but relatively immature by comparison with competing tool chains such as Arm and MIPS. - -The PULP GNU tool chain is based on GCC from 2017, shortly after RISC-V was -added upstream. It lacks all the more recent work on RISC-V optimization -work. It is a research compiler, and does not always follow GNU design principles or coding standards. It does not include any PULP specific tests - -There are also other non-GNU tool chains for RISC-V - -- Clang/LLVM for RISC-V -- IAR RISC-V compiler - -None of these yet supports PULP or CORE-V. - -## External dependencies - -Prequisites: -- all the upstream tool sources -- a suitable platform for regression testing the compiler. -- agreement on the instruction set encodings to be compliant with the RISC-V standard. - -External dependencies -- ongoing tracking of upstream until the CORE-V tool chain is accepted upstream. - -## List of project outputs (deliverables) - -## Project deliverables - -### Final deliverables - -1. extensions to upstream GNU compiler tools to support CORE-V; and -2. revisions to the CORE-V design specifications to clarify ambiguities. - -### Interim deliverables - -1. Reports on progress to the monthly SW TG: - - progress against work packages; - - regression test results; - - updates to the project plan; and - - updates to the risk register. -2. Continuously updated source code as new features are added. - -## TGs impacted/resource requirements - -The software TG will be responsible for oversight of the planning and delivery of this project. - -## OpenHW engineering staff resource plan: requirement and availability - -- Duncan Bees - program management oversight - -## Engineering resource supplied by members - requirement and availability - -Previous work by Craig Blackmore of Embecosm has estimated the effort to be 15 -engineer months work *for experienced GNU tool chain engineers*. This is to -achieve a tested functional tool chain *without* optimization. - -- Embecosm has already contributed around 3 engineer months to CORE-V GNU compiler tool chain development, and is willing to contribute another 3 engineer months during 2020 and early 2021. -- a further 9 engineer months is needed to complete the project - -*Note:* This is effort by GNU compiler tool chain specialist engineers. - -## OpenHW marketing resource - requirement and availability - -- press release support if/when CORE-V is accepted upstream. - -## Marketing resource supplied by members - requirement and availability - -- No resource requirements yet identified - -## Funding supplied by OpenHW - requirement and availability - -- None proposed - -## Funding supplied by members - requirement and availability - -- An alternative to support in kind is funding of effort by Embecosm. - -## Architecture diagram - -The standard GNU tool chain components are shown in the following diagram. - -![](images/gnu-tools.png) - -## Who would make use of OpenHW output - -See [Explanation of why OpenHW should do this project](#explanation-of-why-openhw-should-do-this-project) - -## Project license model - -Each component will use the license of the corresponding upstream RISC-V component. - -## Description of initial code contribution, if required - -- a GNU tool chain with support for CORE_V open hardware loop supplied by Embecosm. - -## Repository structure - -The respositories are mirrors of the upstream repositories. - -## Project distribution model - -The delivered code will be distributed as part of the upstream projects. - -Pending upstream adoption, the source code for the components will be available through mirror repositories under OpenHW Group GitHub. - -## Preliminary risk register - -This will become a separate document at full project launch. - -Risk is scored as likelihood (1-10) x impact (1-3) with mitigation required for any risk with score of 10 or more, of with an impact of 3 (project killer). - -| Risk | L | I | R | Mitigation | -|:----------------------------- | ---:| ---:| ---:|:---------------------------| -| Isufficient resource available | 5 | 3 | 15 | Socialize around OpenHW members to find expertise or funding. | -| Ownership of software for upstreaming | 5 | 2 | 10 | Ensure OpenHW group has FSF approval, discuss transfer of ownership with Luca Benini, clean room rewrite as last resort. | -| No process for allocating new relocations | 5 | 2 | 10 | Propose new process to RISC-V International psABI group, suggest allocation is coincident with upstreaming. | - -## Preliminary project plan - -This will become a separate document at full project launch. - -The support of any instruction set extension in the GNU compiler tool chain breaks into four work packages. - -1. *Addition of the instructions to the GNU assembler and linker.* The GNU assembler tables are modified to add the missing instructions. Where new operand types are added, the parser is extended as appropriate. Tests are added to `testsuite/gas/riscv` to exercise each instruction, including tests for all failure modes. - - If operands may be relocatable symbols, and cannot use existing relocations, the linker is extended with new relocations. - - At the end of this work package, the instructions can be used with the GNU assembler, or within GCC as inline assembly code. - -2. *Add intrinsic and/or builtin functions to GCC.* Intrinsic functions are just wrappers around inline assembly code provided for convenience. Builtin functions are integral to the compiler, giving greater opportunity for the compiler to optimize seamlessly around the new instructions. In general builtin functions are to be preferred, but they are more work, and in some cases may make little difference, so intrinsic functions will suffice. - - Builtin or intrinsic functions are added as appropriate. Tests will be added to `testsuite/gcc.target/riscv` to exercise each function, including tests for all failure modes. - - It should be noted that some instructions may not be suitable for direct intrinsic or builtin functions, particularly if they only make sense within a looping context. In such cases derivative builtin functions using the new instructions may be more useful (for example optimized `memcpy`). - - At the end of this work package the instructions can be used directly from C or C++ via the intrinsic/builtin functions. - -3. *Provide instruction generation patterns to GCC.* GCC is a pattern matching compiler. Patterns in the GCC intermediate representation are used to lower the intermediate statements to RISC-V code. Patterns will be provided to lower code to use the new instructions where this is advantageous. - - Tests are added to `testsuite/gcc.target/riscv` to verify that the patterns are being applied correctly. In addition benchmarking, for example with [Embench](https:://embench.org), will be used to measure the benefit obtained by generating the new instructions. - - Some of the instruction set extensions will prove harder than others to generate, particularly for the post-increment instructions. Getting effective use of auto-increment instructions in a compiler target such as RISC-V, which has been optimized without them, is a challenge. - - At the end of this work package, appropriate C or C++ code will generate object code using the new instructions. It is worth noting that without optimization, the cases where this happens may be limited. - -4. *Extend GCC optimization to take advantage of new instructions.* This is where GCC optimization passes are modified and extended to try to increase the opportunity to use the new instructions. This may involve changes to existing passes, or writing new passes, and is an inherently open ended task. - - Tests are again be added `testsuite/gcc.target/riscv` to verify that the optimizations are being applied. Benchmarking is used to measure the benefit obtained by optimization. This is done at the start of this work package, since the results will guide the optimization strategy. - - As with code generation, some of the instruction set extensions will prove harder than others to optimize, particularly for the post-increment instructions. Optimizing use of auto-increment instructions in a compiler target such as RISC-V, which has been optimized without them, is a challenge. - - At the end of this work package, the quality of code generated from C or C++ should be improved. It is worth noting that optimization is a very inexact science. It is usual to try 10 or 20 different optimization strategies, of which 20% will have a negative effect, 60% will have a minimal effect and only 20% will make a significant difference. - -In addition there are there are two work packages which apply throughout - -5. *Continuous integration and test.* This is an essential prerequisite to any GNU tool chain development. The project must be able to run the GCC, GNU assembler and GNU linker regression tests and nay benchmarking on a regular basis. This may use the Hardware TG reference FPGA platform or a simulation model of the platform. - -6. *Extend tool chain drivers for CORE-V.* The GNU compiler tools will build out of the box with any vendor specified, so tools can be named `riscv-corev-elf-* rather than riscv-unknown-elf-*. The vendor field is used to control whether code for CORE-V extensions is included in the tool chain. - - It is important that the user can control which CORE-V instructions are included, which is achieved through the -march option to the tools. It uses the syntax specified in chapter 27 of the current RISC-V ISA standard. Vendor specific instruction set extensions are alphabetic and prefixed by X. We shall provide support for `Xcorev` to provide support for all extensions, and the following to support specific subsets: - - - hardware loop: `Xcorevhwl` - - multiple accumulate: `Xcorevmac` - - post-increment and register-indexed load/store: `Xcorevpostinc` - - direct branches: `Xcorevbi` - - general ALU operations: `Xcorevalu` - -Finally there is a work package to prepare for the future - -7. *Support generic instruction set extensions to CORE-V.* There is no credible automated way to provide an optimizing compiler from a specification of an instruction. We therefore will define a process by which the compiler can be manuall extended by specialist experts in GCC optimization. - -However... - -There is an automated technology, CGEN, which allows automatic creation of the assembler, disassembler and instruction set simulator from a semi-formal specification of the architecture in Scheme. This is widely used for architectures in the GNU tool chain. - -CGEN has not been used to generate the assembler/disassembler in upstream RISC-V tools. However the CGEN specification has been written. This project can extend this specification to support CORE-V. This then provides a faster way to implement work package 1 for future instruction set extensions. - -### Program of work - -We propose the following work sequence within the scope of Phase 1 of this PPL: - -- work package 5; -- work package 6; -- work packages 1, 2 and 3 for hardware loop; -- work packages 1, 2 and 3 for multiple accumulate; -- work packages 1, 2 and 3 for post-increment and register-indexed load/store; -- work packages 1, 2 and 3 for direct branches; -- work packages 1, 2 and 3 for general ALU operations; and -- work package 7. - -Note that we do not propose any optimization work as part of this project. +# OpenHW Preliminary Project Proposal: CORE-V GNU compiler tool chain + +## Summary of project + +This proposal is for a baseline GNU compiler tool chain for CORE-V comprising: + +- GNU binutils + + - assembler + - linker + - low level utilities + +- GNU compiler collection for C and C++ + - compiler + - emulation library (`libgcc`) + - C++ standard library (`libstdc++v3`) + +- GNU debugger (GDB) +- a standard C library + +Because of the scale of this project, the work is composed in three phases: + +1. support for bare metal use of C with CV32E40P (32-bit) and the _Newlib_ C library; +2. support for Linux application use of C and C++ with CVA6 (32-/64-bit) and the _GlibC_ C library; and +3. support for other RTOS + +The proposal addresses just the first phase. Other phases will be the subject of separate proposals. Phase 1 will provide the following. + +- support for the following CORE-V instruction set extensions: + + - hardware loop; + - multiple accumulate; + - post-increment and register-indexed load/store; + - direct branches; and + - general ALU operations. + +- support for a generic CORE-V instruction set extension interface: + + - this will provide a commercial driver for future tool chain development for these extensions. + +In order to support the Software TG primary goal of developing a thriving commercial ecosystem, only a basic implementation will be provided. By basic implemention, we mean that the assembler/linker will support the instructions, the compiler will have intrinisc/builtin function support and the compiler will have patterns to generate the instructions from C code in obvious circumstances. + +However there will be no attempt to provide compiler optimization (which is a much bigger task). Software companies will rely on the majority of work still needing to be done in order to drive their businesses. + +In order to support the Software TG secondary goal of upstreaming all open source tool developments: + +- all development will be kept compliant with GNU coding standards; +- the implemenation will follow the upsrtream tool design conventions; and +- the design will remain consistent with the standard RISC-V GNU compiler tool chain. + +The finished work will be contributed and maintained upstream. + +### Nature of the development + +This project is modification of a set of existing public open source code bases maintained as projects of the Free Software Foundation (FSF). As such the processes used within OpenHW will reflect the processes of those upstream projects. + +These code bases are very large: + +- GCC: 6.2MLOC +- binutils and GDB: 3.9MLOC +- newlib or GlibC: 0.9MLOC / 1.3MLOC + +The code bases include substantial regression test suites, and success with these test suites is a pre-requisite of upstream acceptance of any patch. The GCC test suite is the largest of these, which in its standard configuration comprises around 100,000 C tests and 50,000 C++ tests. + +Until CORE-V is accepted upstream, code will be developed in narrow mirrors of upstream repositories, featuring a single development branch based on upstream top of tree. This will be used as the basis of the patches to be submitted for upstreaming. + +Once CORE-V is accepted upstream, code will be developed exclusively in upstream FSF repositories and the narrow mirrors will be removed. + +### Summary timeline + +- Preliminary Project Launch (PPL, this document): early October 2020 + + - includes project plan + +- Project Launch (PL): end October 2020 +- First release (hardware loop support): end October 2020 +- Upstreaming of first release: objective is to include in GCC 11.1 in Q2/2021 + + - patch must be submitted by GCC stage 3 gate in early November 2020 + - requires cooperation from RISC-V GCC maintainers + - otherwise will be delayed to GCC 12.1 in Q2/2022. + +- Subsequent releases to support further instruction set extensions will be timed according to available resource. + +## OpenHW members/participants committed to participate in this project + +All OpenHW group members are invited to contributed expertise to this project. At present we are aware of: + +1. Embecosm +2. To be checked: Thales (phase 2) + +## Project Manager and technical lead + +- Jessica Mills, Embecosm, supported by Jeremy Bennett, Embecosm + +This is a much lighter role than a traditional project manager, since the requirements are fully defined through the hardware design process. The primary roles will be: +- tracking and reporting status to OpenHW Software TG and Technical WG +- identifying and resolving issues related to the outcome. + +Jessica Mills is currently project managing the CORE-V GCC development effort +within Embecosm, work she co-presented at OSDForum in September 2020. + +## Project documents + +The following project documents will be created: +- Preliminary Project Proposal (this document) + + - including an initial project plan + - including an initial risk register + +- Project Proposal, an updated version of this document + + - separate detailed project plan + - separate risk register + +## Virtual customer + +It is proposed that the OpenHW Group Hardware TG act as a "virtual customer" to exercise the compiler as it is developed. + +While the tool chain will have been thoroughly tested, it will benefit from the OpenHW Group Hardware TG being able to use if with their reference applications. + +## Summary of requirements + +The requirements are captured in the [OpenHW Group CV32E40P User Manual](https://core-v-docs-verif-strat.readthedocs.io/projects/cv32e40p_um/en/latest/). + +## Explanation of why OpenHW should do this project + +A processor is only useful with a robust, up-to-date, proven compiler tool chain. CORE-V, being a strict RISC-V derivative can use a standard RISC-V compiler tool chain, but in these circumstances will not be able to take advantage of any of the extended ISA features of the CORE-V processors. + +This project will provide a baseline tool chain allowing these extensions to be used, albeit without optimization, from the CORE-V tool chain. + +## Industry landscape + +Description of competing, alternative, or related efforts in the industry + +### Related efforts to be described + +The upstream GNU tool chain projects already support standard RISC-V. It is reasonably standard, but relatively immature by comparison with competing tool chains such as Arm and MIPS. + +The PULP GNU tool chain is based on GCC from 2017, shortly after RISC-V was +added upstream. It lacks all the more recent work on RISC-V optimization +work. It is a research compiler, and does not always follow GNU design principles or coding standards. It does not include any PULP specific tests + +There are also other non-GNU tool chains for RISC-V + +- Clang/LLVM for RISC-V +- IAR RISC-V compiler + +None of these yet supports PULP or CORE-V. + +## External dependencies + +Prequisites: +- all the upstream tool sources +- a suitable platform for regression testing the compiler. +- agreement on the instruction set encodings to be compliant with the RISC-V standard. + +External dependencies +- ongoing tracking of upstream until the CORE-V tool chain is accepted upstream. + +## List of project outputs (deliverables) + +## Project deliverables + +### Final deliverables + +1. extensions to upstream GNU compiler tools to support CORE-V; and +2. revisions to the CORE-V design specifications to clarify ambiguities. + +### Interim deliverables + +1. Reports on progress to the monthly SW TG: + - progress against work packages; + - regression test results; + - updates to the project plan; and + - updates to the risk register. +2. Continuously updated source code as new features are added. + +## TGs impacted/resource requirements + +The software TG will be responsible for oversight of the planning and delivery of this project. + +## OpenHW engineering staff resource plan: requirement and availability + +- Duncan Bees - program management oversight + +## Engineering resource supplied by members - requirement and availability + +Previous work by Craig Blackmore of Embecosm has estimated the effort to be 15 +engineer months work *for experienced GNU tool chain engineers*. This is to +achieve a tested functional tool chain *without* optimization. + +- Embecosm has already contributed around 3 engineer months to CORE-V GNU compiler tool chain development, and is willing to contribute another 3 engineer months during 2020 and early 2021. +- a further 9 engineer months is needed to complete the project + +*Note:* This is effort by GNU compiler tool chain specialist engineers. + +## OpenHW marketing resource - requirement and availability + +- press release support if/when CORE-V is accepted upstream. + +## Marketing resource supplied by members - requirement and availability + +- No resource requirements yet identified + +## Funding supplied by OpenHW - requirement and availability + +- None proposed + +## Funding supplied by members - requirement and availability + +- An alternative to support in kind is funding of effort by Embecosm. + +## Architecture diagram + +The standard GNU tool chain components are shown in the following diagram. + +![](images/gnu-tools.png) + +## Who would make use of OpenHW output + +See [Explanation of why OpenHW should do this project](#explanation-of-why-openhw-should-do-this-project) + +## Project license model + +Each component will use the license of the corresponding upstream RISC-V component. + +## Description of initial code contribution, if required + +- a GNU tool chain with support for CORE_V open hardware loop supplied by Embecosm. + +## Repository structure + +The respositories are mirrors of the upstream repositories. + +## Project distribution model + +The delivered code will be distributed as part of the upstream projects. + +Pending upstream adoption, the source code for the components will be available through mirror repositories under OpenHW Group GitHub. + +## Preliminary risk register + +This will become a separate document at full project launch. + +Risk is scored as likelihood (1-10) x impact (1-3) with mitigation required for any risk with score of 10 or more, of with an impact of 3 (project killer). + +| Risk | L | I | R | Mitigation | +|:----------------------------- | ---:| ---:| ---:|:---------------------------| +| Isufficient resource available | 5 | 3 | 15 | Socialize around OpenHW members to find expertise or funding. | +| Ownership of software for upstreaming | 5 | 2 | 10 | Ensure OpenHW group has FSF approval, discuss transfer of ownership with Luca Benini, clean room rewrite as last resort. | +| No process for allocating new relocations | 5 | 2 | 10 | Propose new process to RISC-V International psABI group, suggest allocation is coincident with upstreaming. | + +## Preliminary project plan + +This will become a separate document at full project launch. + +The support of any instruction set extension in the GNU compiler tool chain breaks into four work packages. + +1. *Addition of the instructions to the GNU assembler and linker.* The GNU assembler tables are modified to add the missing instructions. Where new operand types are added, the parser is extended as appropriate. Tests are added to `testsuite/gas/riscv` to exercise each instruction, including tests for all failure modes. + + If operands may be relocatable symbols, and cannot use existing relocations, the linker is extended with new relocations. + + At the end of this work package, the instructions can be used with the GNU assembler, or within GCC as inline assembly code. + +2. *Add intrinsic and/or builtin functions to GCC.* Intrinsic functions are just wrappers around inline assembly code provided for convenience. Builtin functions are integral to the compiler, giving greater opportunity for the compiler to optimize seamlessly around the new instructions. In general builtin functions are to be preferred, but they are more work, and in some cases may make little difference, so intrinsic functions will suffice. + + Builtin or intrinsic functions are added as appropriate. Tests will be added to `testsuite/gcc.target/riscv` to exercise each function, including tests for all failure modes. + + It should be noted that some instructions may not be suitable for direct intrinsic or builtin functions, particularly if they only make sense within a looping context. In such cases derivative builtin functions using the new instructions may be more useful (for example optimized `memcpy`). + + At the end of this work package the instructions can be used directly from C or C++ via the intrinsic/builtin functions. + +3. *Provide instruction generation patterns to GCC.* GCC is a pattern matching compiler. Patterns in the GCC intermediate representation are used to lower the intermediate statements to RISC-V code. Patterns will be provided to lower code to use the new instructions where this is advantageous. + + Tests are added to `testsuite/gcc.target/riscv` to verify that the patterns are being applied correctly. In addition benchmarking, for example with [Embench](https:://embench.org), will be used to measure the benefit obtained by generating the new instructions. + + Some of the instruction set extensions will prove harder than others to generate, particularly for the post-increment instructions. Getting effective use of auto-increment instructions in a compiler target such as RISC-V, which has been optimized without them, is a challenge. + + At the end of this work package, appropriate C or C++ code will generate object code using the new instructions. It is worth noting that without optimization, the cases where this happens may be limited. + +4. *Extend GCC optimization to take advantage of new instructions.* This is where GCC optimization passes are modified and extended to try to increase the opportunity to use the new instructions. This may involve changes to existing passes, or writing new passes, and is an inherently open ended task. + + Tests are again be added `testsuite/gcc.target/riscv` to verify that the optimizations are being applied. Benchmarking is used to measure the benefit obtained by optimization. This is done at the start of this work package, since the results will guide the optimization strategy. + + As with code generation, some of the instruction set extensions will prove harder than others to optimize, particularly for the post-increment instructions. Optimizing use of auto-increment instructions in a compiler target such as RISC-V, which has been optimized without them, is a challenge. + + At the end of this work package, the quality of code generated from C or C++ should be improved. It is worth noting that optimization is a very inexact science. It is usual to try 10 or 20 different optimization strategies, of which 20% will have a negative effect, 60% will have a minimal effect and only 20% will make a significant difference. + +In addition there are there are two work packages which apply throughout + +5. *Continuous integration and test.* This is an essential prerequisite to any GNU tool chain development. The project must be able to run the GCC, GNU assembler and GNU linker regression tests and nay benchmarking on a regular basis. This may use the Hardware TG reference FPGA platform or a simulation model of the platform. + +6. *Extend tool chain drivers for CORE-V.* The GNU compiler tools will build out of the box with any vendor specified, so tools can be named `riscv-corev-elf-* rather than riscv-unknown-elf-*. The vendor field is used to control whether code for CORE-V extensions is included in the tool chain. + + It is important that the user can control which CORE-V instructions are included, which is achieved through the -march option to the tools. It uses the syntax specified in chapter 27 of the current RISC-V ISA standard. Vendor specific instruction set extensions are alphabetic and prefixed by X. We shall provide support for `Xcorev` to provide support for all extensions, and the following to support specific subsets: + + - hardware loop: `Xcorevhwl` + - multiple accumulate: `Xcorevmac` + - post-increment and register-indexed load/store: `Xcorevpostinc` + - direct branches: `Xcorevbi` + - general ALU operations: `Xcorevalu` + +Finally there is a work package to prepare for the future + +7. *Support generic instruction set extensions to CORE-V.* There is no credible automated way to provide an optimizing compiler from a specification of an instruction. We therefore will define a process by which the compiler can be manuall extended by specialist experts in GCC optimization. + +However... + +There is an automated technology, CGEN, which allows automatic creation of the assembler, disassembler and instruction set simulator from a semi-formal specification of the architecture in Scheme. This is widely used for architectures in the GNU tool chain. + +CGEN has not been used to generate the assembler/disassembler in upstream RISC-V tools. However the CGEN specification has been written. This project can extend this specification to support CORE-V. This then provides a faster way to implement work package 1 for future instruction set extensions. + +### Program of work + +We propose the following work sequence within the scope of Phase 1 of this PPL: + +- work package 5; +- work package 6; +- work packages 1, 2 and 3 for hardware loop; +- work packages 1, 2 and 3 for multiple accumulate; +- work packages 1, 2 and 3 for post-increment and register-indexed load/store; +- work packages 1, 2 and 3 for direct branches; +- work packages 1, 2 and 3 for general ALU operations; and +- work package 7. + +Note that we do not propose any optimization work as part of this project. diff --git a/program/Project-Descriptions-and-Plans/CORE-V-HAL/HAL-diagram-PC.png b/Project-Descriptions-and-Plans/CORE-V-HAL/HAL-diagram-PC.png similarity index 100% rename from program/Project-Descriptions-and-Plans/CORE-V-HAL/HAL-diagram-PC.png rename to Project-Descriptions-and-Plans/CORE-V-HAL/HAL-diagram-PC.png diff --git a/program/Project-Descriptions-and-Plans/CORE-V-HAL/Hardware-Abstraction-Layer-HAL-Requirements-for-PC.pptx b/Project-Descriptions-and-Plans/CORE-V-HAL/Hardware-Abstraction-Layer-HAL-Requirements-for-PC.pptx similarity index 100% rename from program/Project-Descriptions-and-Plans/CORE-V-HAL/Hardware-Abstraction-Layer-HAL-Requirements-for-PC.pptx rename to Project-Descriptions-and-Plans/CORE-V-HAL/Hardware-Abstraction-Layer-HAL-Requirements-for-PC.pptx diff --git a/program/Project-Descriptions-and-Plans/CORE-V-HAL/Project-Concept-HAL.md b/Project-Descriptions-and-Plans/CORE-V-HAL/Project-Concept-HAL.md similarity index 100% rename from program/Project-Descriptions-and-Plans/CORE-V-HAL/Project-Concept-HAL.md rename to Project-Descriptions-and-Plans/CORE-V-HAL/Project-Concept-HAL.md diff --git a/program/Project-Descriptions-and-Plans/CORE-V-IDE/CORE-V-IDE-prelminary-project-proposal.md b/Project-Descriptions-and-Plans/CORE-V-IDE/CORE-V-IDE-prelminary-project-proposal.md similarity index 97% rename from program/Project-Descriptions-and-Plans/CORE-V-IDE/CORE-V-IDE-prelminary-project-proposal.md rename to Project-Descriptions-and-Plans/CORE-V-IDE/CORE-V-IDE-prelminary-project-proposal.md index 9b6f409eb..c8b990140 100644 --- a/program/Project-Descriptions-and-Plans/CORE-V-IDE/CORE-V-IDE-prelminary-project-proposal.md +++ b/Project-Descriptions-and-Plans/CORE-V-IDE/CORE-V-IDE-prelminary-project-proposal.md @@ -1,271 +1,271 @@ -# OpenHW Project Proposal -# CORE-V IDE - - - -## Summary of project -This project proposal is for the CORE-V IDE project. CORE-V IDE will develop an open-source CORE-V version of the Eclipse CDT (C/C++ Development Tools) based IDE (Integrated Developmnent Environmnent). CORE-V IDE will provide the baseline capabilities for a C/C++ IDE suitable for both 32 and 64 bit CORE-V devices. Specific CORE-V IDEs will be able to be instantiated from the CORE-V IDE. - -In line with the Software TG primary goal of developing a thriving commercial ecosystem, this implementation is intended to be the basis on which others will develop commercial products, both open source and proprietary. - -Also in keeping with a Software TG goal, any open source tools will be contributed and maintained upstream. - -CORE-V IDE builds upon Eclipse CDT 10.0, Eclipse Embedded CDT, and potentially other projects. CORE-V IDE can be thought of as an OpenHW branded layer on top of those foundation layers, which integrates CORE-V technical tools (OpenHW reference tool chain, CORE-V libraries, CORE-V debugger) to provide the capabilities for a full IDE. As versions of the CORE-V tool chain become available, they can be integrated with CORE-V IDE package. - -Note that alternative tool chains, libraries and debuggers must also be integrate-able with CORE-V IDE. - -This project will provides a foundation for IDEs for all versions of CORE-V device. -Although instantiations of the complete IDE may be specific for particular devices, the initial OpenHW distribution would be a base/foundation package for all devices. - -Note that it is thought that C/C++ is the most immediate programming language requirement for CORE-V applications. However, this project also seeks to provide underpinning for future language support in CORE-V IDE, such as Java (building on Eclipse JDT). - -The present preliminary project proposal is prepared for the OpenHW TWG (Technical Working Group) meeting of August 31 2020 and has been prepared by members of the OpenHW SW TG (Software Task Group). The project proponents seek a "Preliminary Project Launch" gate approval. - -Additional aspects of this project: -- The first target instantiation of the CORE-V IDE will be for the CV32E40P core implementation for the Genesis FPGA board by the OpenHW HW Group. The OpenHW HW Group is considered the "lead customer". -- A real-world application to exercise the IDE on the above target board will also need to be developed. - -- It is thought that IDE can be an aspect of the verification of the CORE-V RTL. - -**Summary of Timeline** - -- Preliminary Project Launch (PPL) in the OpenHW Group process is proposed for end August 202s -- Project Launch (PL) in the OpenHW Group process is proposed for mid-September 2020. The project would also be launched at this time as an Eclipse Foundation process. -- Project Plan Available (PPA) is proposed for mid-October 2020 -- **First Integration at the end of 2020** with the aim to bring up a first prototype. The first prototype would enable the creation of a "hello world application." The CORE-V IDE may be demonstratable at that point. -- As the project progresses, the intent is to release it on an ongoing basis the Eclipse Foundation cadence, i.e. 4x per year. -- The **First version to be released** could be 3Q of 2021. - -## OpenHW Members/Participants committed to participate in CORE-V IDE project -1. Ashling -2. Arsysop (Alexander Fedorov) -3. Embecosm -4. To be checked: Alibaba, CMC, Thales - -See Section "Engineering resource supplied by members - requirement and availability" for specifics of member involvement. - -## Technical Project Leader(s) (TPLs) -The following persons will investigate and resolve overall technical issues related to the IDE -1. Alexander Fedorov -2. Hugh O'Keeffe or an alternative person from Ashling - -## Project Manager (PM) -The following is tentative: -- Florian Zaruba of OpenHW staff will act as project manager -- Jeremy Bennett of Embecosm and Duncan Bees of OpenHW staff will act as project management mentors. -The project manager would be responsible, in conjuction with the TPLs, to create the project plan, collect requirements for features, track status and report status to the OpenHW TWG, and identify and resolve issues related to the successful outcome. - - -## Project Documents -The following project documents will be created: -- Preliminary Project Proposal (this document) -- Project Proposal, an updated version of this document -- Project Plan -- Feature Description (initial version here: https://github.com/openhwgroup/core-v-sw/blob/master/planning/openhw-ide-requirement.md) -- Build and Delivery Description - - - - -## Virtual customer -The project team would like to explore the concept of virtual customer to help provide suggestions on feature requirements, participate in ongoing backlog grooming, and review and feedback on CORE-V IDE as it is released. It is suggested that members of the HW group can act in this role as the IDE is used with the FPGA implementation of CV32E40P - - -## Summary of requirements - -The present document gives a present snapshot of requirements and Preliminary Project Proposal, the requirements document https://github.com/openhwgroup/core-v-sw/blob/master/planning/openhw-ide-requirement.md will be used as the reference going forward. - -### Introduction -Use case list would be useful - -### Initial project requirements - -1. Support for both Linux and 64 bit Windows -2. Supplied as a ZIPped archive...no installer needed...just extract and ready to run -3. “OpenHW IDE” splash-screen and "about" box with openHW Group graphics. -4. Set version to v0.0.1 -5. Build on latest, released Eclipse, CDT and GNU MCU plug-ins (now known as Eclipse Embedded CDT (C/C++ Development Tools)) -6. Latest Embecosm CORE-V toolchain -7. OpenOCD (Open On-Chip Debugger, with JTAG support) for CORE-V -8. Simple Eclipse project ready-to-run on Genesys 2 board (e.g. LED toggle) including Opella-LD OpenOCD launch (Opella-LD is Ashling's low-cost, FTDI based probe not to be confused with the existing Opella-XD) -9. OpenHW IDE getting started guide documentation with Genesys 2 board - - -### Future enhancements: - - -10. Automating the build to “pull” all the latest components from their respective repos etc -11. Improved documentation and more board examples -12. Support for PlatformIO -12. Various improvements - - - -## Explanation of why OpenHW should do this project - -Must of industrial software development is carried out within an IDE, commonly based on either Eclipse (especially Eclipse CDT) or Microsoft Visual Studio Code (especially PlatformIO). To be considered a serious player, OpenHW Group must be able to offer an IDE based on at least one of these architectures. - -We have chosen to start with Eclipse CDT and focused on the embedded use case (which could also include CVA6 applications), because: - -1. We have access to the necessary expertise through our members and the Eclipse Foundation; -2. Eclipse CDT, while quite old, is still the most widely used IDE in the embedded sector; and -3. Embedded products will be the primary users of CV32E40P, the first core from OpenHW Group - -This work will tie in with other OpenHW Group work developing the GNU compiler tool chain and the reference FPGA platform. - - - - - -## Industry landscape: description of competing, alternative, or related efforts in the industry - -### Related efforts to be described - -- Eclipse CDT -- (GNU MCU) Eclipse Embedded CDT (Describe support for existing RISC-V devices) -- Eclipse Theia -- PlatformIO (based on MS Visual Code Studio) - -## External dependencies - -The first build of CORE-V CDT builds on the following: -- Eclipse Platform 2020-09 -- Eclipse CDT 10.0 -- Other components from Eclipse SimRel 2020-09 -- A suitable tool chain (see options below) - -The CORE-V IDE will be capable of integrating with any compliant tool chain, notably GNU and Clang/LLVM. A the time of writing, the following tool chains are available: - - -### PULP GNU tool chain as-is - -This is a research tool chain from ETHZ and U of Bologna which has the following attributes: -- It is updated often as research projects need. -- A precompiled version is available, compiled and tested from Embecosm, updated weekly. -- Drawbacks are that it is out of date (based on earlier release of GCC), doesn't meet coding standards, and lacks testing - - - -### Standard RISC-V GNU tool chain -This is the standard RISC-V GCC tool chain whose attributes include: -- The development is hosted by the FSF (Free software foundation). It is completely up to date with GCC and binutils. There are many commits per day. -- It has no Pulp features -- A precompiled version of that toolchain is available from Embecosm and possibly others. From Embecosm, the latest version is updated weekly. The latest stable release is 10.2.0 -- It is currently used in the Ashling IDE product. - -### Standard Clang/LLVM tool chain -The development is hosted by the LLVM Foundation. It is completely up to date with GCC and binutils. There are many commits per day. -- It has no Pulp features -- A precompiled version of that toolchain is available from Embecosm and possibly others. From Embecosm, the latest version is updated weekly. The latest stable release is 10.0.1 - -### OpenHW CORE-V Reference GNU tool chain -This is a separate project in OpenHW managed within the SW TG. -- The project starts from the standard GCC tools (FSF) and adds CORE-V instructions -- The binutils-gdb repository in OpenHW github currently has 2 branches - - Stable (currently, this repository is a mirror of FSF). - - Development (first commits to this repository will have support for CORE-V hardware loop) -Although support for this tool chain is not a pre-requisite, the OpenHW IDE should support it when it is available. - - - -## List of project outputs - -*Need a list of outputs, i.e.* -- *Documents to be produced* -- *Downloadable code to be produced* - - -## TGs Impacted/Resource requirements - -The software TG will be responsible for oversight of the planning and delivery of this project. - - -## OpenHW engineering staff resource plan: requirement and availability - -- Florian Zaruba - technical contribution and project planning -- Duncan Bees - program management oversight - -## Engineering resource supplied by members - requirement and availability - - -1. Ashling will contribute IDE expertise and coding resources (integration of embedded CDT with tool chain, debug support). -2. Alexander Fedorov (Arsysop) will contribute overall architecture and technical leadership, release engineering, and collaboration with Eclipse IDE/CDT ecosystem. -3. Embecosm will contribute CORE-V compiler tool chain and packaging or stabilization if necessary - - -## OpenHW marketing resource - requirement and availability - -- Initial artwork suppplied by Publitek -- No additional resource requirements yet identified - -## Marketing resource supplied by members - requirement and availability -- No resource requirements yet identified - -## Funding supplied by OpenHW - requirement and availability -- Supply of CV32 FPGA development boards to be investigated - - -## Funding supplied by members - requirement and availability -- No funding requirements yet identified - - - -## Architecture diagram -*Need diagram showing SW architecture and also real-world physical setup for intended use. Action to Alexander* - -## Who would make use of OpenHW output -Refer to "Explanation of why OpenHW should do this project" - -## Project license model - -This project will be distributed under EPL 2.0. -License architecture to be reviewed with EF staff. - - -## Description of initial code contribution, if required -Need to describe initial CQ contents. - - -## Repository Structure - -Refer to https://github.com/openhwgroup/core-v-ide-cdt/blob/master/README.md - - -## Project distribution model - -The project code will be distributed using an Eclipse p2 repository and an archive for each target platform. - - - - -## Preliminary Project plan - - -A separate project plan document will be developed to detail and sequence project activities. -The information here is meant to provide a sketch only. -See also timeline comments in the project summary section. - - -1. Organization of the Project - - OpenHW PPL - - OpenHW PL - - OpenHW project plan - - Eclipse Project Initiation and initial Contribution Questionnaires - - Kanban board for ongoing features - - Github repo creation - - definition of any requirements related to P2 distribution - -2. Stub IDE (done) -- Core-V artwork and branding for IDE - -3. Integrating the various components -- OpenHW reference GNU tools -- OpenOCD software -- Other toolchains - -4. Simple hello world application to test the entire toolchain - - -### Longer term -1.Simulator integration - There are many (Verilator/GDB Simulator/QEMU Simulation/OVPSim). - - +# OpenHW Project Proposal +# CORE-V IDE + + + +## Summary of project +This project proposal is for the CORE-V IDE project. CORE-V IDE will develop an open-source CORE-V version of the Eclipse CDT (C/C++ Development Tools) based IDE (Integrated Developmnent Environmnent). CORE-V IDE will provide the baseline capabilities for a C/C++ IDE suitable for both 32 and 64 bit CORE-V devices. Specific CORE-V IDEs will be able to be instantiated from the CORE-V IDE. + +In line with the Software TG primary goal of developing a thriving commercial ecosystem, this implementation is intended to be the basis on which others will develop commercial products, both open source and proprietary. + +Also in keeping with a Software TG goal, any open source tools will be contributed and maintained upstream. + +CORE-V IDE builds upon Eclipse CDT 10.0, Eclipse Embedded CDT, and potentially other projects. CORE-V IDE can be thought of as an OpenHW branded layer on top of those foundation layers, which integrates CORE-V technical tools (OpenHW reference tool chain, CORE-V libraries, CORE-V debugger) to provide the capabilities for a full IDE. As versions of the CORE-V tool chain become available, they can be integrated with CORE-V IDE package. + +Note that alternative tool chains, libraries and debuggers must also be integrate-able with CORE-V IDE. + +This project will provides a foundation for IDEs for all versions of CORE-V device. +Although instantiations of the complete IDE may be specific for particular devices, the initial OpenHW distribution would be a base/foundation package for all devices. + +Note that it is thought that C/C++ is the most immediate programming language requirement for CORE-V applications. However, this project also seeks to provide underpinning for future language support in CORE-V IDE, such as Java (building on Eclipse JDT). + +The present preliminary project proposal is prepared for the OpenHW TWG (Technical Working Group) meeting of August 31 2020 and has been prepared by members of the OpenHW SW TG (Software Task Group). The project proponents seek a "Preliminary Project Launch" gate approval. + +Additional aspects of this project: +- The first target instantiation of the CORE-V IDE will be for the CV32E40P core implementation for the Genesis FPGA board by the OpenHW HW Group. The OpenHW HW Group is considered the "lead customer". +- A real-world application to exercise the IDE on the above target board will also need to be developed. - +- It is thought that IDE can be an aspect of the verification of the CORE-V RTL. + +**Summary of Timeline** + +- Preliminary Project Launch (PPL) in the OpenHW Group process is proposed for end August 202s +- Project Launch (PL) in the OpenHW Group process is proposed for mid-September 2020. The project would also be launched at this time as an Eclipse Foundation process. +- Project Plan Available (PPA) is proposed for mid-October 2020 +- **First Integration at the end of 2020** with the aim to bring up a first prototype. The first prototype would enable the creation of a "hello world application." The CORE-V IDE may be demonstratable at that point. +- As the project progresses, the intent is to release it on an ongoing basis the Eclipse Foundation cadence, i.e. 4x per year. +- The **First version to be released** could be 3Q of 2021. + +## OpenHW Members/Participants committed to participate in CORE-V IDE project +1. Ashling +2. Arsysop (Alexander Fedorov) +3. Embecosm +4. To be checked: Alibaba, CMC, Thales + +See Section "Engineering resource supplied by members - requirement and availability" for specifics of member involvement. + +## Technical Project Leader(s) (TPLs) +The following persons will investigate and resolve overall technical issues related to the IDE +1. Alexander Fedorov +2. Hugh O'Keeffe or an alternative person from Ashling + +## Project Manager (PM) +The following is tentative: +- Florian Zaruba of OpenHW staff will act as project manager +- Jeremy Bennett of Embecosm and Duncan Bees of OpenHW staff will act as project management mentors. +The project manager would be responsible, in conjuction with the TPLs, to create the project plan, collect requirements for features, track status and report status to the OpenHW TWG, and identify and resolve issues related to the successful outcome. + + +## Project Documents +The following project documents will be created: +- Preliminary Project Proposal (this document) +- Project Proposal, an updated version of this document +- Project Plan +- Feature Description (initial version here: https://github.com/openhwgroup/core-v-sw/blob/master/planning/openhw-ide-requirement.md) +- Build and Delivery Description + + + + +## Virtual customer +The project team would like to explore the concept of virtual customer to help provide suggestions on feature requirements, participate in ongoing backlog grooming, and review and feedback on CORE-V IDE as it is released. It is suggested that members of the HW group can act in this role as the IDE is used with the FPGA implementation of CV32E40P + + +## Summary of requirements + +The present document gives a present snapshot of requirements and Preliminary Project Proposal, the requirements document https://github.com/openhwgroup/core-v-sw/blob/master/planning/openhw-ide-requirement.md will be used as the reference going forward. + +### Introduction +Use case list would be useful + +### Initial project requirements + +1. Support for both Linux and 64 bit Windows +2. Supplied as a ZIPped archive...no installer needed...just extract and ready to run +3. “OpenHW IDE” splash-screen and "about" box with openHW Group graphics. +4. Set version to v0.0.1 +5. Build on latest, released Eclipse, CDT and GNU MCU plug-ins (now known as Eclipse Embedded CDT (C/C++ Development Tools)) +6. Latest Embecosm CORE-V toolchain +7. OpenOCD (Open On-Chip Debugger, with JTAG support) for CORE-V +8. Simple Eclipse project ready-to-run on Genesys 2 board (e.g. LED toggle) including Opella-LD OpenOCD launch (Opella-LD is Ashling's low-cost, FTDI based probe not to be confused with the existing Opella-XD) +9. OpenHW IDE getting started guide documentation with Genesys 2 board + + +### Future enhancements: + + +10. Automating the build to “pull” all the latest components from their respective repos etc +11. Improved documentation and more board examples +12. Support for PlatformIO +12. Various improvements + + + +## Explanation of why OpenHW should do this project + +Must of industrial software development is carried out within an IDE, commonly based on either Eclipse (especially Eclipse CDT) or Microsoft Visual Studio Code (especially PlatformIO). To be considered a serious player, OpenHW Group must be able to offer an IDE based on at least one of these architectures. + +We have chosen to start with Eclipse CDT and focused on the embedded use case (which could also include CVA6 applications), because: + +1. We have access to the necessary expertise through our members and the Eclipse Foundation; +2. Eclipse CDT, while quite old, is still the most widely used IDE in the embedded sector; and +3. Embedded products will be the primary users of CV32E40P, the first core from OpenHW Group + +This work will tie in with other OpenHW Group work developing the GNU compiler tool chain and the reference FPGA platform. + + + + + +## Industry landscape: description of competing, alternative, or related efforts in the industry + +### Related efforts to be described + +- Eclipse CDT +- (GNU MCU) Eclipse Embedded CDT (Describe support for existing RISC-V devices) +- Eclipse Theia +- PlatformIO (based on MS Visual Code Studio) + +## External dependencies + +The first build of CORE-V CDT builds on the following: +- Eclipse Platform 2020-09 +- Eclipse CDT 10.0 +- Other components from Eclipse SimRel 2020-09 +- A suitable tool chain (see options below) + +The CORE-V IDE will be capable of integrating with any compliant tool chain, notably GNU and Clang/LLVM. A the time of writing, the following tool chains are available: + + +### PULP GNU tool chain as-is + +This is a research tool chain from ETHZ and U of Bologna which has the following attributes: +- It is updated often as research projects need. +- A precompiled version is available, compiled and tested from Embecosm, updated weekly. +- Drawbacks are that it is out of date (based on earlier release of GCC), doesn't meet coding standards, and lacks testing + + + +### Standard RISC-V GNU tool chain +This is the standard RISC-V GCC tool chain whose attributes include: +- The development is hosted by the FSF (Free software foundation). It is completely up to date with GCC and binutils. There are many commits per day. +- It has no Pulp features +- A precompiled version of that toolchain is available from Embecosm and possibly others. From Embecosm, the latest version is updated weekly. The latest stable release is 10.2.0 +- It is currently used in the Ashling IDE product. + +### Standard Clang/LLVM tool chain +The development is hosted by the LLVM Foundation. It is completely up to date with GCC and binutils. There are many commits per day. +- It has no Pulp features +- A precompiled version of that toolchain is available from Embecosm and possibly others. From Embecosm, the latest version is updated weekly. The latest stable release is 10.0.1 + +### OpenHW CORE-V Reference GNU tool chain +This is a separate project in OpenHW managed within the SW TG. +- The project starts from the standard GCC tools (FSF) and adds CORE-V instructions +- The binutils-gdb repository in OpenHW github currently has 2 branches + - Stable (currently, this repository is a mirror of FSF). + - Development (first commits to this repository will have support for CORE-V hardware loop) +Although support for this tool chain is not a pre-requisite, the OpenHW IDE should support it when it is available. + + + +## List of project outputs + +*Need a list of outputs, i.e.* +- *Documents to be produced* +- *Downloadable code to be produced* + + +## TGs Impacted/Resource requirements + +The software TG will be responsible for oversight of the planning and delivery of this project. + + +## OpenHW engineering staff resource plan: requirement and availability + +- Florian Zaruba - technical contribution and project planning +- Duncan Bees - program management oversight + +## Engineering resource supplied by members - requirement and availability + + +1. Ashling will contribute IDE expertise and coding resources (integration of embedded CDT with tool chain, debug support). +2. Alexander Fedorov (Arsysop) will contribute overall architecture and technical leadership, release engineering, and collaboration with Eclipse IDE/CDT ecosystem. +3. Embecosm will contribute CORE-V compiler tool chain and packaging or stabilization if necessary + + +## OpenHW marketing resource - requirement and availability + +- Initial artwork suppplied by Publitek +- No additional resource requirements yet identified + +## Marketing resource supplied by members - requirement and availability +- No resource requirements yet identified + +## Funding supplied by OpenHW - requirement and availability +- Supply of CV32 FPGA development boards to be investigated + + +## Funding supplied by members - requirement and availability +- No funding requirements yet identified + + + +## Architecture diagram +*Need diagram showing SW architecture and also real-world physical setup for intended use. Action to Alexander* + +## Who would make use of OpenHW output +Refer to "Explanation of why OpenHW should do this project" + +## Project license model + +This project will be distributed under EPL 2.0. +License architecture to be reviewed with EF staff. + + +## Description of initial code contribution, if required +Need to describe initial CQ contents. + + +## Repository Structure + +Refer to https://github.com/openhwgroup/core-v-ide-cdt/blob/master/README.md + + +## Project distribution model + +The project code will be distributed using an Eclipse p2 repository and an archive for each target platform. + + + + +## Preliminary Project plan + + +A separate project plan document will be developed to detail and sequence project activities. +The information here is meant to provide a sketch only. +See also timeline comments in the project summary section. + + +1. Organization of the Project + - OpenHW PPL + - OpenHW PL + - OpenHW project plan + - Eclipse Project Initiation and initial Contribution Questionnaires + - Kanban board for ongoing features + - Github repo creation + - definition of any requirements related to P2 distribution + +2. Stub IDE (done) +- Core-V artwork and branding for IDE + +3. Integrating the various components +- OpenHW reference GNU tools +- OpenOCD software +- Other toolchains + +4. Simple hello world application to test the entire toolchain + + +### Longer term +1.Simulator integration - There are many (Verilator/GDB Simulator/QEMU Simulation/OVPSim). + + diff --git a/program/Project-Descriptions-and-Plans/CORE-V-L1-DCACHE/20220523-OHG-ProjectConcept-CEA_L1_Dcache.md b/Project-Descriptions-and-Plans/CORE-V-L1-DCACHE/20220523-OHG-ProjectConcept-CEA_L1_Dcache.md similarity index 100% rename from program/Project-Descriptions-and-Plans/CORE-V-L1-DCACHE/20220523-OHG-ProjectConcept-CEA_L1_Dcache.md rename to Project-Descriptions-and-Plans/CORE-V-L1-DCACHE/20220523-OHG-ProjectConcept-CEA_L1_Dcache.md diff --git a/program/Project-Descriptions-and-Plans/CORE-V-MCU-DEV-KIT/CORE-V_DEV-KIT_project_concept_approved.md b/Project-Descriptions-and-Plans/CORE-V-MCU-DEV-KIT/CORE-V_DEV-KIT_project_concept_approved.md similarity index 100% rename from program/Project-Descriptions-and-Plans/CORE-V-MCU-DEV-KIT/CORE-V_DEV-KIT_project_concept_approved.md rename to Project-Descriptions-and-Plans/CORE-V-MCU-DEV-KIT/CORE-V_DEV-KIT_project_concept_approved.md diff --git a/program/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/Arnold2-arch.png b/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/Arnold2-arch.png similarity index 100% rename from program/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/Arnold2-arch.png rename to Project-Descriptions-and-Plans/CORE-V-MCU-SoC/Arnold2-arch.png diff --git a/program/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/CORE-V_MCU_Project_Plan_Nov10_2021.xlsx b/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/CORE-V_MCU_Project_Plan_Nov10_2021.xlsx similarity index 100% rename from program/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/CORE-V_MCU_Project_Plan_Nov10_2021.xlsx rename to Project-Descriptions-and-Plans/CORE-V-MCU-SoC/CORE-V_MCU_Project_Plan_Nov10_2021.xlsx diff --git a/program/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/CORE-V_MCU_Project_Plan_Oct27_2021.xlsx b/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/CORE-V_MCU_Project_Plan_Oct27_2021.xlsx similarity index 100% rename from program/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/CORE-V_MCU_Project_Plan_Oct27_2021.xlsx rename to Project-Descriptions-and-Plans/CORE-V-MCU-SoC/CORE-V_MCU_Project_Plan_Oct27_2021.xlsx diff --git a/program/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/Core-V-MCU-SoC-Plan.pod b/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/Core-V-MCU-SoC-Plan.pod similarity index 100% rename from program/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/Core-V-MCU-SoC-Plan.pod rename to Project-Descriptions-and-Plans/CORE-V-MCU-SoC/Core-V-MCU-SoC-Plan.pod diff --git a/program/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/MCU-PL-Document.md b/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/MCU-PL-Document.md similarity index 100% rename from program/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/MCU-PL-Document.md rename to Project-Descriptions-and-Plans/CORE-V-MCU-SoC/MCU-PL-Document.md diff --git a/program/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/MCU-SoC-Project-Plan-at-PL.xlsx b/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/MCU-SoC-Project-Plan-at-PL.xlsx similarity index 100% rename from program/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/MCU-SoC-Project-Plan-at-PL.xlsx rename to Project-Descriptions-and-Plans/CORE-V-MCU-SoC/MCU-SoC-Project-Plan-at-PL.xlsx diff --git a/program/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/PA-document-Oct-25-2021.md b/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/PA-document-Oct-25-2021.md similarity index 96% rename from program/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/PA-document-Oct-25-2021.md rename to Project-Descriptions-and-Plans/CORE-V-MCU-SoC/PA-document-Oct-25-2021.md index 145d9f5bf..9ff66ae94 100644 --- a/program/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/PA-document-Oct-25-2021.md +++ b/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/PA-document-Oct-25-2021.md @@ -1,591 +1,591 @@ -OpenHW Plan Approve Proposal Document - - - - - - -# Title of Project - - -Design and Fabrication of CORE-V MCU System on Chip (MCU project). - -## Summary of project - - - - -This project builds upon the OpenHW CV32E40P core, the core-v-mcu FPGA implementation, and embedded FPGA components to design and fabricate an evaluation SoC. The MCU will be at the heart of an open source tools and IP ecosystem under which commercial SoC devices and their associated software applications can be rapidly brought to market. - - -The CORE-V MCU project is one of three related project: -* CORE-V MCU (this project) delivers the MCU SoC with initial testing on a bench test board with limited test software. -* CORE-V Dev-Kit delivers, manufactures and distributes a development board that integrates the MCU together with the SDK. -* CORE-V SDK delivers the out-of-box software stack to support the Dev-Kit. - - -These three projects together will as a whole provide a real-world development environment. - - -Key aspects of the MCU project are: -* Bring-up OpenHW CV32E40P core within an updated MCU platform on a bench test board and FPGA. -* Achieve test software bringup on FPGA and SoC implementations of the CORE-V MCU. -* Incorporate eFPGA that enables people to use configurable accelerators for AI-type applications. The eFPGA block itself is not open source, but it can be programmed using an open source tool flow that will be delivered as a component of the SDK project. -* Provide a starting point for the design of commercial SoC devices based on CV32E40P. -* The MCU is not in itself meant as a product; rather, it provides a proof-of-concept and evaluation instantiation of the CV32E40P within an MCU architecture. -* The MCU project will bring the CV32E40P IP to TRL6 from a starting point at TRL5. -* The MCU will de-risk and accelerate others to adopt the CV32E40P in their own SoC. - - - - - - -## Components -The project comprises two main components -1) - Emulation (FPGA board) Release of CORE-V MCU -2) - Design, Fabrication and Initial Test of the CORE-V MCU SoC Device - - -### Component 1 - Emulation Release (FPGA) - - -The emulation release provides a development platform for OpenHW tools developers and an initial evaluation platform for 3rd parties -* The FPGA design takes as input the completed design and verification of the CV32E40P core (Release 1.0.0 from December 2020) -* RTL Freeze version for the FPGA -* GDS Freeze update version for FPGA -* Updated user guide for the FPGA - CMC, Quicklogic -* Prototype CORE-V MCU software based on test software used for the MCU SoC Device - Quicklogic - - -### Component 2 - Design and Fabrication of the SoC Device - - -#### 2A - Front end SoC design - - -The Front-end SoC design is primarily resourced by or through QuickLogic. Key aspects -* Starting from CORE-V FPGA design. -* Integrate eFPGA (logic array, fixed function blocks for accelerators, and configuration controller) from QuickLogic -* Integrate technology specific elements required by ASIC implementation - * I/O - * Memory - * PLL -* Ensure DFT compatibility -* Basic functional verification - * Emulation - * Simulation - - - - - - -#### 2B- Backend SoC design -The Back-end SoC design is primarily resourced by CMC -* Leading to GDS2 netlist -* External bias generator - - -#### 2C- Wafer Fabrication -The Wafer fabrication is at Global Foundries and is managed by CMC. -* Built on 22FDX on the 2245 shuttle run[resourced by Global Foundries] -* The MCU project will initially manufacture a limited number (50-100) devices that will be used for bring-up testing and to supply an initial batch of Dev-Kit -* Note that for the purpose of Dev-Kit manufacture, not within this project, several thousand devices will be manufactured on a shuttle run to be determined - - - - -#### 2D - MCU Chip Package Design and Assembly -The chip packaging plan is by Quicklogic. -* Packing plan will be created [Anthony Le - Quicklogic] -* Package selection - a standard package will be used [CMC - Feng] -* The chips will be assembled in standard package with footprint that can be used with mainstream PCBs -* Package assembly will be carried out by a CMC subcontractor [CMC - Feng] -* First batch of packaged chips will be used for device characterization on Test PCB and first batch of Dev-Kit - - -#### 2E - Test PCB (AKA Bench Board) and Device Testing -The Test PCB design is by Quicklogic, and device characterization and testing by Quicklogic. -The manufacturing of the test PCB is by CMC. -* Testing approach within this project is based on a bench test board and chip characterization tests defined within this project -* Bench test PCB will be designed by Quicklogic [Anthony Le] -* Test PCB requirements will be documented -* PCB Schematic design -* PCB Part selection -* PCB Layout -* PCB Manufacture -* Small volume of PCB will be manufactured by CMC subcontractor -* Initial testing of PCB without MCU will be handled by Quicklogic [Anthony Le] -* Characterization plan to test MCU within Test PCB will be written by Quicklogic [Anthony Le] -* PCB/MCU testing will be done in two phases - quick bringup testing and full characterization testing including basic software for emulation - - - - -*Move the following to DeV-Kit Project* -#### Design and Build of the Evaluation (Eval) Kit (Board + Enabling Tools and Software) -Elements are: - - -* Specify and design board oard based on standard form factor for microcontroller-class SoCs so that existing, readily-accessible add-on peripheral boards can be connected (e.g. Adafruit Feather, Arduino Uno, etc) -* Package and SDK based on FreeRTOS -* Enable/document the use of FOSS FPGA tools to configure the eFPGA ) -* Documentation: lightweight user guide of the device such that a competent hardware or software engineer can evaluate the device on the Eval Kit. -* Develop the test methodology for the Eval Kit - - Initial test of first run - - Mass production (MP) testing - - -#### Define and Implement Distribution Model for the Eval Kit -As of PL, further discussion needed to: -* Define the responsible person/entity for contracting manufacture - - Board manufacture and assembly - - Production test -* Develop the distribution model (including cost and price aspects) for the Eval Kit - - - - - - -### Summary of Timeline - - - - -See PA Planning Spreadsheet for detailed breakdown - - -As of PA, the following major phases are identified and approximate timelines for completion are indicated as follows: - - -* Initial FPGA emulation as build - May 2021 -* Prototype FreeRTOS/MCU integration - June 2021 -* Emulation release and updated user guide for FPGA board - January 2022 -* Front-End SoC Design - design finalization in November 2021 -* Back-End SoC Design - November until January 2022 -* Design Submission to Global Foundries - January 2022 -* SoC Packaging Design - January 2022 -* Final design submission deadline - mid February 2022 -* Test PCB Design complete - Feb 2022 -* Devices back from GF - TBD (check on this) -* PCB Manufacture and assembly complete - March 2022 -* Device characterization plan complete - May 2022 -* Device packaging complete - June 30 2022 (check on this) -* PCB + MCU initial bringup - July 20 2022 -* PCB + MCU full characterization test result - TBD - - - - - - - - - - - - -## OpenHW Members/Participants committed to participate in CORE-V MCU project - - -* CMC -* QuickLogic -* GLOBALFOUNDRIES - - - - -## Technical Project Leader(s) (TPLs) -* Front end: Greg Martin (QuickLogic) -* Backend: Gayathri Singh (CMC) -* Test PCB: Anthony Le (QuickLogic) - (devkit) -* Test software CORE-V MCU SDK: Greg Martin (Quicklogic) - - - - - - -## Project Manager (PM) -* Front end: Jasper Lin -* Back end: Hugh Pollitt-Smith - - - - -## Project Documents -The following project documents will be created: - - - - -* PA document (this document) -* Project plan spreadsheet -* CORE-V MCU User Manual(read the docs) -* CORE-V MCU Datasheet include operating conditions, AC/DC parameters, basic timing information (*) -* Test PCB Specification -* Whole product test specification including SoC SW testing -* Verification plan -* Device characterization plan -* FPGA user guide for CORE-V MCU emulation platform -* Chip package design - - - - - - - - -Verification and Testing - - -Functional FPGA based SW package to do full verification of the peripherals - using as test vectors for RTL verification -"Whole Product Test" spec (SoC benchboard SW/s/w testing - preRTOS, FreeRTOS) -Static timing requirements/test logs -Logic equivalence verification, post P&R) -Characterization plan (testing first received board + chip) - -(*) These documentation will be created as markdown documents - - - - -## Summary of requirements - - - - -Importance for the Project of Key SoC Aspects -A = high importance -B = medium importance -C = low importance - - - - -| Item | Importance | Notes | -| ----------------- | :------: | -------------------------------------- | -| CPU correctness | A | | -| TTM | A | No part, no evaluation | -| Test | B+ | Defective parts = poor UX | -| Power | B | Show the potential; let commercial implementeors wring out the last microwatts | -| Peripherals | C | Must perform basic functions | -| Performance | C | Show the potential; let commercial implementers wring out the last MHz | -| Area | C | Volume is low, die is small so silicon cost not an issue | - - - - - - - - - - - - -### Future enhancements: -Future enhancements, which are not current CORE-V MCU project goals, may include the following: - - - - -* Redesigned MCU platform for all OpenHW cores - - Validating new processor cores or significant enhancements to the current processor core(s) -* Validating heterogeneous systems with multiple processor cores that have high degree of interaction - - E.g., CV-X-IF support -* Validating new memory IP that is tightly coupled with processor cores (e.g. MRAM) -* Validating new integration techniques that impact how the processor cores interact with the system (e.g. chiplets) -* Validating tools enhancements that automate the modification or configuration of processor cores -* Implementation using other fabrication processes or packaging types - - - - -## Explanation of why OpenHW should do this project -Key objectives: -OpenHW will bring a unique value to the industry by integrating a fully verified CV32E40P core with the MCU evaluation platform, including the industry’s widest set of software tools for RISC-V devices, with mainly open-source artifacts under a permissive license scheme with low exposure to export control. This effort will greatly enable the expansion of an ecosystem around the CORE-V devices. Specifically: - - -* Creates a 'proof point' for CV32E40P core to reduce risk of adoption when being used in commercialized SoCs -* Enables interested parties to evaluate suitability of CV32E40P core -* Demonstrates baseline performance/power/energy-efficiency of CV32E40P on GF22FDX, but without optimization -* Demonstrates how eFPGA accelerators can significantly enhance the performance/power/energy-efficiency capabilities when tightly coupled with RISC-V processor -* Demonstrates that OpenHW can be used to enable rapid, and inexpensive Proof-of-Concept for new IP and tools -* Enable implementers to quickly create commercial derivatives from CV32E40P - - - - -## Industry landscape: description of competing, alternative, or related efforts in the industry - - - - -### OpenFPGA -Reference to OpenFPGA concerning comparable initiative to open source eFPGA flow -https://openfpga.readthedocs.io/en/master/overview/motivation/ - - - - -### Potentially comparable (RISC-V) industry platforms -* NXP Vega board -* SiFive: HiFive board (check if open source) - - - - - - -### Related efforts to be described -The foundational elements of this project are described in this related effort concerning the Arnold Device: https://arxiv.org/pdf/2006.14256.pdf - - -The SDK-Dev-Kit has passed Project Concept as of the CORE-V MCU Plan Approved Gate. - - - - - - -## External dependencies - - - - -* GF22 PDK: GLOBALFOUNDRIES -Overview https://www.globalfoundries.com/sites/default/files/22fdx-product-brief.pdf -- standard cells libraries: Synopsys/GLOBALFOUNDRIES - - memory macros: Synopsys/GLOBALFOUNDRIES - - I/O: Synopsys/GLOBALFOUNDRIES -* PLL: Has been selected (QL) and request has been put in to GF (CMC) -* eFPGA & FOSS Tools: QuickLogic -* ASIC design tools: Cadence - - - - - - - - - - - - - - - - -## List of project outputs - - - - -Cores-TG: - - - - -* Core documentation -* Configurable RTL source code - - - - -Verification: -* Verification plan -* Test sequences -* Functional FPGA based SW package to do full verification of the peripherals - using as test vectors for RTL verification -* Static timing requirements/test logs -* Logic equivalence verification, post P&R) -* Verification results -* Bug reports -* Verification report - - - - -HW: - - -* Tested SoC assembled in package -* Test PCB -* eFPGA gateware associated with accelerating added-value SW application of TensorFlow Lite for Microcontroller -* Documentation - - - - -SW: - - -* Initial open-source test SW suite (compliant with sustainable open-source solution expectations) -* Open-source bare metal BSP compatible with dev kit -* Open source RTOS port (FreeRTOS) -* FOSS FPGA Tools that supports RTL-to-bitstream - - - - -Potential additional outputs (not committed): -* Added-value SW SDK for TensorFlow Lite for Microcontroller -* Example application of eFPGA-accelerated Tensorflow Lite for Microcontroller-created visual wake word - - - - -## TGs Impacted/Resource requirements - - -* Work is carried out by HW T - - - - -## OpenHW engineering staff resource plan: requirement and availability - - -* Overall architecture guidance: Florian Zaruba -* Project management coaching: Duncan Bees -* Verification coaching: Mike Thompson - - - - - - -## Engineering resource supplied by members - requirement and availability - - -* As of PA, sufficient resources are available within project companies for components other than simulation. - - - - -## OpenHW marketing resource - requirement and availability -## Marketing resource supplied by members - requirement and availability - - - - -## Funding supplied by OpenHW - requirement and availability -n/a - - - - -## Funding supplied by members - requirement and availability -n/a - - - - -## Architecture diagram -![Arnold2, arch diagram](./Arnold2-arch.png) - - - - - - -## Who would make use of OpenHW output -* Any developer and/or researcher that wants to commercialize an implementation of the CV32E40P core, be it FPGA-based or in an new SoC. This could include an OEM, a semiconductor company, etc. -* Any developer and/or researcher that is interested in evaluating the performance and power tradeoffs of an SoC implementation on FDSOI processes -* Any developer and/or researcher that wants to develop AI-based applications using a hybrid RISC-V/eFPGA implementation -* Current OpenHW Group Members -* Future OpenHW Group ActiveProjects - - - - -## Project license model -The project artefacts and outputs will be licensed under Apache 2.0 for SW code and Solderpad 0.51 or Solderpad 2.0 for HW/RTL codes. - - - - -Note about open source nature of the project -* The MCU itself, i.e., the RTL code required to build the emulation, is open source, and follows the project license above -* The SoC implementation based on the MCU, which includes commercial libraries, is built out of the public domain. The following components of synthesis specifically are private: - * PLL - * I/O - * Standard cell library - * Clock gating cells - * Memories - * ROM - * eFPGA core -* The resulting GDS files are proprietary -* The Test PCB kit design files (i.e. schematics) are open source -* The Test PCB Gerber files related to the Eval kit are open source - - - - -Note on tools used -* eFPGA tools are open source -* The Eval design tools used are for further study. Some open source tools such as KiCad are candidates - -* Third-party open-source contributions will generally retain their own licence model. The starting point is the open source core-v-MCU FPGA emulation, but the nature of ASIC PDKs, libraries and IPs means that the ASIC version will not be open. - - - - -"Viral" licences, such as GPL, will be avoided. To the extent possible, all open source licenses should be permissive. - - - - -## Description of initial code contribution, if required -The existing code contribution comes from a combination of the OpenHW group, the RTL that is able to be distributed publicly from ETH Zurich Github repository, and the FOSS Tools from the QuickLogic Github repository. - - - - -## Repository Structure - - - - -The contents of core-v-mcu are: -* MCU RTL -* MCU documentation -* Fpga build files - - - - - - - - - - - - - - -## Project distribution model -* OpenHW GitHub Repository - - - - -## Project plan -See PA spreadsheet - - - - -## ISSUES AND RISKS - - -* Who will pay for the manufacture of required tests boards -* Licensing of PLL still needs to be completed -* Delivery schedule from GF of fabricated devices and timeline for packaging needs more care and attention +OpenHW Plan Approve Proposal Document + + + + + + +# Title of Project + + +Design and Fabrication of CORE-V MCU System on Chip (MCU project). + +## Summary of project + + + + +This project builds upon the OpenHW CV32E40P core, the core-v-mcu FPGA implementation, and embedded FPGA components to design and fabricate an evaluation SoC. The MCU will be at the heart of an open source tools and IP ecosystem under which commercial SoC devices and their associated software applications can be rapidly brought to market. + + +The CORE-V MCU project is one of three related project: +* CORE-V MCU (this project) delivers the MCU SoC with initial testing on a bench test board with limited test software. +* CORE-V Dev-Kit delivers, manufactures and distributes a development board that integrates the MCU together with the SDK. +* CORE-V SDK delivers the out-of-box software stack to support the Dev-Kit. + + +These three projects together will as a whole provide a real-world development environment. + + +Key aspects of the MCU project are: +* Bring-up OpenHW CV32E40P core within an updated MCU platform on a bench test board and FPGA. +* Achieve test software bringup on FPGA and SoC implementations of the CORE-V MCU. +* Incorporate eFPGA that enables people to use configurable accelerators for AI-type applications. The eFPGA block itself is not open source, but it can be programmed using an open source tool flow that will be delivered as a component of the SDK project. +* Provide a starting point for the design of commercial SoC devices based on CV32E40P. +* The MCU is not in itself meant as a product; rather, it provides a proof-of-concept and evaluation instantiation of the CV32E40P within an MCU architecture. +* The MCU project will bring the CV32E40P IP to TRL6 from a starting point at TRL5. +* The MCU will de-risk and accelerate others to adopt the CV32E40P in their own SoC. + + + + + + +## Components +The project comprises two main components +1) - Emulation (FPGA board) Release of CORE-V MCU +2) - Design, Fabrication and Initial Test of the CORE-V MCU SoC Device + + +### Component 1 - Emulation Release (FPGA) + + +The emulation release provides a development platform for OpenHW tools developers and an initial evaluation platform for 3rd parties +* The FPGA design takes as input the completed design and verification of the CV32E40P core (Release 1.0.0 from December 2020) +* RTL Freeze version for the FPGA +* GDS Freeze update version for FPGA +* Updated user guide for the FPGA - CMC, Quicklogic +* Prototype CORE-V MCU software based on test software used for the MCU SoC Device - Quicklogic + + +### Component 2 - Design and Fabrication of the SoC Device + + +#### 2A - Front end SoC design + + +The Front-end SoC design is primarily resourced by or through QuickLogic. Key aspects +* Starting from CORE-V FPGA design. +* Integrate eFPGA (logic array, fixed function blocks for accelerators, and configuration controller) from QuickLogic +* Integrate technology specific elements required by ASIC implementation + * I/O + * Memory + * PLL +* Ensure DFT compatibility +* Basic functional verification + * Emulation + * Simulation + + + + + + +#### 2B- Backend SoC design +The Back-end SoC design is primarily resourced by CMC +* Leading to GDS2 netlist +* External bias generator + + +#### 2C- Wafer Fabrication +The Wafer fabrication is at Global Foundries and is managed by CMC. +* Built on 22FDX on the 2245 shuttle run[resourced by Global Foundries] +* The MCU project will initially manufacture a limited number (50-100) devices that will be used for bring-up testing and to supply an initial batch of Dev-Kit +* Note that for the purpose of Dev-Kit manufacture, not within this project, several thousand devices will be manufactured on a shuttle run to be determined + + + + +#### 2D - MCU Chip Package Design and Assembly +The chip packaging plan is by Quicklogic. +* Packing plan will be created [Anthony Le - Quicklogic] +* Package selection - a standard package will be used [CMC - Feng] +* The chips will be assembled in standard package with footprint that can be used with mainstream PCBs +* Package assembly will be carried out by a CMC subcontractor [CMC - Feng] +* First batch of packaged chips will be used for device characterization on Test PCB and first batch of Dev-Kit + + +#### 2E - Test PCB (AKA Bench Board) and Device Testing +The Test PCB design is by Quicklogic, and device characterization and testing by Quicklogic. +The manufacturing of the test PCB is by CMC. +* Testing approach within this project is based on a bench test board and chip characterization tests defined within this project +* Bench test PCB will be designed by Quicklogic [Anthony Le] +* Test PCB requirements will be documented +* PCB Schematic design +* PCB Part selection +* PCB Layout +* PCB Manufacture +* Small volume of PCB will be manufactured by CMC subcontractor +* Initial testing of PCB without MCU will be handled by Quicklogic [Anthony Le] +* Characterization plan to test MCU within Test PCB will be written by Quicklogic [Anthony Le] +* PCB/MCU testing will be done in two phases - quick bringup testing and full characterization testing including basic software for emulation + + + + +*Move the following to DeV-Kit Project* +#### Design and Build of the Evaluation (Eval) Kit (Board + Enabling Tools and Software) +Elements are: + + +* Specify and design board oard based on standard form factor for microcontroller-class SoCs so that existing, readily-accessible add-on peripheral boards can be connected (e.g. Adafruit Feather, Arduino Uno, etc) +* Package and SDK based on FreeRTOS +* Enable/document the use of FOSS FPGA tools to configure the eFPGA ) +* Documentation: lightweight user guide of the device such that a competent hardware or software engineer can evaluate the device on the Eval Kit. +* Develop the test methodology for the Eval Kit + - Initial test of first run + - Mass production (MP) testing + + +#### Define and Implement Distribution Model for the Eval Kit +As of PL, further discussion needed to: +* Define the responsible person/entity for contracting manufacture + - Board manufacture and assembly + - Production test +* Develop the distribution model (including cost and price aspects) for the Eval Kit + + + + + + +### Summary of Timeline + + + + +See PA Planning Spreadsheet for detailed breakdown + + +As of PA, the following major phases are identified and approximate timelines for completion are indicated as follows: + + +* Initial FPGA emulation as build - May 2021 +* Prototype FreeRTOS/MCU integration - June 2021 +* Emulation release and updated user guide for FPGA board - January 2022 +* Front-End SoC Design - design finalization in November 2021 +* Back-End SoC Design - November until January 2022 +* Design Submission to Global Foundries - January 2022 +* SoC Packaging Design - January 2022 +* Final design submission deadline - mid February 2022 +* Test PCB Design complete - Feb 2022 +* Devices back from GF - TBD (check on this) +* PCB Manufacture and assembly complete - March 2022 +* Device characterization plan complete - May 2022 +* Device packaging complete - June 30 2022 (check on this) +* PCB + MCU initial bringup - July 20 2022 +* PCB + MCU full characterization test result - TBD + + + + + + + + + + + + +## OpenHW Members/Participants committed to participate in CORE-V MCU project + + +* CMC +* QuickLogic +* GLOBALFOUNDRIES + + + + +## Technical Project Leader(s) (TPLs) +* Front end: Greg Martin (QuickLogic) +* Backend: Gayathri Singh (CMC) +* Test PCB: Anthony Le (QuickLogic) + (devkit) +* Test software CORE-V MCU SDK: Greg Martin (Quicklogic) + + + + + + +## Project Manager (PM) +* Front end: Jasper Lin +* Back end: Hugh Pollitt-Smith + + + + +## Project Documents +The following project documents will be created: + + + + +* PA document (this document) +* Project plan spreadsheet +* CORE-V MCU User Manual(read the docs) +* CORE-V MCU Datasheet include operating conditions, AC/DC parameters, basic timing information (*) +* Test PCB Specification +* Whole product test specification including SoC SW testing +* Verification plan +* Device characterization plan +* FPGA user guide for CORE-V MCU emulation platform +* Chip package design + + + + + + + + +Verification and Testing + + +Functional FPGA based SW package to do full verification of the peripherals - using as test vectors for RTL verification +"Whole Product Test" spec (SoC benchboard SW/s/w testing - preRTOS, FreeRTOS) +Static timing requirements/test logs +Logic equivalence verification, post P&R) +Characterization plan (testing first received board + chip) + +(*) These documentation will be created as markdown documents + + + + +## Summary of requirements + + + + +Importance for the Project of Key SoC Aspects +A = high importance +B = medium importance +C = low importance + + + + +| Item | Importance | Notes | +| ----------------- | :------: | -------------------------------------- | +| CPU correctness | A | | +| TTM | A | No part, no evaluation | +| Test | B+ | Defective parts = poor UX | +| Power | B | Show the potential; let commercial implementeors wring out the last microwatts | +| Peripherals | C | Must perform basic functions | +| Performance | C | Show the potential; let commercial implementers wring out the last MHz | +| Area | C | Volume is low, die is small so silicon cost not an issue | + + + + + + + + + + + + +### Future enhancements: +Future enhancements, which are not current CORE-V MCU project goals, may include the following: + + + + +* Redesigned MCU platform for all OpenHW cores + - Validating new processor cores or significant enhancements to the current processor core(s) +* Validating heterogeneous systems with multiple processor cores that have high degree of interaction + - E.g., CV-X-IF support +* Validating new memory IP that is tightly coupled with processor cores (e.g. MRAM) +* Validating new integration techniques that impact how the processor cores interact with the system (e.g. chiplets) +* Validating tools enhancements that automate the modification or configuration of processor cores +* Implementation using other fabrication processes or packaging types + + + + +## Explanation of why OpenHW should do this project +Key objectives: +OpenHW will bring a unique value to the industry by integrating a fully verified CV32E40P core with the MCU evaluation platform, including the industry’s widest set of software tools for RISC-V devices, with mainly open-source artifacts under a permissive license scheme with low exposure to export control. This effort will greatly enable the expansion of an ecosystem around the CORE-V devices. Specifically: + + +* Creates a 'proof point' for CV32E40P core to reduce risk of adoption when being used in commercialized SoCs +* Enables interested parties to evaluate suitability of CV32E40P core +* Demonstrates baseline performance/power/energy-efficiency of CV32E40P on GF22FDX, but without optimization +* Demonstrates how eFPGA accelerators can significantly enhance the performance/power/energy-efficiency capabilities when tightly coupled with RISC-V processor +* Demonstrates that OpenHW can be used to enable rapid, and inexpensive Proof-of-Concept for new IP and tools +* Enable implementers to quickly create commercial derivatives from CV32E40P + + + + +## Industry landscape: description of competing, alternative, or related efforts in the industry + + + + +### OpenFPGA +Reference to OpenFPGA concerning comparable initiative to open source eFPGA flow +https://openfpga.readthedocs.io/en/master/overview/motivation/ + + + + +### Potentially comparable (RISC-V) industry platforms +* NXP Vega board +* SiFive: HiFive board (check if open source) + + + + + + +### Related efforts to be described +The foundational elements of this project are described in this related effort concerning the Arnold Device: https://arxiv.org/pdf/2006.14256.pdf + + +The SDK-Dev-Kit has passed Project Concept as of the CORE-V MCU Plan Approved Gate. + + + + + + +## External dependencies + + + + +* GF22 PDK: GLOBALFOUNDRIES +Overview https://www.globalfoundries.com/sites/default/files/22fdx-product-brief.pdf +- standard cells libraries: Synopsys/GLOBALFOUNDRIES + - memory macros: Synopsys/GLOBALFOUNDRIES + - I/O: Synopsys/GLOBALFOUNDRIES +* PLL: Has been selected (QL) and request has been put in to GF (CMC) +* eFPGA & FOSS Tools: QuickLogic +* ASIC design tools: Cadence + + + + + + + + + + + + + + + + +## List of project outputs + + + + +Cores-TG: + + + + +* Core documentation +* Configurable RTL source code + + + + +Verification: +* Verification plan +* Test sequences +* Functional FPGA based SW package to do full verification of the peripherals - using as test vectors for RTL verification +* Static timing requirements/test logs +* Logic equivalence verification, post P&R) +* Verification results +* Bug reports +* Verification report + + + + +HW: + + +* Tested SoC assembled in package +* Test PCB +* eFPGA gateware associated with accelerating added-value SW application of TensorFlow Lite for Microcontroller +* Documentation + + + + +SW: + + +* Initial open-source test SW suite (compliant with sustainable open-source solution expectations) +* Open-source bare metal BSP compatible with dev kit +* Open source RTOS port (FreeRTOS) +* FOSS FPGA Tools that supports RTL-to-bitstream + + + + +Potential additional outputs (not committed): +* Added-value SW SDK for TensorFlow Lite for Microcontroller +* Example application of eFPGA-accelerated Tensorflow Lite for Microcontroller-created visual wake word + + + + +## TGs Impacted/Resource requirements + + +* Work is carried out by HW T + + + + +## OpenHW engineering staff resource plan: requirement and availability + + +* Overall architecture guidance: Florian Zaruba +* Project management coaching: Duncan Bees +* Verification coaching: Mike Thompson + + + + + + +## Engineering resource supplied by members - requirement and availability + + +* As of PA, sufficient resources are available within project companies for components other than simulation. + + + + +## OpenHW marketing resource - requirement and availability +## Marketing resource supplied by members - requirement and availability + + + + +## Funding supplied by OpenHW - requirement and availability +n/a + + + + +## Funding supplied by members - requirement and availability +n/a + + + + +## Architecture diagram +![Arnold2, arch diagram](./Arnold2-arch.png) + + + + + + +## Who would make use of OpenHW output +* Any developer and/or researcher that wants to commercialize an implementation of the CV32E40P core, be it FPGA-based or in an new SoC. This could include an OEM, a semiconductor company, etc. +* Any developer and/or researcher that is interested in evaluating the performance and power tradeoffs of an SoC implementation on FDSOI processes +* Any developer and/or researcher that wants to develop AI-based applications using a hybrid RISC-V/eFPGA implementation +* Current OpenHW Group Members +* Future OpenHW Group ActiveProjects + + + + +## Project license model +The project artefacts and outputs will be licensed under Apache 2.0 for SW code and Solderpad 0.51 or Solderpad 2.0 for HW/RTL codes. + + + + +Note about open source nature of the project +* The MCU itself, i.e., the RTL code required to build the emulation, is open source, and follows the project license above +* The SoC implementation based on the MCU, which includes commercial libraries, is built out of the public domain. The following components of synthesis specifically are private: + * PLL + * I/O + * Standard cell library + * Clock gating cells + * Memories + * ROM + * eFPGA core +* The resulting GDS files are proprietary +* The Test PCB kit design files (i.e. schematics) are open source +* The Test PCB Gerber files related to the Eval kit are open source + + + + +Note on tools used +* eFPGA tools are open source +* The Eval design tools used are for further study. Some open source tools such as KiCad are candidates + +* Third-party open-source contributions will generally retain their own licence model. The starting point is the open source core-v-MCU FPGA emulation, but the nature of ASIC PDKs, libraries and IPs means that the ASIC version will not be open. + + + + +"Viral" licences, such as GPL, will be avoided. To the extent possible, all open source licenses should be permissive. + + + + +## Description of initial code contribution, if required +The existing code contribution comes from a combination of the OpenHW group, the RTL that is able to be distributed publicly from ETH Zurich Github repository, and the FOSS Tools from the QuickLogic Github repository. + + + + +## Repository Structure + + + + +The contents of core-v-mcu are: +* MCU RTL +* MCU documentation +* Fpga build files + + + + + + + + + + + + + + +## Project distribution model +* OpenHW GitHub Repository + + + + +## Project plan +See PA spreadsheet + + + + +## ISSUES AND RISKS + + +* Who will pay for the manufacture of required tests boards +* Licensing of PLL still needs to be completed +* Delivery schedule from GF of fabricated devices and timeline for packaging needs more care and attention * Achieving handoff of front-end RTL for commencing of back-end place and route needs careful attention \ No newline at end of file diff --git a/program/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/Preliminary-project-proposal-for-MCU-SoC.md b/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/Preliminary-project-proposal-for-MCU-SoC.md similarity index 100% rename from program/Project-Descriptions-and-Plans/CORE-V-MCU-SoC/Preliminary-project-proposal-for-MCU-SoC.md rename to Project-Descriptions-and-Plans/CORE-V-MCU-SoC/Preliminary-project-proposal-for-MCU-SoC.md diff --git a/program/Project-Descriptions-and-Plans/CORE-V-MCU-UVM/MCU_UVM_Full.png b/Project-Descriptions-and-Plans/CORE-V-MCU-UVM/MCU_UVM_Full.png similarity index 100% rename from program/Project-Descriptions-and-Plans/CORE-V-MCU-UVM/MCU_UVM_Full.png rename to Project-Descriptions-and-Plans/CORE-V-MCU-UVM/MCU_UVM_Full.png diff --git a/program/Project-Descriptions-and-Plans/CORE-V-MCU-UVM/MCU_UVM_Full.vsdx b/Project-Descriptions-and-Plans/CORE-V-MCU-UVM/MCU_UVM_Full.vsdx similarity index 100% rename from program/Project-Descriptions-and-Plans/CORE-V-MCU-UVM/MCU_UVM_Full.vsdx rename to Project-Descriptions-and-Plans/CORE-V-MCU-UVM/MCU_UVM_Full.vsdx diff --git a/program/Project-Descriptions-and-Plans/CORE-V-MCU-UVM/MCU_UVM_Simplified.png b/Project-Descriptions-and-Plans/CORE-V-MCU-UVM/MCU_UVM_Simplified.png similarity index 100% rename from program/Project-Descriptions-and-Plans/CORE-V-MCU-UVM/MCU_UVM_Simplified.png rename to Project-Descriptions-and-Plans/CORE-V-MCU-UVM/MCU_UVM_Simplified.png diff --git a/program/Project-Descriptions-and-Plans/CORE-V-MCU-UVM/MCU_UVM_Simplified.vsdx b/Project-Descriptions-and-Plans/CORE-V-MCU-UVM/MCU_UVM_Simplified.vsdx similarity index 100% rename from program/Project-Descriptions-and-Plans/CORE-V-MCU-UVM/MCU_UVM_Simplified.vsdx rename to Project-Descriptions-and-Plans/CORE-V-MCU-UVM/MCU_UVM_Simplified.vsdx diff --git a/program/Project-Descriptions-and-Plans/CORE-V-MCU-UVM/TWG_Presentation_2022-01-24.pptx b/Project-Descriptions-and-Plans/CORE-V-MCU-UVM/TWG_Presentation_2022-01-24.pptx similarity index 100% rename from program/Project-Descriptions-and-Plans/CORE-V-MCU-UVM/TWG_Presentation_2022-01-24.pptx rename to Project-Descriptions-and-Plans/CORE-V-MCU-UVM/TWG_Presentation_2022-01-24.pptx diff --git a/program/Project-Descriptions-and-Plans/CORE-V-MCU-UVM/mcu_uvm_project_concept.md b/Project-Descriptions-and-Plans/CORE-V-MCU-UVM/mcu_uvm_project_concept.md similarity index 100% rename from program/Project-Descriptions-and-Plans/CORE-V-MCU-UVM/mcu_uvm_project_concept.md rename to Project-Descriptions-and-Plans/CORE-V-MCU-UVM/mcu_uvm_project_concept.md diff --git a/program/Project-Descriptions-and-Plans/CORE-V-VEC-Research/PPL proposal for Core-V-VEC Research Project.md b/Project-Descriptions-and-Plans/CORE-V-VEC-Research/PPL proposal for Core-V-VEC Research Project.md similarity index 98% rename from program/Project-Descriptions-and-Plans/CORE-V-VEC-Research/PPL proposal for Core-V-VEC Research Project.md rename to Project-Descriptions-and-Plans/CORE-V-VEC-Research/PPL proposal for Core-V-VEC Research Project.md index c52ca8350..b2889e448 100644 --- a/program/Project-Descriptions-and-Plans/CORE-V-VEC-Research/PPL proposal for Core-V-VEC Research Project.md +++ b/Project-Descriptions-and-Plans/CORE-V-VEC-Research/PPL proposal for Core-V-VEC Research Project.md @@ -1,168 +1,168 @@ -# OpenHW Preliminary Project Launch (PPL) Proposal - Core-V-VEC Research Project -# Title of Project - -This is the PPL for the Core-V-VEC project. This is a research-oriented project driven by several OpenHW members to develop an enhanced version of the "Ara" Coprocessor. -The Ara VP is a state-of-the-art parametric in-order high-performance 64-bit vector unit based on version 0.5 of the RISC-V “V” specification, which works in tandem with the Ariane application-class RV64GC scalar processor core - - -Fhe Mitacs Accelerate research proposal document ("Research Proposal") describes the proposed research in full detail -"RISC-V Vector Processor for High-throughput Multidimensional Sensor Data Processing & Machine Learning Acceleration at the Edge" -for details. - - ## Summary of project - -The main goal of the project is to undertake research that will result in improved the functionality and performance of Ara. -Research will focus on two main areas -(i) Energy efficient handling for low precision operands -(ii) Autonomous memory interface to provide direct memory access from Ara, which will improve energy efficiency of the system. -Since the time that Ara was first developed, the RISC-V Foundation vector extensions have been further refined and updating Ara to meet this specification is a component of the project. -Also, the project will bring Ara under the OpenHW umbrella and home the repository in the OpenHW organization. - -The following is the abstract from the Research Proposal Nov 20, 2020 version - -Today’s main challenge of advanced computing solutions consists in increasing the performances of systems while keeping their power envelope within tight bounds, as dictated by the needs of a wide range of applications: from small Internet of Things (IoT) all the way up to High Performance Computing (HPC). This high demand for energy-efficiency, coupled with the limitations of technology scaling – which no longer provides improved performances at constant power densities – is leading designers to explore new microarchitectures with the goal of pulling more performances out of a constrained power budget. This project will enter into this trend by revisiting the vector processing model, which provides a highly efficient way of exploiting data parallelism in scientific and matrix-oriented computations, as well as in high-throughput multi-dimensional digital signal processing and machine learning (ML) algorithms under real-time constraints. Indeed, the efficiency of vector processors (VPs) comes from their ability to perform parallel-data computations on very large vectors, thereby amortizing the overhead of fetching and decoding instructions. The starting point for this project will be from the VP that follows the specifications of the open-source RISC-V ISA “V” vector extension, and it will take place within a larger research project known as the PULP Platform [1]. Specifically, this project will extend on prior works, performed as part of the PULP Platform, that led to a first-generation RISC-V VP called Ara. The Ara VP is a state-of-the-art parametric in-order high-performance 64-bit vector unit based on version 0.5 of the RISC-V “V” specification, which works in tandem with the Ariane application-class RV64GC scalar processor core. Early analysis of Ara has shown that it achieves up to 41 DP-GFLOPS/W, which is superior to similar vector processors found in the literature. Yet, insights gained with this analysis also highlighted that addressing specific limitations of Ara would significantly improve its energy-efficiency. In addition, Ara must be updated to support the most recent version of the RISC-V “V” extension (from version 0.5 to version 0.9), which is continuously evolving. With the objective of improving the energy-efficiency of Ara, this project will explore two main research areas: 1) A more autonomous memory subsystem will be added to Ara. This will reduce stalls in the scalar processor due to interactions with the vector processor, while extracting more bandwidth from the memory hierarchy, thereby improving the overall energy efficiency of the system. 2) Ara will be extended to support low-precision instructions, that is, operations performed on low-precisions (e.g. sub-byte) vector operands. This addition to Ara’s datapath will benefit a new class of ML models, such as Binary Neural Nets or XNOR networks, that have demonstrated improved performances compared to ordinary neural network models by operating on low-precision data. Both research areas will require extensive work at the hardware and the software levels. On the software side, dedicated libraries, mixing intrinsics and optimized macros that exploit Ara’s features, will be developed in an effort to develop a benchmark suite targeting key application kernels used in (binary) neural networks. On the hardware side, RTL development will be supported by simulations and rapid FPGA prototyping. An important milestone of this project is the implementation and the fabrication of improved Ara VP core prototypes using the GLOBALFOUNDERIES 22FDX 22 nm technology, which will showcase the proposed microarchitecture through energy-efficiency measurements. Our Ara VP design and its associated software stack will be open-sourced under a liberal license as part of the CORE-V family of RISC-V processors – derived from the PULP Platform – of the OpenHW group, with the intention of stimulating future open-source hardware collaboration involving Canadian industries and universities. - -Note that unlike other OpenHW Projects, for example the cv32e40p project, it is not the goal of the Core-V-VEC Research Project to produce industrial quality IP. -Rather, this project produces a set of outputs (RTL, research papers, source code, test chip) that could serve as "advanced input" to industrial quality IP projects should OpenHW choose to underake that. - - - - - -### Components of the Research Proposal - -The scope of this project is quite wide and constitutes a number of activities that for an industrial quality project, might be treated as independent projects. -The current intent is to manage this research project as one OpenHW project, and consider in future splitting into separate "industrialization" projects. - - -T1. Setting up the PULP Platform environment to support the development of the Ara VP: -T2. Emulating the Ara VP on FPGA: -T3. Benchmarking the Ara VP -T4. Supporting the most recent RISC-V “V” vector ISA extension [7]: -T5. Improving the energy efficiency of the Ara VP via autonomous memory subsystems -T6. Extending Ara to support low-precision ISA extensions: -T7. Providing software support for the Ara VP -T8. Implementing the Ara VP in the GF 22FDX ASIC technology - -### Summary of Timeline - -The Research Proposal provides a detailed schedule for each person working on it. Essentially this is a 2 year project with activities broken out into 4 month chunks. The starting date is January 2021. - -![Image of Research Proposal Timeline] -(https://github.com/openhwgroup/core-v-docs/blob/master/program/images/VEC%20schedule.png) - -Source: Presentation of Hugh Pollitt-Smith, CMC - -## OpenHW Members/Participants committed to participate - -The Research Proposal names 6 interns who are doing the work of the project. -The project funding (for the interns) is provided by CMC Microsystems and Mitacs on an approximately equal basis. Note that this is the first example of the OpenHW Accelerate Program, which brings together academic, peer-reviewed research funding from Mitacs and other OpenHW members. - - -## Technical Project Leader(s) (TPLs) -Frank Gurkaynak, ETH Zurich Professor -Mickael Fiorentino, Polytechnique Montreal, Post-Doctoral Fellow and project intern - - -## Project Manager (PM) -Hugh Politt Smith, CMC - - -## Project Documents -See list of project outputs below. A specific set of documents is not as yet itemized. - -## Summary of requirements -These technical requirements are driving the Ara coprocessor. - -Applications: -- High-throughput multi-dimensional digital signal processing. For example, sensor fusion, e.g. aggregation of automotive sensor data. -- Machine learning (ML) algorithms under real-time constrain -- IoT to High Performance Computing (HPC) -- Highly efficient way of exploiting data parallelism in scientific and matrix-oriented computations - -Specific requirements to be addressed: -- Extreme energy efficiency for vector arithmetic -- Specific focus on energy efficiency for low-precision operands -- Update Ara to support version 0.9 of the RISC-V "V" extension - -## Explanation of why OpenHW should do this project -OpenHW through its members is developing a full ecosystem around the Core-V cores and related IP and tooling. The external Vector processor is one of several industry approaches for acceleration of vector-math intensive applications. It will be an important part of the OpenHW Core-V ecosystem. -This is the lead project for OpenHW's Accelerate program and will pave the way for future industry-academic collaboration projects within the OpenHW ecosystem. - -## Industry landscape: description of competing, alternative, or related efforts in the industry -Check paper reference [14] for potential description of alternative approaches - -## External dependencies -Leave open for now - -## List of project outputs - -(1) Open source RTL code -(2) Open source code for software ecosystem (RISC-V assembly, c/c++, python) -(3) ASIC implementatoin, EDA scripts, tape-out, characterization in GF 22FDX technology -(4) FPGA emulation targeting CMC-supported boards -(5) Technical documentation and training materials -(6) Mitacs final report -(7) Student PhD/MSc theses, conference and journal papers -(8) Test chips and demonstration boards - - -## TGs Impacted/Resource requirements - -The primary TG that will have oversight is the to-be-formed University Outeach Task Group. -Although the project scope includes activities carried out in SW, Cores, Verification, and HW, those TG will not have direct oversight as this is not an industrialization project. -On the other hand, there will be some involvement of processes from these groups, for example verification framework, and the project is expected to provide updates to the relevant TG as work progresses. - -### University Outreach Task Group (under MWG) -The project manager of this OpenHW group is expected to report the overall progress, issues, roadblocks, and changes to the UOTG - - - -## OpenHW engineering staff resource plan: requirement and availability -## Engineering resource supplied by members - requirement and availability - -The interns driving the work, under the funding model described above, are identified in the Research Proposal. - -## OpenHW marketing resource - requirement and availability -## Marketing resource supplied by members - requirement and availability -## Funding supplied by OpenHW - requirement and availability -## Funding supplied by members - requirement and availability - -Already described above - -## Architecture diagram - - -![Image of Ara architecture] -(https://github.com/DBees/core-v-docs/blob/master/program/images/ARA%20block%20diagram.png) - -Screenshot From M. Cavalcante, F. Schuiki, F. Zaruba, M. Schaffner, and L. Benini, “Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI,” IEEE Trans. Very Large Scale Integr. VLSI Syst., vol. 28, no. 2, pp. 530–543, Feb. 2020, doi: 10.1109/TVLSI.2019.2950087. - - -## Who would make use of OpenHW output - -(i) Academic community - -(ii) OpenHW members may industrialize within OpenHW - -(iii) Any industry members may take the results privately and advance further - -## Project license model -Expectation -- existing license model for Ara at the moment and going forward under SHL 2.0 - need to verify -- sw work Apache 2.0 -- Not expected to be run as Eclipse project, but should be treated under OpenHW/Eclipse IP process -- verify MCCA status of key participants - -## Description of initial code contribution, if required -Need reference to the current state of the Ara code and repository - -## Repository Structure -An OpenHW GitHub Repository will be used for the Ara coprocessor as it evolves. The point at which, and mechanism for which the Ara code is transferred from ETHZ to OpenHW is not yet defined. - -## Project distribution model -Not yet defined - -## Preliminary Project plan - +# OpenHW Preliminary Project Launch (PPL) Proposal - Core-V-VEC Research Project +# Title of Project + +This is the PPL for the Core-V-VEC project. This is a research-oriented project driven by several OpenHW members to develop an enhanced version of the "Ara" Coprocessor. +The Ara VP is a state-of-the-art parametric in-order high-performance 64-bit vector unit based on version 0.5 of the RISC-V “V” specification, which works in tandem with the Ariane application-class RV64GC scalar processor core + + +Fhe Mitacs Accelerate research proposal document ("Research Proposal") describes the proposed research in full detail +"RISC-V Vector Processor for High-throughput Multidimensional Sensor Data Processing & Machine Learning Acceleration at the Edge" +for details. + + ## Summary of project + +The main goal of the project is to undertake research that will result in improved the functionality and performance of Ara. +Research will focus on two main areas +(i) Energy efficient handling for low precision operands +(ii) Autonomous memory interface to provide direct memory access from Ara, which will improve energy efficiency of the system. +Since the time that Ara was first developed, the RISC-V Foundation vector extensions have been further refined and updating Ara to meet this specification is a component of the project. +Also, the project will bring Ara under the OpenHW umbrella and home the repository in the OpenHW organization. + +The following is the abstract from the Research Proposal Nov 20, 2020 version + +Today’s main challenge of advanced computing solutions consists in increasing the performances of systems while keeping their power envelope within tight bounds, as dictated by the needs of a wide range of applications: from small Internet of Things (IoT) all the way up to High Performance Computing (HPC). This high demand for energy-efficiency, coupled with the limitations of technology scaling – which no longer provides improved performances at constant power densities – is leading designers to explore new microarchitectures with the goal of pulling more performances out of a constrained power budget. This project will enter into this trend by revisiting the vector processing model, which provides a highly efficient way of exploiting data parallelism in scientific and matrix-oriented computations, as well as in high-throughput multi-dimensional digital signal processing and machine learning (ML) algorithms under real-time constraints. Indeed, the efficiency of vector processors (VPs) comes from their ability to perform parallel-data computations on very large vectors, thereby amortizing the overhead of fetching and decoding instructions. The starting point for this project will be from the VP that follows the specifications of the open-source RISC-V ISA “V” vector extension, and it will take place within a larger research project known as the PULP Platform [1]. Specifically, this project will extend on prior works, performed as part of the PULP Platform, that led to a first-generation RISC-V VP called Ara. The Ara VP is a state-of-the-art parametric in-order high-performance 64-bit vector unit based on version 0.5 of the RISC-V “V” specification, which works in tandem with the Ariane application-class RV64GC scalar processor core. Early analysis of Ara has shown that it achieves up to 41 DP-GFLOPS/W, which is superior to similar vector processors found in the literature. Yet, insights gained with this analysis also highlighted that addressing specific limitations of Ara would significantly improve its energy-efficiency. In addition, Ara must be updated to support the most recent version of the RISC-V “V” extension (from version 0.5 to version 0.9), which is continuously evolving. With the objective of improving the energy-efficiency of Ara, this project will explore two main research areas: 1) A more autonomous memory subsystem will be added to Ara. This will reduce stalls in the scalar processor due to interactions with the vector processor, while extracting more bandwidth from the memory hierarchy, thereby improving the overall energy efficiency of the system. 2) Ara will be extended to support low-precision instructions, that is, operations performed on low-precisions (e.g. sub-byte) vector operands. This addition to Ara’s datapath will benefit a new class of ML models, such as Binary Neural Nets or XNOR networks, that have demonstrated improved performances compared to ordinary neural network models by operating on low-precision data. Both research areas will require extensive work at the hardware and the software levels. On the software side, dedicated libraries, mixing intrinsics and optimized macros that exploit Ara’s features, will be developed in an effort to develop a benchmark suite targeting key application kernels used in (binary) neural networks. On the hardware side, RTL development will be supported by simulations and rapid FPGA prototyping. An important milestone of this project is the implementation and the fabrication of improved Ara VP core prototypes using the GLOBALFOUNDERIES 22FDX 22 nm technology, which will showcase the proposed microarchitecture through energy-efficiency measurements. Our Ara VP design and its associated software stack will be open-sourced under a liberal license as part of the CORE-V family of RISC-V processors – derived from the PULP Platform – of the OpenHW group, with the intention of stimulating future open-source hardware collaboration involving Canadian industries and universities. + +Note that unlike other OpenHW Projects, for example the cv32e40p project, it is not the goal of the Core-V-VEC Research Project to produce industrial quality IP. +Rather, this project produces a set of outputs (RTL, research papers, source code, test chip) that could serve as "advanced input" to industrial quality IP projects should OpenHW choose to underake that. + + + + + +### Components of the Research Proposal + +The scope of this project is quite wide and constitutes a number of activities that for an industrial quality project, might be treated as independent projects. +The current intent is to manage this research project as one OpenHW project, and consider in future splitting into separate "industrialization" projects. + + +T1. Setting up the PULP Platform environment to support the development of the Ara VP: +T2. Emulating the Ara VP on FPGA: +T3. Benchmarking the Ara VP +T4. Supporting the most recent RISC-V “V” vector ISA extension [7]: +T5. Improving the energy efficiency of the Ara VP via autonomous memory subsystems +T6. Extending Ara to support low-precision ISA extensions: +T7. Providing software support for the Ara VP +T8. Implementing the Ara VP in the GF 22FDX ASIC technology + +### Summary of Timeline + +The Research Proposal provides a detailed schedule for each person working on it. Essentially this is a 2 year project with activities broken out into 4 month chunks. The starting date is January 2021. + +![Image of Research Proposal Timeline] +(https://github.com/openhwgroup/core-v-docs/blob/master/program/images/VEC%20schedule.png) + +Source: Presentation of Hugh Pollitt-Smith, CMC + +## OpenHW Members/Participants committed to participate + +The Research Proposal names 6 interns who are doing the work of the project. +The project funding (for the interns) is provided by CMC Microsystems and Mitacs on an approximately equal basis. Note that this is the first example of the OpenHW Accelerate Program, which brings together academic, peer-reviewed research funding from Mitacs and other OpenHW members. + + +## Technical Project Leader(s) (TPLs) +Frank Gurkaynak, ETH Zurich Professor +Mickael Fiorentino, Polytechnique Montreal, Post-Doctoral Fellow and project intern + + +## Project Manager (PM) +Hugh Politt Smith, CMC + + +## Project Documents +See list of project outputs below. A specific set of documents is not as yet itemized. + +## Summary of requirements +These technical requirements are driving the Ara coprocessor. + +Applications: +- High-throughput multi-dimensional digital signal processing. For example, sensor fusion, e.g. aggregation of automotive sensor data. +- Machine learning (ML) algorithms under real-time constrain +- IoT to High Performance Computing (HPC) +- Highly efficient way of exploiting data parallelism in scientific and matrix-oriented computations + +Specific requirements to be addressed: +- Extreme energy efficiency for vector arithmetic +- Specific focus on energy efficiency for low-precision operands +- Update Ara to support version 0.9 of the RISC-V "V" extension + +## Explanation of why OpenHW should do this project +OpenHW through its members is developing a full ecosystem around the Core-V cores and related IP and tooling. The external Vector processor is one of several industry approaches for acceleration of vector-math intensive applications. It will be an important part of the OpenHW Core-V ecosystem. +This is the lead project for OpenHW's Accelerate program and will pave the way for future industry-academic collaboration projects within the OpenHW ecosystem. + +## Industry landscape: description of competing, alternative, or related efforts in the industry +Check paper reference [14] for potential description of alternative approaches + +## External dependencies +Leave open for now + +## List of project outputs + +(1) Open source RTL code +(2) Open source code for software ecosystem (RISC-V assembly, c/c++, python) +(3) ASIC implementatoin, EDA scripts, tape-out, characterization in GF 22FDX technology +(4) FPGA emulation targeting CMC-supported boards +(5) Technical documentation and training materials +(6) Mitacs final report +(7) Student PhD/MSc theses, conference and journal papers +(8) Test chips and demonstration boards + + +## TGs Impacted/Resource requirements + +The primary TG that will have oversight is the to-be-formed University Outeach Task Group. +Although the project scope includes activities carried out in SW, Cores, Verification, and HW, those TG will not have direct oversight as this is not an industrialization project. +On the other hand, there will be some involvement of processes from these groups, for example verification framework, and the project is expected to provide updates to the relevant TG as work progresses. + +### University Outreach Task Group (under MWG) +The project manager of this OpenHW group is expected to report the overall progress, issues, roadblocks, and changes to the UOTG + + + +## OpenHW engineering staff resource plan: requirement and availability +## Engineering resource supplied by members - requirement and availability + +The interns driving the work, under the funding model described above, are identified in the Research Proposal. + +## OpenHW marketing resource - requirement and availability +## Marketing resource supplied by members - requirement and availability +## Funding supplied by OpenHW - requirement and availability +## Funding supplied by members - requirement and availability + +Already described above + +## Architecture diagram + + +![Image of Ara architecture] +(https://github.com/DBees/core-v-docs/blob/master/program/images/ARA%20block%20diagram.png) + +Screenshot From M. Cavalcante, F. Schuiki, F. Zaruba, M. Schaffner, and L. Benini, “Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI,” IEEE Trans. Very Large Scale Integr. VLSI Syst., vol. 28, no. 2, pp. 530–543, Feb. 2020, doi: 10.1109/TVLSI.2019.2950087. + + +## Who would make use of OpenHW output + +(i) Academic community + +(ii) OpenHW members may industrialize within OpenHW + +(iii) Any industry members may take the results privately and advance further + +## Project license model +Expectation +- existing license model for Ara at the moment and going forward under SHL 2.0 - need to verify +- sw work Apache 2.0 +- Not expected to be run as Eclipse project, but should be treated under OpenHW/Eclipse IP process +- verify MCCA status of key participants + +## Description of initial code contribution, if required +Need reference to the current state of the Ara code and repository + +## Repository Structure +An OpenHW GitHub Repository will be used for the Ara coprocessor as it evolves. The point at which, and mechanism for which the Ara code is transferred from ETHZ to OpenHW is not yet defined. + +## Project distribution model +Not yet defined + +## Preliminary Project plan + Project Manager is tasked with creating a project plan for the PL gate \ No newline at end of file diff --git a/program/Project-Descriptions-and-Plans/CV-X-IF/CV_X_Interface_project_concept.pdf b/Project-Descriptions-and-Plans/CV-X-IF/CV_X_Interface_project_concept.pdf similarity index 100% rename from program/Project-Descriptions-and-Plans/CV-X-IF/CV_X_Interface_project_concept.pdf rename to Project-Descriptions-and-Plans/CV-X-IF/CV_X_Interface_project_concept.pdf diff --git a/program/Project-Descriptions-and-Plans/CV-X-IF/CV_X_Interface_project_launch.pdf b/Project-Descriptions-and-Plans/CV-X-IF/CV_X_Interface_project_launch.pdf similarity index 100% rename from program/Project-Descriptions-and-Plans/CV-X-IF/CV_X_Interface_project_launch.pdf rename to Project-Descriptions-and-Plans/CV-X-IF/CV_X_Interface_project_launch.pdf diff --git a/program/Project-Descriptions-and-Plans/CV-X-IF/TWG-2021-06-28_cvxif.pptx b/Project-Descriptions-and-Plans/CV-X-IF/TWG-2021-06-28_cvxif.pptx similarity index 100% rename from program/Project-Descriptions-and-Plans/CV-X-IF/TWG-2021-06-28_cvxif.pptx rename to Project-Descriptions-and-Plans/CV-X-IF/TWG-2021-06-28_cvxif.pptx diff --git a/program/Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-Project-Concept-June-28-2021.pptx b/Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-Project-Concept-June-28-2021.pptx similarity index 100% rename from program/Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-Project-Concept-June-28-2021.pptx rename to Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-Project-Concept-June-28-2021.pptx diff --git a/program/Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-Project-Launch-Nov-22-2021.pptx b/Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-Project-Launch-Nov-22-2021.pptx similarity index 100% rename from program/Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-Project-Launch-Nov-22-2021.pptx rename to Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-Project-Launch-Nov-22-2021.pptx diff --git a/program/Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-preliminary-project-proposal.md b/Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-preliminary-project-proposal.md similarity index 98% rename from program/Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-preliminary-project-proposal.md rename to Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-preliminary-project-proposal.md index 8e0a238a6..21a825e3e 100644 --- a/program/Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-preliminary-project-proposal.md +++ b/Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-preliminary-project-proposal.md @@ -1,131 +1,131 @@ - -# OpenHW Preliminary Project Proposal: CV32E40P Second RTL Freeze (v2) - -## Summary of project - -This proposal is for a second RTL freeze or release of the CV32E40P, henceforth referred to as CV32E40Pv2. This release may include verification of additional parameter options, bug fixes, re-enabled RTL and/or new RTL and additional verification as required. This release should not remove features or otherwise break compatibility with the previous RTL freeze. Such changes should be reserved for the CV32E40 or a fork/variant. - -During initial development of the CV32E40P, some features were disabled, skipped, implemented in a minimal fashion or inadequately verified. Most notably, the PULP instructions were removed via a parameter. This was due to insufficient toolchain support and verification. The original intent of the CV32E40P is to include these PULP instructions as described in the [CV32E40* Features and Parameters](https://github.com/openhwgroup/core-v-docs/blob/master/cores/cv32e40p/CV32E40P_and%20CV32E40_Features_Parameters.pdf). - -What follows is a description of the different work items to be included in the CV32E40Pv2. - -### Add Selected PULP Extensions (Verification) - -These are the existing PULP instructions minus the bit manipulation (superseded by the draft B Extension) and SIMD (superseded by the draft P Extension). - -* Hardware loop (`Xcorevhwl`) -* Multiply accumulate (`Xcorevmac`) -* Post-increment and register-indexed load/store (`Xcorevpostinc`) -* Direct branches (`Xcorevbi`) -* General ALU operations (`Xvorevalu`) - -These instructions generally improve the power/performance point as well as reduce code size in selected applications, producing a core with compelling open source advantages. - -### Instruction Encoding (OPCODE) changes to align with RISC-V standard (RTL and Verification) - -As described in issue [#452](https://github.com/openhwgroup/cv32e40p/issues/452), the RTL needs to be updated to match RISC-V standard. Without correcting the instruction encodings to fit within the custom space defined by the RISC-V standard, the toolchain can't be completed, upstreamed and maintained. - -### Conversion to Draft Standard Extensions (RTL and Verification) - -The bit manipulation and SIMD PULP instructions are to be superseded by the draft B and P extensions respectively. Due to the overlap with the draft standard extensions as well as resource constraints, the CORE-V GNU compiler toolchain will not support these instructions. Without toolchain support these instructions cannot be verified or used by software. Due to the instruction encoding differences the PULP instructions in CV32E40Pv2 will not be binary compatible or supported by the existing PULP toolchain and therefore will not be usable for existing PULP users. - -For these reasons the existing instructions will be updated or replaced with draft standard compliant variants. This approach will keep the bit manipulation and SIMD features in the CV32E40P, albeit in a different form. Switching to the draft standard extension instructions will allow OpenHW to leverage existing toolchain support and modeling software for verification. - -#### Bit Manipulation (more important) -Can be useful for e.g. cryptographic application - -#### SIMD -Can be useful for signal processing - -### Debug Trigger Enhancement (RTL and Verification) - -Current debug trigger (hardware breakpoint) implementation only supports a single instruction breakpoint. The RISC-V Debug Specification provides a richer set of features like multiple breakpoints, data related breakpoints, etc. - -The debug trigger implementation should be extended with the following additional features: -* Parameterizable number of breakpoints (such as 2 or 4 instead of 1) -* Load/store address breakpoints (break when you access a certain memory address with a load/store instruction) -* Option to configure the triggers to throw an exception instead of halting the core - -#### Debug Module (Documentation, RTL and Verification) - -The CV32E40P supports a a debug request input to place the core into debug mode. The scope of the CV32E40P v2 could be expanded to include a Debug Module compliant with the RISC-V debug specification (v0.13.1 or higher). -An obvious source for such a DM is the [PULP RISCV-dbg](https://github.com/pulp-platform/riscv-dbg) project. Other implementation options are also available dependent upon member interest and contributions. - -The DM could be tighly integrated into CV32E40P v2 or loosely coupled. - -### FPU (RTL, Verification, Documentation) - -The CV32E40P has RTL to instantiate the FPU from the `fpnew` project from ETH. This project remains in the ETH GitHub. It is an implementation of the RISC-V standard FPU extension specification (F extension). It is not supported in the current version of the CV32E40P. The RTL may have become stale; however, the majority of the work will be in the verification and documentation. - -### Summary of Timeline - -To be checked - -## OpenHW Members/Participants committed to participate in CV32E40Pv2 project - -EM Microelectronic - -## Technical Project Leader(s) (TPLs) - -## Project Manager (PM) - -## Project Documents - -## Summary of requirements - -### Introduction - -### Initial project requirements - -### Future enhancements: - - -## Explanation of why OpenHW should do this project - -## Industry landscape: description of competing, alternative, or related efforts in the industry - -### Related efforts to be described - -## External dependencies - -### Ownership of fpnew - -ETH owns this repository and we have not engaged with them to understand if OpenHW could take over support, to instantiate, fork, etc. - -### Ownership of ETH Debug Module - -ETH owns this repository but it is not active. We have not engaged with them to understand if OpenHW could take over support, to instantiate, fork, etc. - -## List of project outputs - -## TGs Impacted/Resource requirements - -## OpenHW engineering staff resource plan: requirement and availability - -## Engineering resource supplied by members - requirement and availability - -## OpenHW marketing resource - requirement and availability - -## Marketing resource supplied by members - requirement and availability - -## Funding supplied by OpenHW - requirement and availability - -## Funding supplied by members - requirement and availability - -## Architecture diagram - -## Who would make use of OpenHW output - -## Project license model - - -## Description of initial code contribution, if required - -## Repository Structure - -## Project distribution model - -## Preliminary Project plan - -### Risk Register - + +# OpenHW Preliminary Project Proposal: CV32E40P Second RTL Freeze (v2) + +## Summary of project + +This proposal is for a second RTL freeze or release of the CV32E40P, henceforth referred to as CV32E40Pv2. This release may include verification of additional parameter options, bug fixes, re-enabled RTL and/or new RTL and additional verification as required. This release should not remove features or otherwise break compatibility with the previous RTL freeze. Such changes should be reserved for the CV32E40 or a fork/variant. + +During initial development of the CV32E40P, some features were disabled, skipped, implemented in a minimal fashion or inadequately verified. Most notably, the PULP instructions were removed via a parameter. This was due to insufficient toolchain support and verification. The original intent of the CV32E40P is to include these PULP instructions as described in the [CV32E40* Features and Parameters](https://github.com/openhwgroup/core-v-docs/blob/master/cores/cv32e40p/CV32E40P_and%20CV32E40_Features_Parameters.pdf). + +What follows is a description of the different work items to be included in the CV32E40Pv2. + +### Add Selected PULP Extensions (Verification) + +These are the existing PULP instructions minus the bit manipulation (superseded by the draft B Extension) and SIMD (superseded by the draft P Extension). + +* Hardware loop (`Xcorevhwl`) +* Multiply accumulate (`Xcorevmac`) +* Post-increment and register-indexed load/store (`Xcorevpostinc`) +* Direct branches (`Xcorevbi`) +* General ALU operations (`Xvorevalu`) + +These instructions generally improve the power/performance point as well as reduce code size in selected applications, producing a core with compelling open source advantages. + +### Instruction Encoding (OPCODE) changes to align with RISC-V standard (RTL and Verification) + +As described in issue [#452](https://github.com/openhwgroup/cv32e40p/issues/452), the RTL needs to be updated to match RISC-V standard. Without correcting the instruction encodings to fit within the custom space defined by the RISC-V standard, the toolchain can't be completed, upstreamed and maintained. + +### Conversion to Draft Standard Extensions (RTL and Verification) + +The bit manipulation and SIMD PULP instructions are to be superseded by the draft B and P extensions respectively. Due to the overlap with the draft standard extensions as well as resource constraints, the CORE-V GNU compiler toolchain will not support these instructions. Without toolchain support these instructions cannot be verified or used by software. Due to the instruction encoding differences the PULP instructions in CV32E40Pv2 will not be binary compatible or supported by the existing PULP toolchain and therefore will not be usable for existing PULP users. + +For these reasons the existing instructions will be updated or replaced with draft standard compliant variants. This approach will keep the bit manipulation and SIMD features in the CV32E40P, albeit in a different form. Switching to the draft standard extension instructions will allow OpenHW to leverage existing toolchain support and modeling software for verification. + +#### Bit Manipulation (more important) +Can be useful for e.g. cryptographic application + +#### SIMD +Can be useful for signal processing + +### Debug Trigger Enhancement (RTL and Verification) + +Current debug trigger (hardware breakpoint) implementation only supports a single instruction breakpoint. The RISC-V Debug Specification provides a richer set of features like multiple breakpoints, data related breakpoints, etc. + +The debug trigger implementation should be extended with the following additional features: +* Parameterizable number of breakpoints (such as 2 or 4 instead of 1) +* Load/store address breakpoints (break when you access a certain memory address with a load/store instruction) +* Option to configure the triggers to throw an exception instead of halting the core + +#### Debug Module (Documentation, RTL and Verification) + +The CV32E40P supports a a debug request input to place the core into debug mode. The scope of the CV32E40P v2 could be expanded to include a Debug Module compliant with the RISC-V debug specification (v0.13.1 or higher). +An obvious source for such a DM is the [PULP RISCV-dbg](https://github.com/pulp-platform/riscv-dbg) project. Other implementation options are also available dependent upon member interest and contributions. + +The DM could be tighly integrated into CV32E40P v2 or loosely coupled. + +### FPU (RTL, Verification, Documentation) + +The CV32E40P has RTL to instantiate the FPU from the `fpnew` project from ETH. This project remains in the ETH GitHub. It is an implementation of the RISC-V standard FPU extension specification (F extension). It is not supported in the current version of the CV32E40P. The RTL may have become stale; however, the majority of the work will be in the verification and documentation. + +### Summary of Timeline + +To be checked + +## OpenHW Members/Participants committed to participate in CV32E40Pv2 project + +EM Microelectronic + +## Technical Project Leader(s) (TPLs) + +## Project Manager (PM) + +## Project Documents + +## Summary of requirements + +### Introduction + +### Initial project requirements + +### Future enhancements: + + +## Explanation of why OpenHW should do this project + +## Industry landscape: description of competing, alternative, or related efforts in the industry + +### Related efforts to be described + +## External dependencies + +### Ownership of fpnew + +ETH owns this repository and we have not engaged with them to understand if OpenHW could take over support, to instantiate, fork, etc. + +### Ownership of ETH Debug Module + +ETH owns this repository but it is not active. We have not engaged with them to understand if OpenHW could take over support, to instantiate, fork, etc. + +## List of project outputs + +## TGs Impacted/Resource requirements + +## OpenHW engineering staff resource plan: requirement and availability + +## Engineering resource supplied by members - requirement and availability + +## OpenHW marketing resource - requirement and availability + +## Marketing resource supplied by members - requirement and availability + +## Funding supplied by OpenHW - requirement and availability + +## Funding supplied by members - requirement and availability + +## Architecture diagram + +## Who would make use of OpenHW output + +## Project license model + + +## Description of initial code contribution, if required + +## Repository Structure + +## Project distribution model + +## Preliminary Project plan + +### Risk Register + diff --git a/program/Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-task-list.xlsx b/Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-task-list.xlsx similarity index 100% rename from program/Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-task-list.xlsx rename to Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-task-list.xlsx diff --git a/program/Project-Descriptions-and-Plans/CV32E40Pv2/Project_Concept_for_CV32E40Pv2_June-28.md b/Project-Descriptions-and-Plans/CV32E40Pv2/Project_Concept_for_CV32E40Pv2_June-28.md similarity index 97% rename from program/Project-Descriptions-and-Plans/CV32E40Pv2/Project_Concept_for_CV32E40Pv2_June-28.md rename to Project-Descriptions-and-Plans/CV32E40Pv2/Project_Concept_for_CV32E40Pv2_June-28.md index d18e7251b..61d3336fb 100644 --- a/program/Project-Descriptions-and-Plans/CV32E40Pv2/Project_Concept_for_CV32E40Pv2_June-28.md +++ b/Project-Descriptions-and-Plans/CV32E40Pv2/Project_Concept_for_CV32E40Pv2_June-28.md @@ -1,202 +1,202 @@ -# OpenHW Project Concept Proposal: CV32E40Pv2 -*The PC proposal introduces the project and explains the market drivers and the "why"* - -# Title of Project - "CV32E40Pv2" -# Project Concept Proposal -## Date of proposal - 2021-06-28 -## Author(s) - Olivier Montfort (Dolphin Design), Pascal Gouedo (Dolphin Design), Yoann Pruvost (Dolphin Design) - -## High Level Summary of project, project components, and deliverables -This proposal is about verifying XPULP, RVF, and Zfinx ISA extensions that were disabled during CV32E40P v1 phase improving performances, power consumption and even code size depending of application programs. - -## Summary of market or input requirements - - - - -### Known market/project requirements at PC gate - -Re-encode in Custom extension and Verify following PULP "basic" instructions: -* Post-increment and register-register indexed load/store -* Hardware loops -* General ALU extensions -* Immediate branch -* Multiply-accumulate - -Re-encode in Custom extension and Verify following PULP instructions: -* Bit manipulation -* SIMD (16 and 8-bit data) -* Event load - -For Multicore cluster area reduction, -* Verify PULP Zfinx? -* or Re-Design (if needed) and Verify Zfinx as described in [zfinx-spec-20210511-0.41](https://github.com/riscv/riscv-zfinx/blob/main/zfinx-spec-20210511-0.41.pdf) -* Make it optional with a parameter? - -Floating Point Unit -* Keep FPU instructions decoding inside the Core and dispatch to APU interface and - Verify RISC-V standard F extension instructions (Zfinx and non-Zfinx) with coupled Core-FPnew? -* or Merge ETH CV-X-IF and only Verify this interface? - -### Potential future design enhancements -* Conversion of PULP Bit Manipulation & SIMD instruction to ratified RISC-V B and P extensions. -* Add Zce extension for further code-size reduction (not required for Multicore cluster). -* Add bus attributes and errors. - -## Who would make use of OpenHW output -Companies needing more performances, less energy consumption or smaller code size for standard control or DSP-like computing applications. - - -## Initial Estimate of Timeline -At Project Concept: -* Preliminary RTL release in 2021 Q4 -* Implementation of the test plan is assumed to be started in July/August 2021 -* Verification is expected to complete in 2022 Q1 - - - -## Explanation of why OpenHW should do this project -* Finalize CV32E40 as originally intended in the [CV32E40 Features and Parameters](https://github.com/openhwgroup/core-v-docs/blob/master/cores/cv32e40p/CV32E40P_and%20CV32E40_Features_Parameters.pdf) to propose a more powerful/optimized version of CV32E40. - - -## Industry landscape: description of competing, alternative, or related efforts in the industry -ARM Cortex M4 - - -## OpenHW Members/Participants committed to participate -* Dolphin Design - Design & Verification - - -## Project Leader(s) -### Technical Project Leader(s) -At of Project Concept, led by -* Pascal Gouedo, Dolphin Design - -### Project Manager, if a PM is designated -None designated - -## Next steps/Investigation towards Project Launch (**PC only**) - -* Verification to be assessed in detail - * Google ISG - * Imperas reference model - * SW GCC toolchain support - -* More granular component breakdown -* Confirmation of Resources -* Confirmation of Schedule -* Initial view of Risk Register -* List of Project Outputs -* Etc. - - - -### Item2 to investigate -Finer grained schedule - - -### Target Date for PL -July TWG (July 26) - - - -
- - -***Part 2, PL fields:*** -*The PL proposal explains the "what". Some of it can be updated directly from the PC proposal* - -# Title of Project - "CORE-V CoresProject XYZ" -# Project Launch Proposal -## Date of proposal - 2021-01-01 -## Author(s) - Joe Smith, Mary Jones - - -## Summary of project - -### Components of the Project - -*Components are major project components or groups of features.* -- *A project may have, for example, 1-10 components.* -- *Components detail the "The what" at high level, not detailed level* -- *Components don't consider timeline.* -- *For example* - - *Component 1 "Compiler changes for standard instructions."* - - *Component 2 "Compiler changes for custom instructions"* - - *Component 3 "Updates to compiler tools".* - -#### Component 1 Description -#### Component 2 Description - - -## Summary of market or input requirements -### Known market/project requirements at PL gate -### Potential future enhancements for future project phases - -## Who would make use of OpenHW output - -## Summary of Timeline -*High level view of timeline, for example timeframe for each component* - -## Explanation of why OpenHW should do this project -*What is the impact of doing/not doing this project on the OpenHW ecosystem. Why is OpenHW best suited to do this project* - -## Industry landscape: description of competing, alternative, or related efforts in the industry - - -## OpenHW Members/Participants committed to participate - - -## Project Leader(s) -### Technical Project Leader(s) -### Project Manager, if a PM is designated - -## Project Documents -### Project Planning Documents -### Project Output Documents - - -## List of project technical outputs -*This is a list of technical artifacts produced by the project* - -### Feature Requirements -*Features are more granular than Components.* -*For SW porting projects, this list serves as the detailed project reference for features* -*For IP Cores or more complext projects, a user manual with requirements specification is produced at the PA gate, which may supercede this list of features* - -#### Feature 1 -#### Feature 2 - - -## External dependencies -*These are external factors on which the project depends, such as external standards ratification, external technology input, etc.* - -## OpenHW TGs Involved -*Which TG will be involved, such as SW, HW, Verification, etc.* - -## Resource Requirements -*This is a list of major resources/people required to implement the project and indication of whether the resources are available* - -### Engineering resource supplied by members - requirement and availability -### OpenHW engineering staff resource plan: requirement and availability -### Marketing resource - requirement and availability -### Funding for project aspects - requirement and availability - -## Architecture and/or context diagrams -*Architecture (internal blocks and interconnections), and context (depiction of the the project content within its operational context), are both encouraged where appropriate to depict functionality to both subject matter experts and to non-experts* - - - -## Project license model - -## Description of initial code contribution, if required - -## Repository Requirements - -## Project distribution model - -## Preliminary Project plan -*A full project plan is not required at PL. A preliminary plan, which can be for instance the schedule for completion of component or feature list, together with responsible resource, should be provided. Full details should be provided at PA gate.* - -## Risk Register -*A list of known risks, for example external dependencies, and any mitigation strategy* +# OpenHW Project Concept Proposal: CV32E40Pv2 +*The PC proposal introduces the project and explains the market drivers and the "why"* + +# Title of Project - "CV32E40Pv2" +# Project Concept Proposal +## Date of proposal - 2021-06-28 +## Author(s) - Olivier Montfort (Dolphin Design), Pascal Gouedo (Dolphin Design), Yoann Pruvost (Dolphin Design) + +## High Level Summary of project, project components, and deliverables +This proposal is about verifying XPULP, RVF, and Zfinx ISA extensions that were disabled during CV32E40P v1 phase improving performances, power consumption and even code size depending of application programs. + +## Summary of market or input requirements + + + + +### Known market/project requirements at PC gate + +Re-encode in Custom extension and Verify following PULP "basic" instructions: +* Post-increment and register-register indexed load/store +* Hardware loops +* General ALU extensions +* Immediate branch +* Multiply-accumulate + +Re-encode in Custom extension and Verify following PULP instructions: +* Bit manipulation +* SIMD (16 and 8-bit data) +* Event load + +For Multicore cluster area reduction, +* Verify PULP Zfinx? +* or Re-Design (if needed) and Verify Zfinx as described in [zfinx-spec-20210511-0.41](https://github.com/riscv/riscv-zfinx/blob/main/zfinx-spec-20210511-0.41.pdf) +* Make it optional with a parameter? + +Floating Point Unit +* Keep FPU instructions decoding inside the Core and dispatch to APU interface and + Verify RISC-V standard F extension instructions (Zfinx and non-Zfinx) with coupled Core-FPnew? +* or Merge ETH CV-X-IF and only Verify this interface? + +### Potential future design enhancements +* Conversion of PULP Bit Manipulation & SIMD instruction to ratified RISC-V B and P extensions. +* Add Zce extension for further code-size reduction (not required for Multicore cluster). +* Add bus attributes and errors. + +## Who would make use of OpenHW output +Companies needing more performances, less energy consumption or smaller code size for standard control or DSP-like computing applications. + + +## Initial Estimate of Timeline +At Project Concept: +* Preliminary RTL release in 2021 Q4 +* Implementation of the test plan is assumed to be started in July/August 2021 +* Verification is expected to complete in 2022 Q1 + + + +## Explanation of why OpenHW should do this project +* Finalize CV32E40 as originally intended in the [CV32E40 Features and Parameters](https://github.com/openhwgroup/core-v-docs/blob/master/cores/cv32e40p/CV32E40P_and%20CV32E40_Features_Parameters.pdf) to propose a more powerful/optimized version of CV32E40. + + +## Industry landscape: description of competing, alternative, or related efforts in the industry +ARM Cortex M4 + + +## OpenHW Members/Participants committed to participate +* Dolphin Design - Design & Verification + + +## Project Leader(s) +### Technical Project Leader(s) +At of Project Concept, led by +* Pascal Gouedo, Dolphin Design + +### Project Manager, if a PM is designated +None designated + +## Next steps/Investigation towards Project Launch (**PC only**) + +* Verification to be assessed in detail + * Google ISG + * Imperas reference model + * SW GCC toolchain support + +* More granular component breakdown +* Confirmation of Resources +* Confirmation of Schedule +* Initial view of Risk Register +* List of Project Outputs +* Etc. + + + +### Item2 to investigate +Finer grained schedule + + +### Target Date for PL +July TWG (July 26) + + + +
+ + +***Part 2, PL fields:*** +*The PL proposal explains the "what". Some of it can be updated directly from the PC proposal* + +# Title of Project - "CORE-V CoresProject XYZ" +# Project Launch Proposal +## Date of proposal - 2021-01-01 +## Author(s) - Joe Smith, Mary Jones + + +## Summary of project + +### Components of the Project + +*Components are major project components or groups of features.* +- *A project may have, for example, 1-10 components.* +- *Components detail the "The what" at high level, not detailed level* +- *Components don't consider timeline.* +- *For example* + - *Component 1 "Compiler changes for standard instructions."* + - *Component 2 "Compiler changes for custom instructions"* + - *Component 3 "Updates to compiler tools".* + +#### Component 1 Description +#### Component 2 Description + + +## Summary of market or input requirements +### Known market/project requirements at PL gate +### Potential future enhancements for future project phases + +## Who would make use of OpenHW output + +## Summary of Timeline +*High level view of timeline, for example timeframe for each component* + +## Explanation of why OpenHW should do this project +*What is the impact of doing/not doing this project on the OpenHW ecosystem. Why is OpenHW best suited to do this project* + +## Industry landscape: description of competing, alternative, or related efforts in the industry + + +## OpenHW Members/Participants committed to participate + + +## Project Leader(s) +### Technical Project Leader(s) +### Project Manager, if a PM is designated + +## Project Documents +### Project Planning Documents +### Project Output Documents + + +## List of project technical outputs +*This is a list of technical artifacts produced by the project* + +### Feature Requirements +*Features are more granular than Components.* +*For SW porting projects, this list serves as the detailed project reference for features* +*For IP Cores or more complext projects, a user manual with requirements specification is produced at the PA gate, which may supercede this list of features* + +#### Feature 1 +#### Feature 2 + + +## External dependencies +*These are external factors on which the project depends, such as external standards ratification, external technology input, etc.* + +## OpenHW TGs Involved +*Which TG will be involved, such as SW, HW, Verification, etc.* + +## Resource Requirements +*This is a list of major resources/people required to implement the project and indication of whether the resources are available* + +### Engineering resource supplied by members - requirement and availability +### OpenHW engineering staff resource plan: requirement and availability +### Marketing resource - requirement and availability +### Funding for project aspects - requirement and availability + +## Architecture and/or context diagrams +*Architecture (internal blocks and interconnections), and context (depiction of the the project content within its operational context), are both encouraged where appropriate to depict functionality to both subject matter experts and to non-experts* + + + +## Project license model + +## Description of initial code contribution, if required + +## Repository Requirements + +## Project distribution model + +## Preliminary Project plan +*A full project plan is not required at PL. A preliminary plan, which can be for instance the schedule for completion of component or feature list, together with responsible resource, should be provided. Full details should be provided at PA gate.* + +## Risk Register +*A list of known risks, for example external dependencies, and any mitigation strategy* diff --git a/program/Project-Descriptions-and-Plans/CV32E40Pv2/Project_Launch_for_CV32E40Pv2_Nov_22_2021.md b/Project-Descriptions-and-Plans/CV32E40Pv2/Project_Launch_for_CV32E40Pv2_Nov_22_2021.md similarity index 97% rename from program/Project-Descriptions-and-Plans/CV32E40Pv2/Project_Launch_for_CV32E40Pv2_Nov_22_2021.md rename to Project-Descriptions-and-Plans/CV32E40Pv2/Project_Launch_for_CV32E40Pv2_Nov_22_2021.md index ba1ad69a0..670768ff0 100644 --- a/program/Project-Descriptions-and-Plans/CV32E40Pv2/Project_Launch_for_CV32E40Pv2_Nov_22_2021.md +++ b/Project-Descriptions-and-Plans/CV32E40Pv2/Project_Launch_for_CV32E40Pv2_Nov_22_2021.md @@ -1,197 +1,197 @@ -# OpenHW Project Launch Proposal: CV32E40Pv2 - -# Title of Project - "CV32E40Pv2" -# Project Launch Proposal -## Date of proposal - 2021-11-22 -## Author(s) - Pascal Gouedo (Dolphin Design), Olivier Montfort (Dolphin Design), Yoann Pruvost (Dolphin Design) - - -## Summary of project -This proposal is about verifying PULP basic instructions disabled during CV32E40Pv1 phase. -The goal of these instructions is to improve performance, power consumption and even code size depending of application programs. - -### Components of the Project - -This project will start from CV32E40P RTL freeze tag cv32e40p_v1.0.0 made in December 10, 2020. - -To be fully compliant with RISC-V ISA, re-encode all PULP instructions in custom-0 to 3 RISC-V extensions (today disseminated in standard extensions) -and verify all re-encoded [PULP instructions](https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst): -* Post-increment and register-register indexed load/store -* Hardware loops -* General ALU extensions -* Immediate branch -* Multiply-accumulate -* Bit manipulation -* SIMD (16 and 8-bit data) -* Event load - -Single Precision Floating Point support -* Keep Floating Point instructions decoding inside the Core and dispatch their execution to APU interface. -* Use ETHZ FPnew as FP execution unit (or FPnew moved to CV-FPU OpenHW Group project?) -* Verify RISC-V F extension instructions with coupled Core-FPnew (in both Zfinx and non-Zfinx modes?) -* Keep it optional with a parameter - -For Multicore cluster area reduction -* Verify PULP Zfinx -* Keep it optional with a parameter to be able to use standard SW toolchain not supporting Zfinx (comment: not mandatory for Dolphin but anyone else?) - -User Manual - -Verification plans and reports - -Implementation reports (PPA) - -#### Component 1 - RTL design - -Same RTL delivery than CV32E40Pv1 but with following parameters settings: -* Support of PULP ISA Extension (incl. custom CSRs and hardware loop, excl. p.elw) - PULP_XPULP = 1 -* Support of PULP Cluster specific features (Event Load, global clock gating,...) - PULP_CLUSTER = 1 -* Optional Support of RISC-V F extension (interfaced via APU interface) - FPU = 0 or 1 -* Optional support of PULP Zfinx if FPU = 1 - PULP_ZFINX = 0 or 1 - -So 3 different configurations will be verified: -* PULP_XPULP = 1, PULP_CLUSTER = 1, FPU = 0 -* PULP_XPULP = 1, PULP_CLUSTER = 1, FPU = 1, PULP_ZFINX = 0 -* PULP_XPULP = 1, PULP_CLUSTER = 1, FPU = 1, PULP_ZFINX = 1 - -#### Component 2 - Documentation -See "Project Documents" section - -## Summary of market or input requirements -### Known market/project requirements at PL gate - - -### Potential future enhancements for future project phases - -## Who would make use of OpenHW output -Companies needing more performances, less power consumption or smaller code size for standard control or DSP-like computing applications. - -## Summary of Timeline -All tasks and their estimated workload are listed in [CV32E40pv2 task list](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-task-list.xlsx). - -Whole project is estimated between 14 and 20 person.months - -With 2 verification and 1 architecture/documentation/design resources, given the project would start in January 2022, RTL freeze and release would be expected end of Q2 2022. - -## Explanation of why OpenHW should do this project -* Finalize CV32E40 as originally intended in the [CV32E40 Features and Parameters](https://github.com/openhwgroup/core-v-docs/blob/master/cores/cv32e40p/CV32E40P_and%20CV32E40_Features_Parameters.pdf) to propose a more powerful/optimized version of CV32E40. - -## Industry landscape: description of competing, alternative, or related efforts in the industry -ARM Cortex M4 - -## OpenHW Members/Participants committed to participate -* Dolphin Design - Design & Verification - -## Project Leader(s) -### Technical Project Leader(s) -* Pascal Gouedo, Dolphin Design - -### Project Manager, if a PM is designated -* Markus Roesch, Dolphin Design - -## Project Documents -### Project Planning Documents -Planning tools will be setup using OpenHW Group recommendations and Dolphin practices (gantt chart using free ganttproject software?, spreadsheet ...). - -### Project Output Documents -1. User Manual -* New encoding for all PULP instructions -* Re-factored FPU chapter with information imported from FPnew documentation -* Integration chapter with additional section about Core + FPU wrapping -2. Verification Architecture (same as CV32E40Pv1) -3. Verification Plans -4. Verification Reports -5. Implementation Reports -* PPA analysis on different technologies and use cases (e.g. either targetting low area or high frequency) - -## List of project technical outputs -* Verified RTL (3 defined configurations?) -* Verification environment including test cases -* Instruction Set Simulator (ISS) -* Documentation (See Project Documents) - -### Feature Requirements -*Features are more granular than Components.* -*For SW porting projects, this list serves as the detailed project reference for features* -*For IP Cores or more complex projects, a user manual with requirements specification is produced at the PA gate, which may supersede this list of features* - -#### Feature 1 -#### Feature 2 - - -## External dependencies -1. SW tooclhain including -* Re-encoded PULP instructions -* PULP Zfinx support -* Floating Point support - -2. Imperas ISS including same features as SW toolchain - -## OpenHW TGs Involved -* Cores TG -* Verification TG -* Software TG - -## Resource Requirements -*This is a list of major resources/people required to implement the project and indication of whether the resources are available* - -### Engineering resource supplied by members - requirement and availability -Dolphin Design -* Pascal Gouedo (architecture/documentation) - xxx % -* Yoann Pruvost (design/documentation) - xxx % -* (design) - xxx % -* Yoann Pruvost (verification lead) - xxx % -* (verification) - 100 % -* (verification) - 100 % - -### OpenHW engineering staff resource plan: requirement and availability -* Davide Schiavone - Technical support -* Mike Thompson - Verification environment lead and Technical support - -### Marketing resource - requirement and availability -### Funding for project aspects - requirement and availability - -## Architecture and/or context diagrams -*Architecture (internal blocks and interconnections), and context (depiction of the the project content within its operational context), are both encouraged where appropriate to depict functionality to both subject matter experts and to non-experts* - -## Project license model - -Solderpad License, Version 2.0 - -## Description of initial code contribution, if required - -Core RTL -* Initial code contribution is from the existing CV32E40Pv1 release already approved by the IP team. -* Does PULP instructions and Features need to be reviwed by IP Team? -FPU RTL -* Initial FPU code contribution is from the existing ETHZ FPnew RTL. -* Does it need to be reviewed by IP Team? - -Verification based on core-v-verif uvm environment. - -## Repository Requirements -* Design and Documentation will use https://github.com/openhwgroup/cv32e40p -* Verification and Reports will use https://github.com/openhwgroup/core-v-verif - -## Project distribution model -* OpenHW GitHub Repository - -## Preliminary Project plan -*A full project plan is not required at PL. A preliminary plan, which can be for instance the schedule for completion of component or feature list, together with responsible resource, should be provided. Full details should be provided at PA gate.* - -## Plan toward PA gate -When are the planned milestones? -* PA – Plan approved – a fully detailed project plan and an agreed requirements specification as component of the User Manual -e/o Q4 2021 - -* PF – Project Freeze – Code released, all project checklists completed , and project completed -e/o Q2 2022 - -## Risk Register -* Avaibility of SW toolchain supporting all PULP instructions and PULP Zfinx -* Avaibility of ISS supporting all PULP instructions and PULP Zfinx -* Avaibility of OneSpin RISC-V app supporting Zfinx +# OpenHW Project Launch Proposal: CV32E40Pv2 + +# Title of Project - "CV32E40Pv2" +# Project Launch Proposal +## Date of proposal - 2021-11-22 +## Author(s) - Pascal Gouedo (Dolphin Design), Olivier Montfort (Dolphin Design), Yoann Pruvost (Dolphin Design) + + +## Summary of project +This proposal is about verifying PULP basic instructions disabled during CV32E40Pv1 phase. +The goal of these instructions is to improve performance, power consumption and even code size depending of application programs. + +### Components of the Project + +This project will start from CV32E40P RTL freeze tag cv32e40p_v1.0.0 made in December 10, 2020. + +To be fully compliant with RISC-V ISA, re-encode all PULP instructions in custom-0 to 3 RISC-V extensions (today disseminated in standard extensions) +and verify all re-encoded [PULP instructions](https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst): +* Post-increment and register-register indexed load/store +* Hardware loops +* General ALU extensions +* Immediate branch +* Multiply-accumulate +* Bit manipulation +* SIMD (16 and 8-bit data) +* Event load + +Single Precision Floating Point support +* Keep Floating Point instructions decoding inside the Core and dispatch their execution to APU interface. +* Use ETHZ FPnew as FP execution unit (or FPnew moved to CV-FPU OpenHW Group project?) +* Verify RISC-V F extension instructions with coupled Core-FPnew (in both Zfinx and non-Zfinx modes?) +* Keep it optional with a parameter + +For Multicore cluster area reduction +* Verify PULP Zfinx +* Keep it optional with a parameter to be able to use standard SW toolchain not supporting Zfinx (comment: not mandatory for Dolphin but anyone else?) + +User Manual + +Verification plans and reports + +Implementation reports (PPA) + +#### Component 1 - RTL design + +Same RTL delivery than CV32E40Pv1 but with following parameters settings: +* Support of PULP ISA Extension (incl. custom CSRs and hardware loop, excl. p.elw) + PULP_XPULP = 1 +* Support of PULP Cluster specific features (Event Load, global clock gating,...) + PULP_CLUSTER = 1 +* Optional Support of RISC-V F extension (interfaced via APU interface) + FPU = 0 or 1 +* Optional support of PULP Zfinx if FPU = 1 + PULP_ZFINX = 0 or 1 + +So 3 different configurations will be verified: +* PULP_XPULP = 1, PULP_CLUSTER = 1, FPU = 0 +* PULP_XPULP = 1, PULP_CLUSTER = 1, FPU = 1, PULP_ZFINX = 0 +* PULP_XPULP = 1, PULP_CLUSTER = 1, FPU = 1, PULP_ZFINX = 1 + +#### Component 2 - Documentation +See "Project Documents" section + +## Summary of market or input requirements +### Known market/project requirements at PL gate + + +### Potential future enhancements for future project phases + +## Who would make use of OpenHW output +Companies needing more performances, less power consumption or smaller code size for standard control or DSP-like computing applications. + +## Summary of Timeline +All tasks and their estimated workload are listed in [CV32E40pv2 task list](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-task-list.xlsx). + +Whole project is estimated between 14 and 20 person.months + +With 2 verification and 1 architecture/documentation/design resources, given the project would start in January 2022, RTL freeze and release would be expected end of Q2 2022. + +## Explanation of why OpenHW should do this project +* Finalize CV32E40 as originally intended in the [CV32E40 Features and Parameters](https://github.com/openhwgroup/core-v-docs/blob/master/cores/cv32e40p/CV32E40P_and%20CV32E40_Features_Parameters.pdf) to propose a more powerful/optimized version of CV32E40. + +## Industry landscape: description of competing, alternative, or related efforts in the industry +ARM Cortex M4 + +## OpenHW Members/Participants committed to participate +* Dolphin Design - Design & Verification + +## Project Leader(s) +### Technical Project Leader(s) +* Pascal Gouedo, Dolphin Design + +### Project Manager, if a PM is designated +* Markus Roesch, Dolphin Design + +## Project Documents +### Project Planning Documents +Planning tools will be setup using OpenHW Group recommendations and Dolphin practices (gantt chart using free ganttproject software?, spreadsheet ...). + +### Project Output Documents +1. User Manual +* New encoding for all PULP instructions +* Re-factored FPU chapter with information imported from FPnew documentation +* Integration chapter with additional section about Core + FPU wrapping +2. Verification Architecture (same as CV32E40Pv1) +3. Verification Plans +4. Verification Reports +5. Implementation Reports +* PPA analysis on different technologies and use cases (e.g. either targetting low area or high frequency) + +## List of project technical outputs +* Verified RTL (3 defined configurations?) +* Verification environment including test cases +* Instruction Set Simulator (ISS) +* Documentation (See Project Documents) + +### Feature Requirements +*Features are more granular than Components.* +*For SW porting projects, this list serves as the detailed project reference for features* +*For IP Cores or more complex projects, a user manual with requirements specification is produced at the PA gate, which may supersede this list of features* + +#### Feature 1 +#### Feature 2 + + +## External dependencies +1. SW tooclhain including +* Re-encoded PULP instructions +* PULP Zfinx support +* Floating Point support + +2. Imperas ISS including same features as SW toolchain + +## OpenHW TGs Involved +* Cores TG +* Verification TG +* Software TG + +## Resource Requirements +*This is a list of major resources/people required to implement the project and indication of whether the resources are available* + +### Engineering resource supplied by members - requirement and availability +Dolphin Design +* Pascal Gouedo (architecture/documentation) - xxx % +* Yoann Pruvost (design/documentation) - xxx % +* (design) - xxx % +* Yoann Pruvost (verification lead) - xxx % +* (verification) - 100 % +* (verification) - 100 % + +### OpenHW engineering staff resource plan: requirement and availability +* Davide Schiavone - Technical support +* Mike Thompson - Verification environment lead and Technical support + +### Marketing resource - requirement and availability +### Funding for project aspects - requirement and availability + +## Architecture and/or context diagrams +*Architecture (internal blocks and interconnections), and context (depiction of the the project content within its operational context), are both encouraged where appropriate to depict functionality to both subject matter experts and to non-experts* + +## Project license model + +Solderpad License, Version 2.0 + +## Description of initial code contribution, if required + +Core RTL +* Initial code contribution is from the existing CV32E40Pv1 release already approved by the IP team. +* Does PULP instructions and Features need to be reviwed by IP Team? +FPU RTL +* Initial FPU code contribution is from the existing ETHZ FPnew RTL. +* Does it need to be reviewed by IP Team? + +Verification based on core-v-verif uvm environment. + +## Repository Requirements +* Design and Documentation will use https://github.com/openhwgroup/cv32e40p +* Verification and Reports will use https://github.com/openhwgroup/core-v-verif + +## Project distribution model +* OpenHW GitHub Repository + +## Preliminary Project plan +*A full project plan is not required at PL. A preliminary plan, which can be for instance the schedule for completion of component or feature list, together with responsible resource, should be provided. Full details should be provided at PA gate.* + +## Plan toward PA gate +When are the planned milestones? +* PA – Plan approved – a fully detailed project plan and an agreed requirements specification as component of the User Manual +e/o Q4 2021 + +* PF – Project Freeze – Code released, all project checklists completed , and project completed +e/o Q2 2022 + +## Risk Register +* Avaibility of SW toolchain supporting all PULP instructions and PULP Zfinx +* Avaibility of ISS supporting all PULP instructions and PULP Zfinx +* Avaibility of OneSpin RISC-V app supporting Zfinx diff --git a/program/Project-Descriptions-and-Plans/CV32E40S/CV32E40S-PPL.md b/Project-Descriptions-and-Plans/CV32E40S/CV32E40S-PPL.md similarity index 100% rename from program/Project-Descriptions-and-Plans/CV32E40S/CV32E40S-PPL.md rename to Project-Descriptions-and-Plans/CV32E40S/CV32E40S-PPL.md diff --git a/program/Project-Descriptions-and-Plans/CV32E40S/CV32E40X_CV32E40S_PA.xlsx b/Project-Descriptions-and-Plans/CV32E40S/CV32E40X_CV32E40S_PA.xlsx similarity index 100% rename from program/Project-Descriptions-and-Plans/CV32E40S/CV32E40X_CV32E40S_PA.xlsx rename to Project-Descriptions-and-Plans/CV32E40S/CV32E40X_CV32E40S_PA.xlsx diff --git a/program/Project-Descriptions-and-Plans/CV32E40S/CV32E40X_CV32E40S_project_plan.pdf b/Project-Descriptions-and-Plans/CV32E40S/CV32E40X_CV32E40S_project_plan.pdf similarity index 100% rename from program/Project-Descriptions-and-Plans/CV32E40S/CV32E40X_CV32E40S_project_plan.pdf rename to Project-Descriptions-and-Plans/CV32E40S/CV32E40X_CV32E40S_project_plan.pdf diff --git a/program/Project-Descriptions-and-Plans/CV32E40X/CV32E40X-PPL.md b/Project-Descriptions-and-Plans/CV32E40X/CV32E40X-PPL.md similarity index 100% rename from program/Project-Descriptions-and-Plans/CV32E40X/CV32E40X-PPL.md rename to Project-Descriptions-and-Plans/CV32E40X/CV32E40X-PPL.md diff --git a/program/Project-Descriptions-and-Plans/CV32E40X/CV32E40X_CV32E40S_PA.xlsx b/Project-Descriptions-and-Plans/CV32E40X/CV32E40X_CV32E40S_PA.xlsx similarity index 100% rename from program/Project-Descriptions-and-Plans/CV32E40X/CV32E40X_CV32E40S_PA.xlsx rename to Project-Descriptions-and-Plans/CV32E40X/CV32E40X_CV32E40S_PA.xlsx diff --git a/program/Project-Descriptions-and-Plans/CV32E40X/CV32E40X_CV32E40S_project_plan.pdf b/Project-Descriptions-and-Plans/CV32E40X/CV32E40X_CV32E40S_project_plan.pdf similarity index 100% rename from program/Project-Descriptions-and-Plans/CV32E40X/CV32E40X_CV32E40S_project_plan.pdf rename to Project-Descriptions-and-Plans/CV32E40X/CV32E40X_CV32E40S_project_plan.pdf diff --git a/program/Project-Descriptions-and-Plans/CV32E41P/CV32E41P-project-proposal.md b/Project-Descriptions-and-Plans/CV32E41P/CV32E41P-project-proposal.md similarity index 100% rename from program/Project-Descriptions-and-Plans/CV32E41P/CV32E41P-project-proposal.md rename to Project-Descriptions-and-Plans/CV32E41P/CV32E41P-project-proposal.md diff --git a/program/Project-Descriptions-and-Plans/CVA6/CVA6-plan-approved-2022.md b/Project-Descriptions-and-Plans/CVA6/CVA6-plan-approved-2022.md similarity index 98% rename from program/Project-Descriptions-and-Plans/CVA6/CVA6-plan-approved-2022.md rename to Project-Descriptions-and-Plans/CVA6/CVA6-plan-approved-2022.md index f1b847478..18fa042f0 100644 --- a/program/Project-Descriptions-and-Plans/CVA6/CVA6-plan-approved-2022.md +++ b/Project-Descriptions-and-Plans/CVA6/CVA6-plan-approved-2022.md @@ -1,388 +1,388 @@ -# OpenHW Project: CVA6 core - -| Gate | Status | -| ------------------------------------ | ---------------------------------------------------------- | -| PC gate: Project Concept | Approved on 2020-09-28 as Preliminary Project Launch (PPL) | -| PL gate: Project Launch | Approved on 2021-01-25 | -| PA gate: Plan Approved | Presented on 2022-02-28 for **2022 workplan**, approved on 2022-03-28 | -| PA gate: Plan Approved | 2023 and beyond workplan in future PA gate | - -Author: Jérôme Quévremont, Thales Research & Technology - -## Summary of project - -The **CVA6** core is a configurable mid-range application RISC-V core able to boot a rich OS like Linux. Its origin is ETH Zürich / University of Bologna's ARIANE core. - -From a single RTL source, several flavors can be configured: 32- or 64-bit architecture (**CV32A6** / **CV64A6**), -with or without FPU, with or without MMU... - -CVA6 targets both **ASIC** and **FPGA soft-core** implementations. - -The ability to have very similar 32- and 64-bit cores should make the transition between both quite seamless. - -The goal of the project is to bring **CVA6** to an industrial maturity known as **TRL5** (technical readiness level): -- Quality documentation -- Add a few features desired by participating members -- High-coverage verification -- Optimizations for FPGA-based products -- SW tools (GCC, GDB, LLVM\*...) -- FPGA prototype and development board -- Linux and FreeRTOS\* support - -\* FreeRTOS and LLVM support are developed in related OpenHW projects. - -In addition to these industrial goals, a sustainable open-source solution, presumably a subset of outputs, will be maintained for researchers, -engineers seeking to evaluate CVA6 and industrial domains that need to support their products for decades. - -### Summary of Timeline - -CVA6 is a long-run project, for which some participants are expecting grants to perform the work needed to reach TRL5. It is therefore difficult to plan the complete project. - -Therefore, in order to keep the project under control, the project plan is defined for **2022 activity**. An update of the plan will be needed beginning of 2023, together with another PA gate. - -## OpenHW Members/Participants committed to participate in CORE-V CVA6 project - -- Thales group: - - Thales Research & Technology (TRT) - - Thales DIS Design Services (INVIA) - - Thales India / Engineering Competence Center (ECC) -- The University of Minho -- ETH Zürich -- U. Bologna (past contribution) - -## Project Leader(s) - -- Project Manager (PM) and Technical project leader (TPL): Jérôme Quévremont, TRT -- Verification leader: Jean-Roch Coulon, INVIA -- FPGA softcore leader: Sébastien Jacq, TRT - -## Project Planning Documents - -The 2022 workplan, based on milestones for various contributions and contributors, is below. - -The progress towards the milestones will be tracked during progress meetings, usually every two weeks. - -## Summary of requirements - -### CVA6 features - -The CVA6 specification has been prepared for the PA gate. -It is temporarily hosted in this [Google Docs file](https://docs.google.com/document/d/11rsoO5WKraMCraSpnsVqmt4hJaCcDG0zq7LTWdXVkf0). -After approval by the TWG, it will be converted to AsciiDoc and managed in OpenHW GitHub. - -As a summary, CVA6 contains: - -| | CV64A6 | CV32A6 | -| :------------------ | :-----------------------------------: | :------------------------------: | -| ISA | RV64IMA\[F\[D\]\]\[C\]_Zicsr_Zifencei | RV32IMA\[F\]\[C\]_Zicsr_Zifencei | -| Privilege levels | M/S/U\* | M/S/U\* | -| Virtual memory | \[Sv39\] | \[Sv32\] | - -\[\] denotes a configurable feature. - -\* In addition, CV64A6 will optionally support RISC-V Hypervisor extension. - -`FENCE.T` is supported and might become a standard RISC-V instruction in the future. - -The **CV-X-IF** interface will allow to extend CVA6 instruction set with an external co-processor. -It will either support proprietary extensions or RISC-V extensions that are not natively supported by CVA6. - -### License scheme - -Because of the nature of its business, Thales expectation is to contribute and get a **sustainable open-source solution** -- to integrate CVA6 in new ASIC and FPGA projects for a long period and to maintain/upgrade them for several decades for industrial domains (avionic, satellite, railways, energy…); -- to permit audit and reviews of verification and tools in the context of certifiable security and functional safety; -- to permit public review to improve the quality of the core and its ecosystem; -- to foster cooperative projects and connections with academy and research. - -Thereforce, Thales expects: -- Not only the core RTL, but also a version of the verification environment and the SW tools are available as open-source. -- Commercial tools can be added to this basic set to deliver additional value (improved quality, coverage...). - - But the project shall not depend on a single-source commercial tool. - - Commercial tools with multiple sources, such as logic simulators, are acceptable. - -In addition, this sustainable open-source solution, lowers barriers for newcomers to OpenHW. They can evaluate CVA6, adopt it, join OpenHW Group, add their "secret sauce"... - -### Verification - -To foster cooperation and efficiency within OpenHW Group, CVA6 will use and contribute to **core-v-verif**. Spike will be used as a reference ISS and Imperas OVPSim is considered too. - -Gateways between OpenHW core-v-verif repositories and Thales internal environment (GitLab, CI...) will be set up. - -## Future enhancements (off project): - -Increasing the core architectural performance (dual issue...), adding RISC-V extensions, delivering a larger subsystem (SMP multi-core, peripherals, accelerators...) - -## Explanation of why OpenHW should do this project - -Like RI5CY, the ARIANE core donated by ETH Zürich and U. Bologna was at the heart of the OpenHW Group creation. We need an application processor core in our portfolio. - -Also, there are very few FPGA technology-independent softcores and CV32A6 is an alternative to proprietary cores. - -## Industry landscape: description of competing, alternative, or related efforts in the industry - -On the core side, for ASIC targets, these are the most comparable competitors (pipeline length, MMU, single issue...): -- ARM: Cortex-A5 -- SiFive: U54 -- CHIPS Alliance / Western Digital: CVA6 between the smaller SweRV EL2 and the larger EH1. -- ANDES: A25 (32-bit) and AX25 (64-bit) -- Gaisler NOEL-V - -On the FPGA side, CV32A6 is a technology-independent alternative to these proprietary cores: -- Xilinx: Microblaze -- MicroChip: Mi-V -- Intel: Nios-II, Nios-V - -On the tool side, CHIPS Alliance has plans to make their tools open-source -([link](https://semiengineering.com/components-for-open-source-verification/), 5th paragraph). - -### Market differentiators - -_This section was initially titled "Related efforts to be described"._ - -To differentiate from the competition, marketing can stress: -- Source code written in SystemVerilog, a widely accepted language; -- Open-source availability of the core; -- Open-source availability of verification artefacts, which is a great step towards certification for security- and safety-critical applications; -- The availability of a family of technology-independent cores optimized for ASIC and FPGA targets; -- The ability to extend the instruction set thanks to the CV-X-IF interface; -- The SW ecosystem running on CVA6, with FreeRTOS and Linux already demonstrated; -- The ability to scale to SMP multi/many-core CPUs thanks to the OpenPiton framework; -- The permissive licence scheme that allows the integration in open-source or closed-source projects or the addition of a "secret sauce"; -- The low exposition to export control -([OpenHW Group Membership Agreement](https://www.openhwgroup.org/membership/openhw-group-membership-agreement-2019-10-16.pdf), section 4.1). - -## External dependencies - -The project relies on: -- Related OpenHW projects (joint with other cores): LLVM, FreeRTOS, core-v-verif, CV-X-IF specification -- Open-source software: GCC, GDB, LLVM, Linux (Yocto, BuildRoot), OpenSBI, UBoot, BBL... -- Open-source verification: Google Riscv-dv, Spike, RISC-V compatibility tests -- Open-source hardware: fpnew (ETH Zürich, soon migrated to OpenHW) -- Eclipse Foundation, GitHub -- Digilent Genesys 2 board -- JADE Design Automation's Register Manager -- Simulators: Verilator (open-source), Siemens Questa, Synopsys VCS, Imperas OVPSim -- Synthesis: Vivado (Xilinx), Synopsys Design Compiler (ASIC) - -CVA6 can be integrated in the OpenPiton framework to build an SMP multi/many-core CPU. - -The RV32F DIV and SQRT simulation sequences will be developed as early as possible so that they can be reused by CV32E40Pv2 project. - -## List of project outputs - -### Documentation: - -The document structure has been defined at the PL gate: -- Specification - - Identifies features agreed upon - - “What” defined as requirements with identifiers - - Some sections are short (references to RISC-V ISA, AXI specs…) -- Users’ guide - - Includes more details than the specification - - For CVA6 integrators and users: HW, SW, ASIC, FPGA… viewpoints -- Design document - - Explains the “How”: design choices… - - Not prescriptive, written during or after the design. - - Useful for next projects. -- Verification Environment Specification - - User manual for the verification environment testbenches, testcases, verification components, etc. - - Description of the testbench structure and theory of operation -- Design Verification Plans - - DVplan, Verification Plan, Vplan: same meaning - - Feature-by-feature listing of the Device Under Test - - and a description of how it will be verified - - and how we know when it is verified (coverage). - -The specification and users' guide are inputs for design verification plans. - -### Design - -- CVA6 configurable RTL source code (TRL5 target) -- Subsystems and FPGA designs, a.k.a. APU, to exercise CVA6 on development boards... - - -### Verification: - -- Versatile generic testbench with adaptation layers for CVA6 - - Subset compliant with _sustainable open-source solution_ expectactions -- Test sequences -- Verification results - - Including code coverage and functional coverage - -### Software: - -- Baremetal BSP for FPGA boards featuring CVA6 -- Linux ports (based on UBoot, OpenSBI and Yocto) -- Toolchains (compiler...) - -LLVM and FreeRTOS are products of related OpenHW projects. - - -## TGs Impacted/Resource requirements - -| | Staff | Members | -| :-------------- | :---: | :-----: | -| Cores TG | X | X | -| Verification TG | X | X | -| SW TG | X | X | - -### OpenHW engineering staff resource plan: requirement and availability - -The OpenHW staff is expected to support the task groups on these missions: -- Mike Thompson on verification -- Florian Zaruba on software and ARIANE knowledge transfer -- Davide Schiavone on core design -- Duncan Bees on project management - -### Engineering resource supplied by members - requirement and availability - -The 2022 workplan below has been prepared according to available members' resources. - -Grants are expected to fuel 2023 workplan with more resources, especially on verification activities. - -### Marketing resource - requirement and availability - -The project needs support from: - -- Rick O'Connor, OpenHW CEO -- Michelle Clancy, Director of Marketing - -to promote CVA6 and attract new participants to the project. - -On the members' side, promotion activities (presentations, demos...) will mainly be addressed by the engineering team. - -Results obtained by the engineering team in 2021 (CV32A6 release, FreeRTOS support, Linux support...) can be used -in 2022 to promote the CVA6 project. - -### Funding for project aspects - requirement and availability - -Some marketing activities (OpenHW TV production...) might need OpenHW funding. - -Participating members provide the necessary tools to their teams. - -## Architecture and/or context diagrams - -![CVA6 pipeline](https://www.allaboutcircuits.com/uploads/articles/Ariane_CPU.jpg) - -## Who would make use of OpenHW output - -Any entity needing a mid-range verified open-source RISC-V application processing core for ASIC and FPGA technologies: -- OpenHW members -- Large and small businesses -- Academy and research -- Future OpenHW projects - -Also refer to the "Market differentiators" section above. - -An open-source project favors collaborative and research projects that can start quickly without commercial and legal burdens. - -## Project license model - -The project artefacts and outputs will be licensed under Apache 2.0 or for SW code and Solderpad 2.0 or 2.1 for HW/RTL codes. - -Third-party open-source contributions will generally retain their own licence model. - -"Viral" licences, such as GPL, will be avoided. - -OVPSim licences will be provided by Imperas. - -## Description of initial code contribution, if required - -Contributions before or off the project: -- ARIANE (CV64A6) and debug, ETH Zürich and University of Bologna -- CV32A6 bare mode, INVIA -- `FENCE.T`, Hensoldt Cyber/ETH Zürich -- CV64A6 Hypervisor extension, University of Minho -- ASIC PPA assessment, INVIA -- FPGA PPA assessment, TRT - -## Repository Structure - -https://github.com/openhwgroup/cva6: the core master directory
-/core: the CVA6 core (defined as the scope of the IP in the specification and targetting 100% coverage)
-/corev_apu: the computing subsystem comprising CVA6
-/docs: CVA6 documents (specification, users' guide...) - -https://github.com/openhwgroup/core-v-verif: the verification home
-/cva6: specific files for the core - -https://github.com/openhwgroup/cva6-sdk: RISC-V tools and Linux - -https://github.com/openhwgroup/core-v-docs/tree/master/program/Project%20Descriptions%20and%20Plans/CVA6: project gates. - -In addition, Thales has set up an internal mirror of GitHub repositories to trigger their countinuous integration environment. - -## Project distribution model - -OpenHW GitHub repository - -## Project plan - -### 2021 contributions (between the PL and PA gates) - -- CVA6 specification, joint work -- CV32A6 MMU and debug, TRT -- Complete CV32A6 release -- Continuous integration environment, INVIA -- Operational Linux 1 (BBL, Buildroot), TRT -- Operational Linux 2 (U-Boot, OpenSBI, Buildroot), TRT -- Operational FreeRTOS, ECC -- Embench-IoT benchmarks, ICP/stall analysis environment, U. Bologna -- Various contributions (bug fixes, documentation...) - -### 2022 workplan - -A waterfall method is used. - -| Related TG | Milestone | Target | Contributor | -| --------------- | ------------------------------------------------------------------------------------------------------------------------------ | ------------- | ----------- | -| Core | +50% frequency and -50% FPGA resource used for the CV32A6 soft-core | 2022-09-30 | TRT | -| Core | Implementation gap: CSR fixes: performance counters size... | 2022-10-31 | ECC | -| Core | Implementation gap: Footprint optimisation of performance counters | 2022-10-31 | ECC | -| Core | L1D feature to support datasize extension to store EDC, ECC or other information. | 2022-12-31 | ECC | -| Core | invalidate L1WTD content with the FENCE.T command. | TBD | ECC? | -| Core | Feature to transform cache ways into a scratchpad | 2022-12-31 | ECC | -| Core | L1I feature to support datasize extension to store EDC, ECC or other information | 2022-12-31 | ECC | -| Core | Add H extension as an option to CV64A6 | 2022-07-31 | U. Minho | -| Core | Add custom temporal fence (`fence.t`) instruction on CV64A6 and CV32A6 | 2022-05-31 | ETH | -| Software | Linux Yocto up and running on CVA6 | 2022-06-30 | TRT | -| Verification | Trigger Thales CI from github/openhwgroup repository and maintain it | 2022-03-31 | INVIA | -| Verification | CV-X-IF: VPlan, coprocessor UVM agent and verification | 2022-06-30 | INVIA | -| Verification | CV32E4\* verification environment reuse | 2022-12-31 | INVIA | -| Verification | First verification steps: RV32F DIV and SQRT simulation in CVA6 DV environment (to be reused by CVE40Pv2) | 2022-12-31 | ECC | -| Verification | Implementation and execution of Virtual Peripheral | 2022-09-30 | ECC | -| Verification | Add riscv-arch-test suite to existing CVA6 core-v-verif CI (32-bit and 64-bit) | 2022-06-30 | ECC | -| Project-wide | Raise a CQ (Eclipse contribution questionnaire) | 2022-06-30 | Jérôme, Mike | -| Verification | CVA6 complete verification pending new grants | 2023 activity | INVIA | -| | _For information:_ | | | -| Related project | FreeRTOS developments - maturing the boot sequence, driver eco-system for peripherals, synchronize with SW TG and MCU FreeRTOS | 2022-10-31 | ECC | -| Off project | Keystone FreeRTOS integration on RISC-V hardware (IBEX, CVA6 etc.), synchronize with SW TG and MCU FreeRTOS | 2022-12-31 | ECC | -| Off project | TensorflowLite deployment on Linux CVA6 | 2022-12-31 | ECC | - -### Project tracking and meetings - -The progress towards 2022 milestones will be tracked in progress meetings. Slides will be updated during the meeting and posted on CVA6 Mattermost channel. - -The various activities (core, verification, software) are led in a unified project way and reported to the relevant task groups. - -The CVA6 meets every week, alternating progress and technical meetings. -The meetings are well suited for East Coast, Europe and India timezones. Once a month, the meeting starts later to accomodate participants from the West Coast. - -### Oustanding topics - -These topics will be defined in CVA6 meetings at the relevant time: -- Overall approach for Github issues and label - -No release plan is defined in 2022 as this PA gate is interim. -No Project Freeze (PF) checklist is planned in 2022. - -### Risk register - -| | Likelihood | Impact | Avoidance / Mitigation | -| ------------------------- | :--------: | :----: | ----------------------------------------------------------------------------- | -| Not enough resources | High | Major | The current team is expecting grants ; more participants welcome | -| Insufficient coordination | Mid | Mid | Weekly meetings | -| Conflicting contributions | Mid | Major | Weekly meetings | -| Export control | Low | Major | Apply OpenHW membership agreement (carefully review non-OpenHW contributions) | -| Lack of market appeal | Mid | Major | Increase CVA6 promotion based on intermediate results | +# OpenHW Project: CVA6 core + +| Gate | Status | +| ------------------------------------ | ---------------------------------------------------------- | +| PC gate: Project Concept | Approved on 2020-09-28 as Preliminary Project Launch (PPL) | +| PL gate: Project Launch | Approved on 2021-01-25 | +| PA gate: Plan Approved | Presented on 2022-02-28 for **2022 workplan**, approved on 2022-03-28 | +| PA gate: Plan Approved | 2023 and beyond workplan in future PA gate | + +Author: Jérôme Quévremont, Thales Research & Technology + +## Summary of project + +The **CVA6** core is a configurable mid-range application RISC-V core able to boot a rich OS like Linux. Its origin is ETH Zürich / University of Bologna's ARIANE core. + +From a single RTL source, several flavors can be configured: 32- or 64-bit architecture (**CV32A6** / **CV64A6**), +with or without FPU, with or without MMU... + +CVA6 targets both **ASIC** and **FPGA soft-core** implementations. + +The ability to have very similar 32- and 64-bit cores should make the transition between both quite seamless. + +The goal of the project is to bring **CVA6** to an industrial maturity known as **TRL5** (technical readiness level): +- Quality documentation +- Add a few features desired by participating members +- High-coverage verification +- Optimizations for FPGA-based products +- SW tools (GCC, GDB, LLVM\*...) +- FPGA prototype and development board +- Linux and FreeRTOS\* support + +\* FreeRTOS and LLVM support are developed in related OpenHW projects. + +In addition to these industrial goals, a sustainable open-source solution, presumably a subset of outputs, will be maintained for researchers, +engineers seeking to evaluate CVA6 and industrial domains that need to support their products for decades. + +### Summary of Timeline + +CVA6 is a long-run project, for which some participants are expecting grants to perform the work needed to reach TRL5. It is therefore difficult to plan the complete project. + +Therefore, in order to keep the project under control, the project plan is defined for **2022 activity**. An update of the plan will be needed beginning of 2023, together with another PA gate. + +## OpenHW Members/Participants committed to participate in CORE-V CVA6 project + +- Thales group: + - Thales Research & Technology (TRT) + - Thales DIS Design Services (INVIA) + - Thales India / Engineering Competence Center (ECC) +- The University of Minho +- ETH Zürich +- U. Bologna (past contribution) + +## Project Leader(s) + +- Project Manager (PM) and Technical project leader (TPL): Jérôme Quévremont, TRT +- Verification leader: Jean-Roch Coulon, INVIA +- FPGA softcore leader: Sébastien Jacq, TRT + +## Project Planning Documents + +The 2022 workplan, based on milestones for various contributions and contributors, is below. + +The progress towards the milestones will be tracked during progress meetings, usually every two weeks. + +## Summary of requirements + +### CVA6 features + +The CVA6 specification has been prepared for the PA gate. +It is temporarily hosted in this [Google Docs file](https://docs.google.com/document/d/11rsoO5WKraMCraSpnsVqmt4hJaCcDG0zq7LTWdXVkf0). +After approval by the TWG, it will be converted to AsciiDoc and managed in OpenHW GitHub. + +As a summary, CVA6 contains: + +| | CV64A6 | CV32A6 | +| :------------------ | :-----------------------------------: | :------------------------------: | +| ISA | RV64IMA\[F\[D\]\]\[C\]_Zicsr_Zifencei | RV32IMA\[F\]\[C\]_Zicsr_Zifencei | +| Privilege levels | M/S/U\* | M/S/U\* | +| Virtual memory | \[Sv39\] | \[Sv32\] | + +\[\] denotes a configurable feature. + +\* In addition, CV64A6 will optionally support RISC-V Hypervisor extension. + +`FENCE.T` is supported and might become a standard RISC-V instruction in the future. + +The **CV-X-IF** interface will allow to extend CVA6 instruction set with an external co-processor. +It will either support proprietary extensions or RISC-V extensions that are not natively supported by CVA6. + +### License scheme + +Because of the nature of its business, Thales expectation is to contribute and get a **sustainable open-source solution** +- to integrate CVA6 in new ASIC and FPGA projects for a long period and to maintain/upgrade them for several decades for industrial domains (avionic, satellite, railways, energy…); +- to permit audit and reviews of verification and tools in the context of certifiable security and functional safety; +- to permit public review to improve the quality of the core and its ecosystem; +- to foster cooperative projects and connections with academy and research. + +Thereforce, Thales expects: +- Not only the core RTL, but also a version of the verification environment and the SW tools are available as open-source. +- Commercial tools can be added to this basic set to deliver additional value (improved quality, coverage...). + - But the project shall not depend on a single-source commercial tool. + - Commercial tools with multiple sources, such as logic simulators, are acceptable. + +In addition, this sustainable open-source solution, lowers barriers for newcomers to OpenHW. They can evaluate CVA6, adopt it, join OpenHW Group, add their "secret sauce"... + +### Verification + +To foster cooperation and efficiency within OpenHW Group, CVA6 will use and contribute to **core-v-verif**. Spike will be used as a reference ISS and Imperas OVPSim is considered too. + +Gateways between OpenHW core-v-verif repositories and Thales internal environment (GitLab, CI...) will be set up. + +## Future enhancements (off project): + +Increasing the core architectural performance (dual issue...), adding RISC-V extensions, delivering a larger subsystem (SMP multi-core, peripherals, accelerators...) + +## Explanation of why OpenHW should do this project + +Like RI5CY, the ARIANE core donated by ETH Zürich and U. Bologna was at the heart of the OpenHW Group creation. We need an application processor core in our portfolio. + +Also, there are very few FPGA technology-independent softcores and CV32A6 is an alternative to proprietary cores. + +## Industry landscape: description of competing, alternative, or related efforts in the industry + +On the core side, for ASIC targets, these are the most comparable competitors (pipeline length, MMU, single issue...): +- ARM: Cortex-A5 +- SiFive: U54 +- CHIPS Alliance / Western Digital: CVA6 between the smaller SweRV EL2 and the larger EH1. +- ANDES: A25 (32-bit) and AX25 (64-bit) +- Gaisler NOEL-V + +On the FPGA side, CV32A6 is a technology-independent alternative to these proprietary cores: +- Xilinx: Microblaze +- MicroChip: Mi-V +- Intel: Nios-II, Nios-V + +On the tool side, CHIPS Alliance has plans to make their tools open-source +([link](https://semiengineering.com/components-for-open-source-verification/), 5th paragraph). + +### Market differentiators + +_This section was initially titled "Related efforts to be described"._ + +To differentiate from the competition, marketing can stress: +- Source code written in SystemVerilog, a widely accepted language; +- Open-source availability of the core; +- Open-source availability of verification artefacts, which is a great step towards certification for security- and safety-critical applications; +- The availability of a family of technology-independent cores optimized for ASIC and FPGA targets; +- The ability to extend the instruction set thanks to the CV-X-IF interface; +- The SW ecosystem running on CVA6, with FreeRTOS and Linux already demonstrated; +- The ability to scale to SMP multi/many-core CPUs thanks to the OpenPiton framework; +- The permissive licence scheme that allows the integration in open-source or closed-source projects or the addition of a "secret sauce"; +- The low exposition to export control +([OpenHW Group Membership Agreement](https://www.openhwgroup.org/membership/openhw-group-membership-agreement-2019-10-16.pdf), section 4.1). + +## External dependencies + +The project relies on: +- Related OpenHW projects (joint with other cores): LLVM, FreeRTOS, core-v-verif, CV-X-IF specification +- Open-source software: GCC, GDB, LLVM, Linux (Yocto, BuildRoot), OpenSBI, UBoot, BBL... +- Open-source verification: Google Riscv-dv, Spike, RISC-V compatibility tests +- Open-source hardware: fpnew (ETH Zürich, soon migrated to OpenHW) +- Eclipse Foundation, GitHub +- Digilent Genesys 2 board +- JADE Design Automation's Register Manager +- Simulators: Verilator (open-source), Siemens Questa, Synopsys VCS, Imperas OVPSim +- Synthesis: Vivado (Xilinx), Synopsys Design Compiler (ASIC) + +CVA6 can be integrated in the OpenPiton framework to build an SMP multi/many-core CPU. + +The RV32F DIV and SQRT simulation sequences will be developed as early as possible so that they can be reused by CV32E40Pv2 project. + +## List of project outputs + +### Documentation: + +The document structure has been defined at the PL gate: +- Specification + - Identifies features agreed upon + - “What” defined as requirements with identifiers + - Some sections are short (references to RISC-V ISA, AXI specs…) +- Users’ guide + - Includes more details than the specification + - For CVA6 integrators and users: HW, SW, ASIC, FPGA… viewpoints +- Design document + - Explains the “How”: design choices… + - Not prescriptive, written during or after the design. + - Useful for next projects. +- Verification Environment Specification + - User manual for the verification environment testbenches, testcases, verification components, etc. + - Description of the testbench structure and theory of operation +- Design Verification Plans + - DVplan, Verification Plan, Vplan: same meaning + - Feature-by-feature listing of the Device Under Test + - and a description of how it will be verified + - and how we know when it is verified (coverage). + +The specification and users' guide are inputs for design verification plans. + +### Design + +- CVA6 configurable RTL source code (TRL5 target) +- Subsystems and FPGA designs, a.k.a. APU, to exercise CVA6 on development boards... + + +### Verification: + +- Versatile generic testbench with adaptation layers for CVA6 + - Subset compliant with _sustainable open-source solution_ expectactions +- Test sequences +- Verification results + - Including code coverage and functional coverage + +### Software: + +- Baremetal BSP for FPGA boards featuring CVA6 +- Linux ports (based on UBoot, OpenSBI and Yocto) +- Toolchains (compiler...) + +LLVM and FreeRTOS are products of related OpenHW projects. + + +## TGs Impacted/Resource requirements + +| | Staff | Members | +| :-------------- | :---: | :-----: | +| Cores TG | X | X | +| Verification TG | X | X | +| SW TG | X | X | + +### OpenHW engineering staff resource plan: requirement and availability + +The OpenHW staff is expected to support the task groups on these missions: +- Mike Thompson on verification +- Florian Zaruba on software and ARIANE knowledge transfer +- Davide Schiavone on core design +- Duncan Bees on project management + +### Engineering resource supplied by members - requirement and availability + +The 2022 workplan below has been prepared according to available members' resources. + +Grants are expected to fuel 2023 workplan with more resources, especially on verification activities. + +### Marketing resource - requirement and availability + +The project needs support from: + +- Rick O'Connor, OpenHW CEO +- Michelle Clancy, Director of Marketing + +to promote CVA6 and attract new participants to the project. + +On the members' side, promotion activities (presentations, demos...) will mainly be addressed by the engineering team. + +Results obtained by the engineering team in 2021 (CV32A6 release, FreeRTOS support, Linux support...) can be used +in 2022 to promote the CVA6 project. + +### Funding for project aspects - requirement and availability + +Some marketing activities (OpenHW TV production...) might need OpenHW funding. + +Participating members provide the necessary tools to their teams. + +## Architecture and/or context diagrams + +![CVA6 pipeline](https://www.allaboutcircuits.com/uploads/articles/Ariane_CPU.jpg) + +## Who would make use of OpenHW output + +Any entity needing a mid-range verified open-source RISC-V application processing core for ASIC and FPGA technologies: +- OpenHW members +- Large and small businesses +- Academy and research +- Future OpenHW projects + +Also refer to the "Market differentiators" section above. + +An open-source project favors collaborative and research projects that can start quickly without commercial and legal burdens. + +## Project license model + +The project artefacts and outputs will be licensed under Apache 2.0 or for SW code and Solderpad 2.0 or 2.1 for HW/RTL codes. + +Third-party open-source contributions will generally retain their own licence model. + +"Viral" licences, such as GPL, will be avoided. + +OVPSim licences will be provided by Imperas. + +## Description of initial code contribution, if required + +Contributions before or off the project: +- ARIANE (CV64A6) and debug, ETH Zürich and University of Bologna +- CV32A6 bare mode, INVIA +- `FENCE.T`, Hensoldt Cyber/ETH Zürich +- CV64A6 Hypervisor extension, University of Minho +- ASIC PPA assessment, INVIA +- FPGA PPA assessment, TRT + +## Repository Structure + +https://github.com/openhwgroup/cva6: the core master directory
+/core: the CVA6 core (defined as the scope of the IP in the specification and targetting 100% coverage)
+/corev_apu: the computing subsystem comprising CVA6
+/docs: CVA6 documents (specification, users' guide...) + +https://github.com/openhwgroup/core-v-verif: the verification home
+/cva6: specific files for the core + +https://github.com/openhwgroup/cva6-sdk: RISC-V tools and Linux + +https://github.com/openhwgroup/core-v-docs/tree/master/program/Project%20Descriptions%20and%20Plans/CVA6: project gates. + +In addition, Thales has set up an internal mirror of GitHub repositories to trigger their countinuous integration environment. + +## Project distribution model + +OpenHW GitHub repository + +## Project plan + +### 2021 contributions (between the PL and PA gates) + +- CVA6 specification, joint work +- CV32A6 MMU and debug, TRT +- Complete CV32A6 release +- Continuous integration environment, INVIA +- Operational Linux 1 (BBL, Buildroot), TRT +- Operational Linux 2 (U-Boot, OpenSBI, Buildroot), TRT +- Operational FreeRTOS, ECC +- Embench-IoT benchmarks, ICP/stall analysis environment, U. Bologna +- Various contributions (bug fixes, documentation...) + +### 2022 workplan + +A waterfall method is used. + +| Related TG | Milestone | Target | Contributor | +| --------------- | ------------------------------------------------------------------------------------------------------------------------------ | ------------- | ----------- | +| Core | +50% frequency and -50% FPGA resource used for the CV32A6 soft-core | 2022-09-30 | TRT | +| Core | Implementation gap: CSR fixes: performance counters size... | 2022-10-31 | ECC | +| Core | Implementation gap: Footprint optimisation of performance counters | 2022-10-31 | ECC | +| Core | L1D feature to support datasize extension to store EDC, ECC or other information. | 2022-12-31 | ECC | +| Core | invalidate L1WTD content with the FENCE.T command. | TBD | ECC? | +| Core | Feature to transform cache ways into a scratchpad | 2022-12-31 | ECC | +| Core | L1I feature to support datasize extension to store EDC, ECC or other information | 2022-12-31 | ECC | +| Core | Add H extension as an option to CV64A6 | 2022-07-31 | U. Minho | +| Core | Add custom temporal fence (`fence.t`) instruction on CV64A6 and CV32A6 | 2022-05-31 | ETH | +| Software | Linux Yocto up and running on CVA6 | 2022-06-30 | TRT | +| Verification | Trigger Thales CI from github/openhwgroup repository and maintain it | 2022-03-31 | INVIA | +| Verification | CV-X-IF: VPlan, coprocessor UVM agent and verification | 2022-06-30 | INVIA | +| Verification | CV32E4\* verification environment reuse | 2022-12-31 | INVIA | +| Verification | First verification steps: RV32F DIV and SQRT simulation in CVA6 DV environment (to be reused by CVE40Pv2) | 2022-12-31 | ECC | +| Verification | Implementation and execution of Virtual Peripheral | 2022-09-30 | ECC | +| Verification | Add riscv-arch-test suite to existing CVA6 core-v-verif CI (32-bit and 64-bit) | 2022-06-30 | ECC | +| Project-wide | Raise a CQ (Eclipse contribution questionnaire) | 2022-06-30 | Jérôme, Mike | +| Verification | CVA6 complete verification pending new grants | 2023 activity | INVIA | +| | _For information:_ | | | +| Related project | FreeRTOS developments - maturing the boot sequence, driver eco-system for peripherals, synchronize with SW TG and MCU FreeRTOS | 2022-10-31 | ECC | +| Off project | Keystone FreeRTOS integration on RISC-V hardware (IBEX, CVA6 etc.), synchronize with SW TG and MCU FreeRTOS | 2022-12-31 | ECC | +| Off project | TensorflowLite deployment on Linux CVA6 | 2022-12-31 | ECC | + +### Project tracking and meetings + +The progress towards 2022 milestones will be tracked in progress meetings. Slides will be updated during the meeting and posted on CVA6 Mattermost channel. + +The various activities (core, verification, software) are led in a unified project way and reported to the relevant task groups. + +The CVA6 meets every week, alternating progress and technical meetings. +The meetings are well suited for East Coast, Europe and India timezones. Once a month, the meeting starts later to accomodate participants from the West Coast. + +### Oustanding topics + +These topics will be defined in CVA6 meetings at the relevant time: +- Overall approach for Github issues and label + +No release plan is defined in 2022 as this PA gate is interim. +No Project Freeze (PF) checklist is planned in 2022. + +### Risk register + +| | Likelihood | Impact | Avoidance / Mitigation | +| ------------------------- | :--------: | :----: | ----------------------------------------------------------------------------- | +| Not enough resources | High | Major | The current team is expecting grants ; more participants welcome | +| Insufficient coordination | Mid | Mid | Weekly meetings | +| Conflicting contributions | Mid | Major | Weekly meetings | +| Export control | Low | Major | Apply OpenHW membership agreement (carefully review non-OpenHW contributions) | +| Lack of market appeal | Mid | Major | Increase CVA6 promotion based on intermediate results | diff --git a/program/Project-Descriptions-and-Plans/CVA6/CVA6-preliminary-project-proposal.md b/Project-Descriptions-and-Plans/CVA6/CVA6-preliminary-project-proposal.md similarity index 98% rename from program/Project-Descriptions-and-Plans/CVA6/CVA6-preliminary-project-proposal.md rename to Project-Descriptions-and-Plans/CVA6/CVA6-preliminary-project-proposal.md index ba8cbafa9..f7fc1a897 100644 --- a/program/Project-Descriptions-and-Plans/CVA6/CVA6-preliminary-project-proposal.md +++ b/Project-Descriptions-and-Plans/CVA6/CVA6-preliminary-project-proposal.md @@ -1,403 +1,403 @@ -# OpenHW Project Proposal: CVA6 core - -| Gate | Status | -| ------------------------------------ | ------------------------------------------ | -| PPL gate: Preliminary Project Launch | Seeking approval at TWG meeting 2020-09-28 | -| PL gate: Project Launch | | -| PPA gate: Project Plan Approved | | - -The goal of this PPL gate is to seek participation of OpenHW members to the CVA6 project and proceed to the PL gate by scoping and planning the project. - -## Summary of project - -The **CVA6** core is a configurable mid-range application RISC-V core able to boot a rich OS like Linux. Its origin is ETH Zürich's ARIANE core. - -From a single RTL source, several flavors can be configured: 32- or 64-bit architecture (**CV32A6** / **CV64A6**), -with or without FPU, with or without MMU, FPGA optimizations... -The ability to have very similar 32- and 64-bit cores should make the transition seamless. - -The goal of the project is to bring **CVA6** to an **industrial maturity**: -- Quality documentation -- Add a few features desired by participating members -- High-coverage verification -- Optimizations for FPGA-based products -- SW tools (GCC, LLVM...) -- FPGA prototype and development board -- Linux support - -In addition to these industrial goals, a **sustainable open-source solution**, presumably a subset of outputs, will be maintained for researchers, -engineers seeking to evaluate CVA6 and industrial domains that need to support their products for decades. - -### Summary of Timeline - -The goal is to have all deliverables ready in **June 2022**. A refined planning should be elaborated for the PL gate. - -## OpenHW Members/Participants committed to participate in CORE-V IDE project - -Confirmed: -- Thales group: - - Thales Research & Technology (TRT) - - Thales DIS Design Services (INVIA) -- Hensoldt Cyber -- ETH Zürich - -To be confirmed: -- Imperas -- Embecosm -- OpenHW staff -- Futurewei? -- **other members needed** - -## Technical Project Leader(s) (TPLs) - -- Technical project leader (TPL): Jérôme Quévremont, TRT -- Documentation leader: Florian Zaruba, OpenHW -- Verification leader: Mike Thompson, OpenHW -- _Need identified leaders on other themes/TG?_ - -## Project Manager (PM) - -Three options (starting from the most desired): -1. Call for participation from an OpenHW member company - - Thales would like to have participation from more OpenHW partners so encourages this. - - Staff can assist. -2. PM is OpenHW staff member. - - Work closely with the TPL to document the plan. - - Note that members own this project. In this case, staff PM would be more in background. -3. PM is also Jérôme - - with support from staff for intergroup coordination and Gantt planning, etc. - - Jérôme (PM) reports status to TWG. - - Risky from Thales resource perspective - -PM role: -- coordinate and document a project plan (key technical and project steps), -- keep track of who is doing what, -- plan sprints/waterfall, -- identify issues that are blocking the way, -- reports issues to TWG, -- related to the technical leader role but a bit more toward the planning, tracking and and reporting. - - -## Project Documents - -See the list of project outputs below. - - -## Summary of requirements - -### Introduction - -These are requirements identified as of the PPL gate. -They are expected to evolve until the PL gate, as members join and refine the project plan. -The detailed specification will be part of the project itself. - -### Initial project requirements - -#### Functional - -Compared to the _legacy_ **ARIANE** donated by ETH Zürich: - -##### Hensoldt Cyber requirements: - -- Support seL4 -- `FENCE.T` instruction, -- Synchronous resets -- Write-back L1 I+D caches - - In connection with ETH Zürich - -##### Thales requirements: - -Configure the core at design-time to get the right performance/area/frequency point: -- Optional RV32 configuration (`XLEN=32` parameter) for embedded applications that are far below the 4 GiB boundaray - - The large similarity between CV32A6 and CV64A6 should ease the transition and reduce SW rework when jumping to the 64-bit architecture. -- Include or exclude the FPU (RISC-V F and D extensions both for CV32A6 and CV64A6) -- Include or exclude the MMU - -Security and functional safety: -- Write-through L1 I+D caches: add a few commands and controls (invalidate/flush, enable/disable, non-cacheable regions, line/way lock, replacement policy, _to be detailed during specification_) -- Advanced performance counters -- At run-time, ability to disable sources of unpredictability (branch predictions...) - -Target ASIC and FPGA products (FPGA not only used as prototypes): -- At design time, select synchronous or asynchronous reset -- Other FPGA optimizations to be identified - - _Note:_ Thales is co-organizing a student contest in France to get fresh ideas on this topic and promote OpenHW. - Some elegant student findings might be injected in CV32A6. Thales will act as a firewall between students and OpenHW. - -#### License scheme - -##### Thales expectactions: - -Because of the nature of its business, Thales expectation is to contribute and get a **sustainable open-source solution** -- to integrate CVA6 in new ASIC and FPGA projects for a long period and to maintain/upgrade them for several decades for industrial domains (avionic, satellite, railways, energy…); -- to permit audit and reviews of verification and tools in the context of certifiable security and functional safety; -- to permit public review to improve the quality of the core and its ecosystem; -- to foster cooperative projects and connections with academy and research. - -Thereforce, Thales expects: -- Not only the core RTL, but also a version of the simulation environment and the SW tools are available as open-source. -- Commercial tools can be added to this basic set to deliver additional value (improved quality, coverage...). - - But the project shall not depend on a single-source commercial tool. - - Commercial tools with multiple sources, such as logic simulators, are acceptable. - -In addition, this sustainable open-source solution, removes barriers for newcomers to OpenHW, -as it was the case for ARIANE with the GNU toolchain and the testbench offered by ETH Zürich. -They can evaluate CVA6, adopt it, join OpenHW Group, add their "secret sauce"... - -> “Open source tools are the best friends of open hardware.” - -#### Verification - -OpenHW CEO's expectaction: unified testbench for all CORE-V cores (CVE4, CVA6) - -Thales expectactions: Industrial quality: -- High coverage -- Complete package (incl. good quality documentation aligned with verification) - -Verification leader's expectactions: -- Coverage-driven verification to ensure completeness and quality of results -- Use of SystemVerilog and UVM -- Industrial quality tools -- On-the-fly, in-simulation checking of DUT against a Reference Model - - Step-and-compare is current technique used -- Ability to offer access and support to non-commercial members of the Open Source community -- Flexibility to support multiple verification components - - e.g. ISGs, RMs, Scoreboards, etc. - -### Future enhancements: - -Adding standard or custom extensions, superscalar, SMP multi-core processor, SoC building blocks, architecture generation, build a silicon application processor... - -## Explanation of why OpenHW should do this project - -Like RI5CY, the ARIANE core donated by ETH Zürich was at the heart of the OpenHW Group creation. We need an application processor core in our portfolio. - -## Industry landscape: description of competing, alternative, or related efforts in the industry - -On the core side, these are the most comparable competitors (pipeline length, MMU, single issue...): -- ARM: Cortex-A5 -- SiFive: U54 -- CHIPS Alliance / Western Digital: CVA6 between the smaller SweRV EL2 and the larger EH1. -- ANDES: A25 (32-bit) and AX25 (64-bit) -- Gaisler NOEL-V is more powerful (dual-issue in-order pipeline). - -On the tool side, CHIPS Alliance has plans to make their tools open-source -([link](https://semiengineering.com/components-for-open-source-verification/), 5th paragraph). - -### Related efforts to be described - -To differentiate from the competition, marketing can stress the: -- open-source availability, -- the permissive licence scheme, -- the low exposition to export control -([OpenHW Group Membership Agreement](https://www.openhwgroup.org/membership/openhw-group-membership-agreement-2019-10-16.pdf), section 4.1). - -## External dependencies - -- Open-source: GCC, LLVM... -- Eclipse Foundation, GitHub -- Metrics -- Digilent Genesys 2 board -- others - -## List of project outputs - -Cores-TG: -- Specification -- Core documentation (structure to be defined for the next gates) -- Configurable RTL source code - -Verification-TG: -- Verification plans (simulation) -- Versatile generic testbench with adaptation layers for CVA6 - - Subset compliant with _sustainable open-source solution_ expectactions -- Test sequences -- Verification results - - Including code coverage and functional coverage -- Option: formal verification - - Verification plan - - Bug reports - - Verification report - -HW TG: -- FPGA design for Digilent 2 board - -SW TG: -- Full open-source SW suite (compliant with _sustainable open-source solution_ expectactions) -- Added-value SW suite -- Open-source baremetal BSP -- Open source Linux port - -## TGs Impacted/Resource requirements - -| | Staff | Members | -| :-------------- | :---: | :-----: | -| Cores TG | X | X | -| Verification TG | X | X | -| HW TG | X | X | -| SW TG | X | X | - -### OpenHW engineering staff resource plan: requirement and availability - -The OpenHW staff is expected to support the task groups according to their usual mission. - -In addition, specific roles: -- Rick O'Connor: promote the project and attract new participants -- Florian Zaruba: documentation leader -- Mike Thompson: verification leader -- Duncan Bees: TDB w.r.t. the selected PM - -The preliminary project plan (last section) shows a dire lack of verification manpower. -Can OpenHW subcontract some tasks if members do not provide enough resources? - -### Engineering resource supplied by members - requirement and availability -According to project plan (last section) - -### OpenHW marketing resource - requirement and availability -TBD - -### Marketing resource supplied by members - requirement and availability -TBD - -### Funding supplied by OpenHW - requirement and availability -TBD - -### Funding supplied by members - requirement and availability -TBD - -## Architecture diagram - -| | CV64A6 | CV32A6 | -| :--------------- | :-----------------: | :-----------------: | -| ISA | RV64IMA\[FD\]CZicsr | RV32IMA\[FD\]CZicsr | -| Privilege levels | M/S/U | M/S/U | -| [Virtual memory] | \[Sv39\] | \[Sv32\] | - -\[\] denotes a configurable feature. - -![CVA6 pipeline](https://www.allaboutcircuits.com/uploads/articles/Ariane_CPU.jpg) - -## Who would make use of OpenHW output - -Any entity needing a mid-range verified open-source RISC-V application processing core for ASIC and FPGA technologies: -- OpenHW members -- Large and small businesses -- Academy and research -- Future OpenHW projects - -These users may integrate the CVA6 core both in open-source or closed-source projects. They may also add their "secret sauce". - -An open-source project favors collaborative and research projects that can start quickly without commercial and legal burdens. - -## Project license model - -The project artefacts and outputs will be licensed under Apache 2.0 for SW code and Solderpad 2.0 for HW/RTL codes. - -Third-party open-source contributions will generally retain their own licence model. - -"Viral" licences, such as GPL, will be avoided. - -Imperas will provide the project contributors the necessary licences for the verification. Some verification actors may need several tokens. - -## Description of initial code contribution, if required - -Contributions below are open-source, _except otherwise mentioned_. -- RTL - - ARIANE, ETH Zürich and University of Bologna - - `XLEN=32` configuration, INVIA - - `FENCE.T`, Hensoldt Cyber -- Verification (to be confirmed, strategy pending) - - Generators: - - RISC-V DV, Google - - Compliance tests, RISC-V International - - FORCE RISC-V, Futurewei (when 32-bit support is implemented) - - References: - - Spike - - RISC-V SAIL model, RISC-V International - - Imperas ISS _(commercial)_ -- SW tools - - Open source tool generation (GCC, GDB...), INVIA - - SW tools, Embecosm _(no source access)_ - -## Repository Structure - -TBD - -## Project distribution model - -OpenHW GitHub repository - -## Risks - -Very preliminary analysis of major risks (feedback welcome): - -| | Likelihood | Impact | Avoidance / Mitigation | -| ----------------------------- | :--------: | :----: | ----------------------------------------------------------------------------- | -| **Not enough resources** | **High** | **Severe** | **Find more contributors / OpenHW subconcracts** | -| Not enough coordination | Mid | Major | PM in addition to the TPL | -| Export control | Low | Major | Apply OpenHW membership agreement (carefully review non-OpenHW contributions) | -| Excessive verification effort | High | Major | Wise selection of verified configurations | -| Lack of market appeal | ? | Major | ? | - - -## Preliminary Project plan - -Preliminary (to be completed and reviewed by participants): - -| TG | Task | Contributor(s) | -| ------------------------ | --------------------------------------------------------------- | --------------------------- | -| Cores | Specifications | Participating members | -| Cores | Documentation | F. Zaruba | -| Cores | Fix lint warning and errors | ? | -| Cores | Develop 32-bit MMU (Sv32) | INVIA | -| Cores | Adapt F,D MMU to 32-bit architecture | ? | -| Cores | Make WT cache configurable | INVIA, TRT | -| Cores | Develop WB cache | ETH Zürich | -| Cores | Safety options to make the core more predictable | TRT | -| Cores | `FENCE.T` instruction | Hensoldt Cyber | -| Cores | Configurable multiplier/divider: 1 or more cycles | ? | -| Cores | Standard extensions: B, V, crypto... | ? | -| Cores | Generic reset (sync/async, active high/low) | Hensoldt Cyber, ETH Zürich? | -| Cores | FPGA optimizations | TRT | -| Cores | _Other tasks?_ | ? | -| HW | FPGA implementation on Genesys 2 | TRT | -| HW | _Other tasks?_ | ? | -| HW | _Other tasks?_ | ? | -| SW | Support GCC rv64gc/r32gc up-to-date versions with multilibs | INVIA | -| SW | Support LLVM rv64gc/r32gc up-to-date versions with multilibs | INVIA | -| SW | _Contribution to be described_ | Embecosm | -| SW | Implement standard extensions (B, V...) in GCC/LLVM | ? | -| SW | Implement standard extensions (B, V...) in Sail ISS | ? | -| SW | Baremetal BSP (Genesys2) | TRT | -| SW | Linux (Genesys 2) | TRT | -| SW | Run benchmarks | TRT | -| SW | _Other tasks?_ | ? | -| Verification (testbench) | Support open source simulator: Veripool (Verilator) | INVIA | -| Verification (testbench) | Support simulators: Mentor, Synopsys, Cadence, Aldec... | | -| Verification (testbench) | Support simulator: Metrics | Staff? | -| Verification (testbench) | Support open source ISS : Spike ans Sail | INVIA | -| Verification (testbench) | Support ISS : Imperas (OVPsim) | Imperas | -| Verification (testbench) | Support Riscv-dv Random Generation with VCS (Synopsys) | INVIA | -| Verification (testbench) | Support FORCE-RISCV generator (32 and 64 bit) | Futurewei? | -| Verification (testbench) | Support “trace and compare” checker | INVIA | -| Verification (testbench) | Support “step and compare” checker | Staff? | -| Verification (testbench) | Implement CI based on open source tools, gitlab-ci | Staff? | -| Verification (testbench) | Define CVA6 HW configs (64/32bits, FPU disable/enable,…) | INVIA and participants | -| Verification (testbench) | Memory preload to boost simulation time with Verilator | INVIA, F. Zaruba | -| Verification (testbench) | Add functional coverage checkers | ? | -| Verification (testbench) | Extract code coverage with Questa | INVIA | -| Verification (testbench) | _Other tasks?_ | ? | -| Verification (tests) | Edit and maintain verifications plans | ? | -| Verification (tests) | Riscv-compliance, riscv-tests regression suites | ? | -| Verification (tests) | Riscv-dv Instruction Random Generation | ? | -| Verification (tests) | FORCE-RISCV Instruction Random Generation | ? | -| Verification (tests) | Continous integration with different CVA6 configurations | ? | -| Verification (tests) | Tests for added extensions | ? | -| Verification (tests) | Add tests to increase coverage | ? | -| Verification (tests) | Reach 100% code coverage | ? | -| Verification (tests) | Reach 100% functional coverage | ? | -| Verification (tests) | Option: formal verification plan | Axiomise | -| Verification (tests) | Option: execute formal verification | Axiomise | -| Verification (tests) | _Other tasks?_ | | - -? denotes an optional task or missing contributors. +# OpenHW Project Proposal: CVA6 core + +| Gate | Status | +| ------------------------------------ | ------------------------------------------ | +| PPL gate: Preliminary Project Launch | Seeking approval at TWG meeting 2020-09-28 | +| PL gate: Project Launch | | +| PPA gate: Project Plan Approved | | + +The goal of this PPL gate is to seek participation of OpenHW members to the CVA6 project and proceed to the PL gate by scoping and planning the project. + +## Summary of project + +The **CVA6** core is a configurable mid-range application RISC-V core able to boot a rich OS like Linux. Its origin is ETH Zürich's ARIANE core. + +From a single RTL source, several flavors can be configured: 32- or 64-bit architecture (**CV32A6** / **CV64A6**), +with or without FPU, with or without MMU, FPGA optimizations... +The ability to have very similar 32- and 64-bit cores should make the transition seamless. + +The goal of the project is to bring **CVA6** to an **industrial maturity**: +- Quality documentation +- Add a few features desired by participating members +- High-coverage verification +- Optimizations for FPGA-based products +- SW tools (GCC, LLVM...) +- FPGA prototype and development board +- Linux support + +In addition to these industrial goals, a **sustainable open-source solution**, presumably a subset of outputs, will be maintained for researchers, +engineers seeking to evaluate CVA6 and industrial domains that need to support their products for decades. + +### Summary of Timeline + +The goal is to have all deliverables ready in **June 2022**. A refined planning should be elaborated for the PL gate. + +## OpenHW Members/Participants committed to participate in CORE-V IDE project + +Confirmed: +- Thales group: + - Thales Research & Technology (TRT) + - Thales DIS Design Services (INVIA) +- Hensoldt Cyber +- ETH Zürich + +To be confirmed: +- Imperas +- Embecosm +- OpenHW staff +- Futurewei? +- **other members needed** + +## Technical Project Leader(s) (TPLs) + +- Technical project leader (TPL): Jérôme Quévremont, TRT +- Documentation leader: Florian Zaruba, OpenHW +- Verification leader: Mike Thompson, OpenHW +- _Need identified leaders on other themes/TG?_ + +## Project Manager (PM) + +Three options (starting from the most desired): +1. Call for participation from an OpenHW member company + - Thales would like to have participation from more OpenHW partners so encourages this. + - Staff can assist. +2. PM is OpenHW staff member. + - Work closely with the TPL to document the plan. + - Note that members own this project. In this case, staff PM would be more in background. +3. PM is also Jérôme + - with support from staff for intergroup coordination and Gantt planning, etc. + - Jérôme (PM) reports status to TWG. + - Risky from Thales resource perspective + +PM role: +- coordinate and document a project plan (key technical and project steps), +- keep track of who is doing what, +- plan sprints/waterfall, +- identify issues that are blocking the way, +- reports issues to TWG, +- related to the technical leader role but a bit more toward the planning, tracking and and reporting. + + +## Project Documents + +See the list of project outputs below. + + +## Summary of requirements + +### Introduction + +These are requirements identified as of the PPL gate. +They are expected to evolve until the PL gate, as members join and refine the project plan. +The detailed specification will be part of the project itself. + +### Initial project requirements + +#### Functional + +Compared to the _legacy_ **ARIANE** donated by ETH Zürich: + +##### Hensoldt Cyber requirements: + +- Support seL4 +- `FENCE.T` instruction, +- Synchronous resets +- Write-back L1 I+D caches + - In connection with ETH Zürich + +##### Thales requirements: + +Configure the core at design-time to get the right performance/area/frequency point: +- Optional RV32 configuration (`XLEN=32` parameter) for embedded applications that are far below the 4 GiB boundaray + - The large similarity between CV32A6 and CV64A6 should ease the transition and reduce SW rework when jumping to the 64-bit architecture. +- Include or exclude the FPU (RISC-V F and D extensions both for CV32A6 and CV64A6) +- Include or exclude the MMU + +Security and functional safety: +- Write-through L1 I+D caches: add a few commands and controls (invalidate/flush, enable/disable, non-cacheable regions, line/way lock, replacement policy, _to be detailed during specification_) +- Advanced performance counters +- At run-time, ability to disable sources of unpredictability (branch predictions...) + +Target ASIC and FPGA products (FPGA not only used as prototypes): +- At design time, select synchronous or asynchronous reset +- Other FPGA optimizations to be identified + - _Note:_ Thales is co-organizing a student contest in France to get fresh ideas on this topic and promote OpenHW. + Some elegant student findings might be injected in CV32A6. Thales will act as a firewall between students and OpenHW. + +#### License scheme + +##### Thales expectactions: + +Because of the nature of its business, Thales expectation is to contribute and get a **sustainable open-source solution** +- to integrate CVA6 in new ASIC and FPGA projects for a long period and to maintain/upgrade them for several decades for industrial domains (avionic, satellite, railways, energy…); +- to permit audit and reviews of verification and tools in the context of certifiable security and functional safety; +- to permit public review to improve the quality of the core and its ecosystem; +- to foster cooperative projects and connections with academy and research. + +Thereforce, Thales expects: +- Not only the core RTL, but also a version of the simulation environment and the SW tools are available as open-source. +- Commercial tools can be added to this basic set to deliver additional value (improved quality, coverage...). + - But the project shall not depend on a single-source commercial tool. + - Commercial tools with multiple sources, such as logic simulators, are acceptable. + +In addition, this sustainable open-source solution, removes barriers for newcomers to OpenHW, +as it was the case for ARIANE with the GNU toolchain and the testbench offered by ETH Zürich. +They can evaluate CVA6, adopt it, join OpenHW Group, add their "secret sauce"... + +> “Open source tools are the best friends of open hardware.” + +#### Verification + +OpenHW CEO's expectaction: unified testbench for all CORE-V cores (CVE4, CVA6) + +Thales expectactions: Industrial quality: +- High coverage +- Complete package (incl. good quality documentation aligned with verification) + +Verification leader's expectactions: +- Coverage-driven verification to ensure completeness and quality of results +- Use of SystemVerilog and UVM +- Industrial quality tools +- On-the-fly, in-simulation checking of DUT against a Reference Model + - Step-and-compare is current technique used +- Ability to offer access and support to non-commercial members of the Open Source community +- Flexibility to support multiple verification components + - e.g. ISGs, RMs, Scoreboards, etc. + +### Future enhancements: + +Adding standard or custom extensions, superscalar, SMP multi-core processor, SoC building blocks, architecture generation, build a silicon application processor... + +## Explanation of why OpenHW should do this project + +Like RI5CY, the ARIANE core donated by ETH Zürich was at the heart of the OpenHW Group creation. We need an application processor core in our portfolio. + +## Industry landscape: description of competing, alternative, or related efforts in the industry + +On the core side, these are the most comparable competitors (pipeline length, MMU, single issue...): +- ARM: Cortex-A5 +- SiFive: U54 +- CHIPS Alliance / Western Digital: CVA6 between the smaller SweRV EL2 and the larger EH1. +- ANDES: A25 (32-bit) and AX25 (64-bit) +- Gaisler NOEL-V is more powerful (dual-issue in-order pipeline). + +On the tool side, CHIPS Alliance has plans to make their tools open-source +([link](https://semiengineering.com/components-for-open-source-verification/), 5th paragraph). + +### Related efforts to be described + +To differentiate from the competition, marketing can stress the: +- open-source availability, +- the permissive licence scheme, +- the low exposition to export control +([OpenHW Group Membership Agreement](https://www.openhwgroup.org/membership/openhw-group-membership-agreement-2019-10-16.pdf), section 4.1). + +## External dependencies + +- Open-source: GCC, LLVM... +- Eclipse Foundation, GitHub +- Metrics +- Digilent Genesys 2 board +- others + +## List of project outputs + +Cores-TG: +- Specification +- Core documentation (structure to be defined for the next gates) +- Configurable RTL source code + +Verification-TG: +- Verification plans (simulation) +- Versatile generic testbench with adaptation layers for CVA6 + - Subset compliant with _sustainable open-source solution_ expectactions +- Test sequences +- Verification results + - Including code coverage and functional coverage +- Option: formal verification + - Verification plan + - Bug reports + - Verification report + +HW TG: +- FPGA design for Digilent 2 board + +SW TG: +- Full open-source SW suite (compliant with _sustainable open-source solution_ expectactions) +- Added-value SW suite +- Open-source baremetal BSP +- Open source Linux port + +## TGs Impacted/Resource requirements + +| | Staff | Members | +| :-------------- | :---: | :-----: | +| Cores TG | X | X | +| Verification TG | X | X | +| HW TG | X | X | +| SW TG | X | X | + +### OpenHW engineering staff resource plan: requirement and availability + +The OpenHW staff is expected to support the task groups according to their usual mission. + +In addition, specific roles: +- Rick O'Connor: promote the project and attract new participants +- Florian Zaruba: documentation leader +- Mike Thompson: verification leader +- Duncan Bees: TDB w.r.t. the selected PM + +The preliminary project plan (last section) shows a dire lack of verification manpower. +Can OpenHW subcontract some tasks if members do not provide enough resources? + +### Engineering resource supplied by members - requirement and availability +According to project plan (last section) + +### OpenHW marketing resource - requirement and availability +TBD + +### Marketing resource supplied by members - requirement and availability +TBD + +### Funding supplied by OpenHW - requirement and availability +TBD + +### Funding supplied by members - requirement and availability +TBD + +## Architecture diagram + +| | CV64A6 | CV32A6 | +| :--------------- | :-----------------: | :-----------------: | +| ISA | RV64IMA\[FD\]CZicsr | RV32IMA\[FD\]CZicsr | +| Privilege levels | M/S/U | M/S/U | +| [Virtual memory] | \[Sv39\] | \[Sv32\] | + +\[\] denotes a configurable feature. + +![CVA6 pipeline](https://www.allaboutcircuits.com/uploads/articles/Ariane_CPU.jpg) + +## Who would make use of OpenHW output + +Any entity needing a mid-range verified open-source RISC-V application processing core for ASIC and FPGA technologies: +- OpenHW members +- Large and small businesses +- Academy and research +- Future OpenHW projects + +These users may integrate the CVA6 core both in open-source or closed-source projects. They may also add their "secret sauce". + +An open-source project favors collaborative and research projects that can start quickly without commercial and legal burdens. + +## Project license model + +The project artefacts and outputs will be licensed under Apache 2.0 for SW code and Solderpad 2.0 for HW/RTL codes. + +Third-party open-source contributions will generally retain their own licence model. + +"Viral" licences, such as GPL, will be avoided. + +Imperas will provide the project contributors the necessary licences for the verification. Some verification actors may need several tokens. + +## Description of initial code contribution, if required + +Contributions below are open-source, _except otherwise mentioned_. +- RTL + - ARIANE, ETH Zürich and University of Bologna + - `XLEN=32` configuration, INVIA + - `FENCE.T`, Hensoldt Cyber +- Verification (to be confirmed, strategy pending) + - Generators: + - RISC-V DV, Google + - Compliance tests, RISC-V International + - FORCE RISC-V, Futurewei (when 32-bit support is implemented) + - References: + - Spike + - RISC-V SAIL model, RISC-V International + - Imperas ISS _(commercial)_ +- SW tools + - Open source tool generation (GCC, GDB...), INVIA + - SW tools, Embecosm _(no source access)_ + +## Repository Structure + +TBD + +## Project distribution model + +OpenHW GitHub repository + +## Risks + +Very preliminary analysis of major risks (feedback welcome): + +| | Likelihood | Impact | Avoidance / Mitigation | +| ----------------------------- | :--------: | :----: | ----------------------------------------------------------------------------- | +| **Not enough resources** | **High** | **Severe** | **Find more contributors / OpenHW subconcracts** | +| Not enough coordination | Mid | Major | PM in addition to the TPL | +| Export control | Low | Major | Apply OpenHW membership agreement (carefully review non-OpenHW contributions) | +| Excessive verification effort | High | Major | Wise selection of verified configurations | +| Lack of market appeal | ? | Major | ? | + + +## Preliminary Project plan + +Preliminary (to be completed and reviewed by participants): + +| TG | Task | Contributor(s) | +| ------------------------ | --------------------------------------------------------------- | --------------------------- | +| Cores | Specifications | Participating members | +| Cores | Documentation | F. Zaruba | +| Cores | Fix lint warning and errors | ? | +| Cores | Develop 32-bit MMU (Sv32) | INVIA | +| Cores | Adapt F,D MMU to 32-bit architecture | ? | +| Cores | Make WT cache configurable | INVIA, TRT | +| Cores | Develop WB cache | ETH Zürich | +| Cores | Safety options to make the core more predictable | TRT | +| Cores | `FENCE.T` instruction | Hensoldt Cyber | +| Cores | Configurable multiplier/divider: 1 or more cycles | ? | +| Cores | Standard extensions: B, V, crypto... | ? | +| Cores | Generic reset (sync/async, active high/low) | Hensoldt Cyber, ETH Zürich? | +| Cores | FPGA optimizations | TRT | +| Cores | _Other tasks?_ | ? | +| HW | FPGA implementation on Genesys 2 | TRT | +| HW | _Other tasks?_ | ? | +| HW | _Other tasks?_ | ? | +| SW | Support GCC rv64gc/r32gc up-to-date versions with multilibs | INVIA | +| SW | Support LLVM rv64gc/r32gc up-to-date versions with multilibs | INVIA | +| SW | _Contribution to be described_ | Embecosm | +| SW | Implement standard extensions (B, V...) in GCC/LLVM | ? | +| SW | Implement standard extensions (B, V...) in Sail ISS | ? | +| SW | Baremetal BSP (Genesys2) | TRT | +| SW | Linux (Genesys 2) | TRT | +| SW | Run benchmarks | TRT | +| SW | _Other tasks?_ | ? | +| Verification (testbench) | Support open source simulator: Veripool (Verilator) | INVIA | +| Verification (testbench) | Support simulators: Mentor, Synopsys, Cadence, Aldec... | | +| Verification (testbench) | Support simulator: Metrics | Staff? | +| Verification (testbench) | Support open source ISS : Spike ans Sail | INVIA | +| Verification (testbench) | Support ISS : Imperas (OVPsim) | Imperas | +| Verification (testbench) | Support Riscv-dv Random Generation with VCS (Synopsys) | INVIA | +| Verification (testbench) | Support FORCE-RISCV generator (32 and 64 bit) | Futurewei? | +| Verification (testbench) | Support “trace and compare” checker | INVIA | +| Verification (testbench) | Support “step and compare” checker | Staff? | +| Verification (testbench) | Implement CI based on open source tools, gitlab-ci | Staff? | +| Verification (testbench) | Define CVA6 HW configs (64/32bits, FPU disable/enable,…) | INVIA and participants | +| Verification (testbench) | Memory preload to boost simulation time with Verilator | INVIA, F. Zaruba | +| Verification (testbench) | Add functional coverage checkers | ? | +| Verification (testbench) | Extract code coverage with Questa | INVIA | +| Verification (testbench) | _Other tasks?_ | ? | +| Verification (tests) | Edit and maintain verifications plans | ? | +| Verification (tests) | Riscv-compliance, riscv-tests regression suites | ? | +| Verification (tests) | Riscv-dv Instruction Random Generation | ? | +| Verification (tests) | FORCE-RISCV Instruction Random Generation | ? | +| Verification (tests) | Continous integration with different CVA6 configurations | ? | +| Verification (tests) | Tests for added extensions | ? | +| Verification (tests) | Add tests to increase coverage | ? | +| Verification (tests) | Reach 100% code coverage | ? | +| Verification (tests) | Reach 100% functional coverage | ? | +| Verification (tests) | Option: formal verification plan | Axiomise | +| Verification (tests) | Option: execute formal verification | Axiomise | +| Verification (tests) | _Other tasks?_ | | + +? denotes an optional task or missing contributors. diff --git a/program/Project-Descriptions-and-Plans/CVA6/CVA6-project-launch.pptx b/Project-Descriptions-and-Plans/CVA6/CVA6-project-launch.pptx similarity index 100% rename from program/Project-Descriptions-and-Plans/CVA6/CVA6-project-launch.pptx rename to Project-Descriptions-and-Plans/CVA6/CVA6-project-launch.pptx diff --git a/program/Project-Descriptions-and-Plans/CVE20/OpenHW-CV32E20-PC-Cores-TG-Meeting_210628.ppt b/Project-Descriptions-and-Plans/CVE20/OpenHW-CV32E20-PC-Cores-TG-Meeting_210628.ppt similarity index 100% rename from program/Project-Descriptions-and-Plans/CVE20/OpenHW-CV32E20-PC-Cores-TG-Meeting_210628.ppt rename to Project-Descriptions-and-Plans/CVE20/OpenHW-CV32E20-PC-Cores-TG-Meeting_210628.ppt diff --git a/program/Project-Descriptions-and-Plans/CVE20/Project-Concept-for-CV32E20.md b/Project-Descriptions-and-Plans/CVE20/Project-Concept-for-CV32E20.md similarity index 100% rename from program/Project-Descriptions-and-Plans/CVE20/Project-Concept-for-CV32E20.md rename to Project-Descriptions-and-Plans/CVE20/Project-Concept-for-CV32E20.md diff --git a/program/Project-Descriptions-and-Plans/CVE20/Project-Launch-for-CV32E20-220209.md b/Project-Descriptions-and-Plans/CVE20/Project-Launch-for-CV32E20-220209.md similarity index 97% rename from program/Project-Descriptions-and-Plans/CVE20/Project-Launch-for-CV32E20-220209.md rename to Project-Descriptions-and-Plans/CVE20/Project-Launch-for-CV32E20-220209.md index 04c93b04f..4bc4d62ca 100644 --- a/program/Project-Descriptions-and-Plans/CVE20/Project-Launch-for-CV32E20-220209.md +++ b/Project-Descriptions-and-Plans/CVE20/Project-Launch-for-CV32E20-220209.md @@ -1,225 +1,225 @@ -# Title of Project - "CV32E20" -# Project Launch Proposal -## Date of proposal - 2021-07-26, Revised 2022-01-21, 2022-02-09 -## Author(s) - Joe Circello (NXP), Lee Hoff (Intrinsix) - -## Summary of project - The CV32E20 proposed project develops a TRL5, area-efficient 2-stage microcontroller core based on Ibex -as part of the CORE-V family of cores, along with a core complex (aka "coreplex") supporting Arm AMBA AHB-5 32-bit bus interfaces, -debug and interrupts. - The scope of the project consists of detailing which of the Ibex parameters are being removed, or verified, or neither verified or removed (left for future work). Completing design enhancements and integration of the interfaces into the core complex. Completing verification and documentation. - -## Components of the Project -### Component 1a "RTL design of the core". - RTL design of the Core starting from Ibex with the following features: - E - Base Integer Instruction Set (embedded) with 16, 32-bit general-purpose registers - I - Base Integer Instruction Set, with 32, 32-bit general-purpose registers - M - Standard Extension for Integer Multiplication and Division - C - Standard Extension for Compressed 16-bit Instructions - User Mode and Machine Mode - Harvard memory OBI bus interfaces - CV32E40P-like interrupt interface (Open Titan CLIC) - Cleaning Ibex RTL of unused parameters - Exposing privilege pins (privilege CSR bits are exposed as bus attribute signals) - Modification to make OBI-compliant bus interfaces. - Adding and extending the rvfi interface - Expose privilege pins as bus address phase attributes - CV32E40P-like Sleep unit - -### Component 1b "RTL design of the core complex". - Integrating interrupt controller - (Open Titan CLIC). - Integrating debug interface - similar to E40P - Integrating OBI2AHB bus bridges - -### Component 2 "Documentation". - - Create core spec from existing Ibex documentation - - Create core complex specification - - Create verification plan and reports - -### Component 3 "Verification of core complex" - - Based on core-v-verif environment - - Verification of the Core ISA configurations: RV32IMC, RV32EMC - - Verification of the Core Complex: DUT0 with RV32IMC, DUT1 with RV32EMC - - -## Summary of market or input requirements: -This project is intended to support embedded applications where, for example, -a state machine based implementation might otherwise be used. Additionally, this core -is targeted for use in applications requiring a small 32-bit processing element. -The core supports the RV32{E,I}MC instruction sets. - -### Known market/project requirements at PL gate -### Potential future enhancements for future project phases -* Zce static code size reduction opcode extension -* Supporting 2 pin compressed JTAG (CJTAG) debug interface -* Investigation of a "tiny FPU " implemention - * Targeted at sensor computations at the edge - * Having FP would be useful for these and other computations -* Low granularity Physical Memory Protection (PMP) module - -## Who would make use of OpenHW output - -Companies developing microcontroller-based embedded (sub)systems or devices. - -## Summary of Timeline - - * Start: 2021Q4 - * Use Ibex Core Specification - * Create Core Complex Specification - End of 2022Q1 - * Complete design / integration - End of 2022Q2 - * Create Core Complex Verification plan and verification spec - End of 2022Q2 - * Execute verification plan to completion - 2022Q4 - * Document detailed completion including reviews - 2022Q4 - - -## Explanation of why OpenHW should do this project - -* A 32 bit microcontroller is viewed as the appropriate low-end programmable core to replace state machine based implementations. -* It is the smallest RISC-V core design and includes standard Debug and ISA, with access to all the software enablement tools included in the CORE-V ecosystem. -* Small size and low power are the key hardware metrics. -* The starting point is Ibex, but Ibex does not include everything needed, such as OBI. It also includes many unneeded paramemters, - which may cause unnecessary verification and maintenance complications. -* The use of Arm AMBA-AHB buses supports the (re)use of many existing 32-bit IP modules, including peripherals, such as crytography devices. -* It is important for OpenHW members to exert control over the features as part of the CORE-V family. - -Overall, the CVE20 core augments the CORE-V family of 32 bit cores with a needed low-end microcontroller. - -## Industry landscape: description of competing, alternative, or related efforts in the industry - -Ibex - from LowRISC -SNITCH - from ETH Zurich - single pipeline, low complexity meant to offload to vector units -Arm Cortex-M0+ - from Arm - -## OpenHW Members/Participants committed to participate - -* Intrinsix - Design and Verification of core-complex, Core Verification -* NXP - Architecture definition, Core Design, Core Verification -* Imperas - Supply Imperas reference model, engineering support and expertise -* Embecosm - Provide tool enablement (SW tools: compilers, assembler/linker, etc.) -* ETH Zurich - (Davide Schiavone) Provide design guidance and contribute RTL design edits - -## Project Leader(s) -### Technical Project Leader(s) -At Project Launch, co-led by -* Lee Hoff, Intrinsix -* Joe Circello, NXP - -### Project Manager, if a PM is designated -None designated. - -## Project Documents -### Project Planning Documents - Detailed project plan - RTL Freeze checklist - -### Project Output Documents - Core specification - Core complex specification - Verification plan - Verification report - - -## List of project technical outputs - Verified RTL for Core and Core Complex (RV32IMC and RV32EMC) - Verification environment including test cases - Documentation - -### Feature Requirements -*Features are more granular than Components.* -*For SW porting projects, this list serves as the detailed project reference for features* -*For IP Cores or more complext projects, a user manual with requirements specification is produced at the PA gate, which may supercede this list of features* - -#### Feature 1 - Decide on features available to user and not available - Configuration of parameters (what is being verified in this project) - Future considerations of what is carried forward -#### Feature 2 - - -## External dependencies -*These are external factors on which the project depends, such as external standards ratification, external technology input, etc.* -*None currently identified* - -## OpenHW TGs Involved -*Cores TG, Verification TG* - -## Resource Requirements -*This is a list of major resources/people required to implement the project and indication of whether the resources are available* - -Core Design RTL --> NXP and Intrinsix resources would need guidance from Davide Schiavone - -Core Complex RTL --> 1-2 resources for 3 months until end of 2Q --> Core Complex is to be handled by NXP and Intrinsix - - -Core Verification -Core Complex Verification - -.> 3-4 FTE resources for (3Q + 4Q) of 2022 --> Intrinsix (USA) and NXP (Europe) resources - -Documentation --> covered as per deliverables above - -Technical Project Management --> potentially covered through NXP and Intrinsix especially by a verification leader --> A committer would be needed, and the above person could do that - - -### Engineering resource supplied by members - requirement and availability -### OpenHW engineering staff resource plan: requirement and availability -discussed above - -### Marketing resource - requirement and availability -### Funding for project aspects - requirement and availability - -## Architecture and/or context diagrams -*Architecture (internal blocks and interconnections), and context (depiction of the the project content within its operational context), are both encouraged where appropriate to depict functionality to both subject matter experts and to non-experts* -Nice to have but not yet available - -## Project license model - Solderpad License - -## Description of initial code contribution, if required - For the core, Initial RTL to be forked or cloned from Ibex. This decision is not yet made. - A CQ will be generated on the Ibex code. - For the core complex, --- Interrupt (CLIC or CLINT) controller from OpenTitan --- OBI to AHB bus gaskets from Intrinsix --- not decided yet if we need a CQ on these elements. - Verification based on core-v-verif uvm environment - - -## Repository Requirements - Design and Documentation will use github under cv32e20 - Verification will use github under core-v-verif - -## Project distribution model -Project artifacts will be released under CORE-V Cores and available on openhw github - - -## Preliminary Project plan -*A full project plan is not required at PL. A preliminary plan, which can be for instance the schedule for completion of component or feature list, together with responsible resource, should be provided. Full details should be provided at PA gate.* - -see the timeline section above - - -## Steps to get to PA gate - -Get the repo in place - -Committer/contributor/repo/Git training for the teams at NXP and Intrinsix (2 hour session) - -Technical teams need to be named and start engaging - -Internal teams to NXP and Intrinsix should understand how to contribute code and navigate their company's policies to make contributions - -Target the April 2022 PA gate to have -- requirements specificaiton for both Core and Complex -- project plan and risk register with task list, names, start and stop dates AND/OR detailed backlog register - - -## Risk Register -*A list of known risks, for example external dependencies, and any mitigation strategy* +# Title of Project - "CV32E20" +# Project Launch Proposal +## Date of proposal - 2021-07-26, Revised 2022-01-21, 2022-02-09 +## Author(s) - Joe Circello (NXP), Lee Hoff (Intrinsix) + +## Summary of project + The CV32E20 proposed project develops a TRL5, area-efficient 2-stage microcontroller core based on Ibex +as part of the CORE-V family of cores, along with a core complex (aka "coreplex") supporting Arm AMBA AHB-5 32-bit bus interfaces, +debug and interrupts. + The scope of the project consists of detailing which of the Ibex parameters are being removed, or verified, or neither verified or removed (left for future work). Completing design enhancements and integration of the interfaces into the core complex. Completing verification and documentation. + +## Components of the Project +### Component 1a "RTL design of the core". + RTL design of the Core starting from Ibex with the following features: + E - Base Integer Instruction Set (embedded) with 16, 32-bit general-purpose registers + I - Base Integer Instruction Set, with 32, 32-bit general-purpose registers + M - Standard Extension for Integer Multiplication and Division + C - Standard Extension for Compressed 16-bit Instructions + User Mode and Machine Mode + Harvard memory OBI bus interfaces + CV32E40P-like interrupt interface (Open Titan CLIC) + Cleaning Ibex RTL of unused parameters + Exposing privilege pins (privilege CSR bits are exposed as bus attribute signals) + Modification to make OBI-compliant bus interfaces. + Adding and extending the rvfi interface + Expose privilege pins as bus address phase attributes + CV32E40P-like Sleep unit + +### Component 1b "RTL design of the core complex". + Integrating interrupt controller - (Open Titan CLIC). + Integrating debug interface - similar to E40P + Integrating OBI2AHB bus bridges + +### Component 2 "Documentation". + - Create core spec from existing Ibex documentation + - Create core complex specification + - Create verification plan and reports + +### Component 3 "Verification of core complex" + - Based on core-v-verif environment + - Verification of the Core ISA configurations: RV32IMC, RV32EMC + - Verification of the Core Complex: DUT0 with RV32IMC, DUT1 with RV32EMC + + +## Summary of market or input requirements: +This project is intended to support embedded applications where, for example, +a state machine based implementation might otherwise be used. Additionally, this core +is targeted for use in applications requiring a small 32-bit processing element. +The core supports the RV32{E,I}MC instruction sets. + +### Known market/project requirements at PL gate +### Potential future enhancements for future project phases +* Zce static code size reduction opcode extension +* Supporting 2 pin compressed JTAG (CJTAG) debug interface +* Investigation of a "tiny FPU " implemention + * Targeted at sensor computations at the edge + * Having FP would be useful for these and other computations +* Low granularity Physical Memory Protection (PMP) module + +## Who would make use of OpenHW output + +Companies developing microcontroller-based embedded (sub)systems or devices. + +## Summary of Timeline + + * Start: 2021Q4 + * Use Ibex Core Specification + * Create Core Complex Specification - End of 2022Q1 + * Complete design / integration - End of 2022Q2 + * Create Core Complex Verification plan and verification spec - End of 2022Q2 + * Execute verification plan to completion - 2022Q4 + * Document detailed completion including reviews - 2022Q4 + + +## Explanation of why OpenHW should do this project + +* A 32 bit microcontroller is viewed as the appropriate low-end programmable core to replace state machine based implementations. +* It is the smallest RISC-V core design and includes standard Debug and ISA, with access to all the software enablement tools included in the CORE-V ecosystem. +* Small size and low power are the key hardware metrics. +* The starting point is Ibex, but Ibex does not include everything needed, such as OBI. It also includes many unneeded paramemters, + which may cause unnecessary verification and maintenance complications. +* The use of Arm AMBA-AHB buses supports the (re)use of many existing 32-bit IP modules, including peripherals, such as crytography devices. +* It is important for OpenHW members to exert control over the features as part of the CORE-V family. + +Overall, the CVE20 core augments the CORE-V family of 32 bit cores with a needed low-end microcontroller. + +## Industry landscape: description of competing, alternative, or related efforts in the industry + +Ibex - from LowRISC +SNITCH - from ETH Zurich - single pipeline, low complexity meant to offload to vector units +Arm Cortex-M0+ - from Arm + +## OpenHW Members/Participants committed to participate + +* Intrinsix - Design and Verification of core-complex, Core Verification +* NXP - Architecture definition, Core Design, Core Verification +* Imperas - Supply Imperas reference model, engineering support and expertise +* Embecosm - Provide tool enablement (SW tools: compilers, assembler/linker, etc.) +* ETH Zurich - (Davide Schiavone) Provide design guidance and contribute RTL design edits + +## Project Leader(s) +### Technical Project Leader(s) +At Project Launch, co-led by +* Lee Hoff, Intrinsix +* Joe Circello, NXP + +### Project Manager, if a PM is designated +None designated. + +## Project Documents +### Project Planning Documents + Detailed project plan + RTL Freeze checklist + +### Project Output Documents + Core specification + Core complex specification + Verification plan + Verification report + + +## List of project technical outputs + Verified RTL for Core and Core Complex (RV32IMC and RV32EMC) + Verification environment including test cases + Documentation + +### Feature Requirements +*Features are more granular than Components.* +*For SW porting projects, this list serves as the detailed project reference for features* +*For IP Cores or more complext projects, a user manual with requirements specification is produced at the PA gate, which may supercede this list of features* + +#### Feature 1 + Decide on features available to user and not available + Configuration of parameters (what is being verified in this project) + Future considerations of what is carried forward +#### Feature 2 + + +## External dependencies +*These are external factors on which the project depends, such as external standards ratification, external technology input, etc.* +*None currently identified* + +## OpenHW TGs Involved +*Cores TG, Verification TG* + +## Resource Requirements +*This is a list of major resources/people required to implement the project and indication of whether the resources are available* + +Core Design RTL +-> NXP and Intrinsix resources would need guidance from Davide Schiavone + +Core Complex RTL +-> 1-2 resources for 3 months until end of 2Q +-> Core Complex is to be handled by NXP and Intrinsix + + +Core Verification +Core Complex Verification + +.> 3-4 FTE resources for (3Q + 4Q) of 2022 +-> Intrinsix (USA) and NXP (Europe) resources + +Documentation +-> covered as per deliverables above + +Technical Project Management +-> potentially covered through NXP and Intrinsix especially by a verification leader +-> A committer would be needed, and the above person could do that + + +### Engineering resource supplied by members - requirement and availability +### OpenHW engineering staff resource plan: requirement and availability +discussed above + +### Marketing resource - requirement and availability +### Funding for project aspects - requirement and availability + +## Architecture and/or context diagrams +*Architecture (internal blocks and interconnections), and context (depiction of the the project content within its operational context), are both encouraged where appropriate to depict functionality to both subject matter experts and to non-experts* +Nice to have but not yet available + +## Project license model + Solderpad License + +## Description of initial code contribution, if required + For the core, Initial RTL to be forked or cloned from Ibex. This decision is not yet made. + A CQ will be generated on the Ibex code. + For the core complex, +-- Interrupt (CLIC or CLINT) controller from OpenTitan +-- OBI to AHB bus gaskets from Intrinsix +-- not decided yet if we need a CQ on these elements. + Verification based on core-v-verif uvm environment + + +## Repository Requirements + Design and Documentation will use github under cv32e20 + Verification will use github under core-v-verif + +## Project distribution model +Project artifacts will be released under CORE-V Cores and available on openhw github + + +## Preliminary Project plan +*A full project plan is not required at PL. A preliminary plan, which can be for instance the schedule for completion of component or feature list, together with responsible resource, should be provided. Full details should be provided at PA gate.* + +see the timeline section above + + +## Steps to get to PA gate + +Get the repo in place + +Committer/contributor/repo/Git training for the teams at NXP and Intrinsix (2 hour session) + +Technical teams need to be named and start engaging + +Internal teams to NXP and Intrinsix should understand how to contribute code and navigate their company's policies to make contributions + +Target the April 2022 PA gate to have +- requirements specificaiton for both Core and Complex +- project plan and risk register with task list, names, start and stop dates AND/OR detailed backlog register + + +## Risk Register +*A list of known risks, for example external dependencies, and any mitigation strategy* diff --git a/program/Project-Descriptions-and-Plans/FORCE-RISCV/FORCE-RISCV-ISG-Feature-Descriptions-and-Project-Plan.md b/Project-Descriptions-and-Plans/FORCE-RISCV/FORCE-RISCV-ISG-Feature-Descriptions-and-Project-Plan.md old mode 100755 new mode 100644 similarity index 98% rename from program/Project-Descriptions-and-Plans/FORCE-RISCV/FORCE-RISCV-ISG-Feature-Descriptions-and-Project-Plan.md rename to Project-Descriptions-and-Plans/FORCE-RISCV/FORCE-RISCV-ISG-Feature-Descriptions-and-Project-Plan.md index 6223b7e87..d5df419bb --- a/program/Project-Descriptions-and-Plans/FORCE-RISCV/FORCE-RISCV-ISG-Feature-Descriptions-and-Project-Plan.md +++ b/Project-Descriptions-and-Plans/FORCE-RISCV/FORCE-RISCV-ISG-Feature-Descriptions-and-Project-Plan.md @@ -1,63 +1,63 @@ -# FORCE-RISCV ISG Feature Descriptions - -## Basic instructions sets RV32IMAFDC, RV64IMAFDC -Able to generate all these instructions either fully randomly or with flexible constraints applied on all operands. - -## Vector extension 0.9 -The complicated Vector extension will be support, able to randomly generate all vector instructions, also flexible constraints can be applied on all operands. - -The vector extension 1.0 will be planned and supported once the specification is released. - -## Application registers and CSR registers -Support all integer, floating point, vector registers and CSR registers. CSR access instructions can be used to target CSR read/writes. - -## Interactive generation mode -Generated instructions are simulated in the linked ISS shared object and enable the ISG to have full knowledge of the architecture states and memory states at all time, thus improve test generation quality. - -The work involved is mainly getting 32-bit to work in this mode. - -## Python scriptable test template -Powerful and extensible Python scriptable test template writing framework. - -The work involved is mainly adjusting the framework to work properly for 32-bit mode. - -## On-demand paging system with user exception control -Page descriptors are created on the fly, on demand. The user will be able to control whether to have certain exceptions or not, page descriptor attribute distributions, page size etc. - -The work involved is mainly support SV32 paging mode. - -## Exceptions and interrupt handling -Exception and interrupt handlers will be supplied to handle all exceptions/interrupts. There is also capability to allow users to specify their own handler if so desire using the hooks provided by the front-end Python framework. - -## MP/MT support for both 32-bit and 64-bit -Implement support for MP/MT test generation. - -## Advanced resource dependency for both 32-bit and 64-bit -Implement support for advanced resource dependency for both 32-bit and 64-bit modes. - -# FORCE-RISCV ISG Project Plan - -## The following features will be finished by end of November 2020. -- Basic instructions sets RV32IMAFDC, RV64IMAFDC -- Vector extension 0.9 -- Application registers and CSR registers - -## The following features will be finished by end of 2020 and reach milestone of a baseline usable 32-bit RISC-V ISG implementation -- The baseline 32-bit mode ISG does not have full virtual memory and exception handling support. But can generate all 32-bit instructions and all registers available. -- Interactive generation mode -- Python scriptable test template - -## The following features will be finished by end of Q1 2021 and reach milestone of a fully functional single core 32-bit RISC-V ISG implementation -- On-demand paging system with user exception control -- Exceptions and interrupt handling - -## The following features will be finished by end of Q2 2021 -- MP/MT support for both 32-bit and 64-bit -- Advanced resource dependency for both 32-bit and 64-bit - - -## On-going feature additions as requested by OpenHW Group members and broader open source community -New features will be requested by the open source community and implemented in an on-going fashion. - -## On-going feature additions as call-for due to RISC-V new extensions and/or extension version upgrades. -New features will be needed as RISC-V bring in new extensions and/or upgrade extensions. +# FORCE-RISCV ISG Feature Descriptions + +## Basic instructions sets RV32IMAFDC, RV64IMAFDC +Able to generate all these instructions either fully randomly or with flexible constraints applied on all operands. + +## Vector extension 0.9 +The complicated Vector extension will be support, able to randomly generate all vector instructions, also flexible constraints can be applied on all operands. + +The vector extension 1.0 will be planned and supported once the specification is released. + +## Application registers and CSR registers +Support all integer, floating point, vector registers and CSR registers. CSR access instructions can be used to target CSR read/writes. + +## Interactive generation mode +Generated instructions are simulated in the linked ISS shared object and enable the ISG to have full knowledge of the architecture states and memory states at all time, thus improve test generation quality. + +The work involved is mainly getting 32-bit to work in this mode. + +## Python scriptable test template +Powerful and extensible Python scriptable test template writing framework. + +The work involved is mainly adjusting the framework to work properly for 32-bit mode. + +## On-demand paging system with user exception control +Page descriptors are created on the fly, on demand. The user will be able to control whether to have certain exceptions or not, page descriptor attribute distributions, page size etc. + +The work involved is mainly support SV32 paging mode. + +## Exceptions and interrupt handling +Exception and interrupt handlers will be supplied to handle all exceptions/interrupts. There is also capability to allow users to specify their own handler if so desire using the hooks provided by the front-end Python framework. + +## MP/MT support for both 32-bit and 64-bit +Implement support for MP/MT test generation. + +## Advanced resource dependency for both 32-bit and 64-bit +Implement support for advanced resource dependency for both 32-bit and 64-bit modes. + +# FORCE-RISCV ISG Project Plan + +## The following features will be finished by end of November 2020. +- Basic instructions sets RV32IMAFDC, RV64IMAFDC +- Vector extension 0.9 +- Application registers and CSR registers + +## The following features will be finished by end of 2020 and reach milestone of a baseline usable 32-bit RISC-V ISG implementation +- The baseline 32-bit mode ISG does not have full virtual memory and exception handling support. But can generate all 32-bit instructions and all registers available. +- Interactive generation mode +- Python scriptable test template + +## The following features will be finished by end of Q1 2021 and reach milestone of a fully functional single core 32-bit RISC-V ISG implementation +- On-demand paging system with user exception control +- Exceptions and interrupt handling + +## The following features will be finished by end of Q2 2021 +- MP/MT support for both 32-bit and 64-bit +- Advanced resource dependency for both 32-bit and 64-bit + + +## On-going feature additions as requested by OpenHW Group members and broader open source community +New features will be requested by the open source community and implemented in an on-going fashion. + +## On-going feature additions as call-for due to RISC-V new extensions and/or extension version upgrades. +New features will be needed as RISC-V bring in new extensions and/or upgrade extensions. diff --git a/program/Project-Descriptions-and-Plans/FORCE-RISCV/FORCE-RISCV-ISG-preliminary-project-proposal.md b/Project-Descriptions-and-Plans/FORCE-RISCV/FORCE-RISCV-ISG-preliminary-project-proposal.md old mode 100755 new mode 100644 similarity index 100% rename from program/Project-Descriptions-and-Plans/FORCE-RISCV/FORCE-RISCV-ISG-preliminary-project-proposal.md rename to Project-Descriptions-and-Plans/FORCE-RISCV/FORCE-RISCV-ISG-preliminary-project-proposal.md diff --git a/program/Project-Descriptions-and-Plans/FORCE-RISCV/FORCE-RISCV-ISG-project-proposal.md b/Project-Descriptions-and-Plans/FORCE-RISCV/FORCE-RISCV-ISG-project-proposal.md old mode 100755 new mode 100644 similarity index 98% rename from program/Project-Descriptions-and-Plans/FORCE-RISCV/FORCE-RISCV-ISG-project-proposal.md rename to Project-Descriptions-and-Plans/FORCE-RISCV/FORCE-RISCV-ISG-project-proposal.md index 7973e13ab..a2714daf7 --- a/program/Project-Descriptions-and-Plans/FORCE-RISCV/FORCE-RISCV-ISG-project-proposal.md +++ b/Project-Descriptions-and-Plans/FORCE-RISCV/FORCE-RISCV-ISG-project-proposal.md @@ -1,142 +1,142 @@ -# OpenHW Project Proposal -# FORCE-RISCV ISG - - -## Summary of project -FORCE-RISCV ISG has been developed in Futurewei Technologies and delivered to OpenHW Group on June 12 2020. - -FORCE-RISCV is a powerful verification tool for RISC-V based CPU design, currently supports 64-bit version of RISC-V with RV64I, M, A, Zicsr, F, D, C extensions, Machine, Supervisor, User modes, dynamic ISS interaction, dynamic Virtual Memory management, loops, configurable state transition, powerful and extensible Python scriptable test template writing framework etc. Vector extension 0.9 support, full paging exception control and advanced memory sub-system verification features are in the work and nearly finished. - -Note that support for 32-bit RISC-V is not there yet, but it will be a major part of this project proposal and will be supported very soon. With 32-bit RISC-V support, many of the current OpenHW Group member's verification need will be satisfied with the powerful features provided by FORCE-RISCV. - -Additional features like MP/MT support and advanced resource dependency is also on the near term plan. - -### Summary of Timeline -- Preliminary Project Launch (PPL) in the OpenHW Group process is proposed for end September 2020 TWG. -- Project Launch (PL) in the OpenHW Group process is proposed for October 2020 TWG. -- Project Plan Available (PPA) is proposed for October 2020 TWG. -- 32-bit version support should be useable by end-of-year -- Fully functional 32-bit RISC-V ISG by end of Q1 2021. -- On-going feature additions will continue afterwards. - -## OpenHW Members/Participants committed to participate in FORCE-RISCV project -1. Futurewei Technologies. -2. Thales Group -3. Additional member support to be confirmed. - -## Technical Project Leader(s) (TPLs) -Jingliang (Leo) Wang - -## Project Manager (PM) -- Jingliang (Leo) Wang -- Duncan Bees / Mike Thompson - program management oversight - -## Project Documents -The following project documents will be created: -- Preliminary Project Proposal (this document) -- Project Proposal, an updated version of this document -- Project Plan -- Feature Description -- Build and Delivery Description - -## Summary of requirements -The present document gives a present snapshot of requirements and Preliminary Project Proposal. More detailed requirements will be available with Project Proposal. - -### Introduction -32-bit RISC-V support and additional new features for both 64-bit and 32-bit RISC-V. - -### Project requirements -1. Support for 32-bit RISC-V instructions. -2. Support for 32-bit RISC-V registers. -3. Support for 32-bit RISC-V virtual memory system. -4. Support for 32-bit RISC-V exception handling. -5. Support for 32-bit RISC-V front-end framework. -6. Support 32-bit RISC-V ISS standalone and shared library. -7. MP/MT support for both 32-bit and 64-bit RISC-V. -8. Advanced resource dependency for both 32-bit and 64-bit RISC-V. - -### Future enhancements: -9. Support for new RISC-V extensions and updates. -10. New features requested by OpenHW Group memebers and broader open source community. - -## Explanation of why OpenHW should do this project - -The following strengths of FORCE-RISCV are in comparison to other open source ISGs where FORCE-RISCV does it better, if we implement support for 32-bit RISC-V, your 32-bit RISC-V design will also benefit from the high quality test generation. - High degree of test configurability via extensive Python front-end APIs. - High quality of randomness with generate-and-step using the linked ISS library, able to achieve high density of interesting test features and reach high micro-architecture coverage requirements. - Generates ELF files directly, no dependency on external toolchain compilation, simplifies the simulation work-flow. - Great test generation speed, able to scale well for heavy MP/MT processor verification. Due to the origin of FORCE-RISCV from server-class CPU projects. - -Additional advanced features like MP/MT and resource dependency will meet the need of more complicated processor design that OpenHW Group might tackle in the future. - -## Industry landscape: description of competing, alternative, or related efforts in the industry - -RISCV-DV from Google is currently a very popular test generator for RISC-V designs. - -### Related efforts to be described -- Google's RISCV-DV released in Jan 23, 2019, 1 year and half before Futurewei Technologies' FORCE-RISCV open source and there is no other open source choices availabe. -- RISCV-DV has all/most basic functionalities that a open source RISC-V 64-bit/32-bit processor project would need. -- RISCV-DV lacks highly fine-grained control that FORCE-RISCV provide and due to not emulating generated instructions test generated are much too coarse to reach high coverage as the processor design get more complicated. -- RISCV-DV would be not possible to be extended further in features beyond certain point. -- Dependency on (customized) GCC toolchain. -- Needs commercial license for System Verilog compile/simulating tools to contribute. -- OpenHW Group don't have much influence on the project direction. - -## External dependencies -- Third party open source libraries/projects with BSD/Apache like/compatible license would need to be updated periodically (quarterly or bi-yearly) to keep up with upstream. - -## List of project outputs -- Buildable working source code supporting both 64-bit and 32-bit RISC-V. -- User manual. -- Examples and tutorials. -- Regression system. - -## TGs Impacted/Resource requirements -- This work will be planned and discussed in the Verification TG. The project plan will be produced by the project manager with assistance of Verification TG, and reviewed/approved in TWG. - -## OpenHW engineering staff resource plan: requirement and availability -- Duncan Bees / Mike Thompson - program management oversight - -## Engineering resource supplied by members - requirement and availability -- Futurewei Technologies will lead the engineering effort. -- We believe this project will benefit OpenHW CPU verification and the ecosystem as a whole. Other members can be involved as follows and increase their involvement as value of the project become more apparent to them: - Setting requirements and feature requests - Help with ISG development. - Help with ISG frontend test template and library development. - Use FORCE-RISCV in OpenHW Group projects, develop test templates for verification purpose and provide feedback. - -## OpenHW marketing resource - requirement and availability -- No additional resource requirements yet identified - -## Marketing resource supplied by members - requirement and availability -- No resource requirements yet identified - -## Funding supplied by OpenHW - requirement and availability -- No funding requirements yet identified - -## Funding supplied by members - requirement and availability -- No funding requirements yet identified - -## Architecture diagram -- Slides presented to TWG on 09/07/2020 contains architecgture diagram: https://github.com/openhwgroup/core-v-docs/blob/master/TWG/MeetingPresentations/2020-09-07%20FORCE-RISCV%20ISG%20-%20status.pdf - -## Who would make use of OpenHW output -CVA6 project will be able to start using FORCE-RISCV 64-bit version. -OpenHW Group members working on 64-bit and/or 32-bit RISC-V processor designs will directly benefit from the FORCE-RISCV with both 64-bit and 32-bit support in the long term. - -## Project license model -The project code will be using Apache 2.0 license. - -## Description of initial code contribution, if required -Initial code contribution has happened on June 12, 2020 from Futurewei Technologies. - -## Repository Structure -Current code repository: https://github.com/openhwgroup/force-riscv - -## Project distribution model -Distribute via OpenHW Group GitHub repository. - -## Project plan -More detailed project plan is available in a seperate file "FORCE-RISCV Feature Descriptions and Project Plan" - - +# OpenHW Project Proposal +# FORCE-RISCV ISG + + +## Summary of project +FORCE-RISCV ISG has been developed in Futurewei Technologies and delivered to OpenHW Group on June 12 2020. + +FORCE-RISCV is a powerful verification tool for RISC-V based CPU design, currently supports 64-bit version of RISC-V with RV64I, M, A, Zicsr, F, D, C extensions, Machine, Supervisor, User modes, dynamic ISS interaction, dynamic Virtual Memory management, loops, configurable state transition, powerful and extensible Python scriptable test template writing framework etc. Vector extension 0.9 support, full paging exception control and advanced memory sub-system verification features are in the work and nearly finished. + +Note that support for 32-bit RISC-V is not there yet, but it will be a major part of this project proposal and will be supported very soon. With 32-bit RISC-V support, many of the current OpenHW Group member's verification need will be satisfied with the powerful features provided by FORCE-RISCV. + +Additional features like MP/MT support and advanced resource dependency is also on the near term plan. + +### Summary of Timeline +- Preliminary Project Launch (PPL) in the OpenHW Group process is proposed for end September 2020 TWG. +- Project Launch (PL) in the OpenHW Group process is proposed for October 2020 TWG. +- Project Plan Available (PPA) is proposed for October 2020 TWG. +- 32-bit version support should be useable by end-of-year +- Fully functional 32-bit RISC-V ISG by end of Q1 2021. +- On-going feature additions will continue afterwards. + +## OpenHW Members/Participants committed to participate in FORCE-RISCV project +1. Futurewei Technologies. +2. Thales Group +3. Additional member support to be confirmed. + +## Technical Project Leader(s) (TPLs) +Jingliang (Leo) Wang + +## Project Manager (PM) +- Jingliang (Leo) Wang +- Duncan Bees / Mike Thompson - program management oversight + +## Project Documents +The following project documents will be created: +- Preliminary Project Proposal (this document) +- Project Proposal, an updated version of this document +- Project Plan +- Feature Description +- Build and Delivery Description + +## Summary of requirements +The present document gives a present snapshot of requirements and Preliminary Project Proposal. More detailed requirements will be available with Project Proposal. + +### Introduction +32-bit RISC-V support and additional new features for both 64-bit and 32-bit RISC-V. + +### Project requirements +1. Support for 32-bit RISC-V instructions. +2. Support for 32-bit RISC-V registers. +3. Support for 32-bit RISC-V virtual memory system. +4. Support for 32-bit RISC-V exception handling. +5. Support for 32-bit RISC-V front-end framework. +6. Support 32-bit RISC-V ISS standalone and shared library. +7. MP/MT support for both 32-bit and 64-bit RISC-V. +8. Advanced resource dependency for both 32-bit and 64-bit RISC-V. + +### Future enhancements: +9. Support for new RISC-V extensions and updates. +10. New features requested by OpenHW Group memebers and broader open source community. + +## Explanation of why OpenHW should do this project + +The following strengths of FORCE-RISCV are in comparison to other open source ISGs where FORCE-RISCV does it better, if we implement support for 32-bit RISC-V, your 32-bit RISC-V design will also benefit from the high quality test generation. + High degree of test configurability via extensive Python front-end APIs. + High quality of randomness with generate-and-step using the linked ISS library, able to achieve high density of interesting test features and reach high micro-architecture coverage requirements. + Generates ELF files directly, no dependency on external toolchain compilation, simplifies the simulation work-flow. + Great test generation speed, able to scale well for heavy MP/MT processor verification. Due to the origin of FORCE-RISCV from server-class CPU projects. + +Additional advanced features like MP/MT and resource dependency will meet the need of more complicated processor design that OpenHW Group might tackle in the future. + +## Industry landscape: description of competing, alternative, or related efforts in the industry + +RISCV-DV from Google is currently a very popular test generator for RISC-V designs. + +### Related efforts to be described +- Google's RISCV-DV released in Jan 23, 2019, 1 year and half before Futurewei Technologies' FORCE-RISCV open source and there is no other open source choices availabe. +- RISCV-DV has all/most basic functionalities that a open source RISC-V 64-bit/32-bit processor project would need. +- RISCV-DV lacks highly fine-grained control that FORCE-RISCV provide and due to not emulating generated instructions test generated are much too coarse to reach high coverage as the processor design get more complicated. +- RISCV-DV would be not possible to be extended further in features beyond certain point. +- Dependency on (customized) GCC toolchain. +- Needs commercial license for System Verilog compile/simulating tools to contribute. +- OpenHW Group don't have much influence on the project direction. + +## External dependencies +- Third party open source libraries/projects with BSD/Apache like/compatible license would need to be updated periodically (quarterly or bi-yearly) to keep up with upstream. + +## List of project outputs +- Buildable working source code supporting both 64-bit and 32-bit RISC-V. +- User manual. +- Examples and tutorials. +- Regression system. + +## TGs Impacted/Resource requirements +- This work will be planned and discussed in the Verification TG. The project plan will be produced by the project manager with assistance of Verification TG, and reviewed/approved in TWG. + +## OpenHW engineering staff resource plan: requirement and availability +- Duncan Bees / Mike Thompson - program management oversight + +## Engineering resource supplied by members - requirement and availability +- Futurewei Technologies will lead the engineering effort. +- We believe this project will benefit OpenHW CPU verification and the ecosystem as a whole. Other members can be involved as follows and increase their involvement as value of the project become more apparent to them: + Setting requirements and feature requests + Help with ISG development. + Help with ISG frontend test template and library development. + Use FORCE-RISCV in OpenHW Group projects, develop test templates for verification purpose and provide feedback. + +## OpenHW marketing resource - requirement and availability +- No additional resource requirements yet identified + +## Marketing resource supplied by members - requirement and availability +- No resource requirements yet identified + +## Funding supplied by OpenHW - requirement and availability +- No funding requirements yet identified + +## Funding supplied by members - requirement and availability +- No funding requirements yet identified + +## Architecture diagram +- Slides presented to TWG on 09/07/2020 contains architecgture diagram: https://github.com/openhwgroup/core-v-docs/blob/master/TWG/MeetingPresentations/2020-09-07%20FORCE-RISCV%20ISG%20-%20status.pdf + +## Who would make use of OpenHW output +CVA6 project will be able to start using FORCE-RISCV 64-bit version. +OpenHW Group members working on 64-bit and/or 32-bit RISC-V processor designs will directly benefit from the FORCE-RISCV with both 64-bit and 32-bit support in the long term. + +## Project license model +The project code will be using Apache 2.0 license. + +## Description of initial code contribution, if required +Initial code contribution has happened on June 12, 2020 from Futurewei Technologies. + +## Repository Structure +Current code repository: https://github.com/openhwgroup/force-riscv + +## Project distribution model +Distribute via OpenHW Group GitHub repository. + +## Project plan +More detailed project plan is available in a seperate file "FORCE-RISCV Feature Descriptions and Project Plan" + + diff --git a/program/Project-Descriptions-and-Plans/FreeRTOS/core-v-free-rtos-ppl.md b/Project-Descriptions-and-Plans/FreeRTOS/core-v-free-rtos-ppl.md similarity index 100% rename from program/Project-Descriptions-and-Plans/FreeRTOS/core-v-free-rtos-ppl.md rename to Project-Descriptions-and-Plans/FreeRTOS/core-v-free-rtos-ppl.md diff --git a/program/Project-Descriptions-and-Plans/LLVM-Toolchain/llvm-toolchain-ppl.md b/Project-Descriptions-and-Plans/LLVM-Toolchain/llvm-toolchain-ppl.md similarity index 100% rename from program/Project-Descriptions-and-Plans/LLVM-Toolchain/llvm-toolchain-ppl.md rename to Project-Descriptions-and-Plans/LLVM-Toolchain/llvm-toolchain-ppl.md diff --git a/program/Project-Descriptions-and-Plans/MCU-Verilator-Model/verilator-modeling-pl.md b/Project-Descriptions-and-Plans/MCU-Verilator-Model/verilator-modeling-pl.md similarity index 100% rename from program/Project-Descriptions-and-Plans/MCU-Verilator-Model/verilator-modeling-pl.md rename to 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program/Project-Descriptions-and-Plans/SDK/sdk-project-concept.md rename to Project-Descriptions-and-Plans/SDK/sdk-project-concept.md diff --git a/README.md b/README.md index 42ed7e774..23c5f7978 100644 --- a/README.md +++ b/README.md @@ -1,24 +1,33 @@ -# core-v-doc -Program and project level documentation for the OpenHW Group's set of CORE-V RISC-V cores. +# programs +Program and project level documentation for all of OpenHW Group's projects including CORE-V RISC-V cores.

Directory contents... + ### TWG Technical Working Group meeting minutes and presentations. -### cores -Architecture and Design documentation for the CORE-V cores. +### TG +Task Group monthly reports, meeting minutes and presentations. This comprises +#### cores-task-group +#### hw-task-group +#### verification-task-group + +Currently the sw-task-grouped is tracked in the core-v-sw repo. + +### OpenHW-Project-Descriptions-and-Plans +This contains one directory per OpenHW project. Each directory should contain gate materials for the project (Project Concept, Project Launch, Plan Approve, and Project Freeze) +Readers can use this information to see all OpenHW projects at a glance -### hw -Information about the hardware and software of the physical platforms built to demonstrate -the capabilities of the CORE-V cores. +### OpenHW-dashboard +This contains a markdown file with project dashboard information for OpenHW. This file is linked from the OpenHW website. -### program -Program Management. Check out the [Program Dashboard](https://github.com/openhwgroup/core-v-docs/blob/master/program/dashboard/Dashboard.md) to see what the OpenHW Group is up to. +### process +This contains OpenHW process and template documents, such as gate templates and RTL Freeze template. -### verif -Verification meeting slides and minutes, plus non-core-specific DV plans. +### Attendance-tracking +This contains attendance tracking for all OpenHW meetings. ## Issues and Troubleshooting -If you find any problems or issues with the documentation, please check out the [issue - tracker](https://github.com/openhwgroup/core-v-docs/issues) and create a new issue if your problem is +If you find any problems or issues with the structure or content of this repo, please check out the [issue + tracker](https://github.com/openhwgroup/programs/issues) and create a new issue if your problem is not yet tracked. diff --git a/cores/CORE-V_Roadmap_April06_2021.pptx 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a/cores/cv32e40p/meeting_minutes/Oct.10.2019.md b/TGs/cores-task-group/cv32e40p/meeting_minutes/Oct.10.2019.md similarity index 98% rename from cores/cv32e40p/meeting_minutes/Oct.10.2019.md rename to TGs/cores-task-group/cv32e40p/meeting_minutes/Oct.10.2019.md index 1433bdddc..faed3cb24 100644 --- a/cores/cv32e40p/meeting_minutes/Oct.10.2019.md +++ b/TGs/cores-task-group/cv32e40p/meeting_minutes/Oct.10.2019.md @@ -1,75 +1,75 @@ -Date: October 10, 2019 - -Attendees: - -Mike Thompson : (OpenHW) : mike@openhwgroup.org - -Davide Schiavonne (OpenHW) : davide@openhwgroup.org - -Arjan Bink (Silicon Labs) : Arjan.Bink@silabs.com - -Sebastian Ahmed (Silicon Labs) : Sebastian.Ahmed@silabs.com - -Steve Richmond (Silicon Labs) : Steve.Richmond@silabs.com - -Paul Zavalney (Silicon Labs) : Paul.Zavalney@silabs.com - - -- Introductions. Noteworthy: - - Mike is the director of engineering for the verification TG - - Davide is the director of engineering for the cores TG - - It was mentioned that Jim Parisien (not present) is the director of engineering for the platform TG - - Steve Richmond will the SiLabs verification TG representative - -- There was a general question on the goal of the meeting. - - The purpose is to define a strategy to have a production-usable RI5CY based cores - by the second half of 2020 and thus: - - Defining a E40P and E40 such that E40 is the longer term RISC-V compliant solution - whereas E40P would have opportunistic updates to align to to standards but be focused - as more of a verification completion effort - - We must judiciously select what changes we make to E40P and target the more comprehensive update to E40 - -- Proposal document walk through (Arjan + all) - - Only slide3 (table) was covered in the call. Arjan first walked through the items - - Discussion whether floating-point should be in the E40P since this had not been really verified (Davide) - - Sebastian mentioned that SiLabs has interest in floating point - - This is clearly a significant verificaiton project (more on this later) - - Arjan mentioned that HW loop adds interrupt latency (due to state saving) - - Davide raised concerns about making "legacy" PULP extensions paramaterized in E40 - - Preference to have E40 and E40P be different repos (makes sense. Re-visit at appropriate time) - - Davide mentioned that multicore clustering support needs to be discussed. This involves an event - unit IP and special barrier load/store instructions which allow the EU to stall & clock-gate cores to synchronize - - Concerns were mostly about the verification burden of this feature and applicability for an "E" core (embedded) - - Davide suggested there may be a couple of "simpler" options such as modifying the EU to deal with CLINT (need elaboration on this) - or just do some sort of SW only solution (e.g. memory semaphores) - - Davide stressed that we should really reduce the scope of new features and focus on verification due - to the (lacking/unknown) verificaiton coverage state - - The team discussed the possibility of moving the stack limit register to E40 for example - - Davide mentioned the recent bug activity coming from various efforts such as formal etc - -- Mike gave a "keeping it real" summary of the state of the verification coverage on RI5CY - - Currently the RI5CY is deemed not production ready (from a quantifiable verification perspective). The design - might very well be in good shape, but we can't measure it. - - Existing environments (such as the Google one) is "show and tell" quality - - Believes that the E40P as currently defined may be a tall ask to verify (need to clarify timeframe) - - Mike plans to do a detailed scrub (feature by feature level) in terms of what has already been verified - - As of today there is no viable/coordinate CI based verification environment for RI5CY - - Mike will start a series of update calls to define the state of the verification of RI5CY - - The group agreed this is the highest priority task right now before we can finalize feautres - - The team discussed that in fact making some of the RI5CY features compliant in E40P may in fact shorten the - verification scope as it provides opportunities to leverage standards based verification projects such as - models, formal etc. The verification landscape study will be critical in determining such opportunities and - thus possibly steering the adoption/re-factoring to standards - -Actions: -======== -- Mike : Schedule the start of a series of calls to update the team on the RI5CY "state of the (verification) union" -- Team : Based on further discussion and verification state finalize E40P target feature list by end of November -- Davide : Send more details on event unit and related barrier load/store instructions ("event load") -- Davide : Track parameterization/split-repo question -- Figure out how to use mattermost in the appropriate way to: - - Organize proposals and meeting minutes (unique channel per instance?) -- Figure out how to track open action items -- Document storage/organization - --------------------------------------------------------------------------------------------------- +Date: October 10, 2019 + +Attendees: + +Mike Thompson : (OpenHW) : mike@openhwgroup.org + +Davide Schiavonne (OpenHW) : davide@openhwgroup.org + +Arjan Bink (Silicon Labs) : Arjan.Bink@silabs.com + +Sebastian Ahmed (Silicon Labs) : Sebastian.Ahmed@silabs.com + +Steve Richmond (Silicon Labs) : Steve.Richmond@silabs.com + +Paul Zavalney (Silicon Labs) : Paul.Zavalney@silabs.com + + +- Introductions. Noteworthy: + - Mike is the director of engineering for the verification TG + - Davide is the director of engineering for the cores TG + - It was mentioned that Jim Parisien (not present) is the director of engineering for the platform TG + - Steve Richmond will the SiLabs verification TG representative + +- There was a general question on the goal of the meeting. + - The purpose is to define a strategy to have a production-usable RI5CY based cores + by the second half of 2020 and thus: + - Defining a E40P and E40 such that E40 is the longer term RISC-V compliant solution + whereas E40P would have opportunistic updates to align to to standards but be focused + as more of a verification completion effort + - We must judiciously select what changes we make to E40P and target the more comprehensive update to E40 + +- Proposal document walk through (Arjan + all) + - Only slide3 (table) was covered in the call. Arjan first walked through the items + - Discussion whether floating-point should be in the E40P since this had not been really verified (Davide) + - Sebastian mentioned that SiLabs has interest in floating point + - This is clearly a significant verificaiton project (more on this later) + - Arjan mentioned that HW loop adds interrupt latency (due to state saving) + - Davide raised concerns about making "legacy" PULP extensions paramaterized in E40 + - Preference to have E40 and E40P be different repos (makes sense. Re-visit at appropriate time) + - Davide mentioned that multicore clustering support needs to be discussed. This involves an event + unit IP and special barrier load/store instructions which allow the EU to stall & clock-gate cores to synchronize + - Concerns were mostly about the verification burden of this feature and applicability for an "E" core (embedded) + - Davide suggested there may be a couple of "simpler" options such as modifying the EU to deal with CLINT (need elaboration on this) + or just do some sort of SW only solution (e.g. memory semaphores) + - Davide stressed that we should really reduce the scope of new features and focus on verification due + to the (lacking/unknown) verificaiton coverage state + - The team discussed the possibility of moving the stack limit register to E40 for example + - Davide mentioned the recent bug activity coming from various efforts such as formal etc + +- Mike gave a "keeping it real" summary of the state of the verification coverage on RI5CY + - Currently the RI5CY is deemed not production ready (from a quantifiable verification perspective). The design + might very well be in good shape, but we can't measure it. + - Existing environments (such as the Google one) is "show and tell" quality + - Believes that the E40P as currently defined may be a tall ask to verify (need to clarify timeframe) + - Mike plans to do a detailed scrub (feature by feature level) in terms of what has already been verified + - As of today there is no viable/coordinate CI based verification environment for RI5CY + - Mike will start a series of update calls to define the state of the verification of RI5CY + - The group agreed this is the highest priority task right now before we can finalize feautres + - The team discussed that in fact making some of the RI5CY features compliant in E40P may in fact shorten the + verification scope as it provides opportunities to leverage standards based verification projects such as + models, formal etc. The verification landscape study will be critical in determining such opportunities and + thus possibly steering the adoption/re-factoring to standards + +Actions: +======== +- Mike : Schedule the start of a series of calls to update the team on the RI5CY "state of the (verification) union" +- Team : Based on further discussion and verification state finalize E40P target feature list by end of November +- Davide : Send more details on event unit and related barrier load/store instructions ("event load") +- Davide : Track parameterization/split-repo question +- Figure out how to use mattermost in the appropriate way to: + - Organize proposals and meeting minutes (unique channel per instance?) +- Figure out how to track open action items +- Document storage/organization + +-------------------------------------------------------------------------------------------------- diff --git a/cores/cva6/cva6_19_2_21.md b/TGs/cores-task-group/cva6/cva6_19_2_21.md similarity index 100% rename from cores/cva6/cva6_19_2_21.md rename to TGs/cores-task-group/cva6/cva6_19_2_21.md diff --git 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b/TGs/verification-task-group/Meetings/Imperas.md similarity index 100% rename from verif/MeetingMinutes/Imperas.md rename to TGs/verification-task-group/Meetings/Imperas.md diff --git a/verif/MeetingMinutes/Issues-Nov-11-2020-continuation-from-Nov-4-meeting.md b/TGs/verification-task-group/Meetings/Issues-Nov-11-2020-continuation-from-Nov-4-meeting.md similarity index 98% rename from verif/MeetingMinutes/Issues-Nov-11-2020-continuation-from-Nov-4-meeting.md rename to TGs/verification-task-group/Meetings/Issues-Nov-11-2020-continuation-from-Nov-4-meeting.md index c06349f42..f212a4e8c 100644 --- a/verif/MeetingMinutes/Issues-Nov-11-2020-continuation-from-Nov-4-meeting.md +++ b/TGs/verification-task-group/Meetings/Issues-Nov-11-2020-continuation-from-Nov-4-meeting.md @@ -1,44 +1,44 @@ -++ Issues Review - continuation meeting -Meeting on Nov 11, 2020 - -++ core-v-docs issues - -General discussions: -1) Do docs related issues gate RTL Freeze. Some debate, but current answer is yes. Some noted that processor companies may deal with this by having an alpha and beta RTL Freeze, where the first gate has open documentation issues. -2) Who has permission to apply labels on issues, close and resolve? Answer, committers with write access. - -Discussed: 16, 40, 78, 128 - -Issue 16 - Vplan for Custom Circuitry -Gating for RTL Freeze -Of several custom features in CV32e40p for which documentation was not available, one (Sleep interface) still gates RTL Freeze as a Vplan is not available. - -Issue 40 - The table formatting in the Verification Strategy is hard to read. This is a read the docs issue. A solution was identified and the issue is moving to closure. - -Issue 78 - Cycle counts for multiply and divide not correct in documentation -Gating for RTL Freeze. However this has been resolved after the meeting - -Issue 128- Update Debug Vplan to consider timing of debug_req_i assertion and de-assertion -Gates RTL Freeze. Oystein is adding some lines in the debug Vplan to the describe the timing of this signal. - -Not discussed as not related to verified components on CV32E40P - 48, 103, 122 - -++ core-v-cv32e40p - -Issue 550 - Implementations does not raise illegal instruction exceptions on machine-mode access to debug registers -This was transferred to core-v-docs as new issue 259 -Take discussion offline for resolution with protagonists - -Specific issue by issue discussion not undertaken, as it is believed that all the issues are open because of labelling strategy and not because they are open bugs. -For example, an issue with a label such as PULP_XPULP is implicitly WAIVED - -Concern that the CV32E40P issue label method is difficult to understand to repository "visitor" -Actions to deal with this: -1) create a pinned issue with issue labeling and filtering explained -2) document in user manual and in readme a record of issues list at time of the commit for RTL Freeze -These refer to (Architecture ID (marchid == machine archid in RISC-V specification), Implementation ID (mimpid, also defined by RISC-V CSR)) - - - - - +++ Issues Review - continuation meeting +Meeting on Nov 11, 2020 + +++ core-v-docs issues + +General discussions: +1) Do docs related issues gate RTL Freeze. Some debate, but current answer is yes. Some noted that processor companies may deal with this by having an alpha and beta RTL Freeze, where the first gate has open documentation issues. +2) Who has permission to apply labels on issues, close and resolve? Answer, committers with write access. + +Discussed: 16, 40, 78, 128 + +Issue 16 - Vplan for Custom Circuitry +Gating for RTL Freeze +Of several custom features in CV32e40p for which documentation was not available, one (Sleep interface) still gates RTL Freeze as a Vplan is not available. + +Issue 40 - The table formatting in the Verification Strategy is hard to read. This is a read the docs issue. A solution was identified and the issue is moving to closure. + +Issue 78 - Cycle counts for multiply and divide not correct in documentation +Gating for RTL Freeze. However this has been resolved after the meeting + +Issue 128- Update Debug Vplan to consider timing of debug_req_i assertion and de-assertion +Gates RTL Freeze. Oystein is adding some lines in the debug Vplan to the describe the timing of this signal. + +Not discussed as not related to verified components on CV32E40P - 48, 103, 122 + +++ core-v-cv32e40p + +Issue 550 - Implementations does not raise illegal instruction exceptions on machine-mode access to debug registers +This was transferred to core-v-docs as new issue 259 +Take discussion offline for resolution with protagonists + +Specific issue by issue discussion not undertaken, as it is believed that all the issues are open because of labelling strategy and not because they are open bugs. +For example, an issue with a label such as PULP_XPULP is implicitly WAIVED + +Concern that the CV32E40P issue label method is difficult to understand to repository "visitor" +Actions to deal with this: +1) create a pinned issue with issue labeling and filtering explained +2) document in user manual and in readme a record of issues list at time of the commit for RTL Freeze +These refer to (Architecture ID (marchid == machine archid in RISC-V specification), Implementation ID (mimpid, also defined by RISC-V CSR)) + + + + + diff --git a/verif/MeetingMinutes/NVIDIA.md b/TGs/verification-task-group/Meetings/NVIDIA.md similarity index 100% rename from verif/MeetingMinutes/NVIDIA.md rename to TGs/verification-task-group/Meetings/NVIDIA.md diff --git a/verif/MeetingMinutes/README.md b/TGs/verification-task-group/Meetings/README.md similarity index 100% rename from verif/MeetingMinutes/README.md rename to TGs/verification-task-group/Meetings/README.md diff --git a/verif/MeetingMinutes/SiliconLabs.md b/TGs/verification-task-group/Meetings/SiliconLabs.md similarity index 100% rename from verif/MeetingMinutes/SiliconLabs.md rename to TGs/verification-task-group/Meetings/SiliconLabs.md diff --git a/verif/MeetingMinutes/Thales.md b/TGs/verification-task-group/Meetings/Thales.md similarity index 100% rename from verif/MeetingMinutes/Thales.md rename to TGs/verification-task-group/Meetings/Thales.md diff --git a/verif/MeetingMinutes/VTG.md b/TGs/verification-task-group/Meetings/VTG.md similarity index 100% rename from verif/MeetingMinutes/VTG.md rename to TGs/verification-task-group/Meetings/VTG.md diff --git a/verif/MeetingMinutes/Verification-Issues-Meeting-Nov4-2020.md b/TGs/verification-task-group/Meetings/Verification-Issues-Meeting-Nov4-2020.md similarity index 97% rename from verif/MeetingMinutes/Verification-Issues-Meeting-Nov4-2020.md rename to TGs/verification-task-group/Meetings/Verification-Issues-Meeting-Nov4-2020.md index 113e5d559..e30de8ce5 100644 --- a/verif/MeetingMinutes/Verification-Issues-Meeting-Nov4-2020.md +++ b/TGs/verification-task-group/Meetings/Verification-Issues-Meeting-Nov4-2020.md @@ -1,89 +1,89 @@ -Meeting report - core-v-verif issues -Attendees: Duncan Bees, Mike Thompson, Steve Richmond, Arjan Bink, Greg Tumbush, John Martin, Lee Moore -The purpose of the meeting was to review open issues on core-v-verif and attempt to resolve them -Scribe: Duncan Bees - - -Issue #47 -- Issue: Update the XPULP compliance testsuite into the uvmt_cv32 CV32E40P verification environment -- Waived for RTL Freeze obvious reason - PULP features not supported in this release. -- General discussion about labeling strategy for Github issues. Are the labels associated with a tag, i.e. will labels made at the time of a tagged -- release stay as they are? -- (In cores repo, a different label system was used. A "PULP" label is used for "PULP" features. This is potentially more permanent. -- AI: Mike will find out what happens to issues on a tag - SUBSEQUENTLY - Mike determined that labels are not associated with a tag -- AI: Mike, when we do tag for RTL Freeze, we should have a document to describe issues - - -Issue #48 -- Similar to 47, this one is functional coverage – same waiving strategy as 47 - -Issue #50 – Task: ensure 100% coverage of ISA instructions -- This issue will be closed once ISA functional coverage is 100% complete - -- Note, the goal is not 100% functinoal coverage in a single run. We would however like to get as close to 100% as possible in a single run. - - -Issue #51 - - similar to #48 - Waived - - - -Issue #65 – Integrating existing tests in CV32 repo -- when we took over RI5CY repo there was a small example testbench. Basically a hello world testbench -- Arjan: remains value to designers. -- This specific issue is for integration of these tests into core-v-verif. -- This will NOT be done -Issue is now closed - -Issue #84 Need single-point-of-control for simulation timescale -- This is gating RTL Freeze -- This is a System Verilog enhancement -- May already be done - MT needs to check on this to see if it is done -- Would need to be run against every simulator to see if it is working properly - (needs assistance from several people) -- Chose option 1 Add simulator-specific timescale control to each simular-specific Makefile. -- MT to report back by end of this week - - -Issue #221 – ci_check does not correctly detect tool errors -- the python script for ci_check doesn’t correctly look at passes and failures and can erroneously report a pass -- We want this fixed -- Not a gating item – but maybe it should be - prefer not to Waive it -- MT will ask for help on python scripting to get this done -- input is YAML -- coding with python dictionaries involved - -Issue #248 – Compare failures due to stalls -- this is not gating -- we don’t want to lose the information -- will be WAIVED – we have a workaround in place - - -Issue #253 - Compliance test cases have mismatches in signature check -- This is gating RTL Freeze -- Make files compile the code, runs through the ISS, then looks for a second signature for an RTL simulation – which we don’t do at this stage. The make files from the compliance test suites don’t understand that. They are looking for a signature – we don’t produce that. -- MT will work with Lee to get the signature check working - - - -Issue #268 – CSR step and compare mistiming with random stalls -- similar to 248 – will be waived – not gating - -Issue #294 – Verilog compile fails on uvmt_cv32_tb.sv on commit 1e77175 using vcs simulator -- This is related to a bug in the Synopsys VCS simulator -- Opened by mtvaden -- this will be closed due to non-response on questions - -Issue #319 – Counters test-program fails in the presense of memory stalls -- prediction of the value in the counter falls apart in presence of memory stalls -- Solution will be that Arjan will split the test in two. -- Counter test case will be removed -- HPM counter will be relaxed to not fail on jump hazards -- Then, dedicated jump hazard test that will be run without wait states -- This can’t be WAIVED for completeness -- Arjan to modify test cases -- MT to integrate the test cases in regression - -cv32e40p – no gating issues -docs – gating issues - +Meeting report - core-v-verif issues +Attendees: Duncan Bees, Mike Thompson, Steve Richmond, Arjan Bink, Greg Tumbush, John Martin, Lee Moore +The purpose of the meeting was to review open issues on core-v-verif and attempt to resolve them +Scribe: Duncan Bees + + +Issue #47 +- Issue: Update the XPULP compliance testsuite into the uvmt_cv32 CV32E40P verification environment +- Waived for RTL Freeze obvious reason - PULP features not supported in this release. +- General discussion about labeling strategy for Github issues. Are the labels associated with a tag, i.e. will labels made at the time of a tagged +- release stay as they are? +- (In cores repo, a different label system was used. A "PULP" label is used for "PULP" features. This is potentially more permanent. +- AI: Mike will find out what happens to issues on a tag - SUBSEQUENTLY - Mike determined that labels are not associated with a tag +- AI: Mike, when we do tag for RTL Freeze, we should have a document to describe issues + + +Issue #48 +- Similar to 47, this one is functional coverage – same waiving strategy as 47 + +Issue #50 – Task: ensure 100% coverage of ISA instructions +- This issue will be closed once ISA functional coverage is 100% complete + +- Note, the goal is not 100% functinoal coverage in a single run. We would however like to get as close to 100% as possible in a single run. + + +Issue #51 - + similar to #48 - Waived + + + +Issue #65 – Integrating existing tests in CV32 repo +- when we took over RI5CY repo there was a small example testbench. Basically a hello world testbench +- Arjan: remains value to designers. +- This specific issue is for integration of these tests into core-v-verif. +- This will NOT be done +Issue is now closed + +Issue #84 Need single-point-of-control for simulation timescale +- This is gating RTL Freeze +- This is a System Verilog enhancement +- May already be done - MT needs to check on this to see if it is done +- Would need to be run against every simulator to see if it is working properly + (needs assistance from several people) +- Chose option 1 Add simulator-specific timescale control to each simular-specific Makefile. +- MT to report back by end of this week + + +Issue #221 – ci_check does not correctly detect tool errors +- the python script for ci_check doesn’t correctly look at passes and failures and can erroneously report a pass +- We want this fixed +- Not a gating item – but maybe it should be - prefer not to Waive it +- MT will ask for help on python scripting to get this done +- input is YAML +- coding with python dictionaries involved + +Issue #248 – Compare failures due to stalls +- this is not gating +- we don’t want to lose the information +- will be WAIVED – we have a workaround in place + + +Issue #253 - Compliance test cases have mismatches in signature check +- This is gating RTL Freeze +- Make files compile the code, runs through the ISS, then looks for a second signature for an RTL simulation – which we don’t do at this stage. The make files from the compliance test suites don’t understand that. They are looking for a signature – we don’t produce that. +- MT will work with Lee to get the signature check working + + + +Issue #268 – CSR step and compare mistiming with random stalls +- similar to 248 – will be waived – not gating + +Issue #294 – Verilog compile fails on uvmt_cv32_tb.sv on commit 1e77175 using vcs simulator +- This is related to a bug in the Synopsys VCS simulator +- Opened by mtvaden +- this will be closed due to non-response on questions + +Issue #319 – Counters test-program fails in the presense of memory stalls +- prediction of the value in the counter falls apart in presence of memory stalls +- Solution will be that Arjan will split the test in two. +- Counter test case will be removed +- HPM counter will be relaxed to not fail on jump hazards +- Then, dedicated jump hazard test that will be run without wait states +- This can’t be WAIVED for completeness +- Arjan to modify test cases +- MT to integrate the test cases in regression + +cv32e40p – no gating issues +docs – gating issues + diff --git a/verif/MeetingMinutes/emmicro-us.md b/TGs/verification-task-group/Meetings/emmicro-us.md similarity index 100% rename from verif/MeetingMinutes/emmicro-us.md rename to TGs/verification-task-group/Meetings/emmicro-us.md diff --git a/verif/CV32E40P/FormalVerificationPlan/CORE-V_VerifPlan_Template.xlsx b/TGs/verification-task-group/Project-Reports/CV32E40P/FormalVerificationPlan/CORE-V_VerifPlan_Template.xlsx similarity index 100% rename from verif/CV32E40P/FormalVerificationPlan/CORE-V_VerifPlan_Template.xlsx rename to TGs/verification-task-group/Project-Reports/CV32E40P/FormalVerificationPlan/CORE-V_VerifPlan_Template.xlsx diff --git a/verif/CV32E40P/FormalVerificationPlan/README.md b/TGs/verification-task-group/Project-Reports/CV32E40P/FormalVerificationPlan/README.md similarity index 100% rename from verif/CV32E40P/FormalVerificationPlan/README.md rename to TGs/verification-task-group/Project-Reports/CV32E40P/FormalVerificationPlan/README.md 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b/TWG-and-TG-Attendance-Tracking/Attendance-Tracking-Instructions.md similarity index 99% rename from program/TWG-and-TG-Attendance-Tracking/Attendance-Tracking-Instructions.md rename to TWG-and-TG-Attendance-Tracking/Attendance-Tracking-Instructions.md index 675bf3a47..3e15b33eb 100644 --- a/program/TWG-and-TG-Attendance-Tracking/Attendance-Tracking-Instructions.md +++ b/TWG-and-TG-Attendance-Tracking/Attendance-Tracking-Instructions.md @@ -1,129 +1,129 @@ -## TG Attendance Tracker Template - - -### Description -This file, AttendanceTemplate2020.md, provides a template for attendance tracking at OpenHW TWG and TG meetings. -Please send any feedback or suggestions to duncan@openhwgroup.org - - -The master table below is meant to be copied for use by committee (TWG/TG/MWG) chairs to create an initial attendance tracking file for each committee. -The master table contains company members and individuals in alphabetical order and a distinct column for each meeting. -The participants listed in the master table are only a subset, and new participants are expected to be added to this master table. -Each committee only needs to track attendance for its own members, so the master table can be edited down for each committee. - - -Note that eligibility to vote in each committee depends on meeting attendance, as described in the OpenHW bylaws. -https://www.openhwgroup.org/membership/openhw-group-bylaws-2019-10-16.pdf - - -### Instructions for Committee Chairs or co-Chairs: - -#### Create Attendance tracking file for your Committee -1. Copy the table below from the template and save it in plain text as TGName_Attendance_2020.md. For example TWG_Attendance_2020.md, TGCores_Attendance_2020.md, -TGVerification_Attendance_2020.md, etc. -2. After editing/updating the table for each meeting, upload the updated file to https://github.com/openhwgroup/core-v-docs/tree/master/program - - -#### To track and record attendance during each meeting -1. Edit the table header to add the date of the meeting you are tracking attendance for. Add new meetings sequentially with the latest meeting at the right of the table. -2. Add a new row for any new company or participant. -3. For meetings previous to the current meeting, leave the square blank for newly added participants. -4. Do a rollcall at the meeting start. For each individual, put a Y or N in the column for that meeting. -5. If an individual arrives late or leaves early, assign Y or N at chair's discretion (i.e. if meeting was substantially attended, assign Y). - -#### Columns -1. Company name -2. Person name -3. Header Date in format: year.month.day (e.g. 20.08.30) -3. Y if person attended, N if person did not attend, blank if unknown - -#### After the meeting -1. Upload the new version of TGName_Attendance_2020.md on Github at the above location. A pull request is not needed. - -#### Conducting polls -1. The attendance table is used to determine eligibility for any votes held during the meeting. The rules are described in Section 13.7 of the bylaws. -2. The attendance table is used to determine eligibility for any email ballots following the same rules. - - -**Member Attendance Master Table** - -| Company | Person |20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD| -|--------------------|------------------|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:| -| AB Open Ltd | | | | | | | | | | | | | | | | | | | | | | | -| Alibaba Group | Yunshai Shang | | | | | | | | | | | | | | | | | | | | | | -| Alibaba Group | Xiaoning Qi | | | | | | | | | | | | | | | | | | | | | | -| Ashling Micro. Ltd | | | | | | | | | | | | | | | | | | | | | | | -| Barcelona Sup.(BSC)| | | | | | | | | | | | | | | | | | | | | | | -| Bluespec Inc | Charlie Hauck | | | | | | | | | | | | | | | | | | | | | | -| BTA Dsgn Svcs Inc | | | | | | | | | | | | | | | | | | | | | | | -| CMC Microsystems | Kevin Dobie | | | | | | | | | | | | | | | | | | | | | | -| CMC Microsystems | H. Pollitt-Smith | | | | | | | | | | | | | | | | | | | | | | -| Ecole de Tech.Sup. | | | | | | | | | | | | | | | | | | | | | | | -| ECSPEC | | | | | | | | | | | | | | | | | | | | | | | -| EM Micro. US Inc | John Martin | | | | | | | | | | | | | | | | | | | | | | -| EM Micro. US Inc | David McConnell | | | | | | | | | | | | | | | | | | | | | | -| EM Micro. US Inc | Greg Tumbush | | | | | | | | | | | | | | | | | | | | | | -| EM Micro. US Inc | Greg Tumbush | | | | | | | | | | | | | | | | | | | | | | -| Embecosm | Jeremy Bennett | | | | | | | | | | | | | | | | | | | | | | -| ETH Zurich | | | | | | | | | | | | | | | | | | | | | | | -| Futurewei Tech. Inc| Jiangliang Wang | | | | | | | | | | | | | | | | | | | | | | -| Futurewei Tech. Inc| Hansheng Tan | | | | | | | | | | | | | | | | | | | | | | -| Global Foundries | | | | | | | | | | | | | | | | | | | | | | | -| GreenWaves Tech. | | | | | | | | | | | | | | | | | | | | | | | -| Hensoldt Cyber GmbH| Mass. Giacometti | | | | | | | | | | | | | | | | | | | | | | -| Hensoldt Cyber GmbH| Marco Sabatano | | | | | | | | | | | | | | | | | | | | | | -| Huawei | | | | | | | | | | | | | | | | | | | | | | | -| IAR Systems Grp. AB| | | | | | | | | | | | | | | | | | | | | | | -| Imperas Sw. Ltd | Simon Davidmann | | | | | | | | | | | | | | | | | | | | | | -| Imperas Sw. Ltd | Duncan Graham | | | | | | | | | | | | | | | | | | | | | | -| Imperas Sw. Ltd | Lee Moore | | | | | | | | | | | | | | | | | | | | | | -| Metrics Tech. Inc | | | | | | | | | | | | | | | | | | | | | | | -| Mitacs | Mel Chaar | | | | | | | | | | | | | | | | | | | | | | -| MNT Research GmbH | | | | | | | | | | | | | | | | | | | | | | | -| NVIDIA | | | | | | | | | | | | | | | | | | | | | | | -| NXP USA, Inc. | Vitor Eschholz | | | | | | | | | | | | | | | | | | | | | | -| NXP USA, Inc. | Vitor Sato | | | | | | | | | | | | | | | | | | | | | | -| NXP USA, Inc. | Jerry Zeng | | | | | | | | | | | | | | | | | | | | | | -| OneSpin | Sven Beyer | | | | | | | | | | | | | | | | | | | | | | -| OneSpin | Sal. Hetalani | | | | | | | | | | | | | | | | | | | | | | -| OneSpin | Nic. Tunsinschi | | | | | | | | | | | | | | | | | | | | | | -| OPERSYS Inc. | | | | | | | | | | | | | | | | | | | | | | | -| Pingtouge Semi.Ltd | | | | | | | | | | | | | | | | | | | | | | | -| Polytechnique Mtrl.| | | | | | | | | | | | | | | | | | | | | | | -| Praesum Comm. | | | | | | | | | | | | | | | | | | | | | | | -| Secure Thingz | | | | | | | | | | | | | | | | | | | | | | | -| Silicon Labs. Inc. | Sebastian Ahmed | | | | | | | | | | | | | | | | | | | | | | -| Silicon Labs. Inc. | Arjan Bink | | | | | | | | | | | | | | | | | | | | | | -| Silicon Labs. Inc. | Oystein Knauserud| | | | | | | | | | | | | | | | | | | | | | -| Silicon Labs. Inc. | A. Piovaccari | | | | | | | | | | | | | | | | | | | | | | -| Silicon Labs. Inc. | Steve Richmond | | | | | | | | | | | | | | | | | | | | | | -| Silicon Labs. Inc. | Paul Zavalney | | | | | | | | | | | | | | | | | | | | | | -| Symbiotic GmbH | Nina Engelhardt | | | | | | | | | | | | | | | | | | | | | | -| Thales | Jerome Quevremont| | | | | | | | | | | | | | | | | | | | | | -| Thales | Jean-Roch Coulon | | | | | | | | | | | | | | | | | | | | | | -| Univ. of Utah | | | | | | | | | | | | | | | | | | | | | | | -| Symbiotic GmbH | | | | | | | | | | | | | | | | | | | | | | | -| UltraSoC Tech. Ltd | | | | | | | | | | | | | | | | | | | | | | | -| Univ. of Bologna | | | | | | | | | | | | | | | | | | | | | | | -| Univ. of Ottawa | | | | | | | | | | | | | | | | | | | | | | | -| Univ. of Toronto | | | | | | | | | | | | | | | | | | | | | | | -| Verifai Inc. | | | | | | | | | | | | | | | | | | | | | | | -| VeriSilicon | Wayne Dai | | | | | | | | | | | | | | | | | | | | | | - -**Guest/Non-Member Attendance Table** - -| Company | Person |20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD| -|--------------------|------------------|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:| -| | | | | | | | | | | | | | | | | | | | | | | | -| | | | | | | | | | | | | | | | | | | | | | | | -| | | | | | | | | | | | | | | | | | | | | | | | - -**OpenHW Attendance Table** - -| Company | Person |20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD| -|--------------------|------------------|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:| -| OpenHW | Duncan Bees | | | | | | | | | | | | | | | | | | | | | | -| OpenHW | Rick O'Connor | | | | | | | | | | | | | | | | | | | | | | -| OpenHW | Davide Schiavone | | | | | | | | | | | | | | | | | | | | | | -| OpenHW | Mike Thompson | | | | | | | | | | | | | | | | | | | | | | -| OpenHW | Florian Zaruba | | | | | | | | | | | | | | | | | | | | | | +## TG Attendance Tracker Template + + +### Description +This file, AttendanceTemplate2020.md, provides a template for attendance tracking at OpenHW TWG and TG meetings. +Please send any feedback or suggestions to duncan@openhwgroup.org + + +The master table below is meant to be copied for use by committee (TWG/TG/MWG) chairs to create an initial attendance tracking file for each committee. +The master table contains company members and individuals in alphabetical order and a distinct column for each meeting. +The participants listed in the master table are only a subset, and new participants are expected to be added to this master table. +Each committee only needs to track attendance for its own members, so the master table can be edited down for each committee. + + +Note that eligibility to vote in each committee depends on meeting attendance, as described in the OpenHW bylaws. +https://www.openhwgroup.org/membership/openhw-group-bylaws-2019-10-16.pdf + + +### Instructions for Committee Chairs or co-Chairs: + +#### Create Attendance tracking file for your Committee +1. Copy the table below from the template and save it in plain text as TGName_Attendance_2020.md. For example TWG_Attendance_2020.md, TGCores_Attendance_2020.md, +TGVerification_Attendance_2020.md, etc. +2. After editing/updating the table for each meeting, upload the updated file to https://github.com/openhwgroup/core-v-docs/tree/master/program + + +#### To track and record attendance during each meeting +1. Edit the table header to add the date of the meeting you are tracking attendance for. Add new meetings sequentially with the latest meeting at the right of the table. +2. Add a new row for any new company or participant. +3. For meetings previous to the current meeting, leave the square blank for newly added participants. +4. Do a rollcall at the meeting start. For each individual, put a Y or N in the column for that meeting. +5. If an individual arrives late or leaves early, assign Y or N at chair's discretion (i.e. if meeting was substantially attended, assign Y). + +#### Columns +1. Company name +2. Person name +3. Header Date in format: year.month.day (e.g. 20.08.30) +3. Y if person attended, N if person did not attend, blank if unknown + +#### After the meeting +1. Upload the new version of TGName_Attendance_2020.md on Github at the above location. A pull request is not needed. + +#### Conducting polls +1. The attendance table is used to determine eligibility for any votes held during the meeting. The rules are described in Section 13.7 of the bylaws. +2. The attendance table is used to determine eligibility for any email ballots following the same rules. + + +**Member Attendance Master Table** + +| Company | Person |20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD| +|--------------------|------------------|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:| +| AB Open Ltd | | | | | | | | | | | | | | | | | | | | | | | +| Alibaba Group | Yunshai Shang | | | | | | | | | | | | | | | | | | | | | | +| Alibaba Group | Xiaoning Qi | | | | | | | | | | | | | | | | | | | | | | +| Ashling Micro. Ltd | | | | | | | | | | | | | | | | | | | | | | | +| Barcelona Sup.(BSC)| | | | | | | | | | | | | | | | | | | | | | | +| Bluespec Inc | Charlie Hauck | | | | | | | | | | | | | | | | | | | | | | +| BTA Dsgn Svcs Inc | | | | | | | | | | | | | | | | | | | | | | | +| CMC Microsystems | Kevin Dobie | | | | | | | | | | | | | | | | | | | | | | +| CMC Microsystems | H. Pollitt-Smith | | | | | | | | | | | | | | | | | | | | | | +| Ecole de Tech.Sup. | | | | | | | | | | | | | | | | | | | | | | | +| ECSPEC | | | | | | | | | | | | | | | | | | | | | | | +| EM Micro. US Inc | John Martin | | | | | | | | | | | | | | | | | | | | | | +| EM Micro. US Inc | David McConnell | | | | | | | | | | | | | | | | | | | | | | +| EM Micro. US Inc | Greg Tumbush | | | | | | | | | | | | | | | | | | | | | | +| EM Micro. US Inc | Greg Tumbush | | | | | | | | | | | | | | | | | | | | | | +| Embecosm | Jeremy Bennett | | | | | | | | | | | | | | | | | | | | | | +| ETH Zurich | | | | | | | | | | | | | | | | | | | | | | | +| Futurewei Tech. Inc| Jiangliang Wang | | | | | | | | | | | | | | | | | | | | | | +| Futurewei Tech. Inc| Hansheng Tan | | | | | | | | | | | | | | | | | | | | | | +| Global Foundries | | | | | | | | | | | | | | | | | | | | | | | +| GreenWaves Tech. | | | | | | | | | | | | | | | | | | | | | | | +| Hensoldt Cyber GmbH| Mass. Giacometti | | | | | | | | | | | | | | | | | | | | | | +| Hensoldt Cyber GmbH| Marco Sabatano | | | | | | | | | | | | | | | | | | | | | | +| Huawei | | | | | | | | | | | | | | | | | | | | | | | +| IAR Systems Grp. AB| | | | | | | | | | | | | | | | | | | | | | | +| Imperas Sw. Ltd | Simon Davidmann | | | | | | | | | | | | | | | | | | | | | | +| Imperas Sw. Ltd | Duncan Graham | | | | | | | | | | | | | | | | | | | | | | +| Imperas Sw. Ltd | Lee Moore | | | | | | | | | | | | | | | | | | | | | | +| Metrics Tech. Inc | | | | | | | | | | | | | | | | | | | | | | | +| Mitacs | Mel Chaar | | | | | | | | | | | | | | | | | | | | | | +| MNT Research GmbH | | | | | | | | | | | | | | | | | | | | | | | +| NVIDIA | | | | | | | | | | | | | | | | | | | | | | | +| NXP USA, Inc. | Vitor Eschholz | | | | | | | | | | | | | | | | | | | | | | +| NXP USA, Inc. | Vitor Sato | | | | | | | | | | | | | | | | | | | | | | +| NXP USA, Inc. | Jerry Zeng | | | | | | | | | | | | | | | | | | | | | | +| OneSpin | Sven Beyer | | | | | | | | | | | | | | | | | | | | | | +| OneSpin | Sal. Hetalani | | | | | | | | | | | | | | | | | | | | | | +| OneSpin | Nic. Tunsinschi | | | | | | | | | | | | | | | | | | | | | | +| OPERSYS Inc. | | | | | | | | | | | | | | | | | | | | | | | +| Pingtouge Semi.Ltd | | | | | | | | | | | | | | | | | | | | | | | +| Polytechnique Mtrl.| | | | | | | | | | | | | | | | | | | | | | | +| Praesum Comm. | | | | | | | | | | | | | | | | | | | | | | | +| Secure Thingz | | | | | | | | | | | | | | | | | | | | | | | +| Silicon Labs. Inc. | Sebastian Ahmed | | | | | | | | | | | | | | | | | | | | | | +| Silicon Labs. Inc. | Arjan Bink | | | | | | | | | | | | | | | | | | | | | | +| Silicon Labs. Inc. | Oystein Knauserud| | | | | | | | | | | | | | | | | | | | | | +| Silicon Labs. Inc. | A. Piovaccari | | | | | | | | | | | | | | | | | | | | | | +| Silicon Labs. Inc. | Steve Richmond | | | | | | | | | | | | | | | | | | | | | | +| Silicon Labs. Inc. | Paul Zavalney | | | | | | | | | | | | | | | | | | | | | | +| Symbiotic GmbH | Nina Engelhardt | | | | | | | | | | | | | | | | | | | | | | +| Thales | Jerome Quevremont| | | | | | | | | | | | | | | | | | | | | | +| Thales | Jean-Roch Coulon | | | | | | | | | | | | | | | | | | | | | | +| Univ. of Utah | | | | | | | | | | | | | | | | | | | | | | | +| Symbiotic GmbH | | | | | | | | | | | | | | | | | | | | | | | +| UltraSoC Tech. Ltd | | | | | | | | | | | | | | | | | | | | | | | +| Univ. of Bologna | | | | | | | | | | | | | | | | | | | | | | | +| Univ. of Ottawa | | | | | | | | | | | | | | | | | | | | | | | +| Univ. of Toronto | | | | | | | | | | | | | | | | | | | | | | | +| Verifai Inc. | | | | | | | | | | | | | | | | | | | | | | | +| VeriSilicon | Wayne Dai | | | | | | | | | | | | | | | | | | | | | | + +**Guest/Non-Member Attendance Table** + +| Company | Person |20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD| +|--------------------|------------------|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:| +| | | | | | | | | | | | | | | | | | | | | | | | +| | | | | | | | | | | | | | | | | | | | | | | | +| | | | | | | | | | | | | | | | | | | | | | | | + +**OpenHW Attendance Table** + +| Company | Person |20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD|20.MM.DD| +|--------------------|------------------|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:| +| OpenHW | Duncan Bees | | | | | | | | | | | | | | | | | | | | | | +| OpenHW | Rick O'Connor | | | | | | | | | | | | | | | | | | | | | | +| OpenHW | Davide Schiavone | | | | | | | | | | | | | | | | | | | | | | +| OpenHW | Mike Thompson | | | | | | | | | | | | | | | | | | | | | | +| OpenHW | Florian Zaruba | | | | | | | | | | | | | | | | | | | | | | diff --git a/program/TWG-and-TG-Attendance-Tracking/TGSoftware_Attendance_2020.md b/TWG-and-TG-Attendance-Tracking/TGSoftware_Attendance_2020.md similarity index 99% rename from program/TWG-and-TG-Attendance-Tracking/TGSoftware_Attendance_2020.md rename to TWG-and-TG-Attendance-Tracking/TGSoftware_Attendance_2020.md index 4f49f811a..440ac6de1 100644 --- a/program/TWG-and-TG-Attendance-Tracking/TGSoftware_Attendance_2020.md +++ b/TWG-and-TG-Attendance-Tracking/TGSoftware_Attendance_2020.md @@ -1,66 +1,66 @@ -## Software TG Attendance Tracker Template - -Only full meetings are shown. Subgroup meetings, joint meetings with other -groups are excluded. - -**Software TG Member Attendance Table** - -| Company | Person |20.05.11|20.06.08|20.07.13|20.08.10|20.09.14|20.10.12|20.11.09|20.12.14|20.MM.DD| -|--------------------|----------------------|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:| -| Alibaba Group | Yunshai Shang | Y | Y | Y | Y | Y | Y | Y | | | -| Ashling Micro. Ltd | Hugh O'Keefe | | | Y | Y | | | | | | -| Ashling Micro. Ltd | Roisin O'Keefe | | | | Y | | | Y | Y | | -| Ashling Micro. Ltd | Promodkumar CM | | | | Y | Y | Y | Y | Y | | -| Ashling Micro. Ltd | Rejeesh SB | | | Y | | | | | | | -| Ashling Micro. Ltd | Vinod appu | | | Y | | | Y | | | | -| CMC Microsystems | Hugh Polliitt-Smith | Y | Y | Y | Y | Y | Y | Y | Y | | -| Codeplay | Michael Wong | | | | | | | Y | Y | | -| Embecosm | Jeremy Bennett | Y | Y | Y | Y | Y | Y | Y | Y | | -| Embecosm | Mary Bennett | | | | Y | Y | Y | Y | | | -| Embecosm | Craig Blackmore | Y | Y | Y | Y | | | | | | -| Embecosm | Simon Cook | | | | | | | | Y | | -| Embecosm | Pietra Ferreira | | | | Y | Y | Y | Y | Y | | -| Embecosm | Philipp Krones | | | | | | | Y | Y | | -| Embecosm | Jessica Mills | | | | Y | Y | Y | Y | Y | | -| Embecosm | Paolo Savini | | Y | Y | | | | | | | -| Embecosm | Shteryana Shopova | | | | | | | | Y | | -| EMUS | John Martin | | | | | | Y | Y | | | -| ETH Zürich | Robert Balas | | | | | | | Y | Y | | -| ETH Zürich | Björn Forsberg | | | | | | | | Y | | -| Imperas | Simon Davidmann | | | | | Y | | | | | -| Futurewei | Liang Peng | | | | | | Y | | | | -| Futurewei | Jingliang (Leo) Wang | | | | | | Y | Y | Y | | -| NXP USA, Inc. | John Waite | | | | Y | | | | | | -| NXP USA, Inc. | Jerry Zeng | | Y | | | | | | | | -| PlatformIO | Ivan Kravets | | | | | | | Y | Y | | -| PlatformIO | Valerii Koval | | | | | | | Y | | | -| Quicklogic | Tim Saxe | | | | | | | | Y | | -| Silicon Labs. Inc. | Arjan Bink | Y | Y | | Y | | Y | | | | -| Silicon Labs. Inc. | Paul Zavalney | | Y | | | | | | | | -| Thales | Zbigniew Chamski | Y | Y | Y | Y | Y | Y | | | | -| Thales | Jean-Roch Coulon | | | | | | | | Y | | -| Thales | André Sintzoff | | | | | | Y | Y | Y | | -| Thales | Sébastien Jacq | | | | | | Y | | | | -| Univeristy Bologna | Nazareno Bruschi | | | | | | | | Y | | -| Univeristy Bologna | Enrico Tabanelli | | | | | | | | Y | | -| Univeristy Bologna | Giuseppe Tagliavini | | | | | | | | Y | | - -**Guest/Non-Member Attendance Table** - -| Company | Person |20.05.11|20.06.08|20.07.13|20.08.10|20.09.14|20.10.12|20.11.09|20.12.14|20.MM.DD| -|--------------------|----------------------|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:| -| Eclipse project | Alexander Fedorov | Y | Y | Y | Y | Y | | Y | Y | | -| Eclipse project | Frédŕic Desbiens | | | | | Y | | | Y | | -| Eclipse project | Brian King | | | | | | Y | | | | -| Publitek | Andrea Barnard | | | Y | | | | | | | - -**OpenHW Attendance Table** - -| Company | Person |20.05.11|20.06.08|20.07.13|20.08.10|20.09.14|20.10.12|20.11.09|20.12.14|20.MM.DD| -|--------------------|----------------------|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:| -| OpenHW | Duncan Bees | | | Y | Y | | Y | Y | Y | | -| OpenHW | Rick O'Connor | Y | | | | Y | | Y | Y | | -| OpenHW | Jim Parisien | Y | Y | | | | | | | | -| OpenHW | Davide Schiavone | | | | | | | | | | -| OpenHW | Mike Thompson | Y | Y | Y | Y | Y | | Y | Y | | -| OpenHW | Florian Zaruba | | | Y | Y | Y | Y | Y | Y | | +## Software TG Attendance Tracker Template + +Only full meetings are shown. Subgroup meetings, joint meetings with other +groups are excluded. + +**Software TG Member Attendance Table** + +| Company | Person |20.05.11|20.06.08|20.07.13|20.08.10|20.09.14|20.10.12|20.11.09|20.12.14|20.MM.DD| +|--------------------|----------------------|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:| +| Alibaba Group | Yunshai Shang | Y | Y | Y | Y | Y | Y | Y | | | +| Ashling Micro. Ltd | Hugh O'Keefe | | | Y | Y | | | | | | +| Ashling Micro. Ltd | Roisin O'Keefe | | | | Y | | | Y | Y | | +| Ashling Micro. Ltd | Promodkumar CM | | | | Y | Y | Y | Y | Y | | +| Ashling Micro. Ltd | Rejeesh SB | | | Y | | | | | | | +| Ashling Micro. Ltd | Vinod appu | | | Y | | | Y | | | | +| CMC Microsystems | Hugh Polliitt-Smith | Y | Y | Y | Y | Y | Y | Y | Y | | +| Codeplay | Michael Wong | | | | | | | Y | Y | | +| Embecosm | Jeremy Bennett | Y | Y | Y | Y | Y | Y | Y | Y | | +| Embecosm | Mary Bennett | | | | Y | Y | Y | Y | | | +| Embecosm | Craig Blackmore | Y | Y | Y | Y | | | | | | +| Embecosm | Simon Cook | | | | | | | | Y | | +| Embecosm | Pietra Ferreira | | | | Y | Y | Y | Y | Y | | +| Embecosm | Philipp Krones | | | | | | | Y | Y | | +| Embecosm | Jessica Mills | | | | Y | Y | Y | Y | Y | | +| Embecosm | Paolo Savini | | Y | Y | | | | | | | +| Embecosm | Shteryana Shopova | | | | | | | | Y | | +| EMUS | John Martin | | | | | | Y | Y | | | +| ETH Zürich | Robert Balas | | | | | | | Y | Y | | +| ETH Zürich | Björn Forsberg | | | | | | | | Y | | +| Imperas | Simon Davidmann | | | | | Y | | | | | +| Futurewei | Liang Peng | | | | | | Y | | | | +| Futurewei | Jingliang (Leo) Wang | | | | | | Y | Y | Y | | +| NXP USA, Inc. | John Waite | | | | Y | | | | | | +| NXP USA, Inc. | Jerry Zeng | | Y | | | | | | | | +| PlatformIO | Ivan Kravets | | | | | | | Y | Y | | +| PlatformIO | Valerii Koval | | | | | | | Y | | | +| Quicklogic | Tim Saxe | | | | | | | | Y | | +| Silicon Labs. Inc. | Arjan Bink | Y | Y | | Y | | Y | | | | +| Silicon Labs. Inc. | Paul Zavalney | | Y | | | | | | | | +| Thales | Zbigniew Chamski | Y | Y | Y | Y | Y | Y | | | | +| Thales | Jean-Roch Coulon | | | | | | | | Y | | +| Thales | André Sintzoff | | | | | | Y | Y | Y | | +| Thales | Sébastien Jacq | | | | | | Y | | | | +| Univeristy Bologna | Nazareno Bruschi | | | | | | | | Y | | +| Univeristy Bologna | Enrico Tabanelli | | | | | | | | Y | | +| Univeristy Bologna | Giuseppe Tagliavini | | | | | | | | Y | | + +**Guest/Non-Member Attendance Table** + +| Company | Person |20.05.11|20.06.08|20.07.13|20.08.10|20.09.14|20.10.12|20.11.09|20.12.14|20.MM.DD| +|--------------------|----------------------|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:| +| Eclipse project | Alexander Fedorov | Y | Y | Y | Y | Y | | Y | Y | | +| Eclipse project | Frédŕic Desbiens | | | | | Y | | | Y | | +| Eclipse project | Brian King | | | | | | Y | | | | +| Publitek | Andrea Barnard | | | Y | | | | | | | + +**OpenHW Attendance Table** + +| Company | Person |20.05.11|20.06.08|20.07.13|20.08.10|20.09.14|20.10.12|20.11.09|20.12.14|20.MM.DD| +|--------------------|----------------------|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:|:------:| +| OpenHW | Duncan Bees | | | Y | Y | | Y | Y | Y | | +| OpenHW | Rick O'Connor | Y | | | | Y | | Y | Y | | +| OpenHW | Jim Parisien | Y | Y | | | | | | | | +| OpenHW | Davide Schiavone | | | | | | | | | | +| OpenHW | Mike Thompson | Y | Y | Y | Y | Y | | Y | Y | | +| OpenHW | Florian Zaruba | | | Y | Y | Y | Y | Y | Y | | diff --git a/program/TWG-and-TG-Attendance-Tracking/TGSoftware_Attendance_2021.md b/TWG-and-TG-Attendance-Tracking/TGSoftware_Attendance_2021.md similarity index 100% rename from program/TWG-and-TG-Attendance-Tracking/TGSoftware_Attendance_2021.md rename to TWG-and-TG-Attendance-Tracking/TGSoftware_Attendance_2021.md diff --git a/program/TWG-and-TG-Attendance-Tracking/TGSoftware_Attendance_2022.md b/TWG-and-TG-Attendance-Tracking/TGSoftware_Attendance_2022.md similarity index 100% rename from program/TWG-and-TG-Attendance-Tracking/TGSoftware_Attendance_2022.md rename to TWG-and-TG-Attendance-Tracking/TGSoftware_Attendance_2022.md diff --git a/program/TWG-and-TG-Attendance-Tracking/TGVerification_Attendance_2020.md b/TWG-and-TG-Attendance-Tracking/TGVerification_Attendance_2020.md similarity index 100% rename from program/TWG-and-TG-Attendance-Tracking/TGVerification_Attendance_2020.md rename to TWG-and-TG-Attendance-Tracking/TGVerification_Attendance_2020.md diff --git a/program/TWG-and-TG-Attendance-Tracking/TGVerification_Attendance_2021.md b/TWG-and-TG-Attendance-Tracking/TGVerification_Attendance_2021.md similarity index 100% rename from program/TWG-and-TG-Attendance-Tracking/TGVerification_Attendance_2021.md rename to TWG-and-TG-Attendance-Tracking/TGVerification_Attendance_2021.md diff --git a/program/TWG-and-TG-Attendance-Tracking/TWG-Attendance.md b/TWG-and-TG-Attendance-Tracking/TWG-Attendance.md similarity index 100% rename from program/TWG-and-TG-Attendance-Tracking/TWG-Attendance.md rename to TWG-and-TG-Attendance-Tracking/TWG-Attendance.md diff --git a/program/TWG-and-TG-Attendance-Tracking/TWG_Attendance_2022-05-23.xlsx b/TWG-and-TG-Attendance-Tracking/TWG_Attendance_2022-05-23.xlsx similarity index 100% rename from program/TWG-and-TG-Attendance-Tracking/TWG_Attendance_2022-05-23.xlsx rename to TWG-and-TG-Attendance-Tracking/TWG_Attendance_2022-05-23.xlsx diff --git a/program/TWG-and-TG-Attendance-Tracking/TWG_Attendance_211214.xlsx b/TWG-and-TG-Attendance-Tracking/TWG_Attendance_211214.xlsx similarity index 100% rename from program/TWG-and-TG-Attendance-Tracking/TWG_Attendance_211214.xlsx rename to TWG-and-TG-Attendance-Tracking/TWG_Attendance_211214.xlsx diff --git a/program/dashboard/Dashboard_SpreadSheetFriendly.md b/dashboard/Dashboard_SpreadSheetFriendly.md similarity index 99% rename from program/dashboard/Dashboard_SpreadSheetFriendly.md rename to dashboard/Dashboard_SpreadSheetFriendly.md index 774d9e5ca..6d08f5ae8 100644 --- a/program/dashboard/Dashboard_SpreadSheetFriendly.md +++ b/dashboard/Dashboard_SpreadSheetFriendly.md @@ -1,72 +1,72 @@ -# OpenHW Project Dashboard - -Last Updated October 4 2022 - -## Status Key -**PC = Project Concept** -  ↓ -**PL = Project Launch** -  ↓ -**PA = Plan Approved** -  ↓ -**PF = Project Freeze** - - + -## Completed Projects with Status = PF -| Name | TRL Achieved | Status | TPL or PM | Repo | PC | PL | PA | PF | PF Estimate | Project Docs | RTD | Project Plan | Project Board | -| -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -| CORE-V CV32E40P | TRL 5 | PF | [David Schiavone](https://github.com/orgs/openhwgroup/people/davideschiavone)
+ [Arjan Binks](https://github.com/orgs/openhwgroup/people/Silabs-ArjanB) | [cv32e40p](https://github.com/openhwgroup/cv32e40p) | n/a | n/a | n/a | 2021.01.20(A) | 2021.01.20(A) | [CV32E40P Readme](https://github.com/openhwgroup/cv32e40p/blob/master/README.md) | [CV32E40P User Manual](https://readthedocs.com/projects/openhw-group-cv32e40p-user-manual/) | | | -| | | | | | | | | | | | | | | - -## Active CORES TG Projects -| Name | TRL Target | Status | TPL or PM | Repo | PC | PL | PA | PF | PF Estimate | Project Docs | RTD | Project Plan | Project Board | -| -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -| CORE-V CV32E40S | TRL 5 | PA | [Oystein Knauserud](https://github.com/silabs-oysteink) | [cv32e40s](https://github.com/openhwgroup/cv32e40s) | 21.02.22 (A) | 21.02.22 (A) | 21.03.22 (A) | | 2023 Q1 | [CV32E40S Combined PPL/PL](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV32E40S/CV32E40S-PPL.md)
+ [PA Slides](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV32E40S/CV32E40X_CV32E40S_project_plan.pdf) | [CV32E40S User Manual](https://readthedocs.com/projects/openhw-group-cv32e40s-user-manual/) | [PA Checklist](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV32E40S/CV32E40X_CV32E40S_PA.xlsx) | | -| CORE-V CV32E40X | TRL 5 | PA | [Oystein Knauserud](https://github.com/silabs-oysteink) | [cv32e40x](https://github.com/openhwgroup/cv32e40x) | 21.02.22 (A) | 21.02.22 (A) | 21.03.22 (A) | | | [CV32E40X Combined PPL/PL](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV32E40X/CV32E40X-PPL.md)
+ [PA Slides](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV32E40S/CV32E40X_CV32E40S_project_plan.pdf) | [CV32E40X User Manual](https://readthedocs.com/projects/openhw-group-cv32e40x-user-manual/) | [PA Checklist](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV32E40S/CV32E40X_CV32E40S_PA.xlsx) | | -| CORE-V CVA6 | TRL 5 | PA | [Jérôme Quévremont](https://github.com/orgs/openhwgroup/people/jquevremont) | [cva6](https://github.com/openhwgroup/cva6) | 20.09.28 (A) | 21.01.20(A) | 22.02.28(A) | | | [CVA6 PPL](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CVA6/CVA6-preliminary-project-proposal.md)
[CVA6 PL](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CVA6/CVA6-project-launch.pptx) | [CVA6 User Manual](https://readthedocs.com/projects/openhw-group-cva6-user-manual/) | [CVA6 PA](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CVA6/CVA6-plan-approved-2022.md) | [CVA6 Kanban Board](https://github.com/orgs/openhwgroup/projects/3) | -| CORE-V CV32E40PV2 | TRL 5 | PL | [Pascal Gouédo](https://github.com/pascalgouedo) | [cv32e40p](https://github.com/openhwgroup/cv32e40p) | 21.06.28 (A) | | | | | [CV32E40Pv2 Project Concept](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV32E40Pv2/Project_Concept_for_CV32E40Pv2_June-28.md)
+ [PC presentation](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-Project-Concept-June-28-2021.pptx)
+ [PL slides](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-Project-Launch-Nov-22-2021.pptx) | | [CV32E40Pv2 Task List at PL](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-task-list.xlsx) | | -| CORE-V CV32E20 | TRL 5 | PL | Lee Hoff
+ Joe Circello | [cve2](https://github.com/openhwgroup/cve2) | 21.06.28 (A) | 2022.02.28(A) | | | | [CV32E20 Project Concept](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CVE20/Project-Concept-for-CV32E20.md)
+ [CV32E20 Project Launch](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CVE20/Project-Launch-for-CV32E20-220209.md) | | | | -| CORE-V CV-X-IF | | PL | | [core-v-xif](https://github.com/openhwgroup/core-v-xif) | 21.06.28 (A) | 21.12.12 (A) | | | | [CV-X-IF Project Concept](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV-X-IF/CV_X_Interface_project_concept.pdf)
+[CV-X-IF Project Launch](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV-X-IF/CV_X_Interface_project_launch.pdf)| | [CV-X-IF User Manual](https://readthedocs.com/projects/openhw-group-core-v-xif/) | | | -| CORE-V CV32E41P | TRL 3 | PC | [Tariq Hurd](https://github.com/tariqkurd-repo) | | 21.06.28 (A) | | | | | [CV32E41P PC](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV32E41P/CV32E41P%20project%20proposal.md) | | | | -| CORE-V CVA5 | TRL 3 | PC | [Eric Matthews](https://github.com/e-matthews) | | | | | | | [CVA5 PC](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CORE-V%20CVA5/PC-Taiga-CVA5.md)
+ [Taiga TWG pres.](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CVA5/SFU_taiga_formal_overview_openhw-2021-28jun.pdf) | | | | -| CORE-V-L1DCACHE | TRL 5 | PC | César Fuguet | | 22.06.27 (A) | | | | | [CORE-V L1 DACHE PC](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CORE-V-L1-DCACHE/20220523-OHG-ProjectConcept-CEA_L1_Dcache.md) | | | | - -## Active HW TG Projects -| Name | TRL Target | Status | TPL or PM | Repo | PC | PL | PA | PF | PF Estimate | Project Docs | RTD | Project Plan | Project Board | -| -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -| CORE-V-MCU | TRL 7 (CPU) | PA | [Greg Martin](https://github.com/gmartin102)
+ [Hugh Pollitt-Smith](https://github.com/orgs/openhwgroup/people/hpollittsmith) | [core-v-mcu](https://github.com/openhwgroup/core-v-mcu) | 20.10.05 (A) | 21.04.26 (A) | 21.12.12 (A) | | | [Project Launch](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CORE-V%20MCU%20SoC/MCU%20PL%20Document.md)
+ [Plan Approved](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CORE-V%20MCU%20SoC/PA%20document%20Oct%2025%202021.md) | | [CORE-V MCU Planning Spreadsheet](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CORE-V%20MCU%20SoC/MCU%20SoC%20Project%20Plan%20at%20PL.xlsx) | [MCU Kanban Board](https://github.com/orgs/openhwgroup/projects/4) | -| CORE-V MCU VERILATOR MODEL | | PL | | [core-v-mcu](https://github.com/openhwgroup/core-v-mcu) | 21.03.22 (A) | 21.05.24 (A) | | | | [Verilator Modeling PL](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/Verilator%20Model/verilator-modeling-pl.md) | | | | -| CORE-V-MCU-DEVKIT | TRL 4 | PL | [Joseph Julicher](https://github.com/n9wxu) | [core-v-mcu devkit](https://github.com/openhwgroup/core-v-mcu-devkit) | 21.12.12 (A) | 22.06.27 (A) | | | | [Project Concept](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CORE-V-MCU-DEV-KIT/CORE-V_DEV-KIT_project_concept_approved.md)
+ [Project Launch](https://docs.google.com/document/d/15v-1zsUEahpGljZNWOrmNEDTp1RlQCiLntFuJ-Hcw0I/edit) | | | | -| CORE-V-TRUSTED-MCU | TRL 7 (CPU) | PC | Abdoulaye Berthe | | 22.07.25 (A) | | | | | [CORE-V-MCU2 Project Concept](https://docs.google.com/document/d/1nW9rFAFHhNkNi53khY3hhynXaHIm4OqJ/edit) | | | | - -## Active VERIFICATION TG Projects -| Name | TRL Target | Status | TPL or PM | Repo | PC | PL | PA | PF | PF Estimate | Project Docs | RTD | Project Plan | Project Board | -| -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -| FORCE-RISCV | | PL | Robert Chu (PM)
+ Jun Chen (TPL) | [force-riscv](https://github.com/openhwgroup/force-riscv) | 20.09.28 (A) | 20.10.26 (A) | | | | [Force-Riscv PC](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/FORCE-RISCV/FORCE-RISCV-ISG-preliminary-project-proposal.md)
+ [Force-Riscv PL](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/FORCE-RISCV/FORCE-RISCV-ISG-project-proposal.md) | | [Force-RiscV Feature List and Project Plan](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/FORCE-RISCV/FORCE-RISCV-ISG-Feature-Descriptions-and-Project-Plan.md) | | -| CORE-V-MCU-UVM | | PC | David Poulin | [core-v-verif](https://github.com/openhwgroup/core-v-verif) | 2022.02.28(A) | | | | | [MCU UVM Project Concept](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CORE-V-MCU-UVM/mcu_uvm_project_concept.md) | | | | -| CORE-V-COPRO VERIF | | PC | [Morris Imfeld](https://github.com/moimfeld) | | 22.06.27 (A) | | | | | [CORE-V-COPRO-VERIF PC](https://drive.google.com/drive/u/1/folders/1aKna8CIDdPWyBN8dTXdAlBUSOiGUj7LW) | | | | -| ADVANCED-RISC-V VERIFICATION METHODOLOGIES | | PC | Simon Davidmann | | 22.07.25 (A) | | | | | [ARVM PC](https://drive.google.com/file/d/1qmPsGV_N4kmc9zSqYOM-Rx2qwFpW-AmU/view) | | | | - -## Active SW TG Projects -| Name | TRL Target | Status | TPL or PM | Repo | PC | PL | PA | PF | PF Estimate | Project Docs | RTD | Project Plan | Project Board | -| -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -| CORE-V GNU TOOLS | | PC | | [corev-gcc](https://github.com/openhwgroup/corev-gcc) | 20.10.05 (A) | | | | | [CORE-V GNU Tools PPL](https://github.com/openhwgroup/core-v-docs/tree/master/program/Project-Descriptions-and-Plans/CORE-V-GNU-Tools) | | | | -| CORE-V LLVM TOOLS | | PC | [Zbigniew Chamski](https://github.com/PicoPET) | [corev-llvm-project](https://github.com/openhwgroup/corev-llvm-project) | | | | | | | | | | -| CORE-V FREERTOS | | PC | [Richard Barry](https://github.com/RichardBarry) | [core-v-freertos](https://github.com/openhwgroup/core-v-freertos)
+ [core-v-freertos-kernel](https://github.com/openhwgroup/core-v-freertos-kernel) | 20.11.30 (A) | | | | | [Free RTOS PPL](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/Free%20RTOS/core-v-free-rtos-ppl.md) | | | | -| CORE-V HAL | | PC | [Yunhai Shang](https://github.com/shangyunhai)
+[Vincent Cui](https://github.com/VincentCui632) | | | | | | | [HAL PC](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CORE-V-HAL/Project-Concept-HAL.md)
+ [HAL PC reqs. pres.](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CORE-V-HAL/Hardware%20-Abstraction-Layer-HAL-Requirements-for-PC.pptx) | | | | -| CORE-V MCU SDK | | PC | | | 21.09.27 (A) | | | | | [SDK Project Concept](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/SDK/sdk-project-concept.md) | | | | -| CORE-V QEMU | | PC | WeiWei Li | | 22.07.25 (A) | | | | | [CORE-V-QEMU PC](https://docs.google.com/document/d/1BmFUVWGLJzyFt5Nm4RERkf7QWk-yEoaVK88GeVNwWTY/edit#heading=h.8jmm43f40zju) | | | | - -## Active UNIVERSITY OUTREACH TG Projects -| Name | TRL Target | Status | TPL or PM | Repo | PC | PL | PA | PF | PF Estimate | Project Docs | RTD | Project Plan | Project Board | -| -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -| CORE-V VEC RESEARCH | TRL 3 | PC | ? + [Hugh Pollitt Smith](https://github.com/orgs/openhwgroup/people/hpollittsmith) | | | | | | | [core-v-VEC research ppl](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CORE-V%20VEC%20Research/PPL%20proposal%20for%20Core-V-VEC%20Research%20Project.md) | | | | - -## Active REGIONAL WORKING GROUPS Projects (Section in Construction) -| Name | TRL Target | Status | TPL or PM | Repo | PC | PL | PA | PF | PF Estimate | Project Docs | RTD | Project Plan | Project Board | -| -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | - -## Closed or Inactive Projects -| Name | TRL Target | Status | TPL or PM | Repo | PC | PL | PA | PF | PF Estimate | Project Docs | RTD | Project Plan | Project Board | -| -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -| CORE-V-IDE-CDT | | Discontinued (merged into CORE-V SDK) | | [core-v-ide-cdt](https://github.com/openhwgroup/core-v-ide-cdt) | | | | | | | | | | +# OpenHW Project Dashboard + +Last Updated October 4 2022 + +## Status Key +**PC = Project Concept** +  ↓ +**PL = Project Launch** +  ↓ +**PA = Plan Approved** +  ↓ +**PF = Project Freeze** + + + +## Completed Projects with Status = PF +| Name | TRL Achieved | Status | TPL or PM | Repo | PC | PL | PA | PF | PF Estimate | Project Docs | RTD | Project Plan | Project Board | +| -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | +| CORE-V CV32E40P | TRL 5 | PF | [David Schiavone](https://github.com/orgs/openhwgroup/people/davideschiavone)
+ [Arjan Binks](https://github.com/orgs/openhwgroup/people/Silabs-ArjanB) | [cv32e40p](https://github.com/openhwgroup/cv32e40p) | n/a | n/a | n/a | 2021.01.20(A) | 2021.01.20(A) | [CV32E40P Readme](https://github.com/openhwgroup/cv32e40p/blob/master/README.md) | [CV32E40P User Manual](https://readthedocs.com/projects/openhw-group-cv32e40p-user-manual/) | | | +| | | | | | | | | | | | | | | + +## Active CORES TG Projects +| Name | TRL Target | Status | TPL or PM | Repo | PC | PL | PA | PF | PF Estimate | Project Docs | RTD | Project Plan | Project Board | +| -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | +| CORE-V CV32E40S | TRL 5 | PA | [Oystein Knauserud](https://github.com/silabs-oysteink) | [cv32e40s](https://github.com/openhwgroup/cv32e40s) | 21.02.22 (A) | 21.02.22 (A) | 21.03.22 (A) | | 2023 Q1 | [CV32E40S Combined PPL/PL](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV32E40S/CV32E40S-PPL.md)
+ [PA Slides](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV32E40S/CV32E40X_CV32E40S_project_plan.pdf) | [CV32E40S User Manual](https://readthedocs.com/projects/openhw-group-cv32e40s-user-manual/) | [PA Checklist](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV32E40S/CV32E40X_CV32E40S_PA.xlsx) | | +| CORE-V CV32E40X | TRL 5 | PA | [Oystein Knauserud](https://github.com/silabs-oysteink) | [cv32e40x](https://github.com/openhwgroup/cv32e40x) | 21.02.22 (A) | 21.02.22 (A) | 21.03.22 (A) | | | [CV32E40X Combined PPL/PL](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV32E40X/CV32E40X-PPL.md)
+ [PA Slides](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV32E40S/CV32E40X_CV32E40S_project_plan.pdf) | [CV32E40X User Manual](https://readthedocs.com/projects/openhw-group-cv32e40x-user-manual/) | [PA Checklist](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV32E40S/CV32E40X_CV32E40S_PA.xlsx) | | +| CORE-V CVA6 | TRL 5 | PA | [Jérôme Quévremont](https://github.com/orgs/openhwgroup/people/jquevremont) | [cva6](https://github.com/openhwgroup/cva6) | 20.09.28 (A) | 21.01.20(A) | 22.02.28(A) | | | [CVA6 PPL](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CVA6/CVA6-preliminary-project-proposal.md)
[CVA6 PL](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CVA6/CVA6-project-launch.pptx) | [CVA6 User Manual](https://readthedocs.com/projects/openhw-group-cva6-user-manual/) | [CVA6 PA](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CVA6/CVA6-plan-approved-2022.md) | [CVA6 Kanban Board](https://github.com/orgs/openhwgroup/projects/3) | +| CORE-V CV32E40PV2 | TRL 5 | PL | [Pascal Gouédo](https://github.com/pascalgouedo) | [cv32e40p](https://github.com/openhwgroup/cv32e40p) | 21.06.28 (A) | | | | | [CV32E40Pv2 Project Concept](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV32E40Pv2/Project_Concept_for_CV32E40Pv2_June-28.md)
+ [PC presentation](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-Project-Concept-June-28-2021.pptx)
+ [PL slides](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-Project-Launch-Nov-22-2021.pptx) | | [CV32E40Pv2 Task List at PL](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV32E40Pv2/CV32E40Pv2-task-list.xlsx) | | +| CORE-V CV32E20 | TRL 5 | PL | Lee Hoff
+ Joe Circello | [cve2](https://github.com/openhwgroup/cve2) | 21.06.28 (A) | 2022.02.28(A) | | | | [CV32E20 Project Concept](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CVE20/Project-Concept-for-CV32E20.md)
+ [CV32E20 Project Launch](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CVE20/Project-Launch-for-CV32E20-220209.md) | | | | +| CORE-V CV-X-IF | | PL | | [core-v-xif](https://github.com/openhwgroup/core-v-xif) | 21.06.28 (A) | 21.12.12 (A) | | | | [CV-X-IF Project Concept](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV-X-IF/CV_X_Interface_project_concept.pdf)
+[CV-X-IF Project Launch](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV-X-IF/CV_X_Interface_project_launch.pdf)| | [CV-X-IF User Manual](https://readthedocs.com/projects/openhw-group-core-v-xif/) | | | +| CORE-V CV32E41P | TRL 3 | PC | [Tariq Hurd](https://github.com/tariqkurd-repo) | | 21.06.28 (A) | | | | | [CV32E41P PC](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CV32E41P/CV32E41P%20project%20proposal.md) | | | | +| CORE-V CVA5 | TRL 3 | PC | [Eric Matthews](https://github.com/e-matthews) | | | | | | | [CVA5 PC](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CORE-V%20CVA5/PC-Taiga-CVA5.md)
+ [Taiga TWG pres.](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CVA5/SFU_taiga_formal_overview_openhw-2021-28jun.pdf) | | | | +| CORE-V-L1DCACHE | TRL 5 | PC | César Fuguet | | 22.06.27 (A) | | | | | [CORE-V L1 DACHE PC](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CORE-V-L1-DCACHE/20220523-OHG-ProjectConcept-CEA_L1_Dcache.md) | | | | + +## Active HW TG Projects +| Name | TRL Target | Status | TPL or PM | Repo | PC | PL | PA | PF | PF Estimate | Project Docs | RTD | Project Plan | Project Board | +| -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | +| CORE-V-MCU | TRL 7 (CPU) | PA | [Greg Martin](https://github.com/gmartin102)
+ [Hugh Pollitt-Smith](https://github.com/orgs/openhwgroup/people/hpollittsmith) | [core-v-mcu](https://github.com/openhwgroup/core-v-mcu) | 20.10.05 (A) | 21.04.26 (A) | 21.12.12 (A) | | | [Project Launch](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CORE-V%20MCU%20SoC/MCU%20PL%20Document.md)
+ [Plan Approved](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CORE-V%20MCU%20SoC/PA%20document%20Oct%2025%202021.md) | | [CORE-V MCU Planning Spreadsheet](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CORE-V%20MCU%20SoC/MCU%20SoC%20Project%20Plan%20at%20PL.xlsx) | [MCU Kanban Board](https://github.com/orgs/openhwgroup/projects/4) | +| CORE-V MCU VERILATOR MODEL | | PL | | [core-v-mcu](https://github.com/openhwgroup/core-v-mcu) | 21.03.22 (A) | 21.05.24 (A) | | | | [Verilator Modeling PL](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/Verilator%20Model/verilator-modeling-pl.md) | | | | +| CORE-V-MCU-DEVKIT | TRL 4 | PL | [Joseph Julicher](https://github.com/n9wxu) | [core-v-mcu devkit](https://github.com/openhwgroup/core-v-mcu-devkit) | 21.12.12 (A) | 22.06.27 (A) | | | | [Project Concept](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CORE-V-MCU-DEV-KIT/CORE-V_DEV-KIT_project_concept_approved.md)
+ [Project Launch](https://docs.google.com/document/d/15v-1zsUEahpGljZNWOrmNEDTp1RlQCiLntFuJ-Hcw0I/edit) | | | | +| CORE-V-TRUSTED-MCU | TRL 7 (CPU) | PC | Abdoulaye Berthe | | 22.07.25 (A) | | | | | [CORE-V-MCU2 Project Concept](https://docs.google.com/document/d/1nW9rFAFHhNkNi53khY3hhynXaHIm4OqJ/edit) | | | | + +## Active VERIFICATION TG Projects +| Name | TRL Target | Status | TPL or PM | Repo | PC | PL | PA | PF | PF Estimate | Project Docs | RTD | Project Plan | Project Board | +| -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | +| FORCE-RISCV | | PL | Robert Chu (PM)
+ Jun Chen (TPL) | [force-riscv](https://github.com/openhwgroup/force-riscv) | 20.09.28 (A) | 20.10.26 (A) | | | | [Force-Riscv PC](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/FORCE-RISCV/FORCE-RISCV-ISG-preliminary-project-proposal.md)
+ [Force-Riscv PL](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/FORCE-RISCV/FORCE-RISCV-ISG-project-proposal.md) | | [Force-RiscV Feature List and Project Plan](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/FORCE-RISCV/FORCE-RISCV-ISG-Feature-Descriptions-and-Project-Plan.md) | | +| CORE-V-MCU-UVM | | PC | David Poulin | [core-v-verif](https://github.com/openhwgroup/core-v-verif) | 2022.02.28(A) | | | | | [MCU UVM Project Concept](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CORE-V-MCU-UVM/mcu_uvm_project_concept.md) | | | | +| CORE-V-COPRO VERIF | | PC | [Morris Imfeld](https://github.com/moimfeld) | | 22.06.27 (A) | | | | | [CORE-V-COPRO-VERIF PC](https://drive.google.com/drive/u/1/folders/1aKna8CIDdPWyBN8dTXdAlBUSOiGUj7LW) | | | | +| ADVANCED-RISC-V VERIFICATION METHODOLOGIES | | PC | Simon Davidmann | | 22.07.25 (A) | | | | | [ARVM PC](https://drive.google.com/file/d/1qmPsGV_N4kmc9zSqYOM-Rx2qwFpW-AmU/view) | | | | + +## Active SW TG Projects +| Name | TRL Target | Status | TPL or PM | Repo | PC | PL | PA | PF | PF Estimate | Project Docs | RTD | Project Plan | Project Board | +| -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | +| CORE-V GNU TOOLS | | PC | | [corev-gcc](https://github.com/openhwgroup/corev-gcc) | 20.10.05 (A) | | | | | [CORE-V GNU Tools PPL](https://github.com/openhwgroup/core-v-docs/tree/master/program/Project-Descriptions-and-Plans/CORE-V-GNU-Tools) | | | | +| CORE-V LLVM TOOLS | | PC | [Zbigniew Chamski](https://github.com/PicoPET) | [corev-llvm-project](https://github.com/openhwgroup/corev-llvm-project) | | | | | | | | | | +| CORE-V FREERTOS | | PC | [Richard Barry](https://github.com/RichardBarry) | [core-v-freertos](https://github.com/openhwgroup/core-v-freertos)
+ [core-v-freertos-kernel](https://github.com/openhwgroup/core-v-freertos-kernel) | 20.11.30 (A) | | | | | [Free RTOS PPL](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/Free%20RTOS/core-v-free-rtos-ppl.md) | | | | +| CORE-V HAL | | PC | [Yunhai Shang](https://github.com/shangyunhai)
+[Vincent Cui](https://github.com/VincentCui632) | | | | | | | [HAL PC](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CORE-V-HAL/Project-Concept-HAL.md)
+ [HAL PC reqs. pres.](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CORE-V-HAL/Hardware%20-Abstraction-Layer-HAL-Requirements-for-PC.pptx) | | | | +| CORE-V MCU SDK | | PC | | | 21.09.27 (A) | | | | | [SDK Project Concept](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/SDK/sdk-project-concept.md) | | | | +| CORE-V QEMU | | PC | WeiWei Li | | 22.07.25 (A) | | | | | [CORE-V-QEMU PC](https://docs.google.com/document/d/1BmFUVWGLJzyFt5Nm4RERkf7QWk-yEoaVK88GeVNwWTY/edit#heading=h.8jmm43f40zju) | | | | + +## Active UNIVERSITY OUTREACH TG Projects +| Name | TRL Target | Status | TPL or PM | Repo | PC | PL | PA | PF | PF Estimate | Project Docs | RTD | Project Plan | Project Board | +| -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | +| CORE-V VEC RESEARCH | TRL 3 | PC | ? + [Hugh Pollitt Smith](https://github.com/orgs/openhwgroup/people/hpollittsmith) | | | | | | | [core-v-VEC research ppl](https://github.com/openhwgroup/core-v-docs/blob/master/program/Project-Descriptions-and-Plans/CORE-V%20VEC%20Research/PPL%20proposal%20for%20Core-V-VEC%20Research%20Project.md) | | | | + +## Active REGIONAL WORKING GROUPS Projects (Section in Construction) +| Name | TRL Target | Status | TPL or PM | Repo | PC | PL | PA | PF | PF Estimate | Project Docs | RTD | Project Plan | Project Board | +| -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | + +## Closed or Inactive Projects +| Name | TRL Target | Status | TPL or PM | Repo | PC | PL | PA | PF | PF Estimate | Project Docs | RTD | Project Plan | Project Board | +| -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | -------------------- | +| CORE-V-IDE-CDT | | Discontinued (merged into CORE-V SDK) | | [core-v-ide-cdt](https://github.com/openhwgroup/core-v-ide-cdt) | | | | | | | | | | diff --git a/program/milestones/CV32E40P/README.md b/milestones/CV32E40P/README.md similarity index 100% rename from program/milestones/CV32E40P/README.md rename to milestones/CV32E40P/README.md diff --git a/program/milestones/CV32E40P/RTL_Freeze_v1.0.0/DesignChecklist.md b/milestones/CV32E40P/RTL_Freeze_v1.0.0/DesignChecklist.md similarity index 100% rename from program/milestones/CV32E40P/RTL_Freeze_v1.0.0/DesignChecklist.md rename to milestones/CV32E40P/RTL_Freeze_v1.0.0/DesignChecklist.md diff --git a/program/milestones/CV32E40P/RTL_Freeze_v1.0.0/Design_openissues.md b/milestones/CV32E40P/RTL_Freeze_v1.0.0/Design_openissues.md similarity index 100% rename from program/milestones/CV32E40P/RTL_Freeze_v1.0.0/Design_openissues.md rename to milestones/CV32E40P/RTL_Freeze_v1.0.0/Design_openissues.md diff --git a/program/milestones/CV32E40P/RTL_Freeze_v1.0.0/DocumentationChecklist.md b/milestones/CV32E40P/RTL_Freeze_v1.0.0/DocumentationChecklist.md similarity index 100% rename from program/milestones/CV32E40P/RTL_Freeze_v1.0.0/DocumentationChecklist.md rename to milestones/CV32E40P/RTL_Freeze_v1.0.0/DocumentationChecklist.md diff --git a/program/milestones/CV32E40P/RTL_Freeze_v1.0.0/Documentation_openissues.md b/milestones/CV32E40P/RTL_Freeze_v1.0.0/Documentation_openissues.md similarity index 100% rename from program/milestones/CV32E40P/RTL_Freeze_v1.0.0/Documentation_openissues.md rename to milestones/CV32E40P/RTL_Freeze_v1.0.0/Documentation_openissues.md diff --git a/program/milestones/CV32E40P/RTL_Freeze_v1.0.0/FormalVerificationChecklist.md b/milestones/CV32E40P/RTL_Freeze_v1.0.0/FormalVerificationChecklist.md similarity index 99% rename from program/milestones/CV32E40P/RTL_Freeze_v1.0.0/FormalVerificationChecklist.md rename to milestones/CV32E40P/RTL_Freeze_v1.0.0/FormalVerificationChecklist.md index 5af63dd27..64653bf0b 100644 --- a/program/milestones/CV32E40P/RTL_Freeze_v1.0.0/FormalVerificationChecklist.md +++ b/milestones/CV32E40P/RTL_Freeze_v1.0.0/FormalVerificationChecklist.md @@ -1,15 +1,15 @@ -## Formal Verification Checklist for Functional RTL Freeze -An item is "signed off" once the `Signed-off By` and `Sign-off Date` cells are filled in. `Signed-off By` should be an email address. If there is an Exception or Waiver, it should be captured as a GitHub issue in core-v-verif and the issue number recorded in the `Exceptions/Waiver/Comment` cell. - -| Category | Item | Sign-off Criteria | Signed-off By | Sign-off Date | Exceptions/Waivers/Comments | -| --------------------- | -------------------------------- | ------------------------------------------------------ | --------------------------- | ------------- | ------------------------------------------ | -| Verification Planning | RV32I Vplan | Completed, reviewed and up-issued per review | nicolae.tusinschi@onespin.com | 2020-12-10 | | -| Verification Planning | RV32C Vplan | Completed, reviewed and up-issued per review | nicolae.tusinschi@onespin.com | 2020-12-10 | | -| Verification Planning | RV32M Vplan | Completed, reviewed and up-issued per review | nicolae.tusinschi@onespin.com | 2020-12-10 | | -| Verification Planning | RV32Zicsr_Zifencei Vplan | Completed, reviewed and up-issued per review | nicolae.tusinschi@onespin.com | 2020-12-10 | | -| Verification Planning | RV32IMC Exceptions Vplan | Completed, reviewed and up-issued per review | nicolae.tusinschi@onespin.com | 2020-12-10 | | -| Verification Planning | Formal Testbench Cross-reference | Each item in Vplan cross-ref’ed to assertions | nicolae.tusinschi@onespin.com | 2020-12-10 | | -| Regression | Formal Testbench | Sign-Off criteria listed in formal vPlans per verification item | sven.beyer@onespin.com | 2020-12-18 | Partial results for M-Ext | -| Final Report | Axiomise RISC-V Formal Toolkit | Posted to GitHub | ashish.darbari@axiomise.com | 2020-12-03 | Filed in "Reports" directory | -| Final Report | Verification Plans | RV32: I,M,C,Zicsr_Zfencei, Xcpt vPlans in GitHub | nicolae.tusinschi@onespin.com | 2020-12-18 | | -| Final Report | Regression Results | Posted to Github | sven.beyer@onespin.com | 2020-12-18 | | +## Formal Verification Checklist for Functional RTL Freeze +An item is "signed off" once the `Signed-off By` and `Sign-off Date` cells are filled in. `Signed-off By` should be an email address. If there is an Exception or Waiver, it should be captured as a GitHub issue in core-v-verif and the issue number recorded in the `Exceptions/Waiver/Comment` cell. + +| Category | Item | Sign-off Criteria | Signed-off By | Sign-off Date | Exceptions/Waivers/Comments | +| --------------------- | -------------------------------- | ------------------------------------------------------ | --------------------------- | ------------- | ------------------------------------------ | +| Verification Planning | RV32I Vplan | Completed, reviewed and up-issued per review | nicolae.tusinschi@onespin.com | 2020-12-10 | | +| Verification Planning | RV32C Vplan | Completed, reviewed and up-issued per review | nicolae.tusinschi@onespin.com | 2020-12-10 | | +| Verification Planning | RV32M Vplan | Completed, reviewed and up-issued per review | nicolae.tusinschi@onespin.com | 2020-12-10 | | +| Verification Planning | RV32Zicsr_Zifencei Vplan | Completed, reviewed and up-issued per review | nicolae.tusinschi@onespin.com | 2020-12-10 | | +| Verification Planning | RV32IMC Exceptions Vplan | Completed, reviewed and up-issued per review | nicolae.tusinschi@onespin.com | 2020-12-10 | | +| Verification Planning | Formal Testbench Cross-reference | Each item in Vplan cross-ref’ed to assertions | nicolae.tusinschi@onespin.com | 2020-12-10 | | +| Regression | Formal Testbench | Sign-Off criteria listed in formal vPlans per verification item | sven.beyer@onespin.com | 2020-12-18 | Partial results for M-Ext | +| Final Report | Axiomise RISC-V Formal Toolkit | Posted to GitHub | ashish.darbari@axiomise.com | 2020-12-03 | Filed in "Reports" directory | +| Final Report | Verification Plans | RV32: I,M,C,Zicsr_Zfencei, Xcpt vPlans in GitHub | nicolae.tusinschi@onespin.com | 2020-12-18 | | +| Final Report | Regression Results | Posted to Github | sven.beyer@onespin.com | 2020-12-18 | | diff --git a/program/milestones/CV32E40P/RTL_Freeze_v1.0.0/IPChecklist.md b/milestones/CV32E40P/RTL_Freeze_v1.0.0/IPChecklist.md similarity index 99% rename from program/milestones/CV32E40P/RTL_Freeze_v1.0.0/IPChecklist.md rename to milestones/CV32E40P/RTL_Freeze_v1.0.0/IPChecklist.md index 51bb5b13f..050b05224 100644 --- a/program/milestones/CV32E40P/RTL_Freeze_v1.0.0/IPChecklist.md +++ b/milestones/CV32E40P/RTL_Freeze_v1.0.0/IPChecklist.md @@ -1,9 +1,9 @@ -## IP Checklist for Functional RTL Freeze -An item is "signed off" once the `Signed-off By` and `Sign-off Date` cells are filled in. `Signed-off By` should be an email address. If there is an Exception or Waiver, it should be captured as a GitHub issue in core-v-docs and the issue number recorded in the `Exceptions/Waiver/Comment` cell. - - -| Category | Item | Sign-off Criteria | Signed-off By | Sign-off Date | Exceptions/Waivers/Comments | -| ---------------- | ------------------------------------------------- | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | --------------------- | ---------- | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | -| IP Review | IP review on core-v-cv32e40p design repo | Eclipse “CQ” audit complete | duncan@openhwgroup.org | 2020-12-17 | https://dev.eclipse.org/ipzilla/show_bug.cgi?id=22444 | -| IP Review | IP review on core-v-verif verification repo | Eclipse “CQ” audit complete | duncan@openhwgroup.org | 2020-12-17 | https://dev.eclipse.org/ipzilla/show_bug.cgi?id=22415 | -| IP Review | IP audit on core-v-docs user documentation only | OpenHW Staff audit complete | duncan@openhwgroup.org | 2020-12-17 | [cv32e40p user manual](https://github.com/openhwgroup/core-v-docs/tree/master/cores/cv32e40p/user_manual/source) and [verification strategy](https://github.com/openhwgroup/core-v-docs/tree/master/verif/Common/CORE-V_Verification_Strategy/source) files have appropriate headers | +## IP Checklist for Functional RTL Freeze +An item is "signed off" once the `Signed-off By` and `Sign-off Date` cells are filled in. `Signed-off By` should be an email address. If there is an Exception or Waiver, it should be captured as a GitHub issue in core-v-docs and the issue number recorded in the `Exceptions/Waiver/Comment` cell. + + +| Category | Item | Sign-off Criteria | Signed-off By | Sign-off Date | Exceptions/Waivers/Comments | +| ---------------- | ------------------------------------------------- | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | --------------------- | ---------- | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | +| IP Review | IP review on core-v-cv32e40p design repo | Eclipse “CQ” audit complete | duncan@openhwgroup.org | 2020-12-17 | https://dev.eclipse.org/ipzilla/show_bug.cgi?id=22444 | +| IP Review | IP review on core-v-verif verification repo | Eclipse “CQ” audit complete | duncan@openhwgroup.org | 2020-12-17 | https://dev.eclipse.org/ipzilla/show_bug.cgi?id=22415 | +| IP Review | IP audit on core-v-docs user documentation only | OpenHW Staff audit complete | duncan@openhwgroup.org | 2020-12-17 | [cv32e40p user manual](https://github.com/openhwgroup/core-v-docs/tree/master/cores/cv32e40p/user_manual/source) and [verification strategy](https://github.com/openhwgroup/core-v-docs/tree/master/verif/Common/CORE-V_Verification_Strategy/source) files have appropriate headers | diff --git a/program/milestones/CV32E40P/RTL_Freeze_v1.0.0/README.md b/milestones/CV32E40P/RTL_Freeze_v1.0.0/README.md similarity index 100% rename from program/milestones/CV32E40P/RTL_Freeze_v1.0.0/README.md rename to milestones/CV32E40P/RTL_Freeze_v1.0.0/README.md diff --git a/program/milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/CV32E40P_Issue_Summary.xlsx b/milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/CV32E40P_Issue_Summary.xlsx similarity index 100% rename from program/milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/CV32E40P_Issue_Summary.xlsx rename to milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/CV32E40P_Issue_Summary.xlsx diff --git a/program/milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/Formal/Axiomise__Final_Update__3__Dec__2020-1.pdf b/milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/Formal/Axiomise__Final_Update__3__Dec__2020-1.pdf similarity index 100% rename from program/milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/Formal/Axiomise__Final_Update__3__Dec__2020-1.pdf rename to milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/Formal/Axiomise__Final_Update__3__Dec__2020-1.pdf diff --git a/program/milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/Formal/Axiomise__Key_Deliverables_Summary__2__Dec__2020.pdf b/milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/Formal/Axiomise__Key_Deliverables_Summary__2__Dec__2020.pdf similarity index 100% rename from program/milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/Formal/Axiomise__Key_Deliverables_Summary__2__Dec__2020.pdf rename to milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/Formal/Axiomise__Key_Deliverables_Summary__2__Dec__2020.pdf diff --git a/program/milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/Formal/OneSpin-CV32E-Results-11012021.pdf b/milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/Formal/OneSpin-CV32E-Results-11012021.pdf similarity index 100% rename from program/milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/Formal/OneSpin-CV32E-Results-11012021.pdf rename to milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/Formal/OneSpin-CV32E-Results-11012021.pdf diff --git a/program/milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/Formal/OneSpin-CV32E-Results-18122020.pdf b/milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/Formal/OneSpin-CV32E-Results-18122020.pdf similarity index 100% rename from program/milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/Formal/OneSpin-CV32E-Results-18122020.pdf rename to milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/Formal/OneSpin-CV32E-Results-18122020.pdf diff --git a/program/milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/README.md b/milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/README.md similarity index 100% rename from program/milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/README.md rename to milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/README.md diff --git a/program/milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/Simulation/README.md b/milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/Simulation/README.md similarity index 100% rename from program/milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/Simulation/README.md rename to milestones/CV32E40P/RTL_Freeze_v1.0.0/Reports/Simulation/README.md diff --git a/program/milestones/CV32E40P/RTL_Freeze_v1.0.0/SimulationVerificationChecklist.md b/milestones/CV32E40P/RTL_Freeze_v1.0.0/SimulationVerificationChecklist.md similarity index 100% rename from program/milestones/CV32E40P/RTL_Freeze_v1.0.0/SimulationVerificationChecklist.md rename to milestones/CV32E40P/RTL_Freeze_v1.0.0/SimulationVerificationChecklist.md diff --git a/program/milestones/CV32E40P/RTL_Freeze_v1.0.0/Verification_openissues.md b/milestones/CV32E40P/RTL_Freeze_v1.0.0/Verification_openissues.md similarity index 100% rename from program/milestones/CV32E40P/RTL_Freeze_v1.0.0/Verification_openissues.md rename to milestones/CV32E40P/RTL_Freeze_v1.0.0/Verification_openissues.md diff --git a/program/milestones/README.md b/milestones/README.md similarity index 100% rename from program/milestones/README.md rename to milestones/README.md diff --git a/program/milestones/templates/OpenHWGroup_Functional_RTL_Freeze_Template.xlsx b/milestones/templates/OpenHWGroup_Functional_RTL_Freeze_Template.xlsx similarity index 100% rename from program/milestones/templates/OpenHWGroup_Functional_RTL_Freeze_Template.xlsx rename to milestones/templates/OpenHWGroup_Functional_RTL_Freeze_Template.xlsx diff --git a/program/milestones/templates/OpenHWGroup_TRL3_for_COREV_RTL_IP_Template.xlsx b/milestones/templates/OpenHWGroup_TRL3_for_COREV_RTL_IP_Template.xlsx similarity index 100% rename from program/milestones/templates/OpenHWGroup_TRL3_for_COREV_RTL_IP_Template.xlsx rename to milestones/templates/OpenHWGroup_TRL3_for_COREV_RTL_IP_Template.xlsx diff --git a/program/process/Cores-Design-and-Verification-Projects-PA-Criteria-Master.xlsx b/process/Cores-Design-and-Verification-Projects-PA-Criteria-Master.xlsx similarity index 100% rename from program/process/Cores-Design-and-Verification-Projects-PA-Criteria-Master.xlsx rename to process/Cores-Design-and-Verification-Projects-PA-Criteria-Master.xlsx diff --git a/program/process/OpenHW-Group-IP-Core-RTL-Freeze-Checklist-and-Release-Process.md b/process/OpenHW-Group-IP-Core-RTL-Freeze-Checklist-and-Release-Process.md similarity index 97% rename from program/process/OpenHW-Group-IP-Core-RTL-Freeze-Checklist-and-Release-Process.md rename to process/OpenHW-Group-IP-Core-RTL-Freeze-Checklist-and-Release-Process.md index e2e900718..918c206eb 100644 --- a/program/process/OpenHW-Group-IP-Core-RTL-Freeze-Checklist-and-Release-Process.md +++ b/process/OpenHW-Group-IP-Core-RTL-Freeze-Checklist-and-Release-Process.md @@ -1,127 +1,127 @@ -# OpenHW Group IP Core - RTL Freeze Checklist and Release Process - -This document describes the release process used by OpenHW Group for IP cores projects. - -In this process, OpenHW validates that a set of RTL Freeze checklist tasks have been completed prior to release. -Checklist completion enables the creation and publishing of one or more "tags" on the project repositories. A consumer of the release accesses the tagged code associated with the release via the tags. OpenHW publishes the release name and description along with the release tags. - - -The following aspects of the release process are described in this document: -* Naming the RTL Freeze release -* Agree on RTL Freeze checklists, contents, and signoff criteria for a project -* Open a Github issue for the checklist signoff -* Complete (signoff) of all checklists associated -* Create a Github tag on each repo included in the release -* Close Github issue -* Publish the release description and the Github tag(s) - -## Naming the Release - -The RTL Freeze release is named with an alphanumberic string incorporating the version number. This name is used in release documentation, tag creation, checklist subdirectory name, and user documentation. -For example, the first RTL Freeze for 'cv32e40p' is named 'cv32e40p_v1.0.0'. -The numberic part of the string is inspired from https://semver.org/, i.e. -"MAJOR version when you make incompatible API changes, -MINOR version when you add functionality in a backwards compatible manner, and -PATCH version when you make backwards compatible bug fixes." - -## RTL Freeze Checklist Creation - -### Establishing and Storing the Checklist - -The checklist is established either at Project Plan Approved (PPA) Gate or at another early stage of the project. -Templates are available in the [core-v-docs/program/milestones/templates](https://github.com/openhwgroup/core-v-docs/tree/master/program/milestones/templates) subdirectory. - -To create a set of checklists for a project, the templates are reviewed and adapted for a particular project. - -Project specific checklists are created and stored in a project-specific subdirectory of the [core-v-docs/program/milestones](https://github.com/openhwgroup/core-v-docs/tree/master/program/milestones) subdirectory. -The name of the project release is used as the checklist subdirectory name, e.g. cv32e40p_v1.0.0 - -### Checklist(s) Description - -Each checklist has a series of rows and columns, with rows containing checklist item to be reviewed, and columns for: - -* Category -* Item -* Sign-off Criteria -* Signed-off By -* Sign-off Date -* Exceptions/Waivers/Comments - -When created, the "Sign-off Date" column is left blank. When both "Signed-off By" and "Sign-off Date" are filled in, that row has been signed off. - -### Meaning of Sign-off -The sign-off of each row item means that the person who has signed it off verifies that the task for that row has been done and the sign-off criterion is met. There is no specific quality metric associated with sign-off. - - - -## Using Github Issues to track the Milestone - -### RTL Freeze Milestone Issue - -At Project Launch, a single Github issue is opened for the RTL Freeze Milestone, in the RTL repository for the release. - -The RTL Freeze Milestone Issue text inlcludes -* The release name -* A pointer to a Checklist File Issue (see below) for each specific checklist file -* The tag name for all the repositories associated with the release - -The RTL Freeze Milestone Issue is assigned to the Technical Project Leader (TPL) or Project Manager (PM). - -### Checklist File Issues - -In addition to the RTL Freeze Milestone Issue, one Github issue per Checklist File is opened. -Each Checklist File Issue is assigned to a project member by the TPL or PM. - - - -## Sign-Off the Checklist(s) - -Updating the Checklist is done by any project member or OpenHW Staff member, in coordination with the Technical Project Leader or Project Manager. - -The "Signed-off By" field is filled in the email address of the person verifying that the task has been done and specified criterion is met. -As stated above, there is no specific quality metric associated with the sign-off. - -The "Signed-off Date", when filled in together with the "Signed-off By", verifies that the item has been signed off. - -The Checklist is updated by pull request. - - -## Create the Github Tag(s) - -The Technical Project Leader or Project Manager for the project verifies that the checklist(s) -have all been signed off. He or she then creates a tag on each repository associated with the release. -Therefore, in a multiple repository project, multiple tags are required. - -For example, the following three repositories tagged for cv32e40p: - -https://github.com/openhwgroup/cv32e40p. This is the repository containing the cv32e40p RTL code -https://github.com/openhwgroup/core-v-verif. This is the resository containing the cv32e40p testbench. -https://github.com/openhwgroup/core-v-docs. This is the repository containing the checklists themselves, as well as user docs. - - -The name of the tag on each repo should include the name of the release. - - - -## Close the Github Issues - -### Closing the Checklist File Issues -When the person assigned each Checklist File Issue has verified that that checklist row in that file has been signed off, he or she closes the issue. - -### Closing the RTL Freeze Milestone Issue -When the person assigned the RTL Freeze Issue has verified that -* each Checklist File Issue is closed -* the release tags are created and the tag names are written in the RTL Freeze issue - -he or she closes the RTL Freeze issue. - - - - -## Publish the Project Release - -The project release is published on the OpenHW website. The following information is published to enable users of the release to access the appropriate code: - -* Release Name -* Release description -* Associated Github tags on project repository(ies) +# OpenHW Group IP Core - RTL Freeze Checklist and Release Process + +This document describes the release process used by OpenHW Group for IP cores projects. + +In this process, OpenHW validates that a set of RTL Freeze checklist tasks have been completed prior to release. +Checklist completion enables the creation and publishing of one or more "tags" on the project repositories. A consumer of the release accesses the tagged code associated with the release via the tags. OpenHW publishes the release name and description along with the release tags. + + +The following aspects of the release process are described in this document: +* Naming the RTL Freeze release +* Agree on RTL Freeze checklists, contents, and signoff criteria for a project +* Open a Github issue for the checklist signoff +* Complete (signoff) of all checklists associated +* Create a Github tag on each repo included in the release +* Close Github issue +* Publish the release description and the Github tag(s) + +## Naming the Release + +The RTL Freeze release is named with an alphanumberic string incorporating the version number. This name is used in release documentation, tag creation, checklist subdirectory name, and user documentation. +For example, the first RTL Freeze for 'cv32e40p' is named 'cv32e40p_v1.0.0'. +The numberic part of the string is inspired from https://semver.org/, i.e. +"MAJOR version when you make incompatible API changes, +MINOR version when you add functionality in a backwards compatible manner, and +PATCH version when you make backwards compatible bug fixes." + +## RTL Freeze Checklist Creation + +### Establishing and Storing the Checklist + +The checklist is established either at Project Plan Approved (PPA) Gate or at another early stage of the project. +Templates are available in the [core-v-docs/program/milestones/templates](https://github.com/openhwgroup/core-v-docs/tree/master/program/milestones/templates) subdirectory. + +To create a set of checklists for a project, the templates are reviewed and adapted for a particular project. + +Project specific checklists are created and stored in a project-specific subdirectory of the [core-v-docs/program/milestones](https://github.com/openhwgroup/core-v-docs/tree/master/program/milestones) subdirectory. +The name of the project release is used as the checklist subdirectory name, e.g. cv32e40p_v1.0.0 + +### Checklist(s) Description + +Each checklist has a series of rows and columns, with rows containing checklist item to be reviewed, and columns for: + +* Category +* Item +* Sign-off Criteria +* Signed-off By +* Sign-off Date +* Exceptions/Waivers/Comments + +When created, the "Sign-off Date" column is left blank. When both "Signed-off By" and "Sign-off Date" are filled in, that row has been signed off. + +### Meaning of Sign-off +The sign-off of each row item means that the person who has signed it off verifies that the task for that row has been done and the sign-off criterion is met. There is no specific quality metric associated with sign-off. + + + +## Using Github Issues to track the Milestone + +### RTL Freeze Milestone Issue + +At Project Launch, a single Github issue is opened for the RTL Freeze Milestone, in the RTL repository for the release. + +The RTL Freeze Milestone Issue text inlcludes +* The release name +* A pointer to a Checklist File Issue (see below) for each specific checklist file +* The tag name for all the repositories associated with the release + +The RTL Freeze Milestone Issue is assigned to the Technical Project Leader (TPL) or Project Manager (PM). + +### Checklist File Issues + +In addition to the RTL Freeze Milestone Issue, one Github issue per Checklist File is opened. +Each Checklist File Issue is assigned to a project member by the TPL or PM. + + + +## Sign-Off the Checklist(s) + +Updating the Checklist is done by any project member or OpenHW Staff member, in coordination with the Technical Project Leader or Project Manager. + +The "Signed-off By" field is filled in the email address of the person verifying that the task has been done and specified criterion is met. +As stated above, there is no specific quality metric associated with the sign-off. + +The "Signed-off Date", when filled in together with the "Signed-off By", verifies that the item has been signed off. + +The Checklist is updated by pull request. + + +## Create the Github Tag(s) + +The Technical Project Leader or Project Manager for the project verifies that the checklist(s) +have all been signed off. He or she then creates a tag on each repository associated with the release. +Therefore, in a multiple repository project, multiple tags are required. + +For example, the following three repositories tagged for cv32e40p: + +https://github.com/openhwgroup/cv32e40p. This is the repository containing the cv32e40p RTL code +https://github.com/openhwgroup/core-v-verif. This is the resository containing the cv32e40p testbench. +https://github.com/openhwgroup/core-v-docs. This is the repository containing the checklists themselves, as well as user docs. + + +The name of the tag on each repo should include the name of the release. + + + +## Close the Github Issues + +### Closing the Checklist File Issues +When the person assigned each Checklist File Issue has verified that that checklist row in that file has been signed off, he or she closes the issue. + +### Closing the RTL Freeze Milestone Issue +When the person assigned the RTL Freeze Issue has verified that +* each Checklist File Issue is closed +* the release tags are created and the tag names are written in the RTL Freeze issue + +he or she closes the RTL Freeze issue. + + + + +## Publish the Project Release + +The project release is published on the OpenHW website. The following information is published to enable users of the release to access the appropriate code: + +* Release Name +* Release description +* Associated Github tags on project repository(ies) diff --git a/program/process/OpenHW-Project-Management-Framework.docx b/process/OpenHW-Project-Management-Framework.docx similarity index 100% rename from program/process/OpenHW-Project-Management-Framework.docx rename to process/OpenHW-Project-Management-Framework.docx diff --git a/program/process/PC_PL_Template_Markdown.md b/process/PC_PL_Template_Markdown.md similarity index 100% rename from program/process/PC_PL_Template_Markdown.md rename to process/PC_PL_Template_Markdown.md diff --git a/program/process/Project-Milestone-Process.md b/process/Project-Milestone-Process.md similarity index 97% rename from program/process/Project-Milestone-Process.md rename to process/Project-Milestone-Process.md index ad7d2da33..210be735e 100644 --- a/program/process/Project-Milestone-Process.md +++ b/process/Project-Milestone-Process.md @@ -1,70 +1,70 @@ -## OpenHW Group Project Milestone Process -The /milestone subdirectory contains the templates and checklist for OpenHW Group projects. - -The Project Milestone process described here is used by OpenHW members and staff to associate Github-tagged milestones with a set of checklists. -The checklist(s) when signed off, confirms that the established task list for the milestone has been completed. - - - -## Technical Milestones - -As per the OpenHW Project Management Framework, the set of project milestones is decided on a per-project basis at the Project Launch gate. -Each Project Milestone is associated with a Checklist(s). - -A Project Milestone typically signifies the completion of a project. -However, a Project Milestone could be used for intermediate checkpoints or releases as well. - -A core development would likely include an RTL Freeze milestone as a minimum. - - -## Process - -### Opening Github Issue - -At Project Launch, a Github issue is opened for each Project Milestone. -This issue(s) is closed when the Milestone(s) is reached. - -### Establishing the Checklist - -The checklist must be established either at Project Plan Approved Gate or early in the project. -Templates are available in the /program/milestones/templates subdirectory. -The templates should be reviewed and adapted as seen fit for a particular project. - -Project specific checklists are then stored in the project repository. - -### Checklist Description - -Each checklist has a series of rows and columns, with rows containing checklist item to be reviewed, and columns for: - -Category -Item -Sign-off Criteria -Signed-off By -Sign-off Date -Exceptions/Waivers/Comments - -This format may be adapted for a project as required. - - -### Signing Off the Checklist - -Updating the Checklist can be done by any project member or OpenHW Staff member, who should coordinate with the Technical Project Leader or Project Manager. - -The "Signed-off By" field should be filled in the email address of the person verifying that the task has been done. -There is no quality metric associated with the sign-off. - -The "Signed-off Date", when filled in together with the "Signed-off By", verifies that the item has been signed off. - -The Checklist is updated by pull request. - - -### Establishing the Github Tag - -When a project has reached a satisfactory point, the Technical Project Leader or Project Manager for the project verifies that the Checklist(s) -have all been signed off or waived. He or she then creates a tag on the repository, which will also tag the Checklist. - - - -## Closing the Github Issue - -The tag should then be copied into the Project Milestone Issue and the Issue closed. +## OpenHW Group Project Milestone Process +The /milestone subdirectory contains the templates and checklist for OpenHW Group projects. + +The Project Milestone process described here is used by OpenHW members and staff to associate Github-tagged milestones with a set of checklists. +The checklist(s) when signed off, confirms that the established task list for the milestone has been completed. + + + +## Technical Milestones + +As per the OpenHW Project Management Framework, the set of project milestones is decided on a per-project basis at the Project Launch gate. +Each Project Milestone is associated with a Checklist(s). + +A Project Milestone typically signifies the completion of a project. +However, a Project Milestone could be used for intermediate checkpoints or releases as well. + +A core development would likely include an RTL Freeze milestone as a minimum. + + +## Process + +### Opening Github Issue + +At Project Launch, a Github issue is opened for each Project Milestone. +This issue(s) is closed when the Milestone(s) is reached. + +### Establishing the Checklist + +The checklist must be established either at Project Plan Approved Gate or early in the project. +Templates are available in the /program/milestones/templates subdirectory. +The templates should be reviewed and adapted as seen fit for a particular project. + +Project specific checklists are then stored in the project repository. + +### Checklist Description + +Each checklist has a series of rows and columns, with rows containing checklist item to be reviewed, and columns for: + +Category +Item +Sign-off Criteria +Signed-off By +Sign-off Date +Exceptions/Waivers/Comments + +This format may be adapted for a project as required. + + +### Signing Off the Checklist + +Updating the Checklist can be done by any project member or OpenHW Staff member, who should coordinate with the Technical Project Leader or Project Manager. + +The "Signed-off By" field should be filled in the email address of the person verifying that the task has been done. +There is no quality metric associated with the sign-off. + +The "Signed-off Date", when filled in together with the "Signed-off By", verifies that the item has been signed off. + +The Checklist is updated by pull request. + + +### Establishing the Github Tag + +When a project has reached a satisfactory point, the Technical Project Leader or Project Manager for the project verifies that the Checklist(s) +have all been signed off or waived. He or she then creates a tag on the repository, which will also tag the Checklist. + + + +## Closing the Github Issue + +The tag should then be copied into the Project Milestone Issue and the Issue closed. diff --git a/program/process/ProjectGatePlanning.xlsx b/process/ProjectGatePlanning.xlsx similarity index 100% rename from program/process/ProjectGatePlanning.xlsx rename to process/ProjectGatePlanning.xlsx diff --git a/program/process/Technical_Readiness_Level_(TRL).pdf b/process/Technical_Readiness_Level_(TRL).pdf similarity index 100% rename from program/process/Technical_Readiness_Level_(TRL).pdf rename to process/Technical_Readiness_Level_(TRL).pdf