openrisc: Define screen_info in kernel setup

README.openrisc

@@ -0,0 +1,15 @@
+Initramfs
+=========
+
+In order to have the initramfs built into your kernel you need to have the following
+options set:
+
+CONFIG_INITRAMFS_SOURCE="arch/or32/support/initramfs arch/or32/support/initramfs.devnodes"
+CONFIG_DEVTMPFS=y
+
+This builds the initramfs from the directory initramfs and adds some extra
+directories and device nodes from the file initramfs.
+
+There is not a hard dependency on devtmpfs, but it makes life easier and the initramfs
+is configured to use it!
+

TODO.openrisc

@@ -0,0 +1,5 @@
+LOAD_CURRENT_THREAD_INFO is not used anywhere
+
+Implement memcpy and memset (string.h)
+
+switch bootmem allocation over to memblock

arch/openrisc/Kconfig

@@ -22,9 +22,11 @@ config OPENRISC
 	select GENERIC_CLOCKEVENTS
 	select GENERIC_STRNCPY_FROM_USER
 	select GENERIC_STRNLEN_USER
+	select GENERIC_SMP_IDLE_THREAD
 	select MODULES_USE_ELF_RELA
 	select HAVE_DEBUG_STACKOVERFLOW
 	select OR1K_PIC
+	select OMPIC if SMP
 
 config MMU
 	def_bool y
@@ -47,6 +49,9 @@ config NO_IOPORT_MAP
 config TRACE_IRQFLAGS_SUPPORT
         def_bool y
 
+config WISHBONE_BUS_BIG_ENDIAN
+	def_bool y
+
 # For now, use generic checksum functions
 #These can be reimplemented in assembly later if so inclined
 config GENERIC_CSUM
@@ -98,8 +103,30 @@ config OPENRISC_HAVE_INST_DIV
 	default y
 	help
 	  Select this if your implementation has a hardware divide instruction
+
+config OPENRISC_HAVE_INST_LWA_SWA
+	bool "Have instruction l.lwa and l.swa"
+	help
+	  Select this if your implementation have l.lwa and l.swa atomic
+	  instructions.
+
 endmenu
 
+config NR_CPUS
+	int "Maximum number of CPUs (2-32)"
+	range 2 32
+	depends on SMP
+	default "2"
+
+config SMP
+	bool "Symmetric Multi-Processing support"
+	depends on OPENRISC_HAVE_INST_LWA_SWA
+	help
+	  This enables support for systems with more than one CPU. If you have
+	  a system with only one CPU, say N. If you have a system with more
+	  than one CPU, say Y.
+
+	  If you don't know what to do here, say N.
 
 source kernel/Kconfig.hz
 source kernel/Kconfig.preempt
@@ -118,6 +145,16 @@ config OPENRISC_NO_SPR_SR_DSX
 	  Say N here if you know that your OpenRISC processor has
 	  SPR_SR_DSX bit implemented. Say Y if you are unsure.
 
+config OPENRISC_HAVE_SHADOW_GPRS
+	bool "Support for shadow gpr files"
+	help
+	  Say Y here if your OpenRISC processor features shadowed
+	  register files. They will in such case be used as a
+	  scratch reg storage on exception entry.
+
+	  On SMP systems, this feature is mandatory.
+	  On a unicore system it's safe to say N here if you are unsure.
+
 config CMDLINE
         string "Default kernel command string"
         default ""

arch/openrisc/boot/dts/de0_nano.dts

@@ -0,0 +1,158 @@
+/dts-v1/;
+/ {
+	compatible = "opencores,de0_nano";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&pic>;
+
+	chosen {
+		bootargs = "console=uart,mmio,0x90000000,115200";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x00000000 0x02000000>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cpu@0 {
+			compatible = "opencores,or1200-rtlsvn481";
+			reg = <0>;
+			clock-frequency = <50000000>;
+		};
+	};
+
+	/*
+	 * OR1K PIC is built into CPU and accessed via special purpose
+	 * registers.  It is not addressable and, hence, has no 'reg'
+	 * property.
+	 */
+	pic: pic {
+		compatible = "opencores,or1k-pic";
+		#interrupt-cells = <1>;
+		interrupt-controller;
+	};
+
+	serial0: serial@90000000 {
+		compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
+		reg = <0x90000000 0x100>;
+		interrupts = <2>;
+		clock-frequency = <50000000>;
+	};
+
+	i2c0: ocores@a0000000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "opencores,i2c-ocores";
+		reg = <0xa0000000 0x8>;
+		interrupts = <10>;
+		clock-frequency = <50000000>;
+
+		reg-shift = <0>;	/* 8 bit registers */
+		reg-io-width = <1>;	/* 8 bit read/write */
+
+		adxl34x@1d {
+			compatible = "adxl34x";
+			reg = <0x1d>;
+			interrupts = <26>;
+		};
+		eeprom@50 {
+			compatible = "at24,24c02";
+			reg = <0x50>;
+			pagesize = <8>;
+		};
+	};
+
+	spi0: spi0@b0000000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "opencores,spi-simple";
+		reg = <0xb0000000 0x5>;
+
+		flash0: mtd@0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "spansion,s25sl064p";
+			reg = <0>;
+			spi-max-frequency = <40000000>;
+			m25p,fast-read;
+
+			partition@0 {
+				label = "FPGA image";
+				reg = <0x00000000 0x000b0000>;
+				read-only;
+			};
+			partition@b0000 {
+				label = "bootloader";
+				reg = <0x000b0000 0x00050000>;
+				read-only;
+			};
+			partition@100000 {
+				label = "free space";
+				reg = <0x00100000 0x00700000>;
+			};
+		};
+	};
+
+	spi1: spi1@b1000000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "opencores,spi-simple";
+		reg = <0xb1000000 0x5>;
+
+		adc@0 {
+			compatible = "adcxx,adcxx8s";
+			reg = <0>;
+			spi-max-frequency = <1000000>;
+		};
+	};
+
+	gpio0: gpio@91000000 {
+		compatible = "opencores,jbtrivial";
+		reg = <0x91000000 0x2>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		xlnx,data-offset = <0>;
+		xlnx,tri-offset = <1>;
+		xlnx,gpio-width = <8>;
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		heartbeat {
+			label = "Heartbeat";
+			gpios = <&gpio0 0 0x0>;
+			linux,default-trigger = "heartbeat";
+		};
+		led1 {
+			label = "led1";
+			gpios = <&gpio0 1 0>;
+		};
+		led2 {
+			label = "led2";
+			gpios = <&gpio0 2 0>;
+		};
+		led3 {
+			label = "led3";
+			gpios = <&gpio0 3 0>;
+		};
+		led4 {
+			label = "led4";
+			gpios = <&gpio0 4 0>;
+		};
+		led5 {
+			label = "led5";
+			gpios = <&gpio0 5 0>;
+		};
+		led6 {
+			label = "led6";
+			gpios = <&gpio0 6 0>;
+		};
+		led7 {
+			label = "led7";
+			gpios = <&gpio0 7 0>;
+		};
+	};
+};

arch/openrisc/boot/dts/simple_smp.dts

@@ -0,0 +1,74 @@
+/dts-v1/;
+/ {
+	compatible = "opencores,or1ksim";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&pic>;
+
+	chosen {
+		bootargs = "console=uart,mmio,0x90000000,115200";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x00000000 0x02000000>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cpu@0 {
+			compatible = "opencores,or1200-rtlsvn481";
+			reg = <0>;
+			clock-frequency = <50000000>;
+		};
+		cpu@1 {
+			compatible = "opencores,or1200-rtlsvn481";
+			reg = <1>;
+			clock-frequency = <50000000>;
+		};
+	};
+
+	ompic: ompic {
+		compatible = "ompic";
+		reg = <0x98000000 0x100>;
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		interrupts = <1>;
+	};
+
+	/*
+	 * OR1K PIC is built into CPU and accessed via special purpose
+	 * registers.  It is not addressable and, hence, has no 'reg'
+	 * property.
+	 */
+	pic: pic {
+		compatible = "opencores,or1k-pic";
+		#interrupt-cells = <1>;
+		interrupt-controller;
+	};
+
+	serial0: serial@90000000 {
+		compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
+		reg = <0x90000000 0x100>;
+		interrupts = <2>;
+		clock-frequency = <50000000>;
+	};
+
+/*
+	enet0: ethoc@92000000 {
+		compatible = "opencores,ethmac-rtlsvn338";
+		reg = <0x92000000 0x100>;
+		interrupts = <4>;
+	};
+        ata@9e000000  {
+                compatible = "ata-generic";
+                reg = <0x9e000040 0x30
+                       0x9e000078 0x10>;
+                pio-mode = <4>;
+                reg-shift = <2>;
+                interrupts = <15>;
+        };
+*/
+
+};