A long tick after the commit directive does not continue to fetch

[zjh070805]

I ran 100 add instructions using se.py, and the code is as follows:"addi x10, x6, 100\n\t"
When tracing their addresses, it is found that every 16 instructions are in a group, after the full commit, there will be about 47,500 ticks without any operation, debug as follows:
649500: system.cpu.fetch: Running stage. 649500: system.cpu.fetch: There are no more threads available to fetch from. 649500: system.cpu.fetch: [tid:0] Fetch is waiting cache response! 649500: system.cpu.decode: Processing [tid:0] 649500: system.cpu.decode: [tid:0] Not blocked, so attempting to run stage. 649500: system.cpu.decode: [tid:0] Nothing to do, breaking out early. 649500: system.cpu.rename: Processing [tid:0] 649500: system.cpu.rename: [tid:0] Free IQ: 64, Free ROB: 192, Free LQ: 32, Free SQ: 32, FreeRM 1(223 224 255 510 31 1 0) 649500: system.cpu.rename: [tid:0] 0 instructions not yet in ROB 649500: system.cpu.rename: calcFreeLQEntries: free lqEntries: 32, loadsInProgress: 0, loads dispatchedToLQ: 0 649500: system.cpu.rename: [tid:0] Not blocked, so attempting to run stage. 649500: system.cpu.rename: [tid:0] Nothing to do, breaking out early. 649500: system.cpu.iew: Issue: Processing [tid:0] 649500: system.cpu.iew: [tid:0] Not blocked, so attempting to run dispatch. 649500: system.cpu.iew: Processing [tid:0] 649500: system.cpu.iew: [tid:0], Dispatch dispatched 0 instructions. 649500: system.cpu.iew: IQ has 64 free entries (Can schedule: 0). LQ has 32 free entries. SQ has 32 free entries. 649500: system.cpu.commit: Getting instructions from Rename stage. 649500: system.cpu.commit: Trying to commit instructions in the ROB. 649500: system.cpu.commit: [tid:0] ROB has 0 insts & 192 free entries. 650000: system.cpu.fetch: Running stage. 650000: system.cpu.fetch: There are no more threads available to fetch from. 650000: system.cpu.fetch: [tid:0] Fetch is waiting cache response! 650000: system.cpu.decode: Processing [tid:0] 650000: system.cpu.decode: [tid:0] Not blocked, so attempting to run stage. 650000: system.cpu.decode: [tid:0] Nothing to do, breaking out early. 650000: system.cpu.rename: Processing [tid:0] 650000: system.cpu.rename: [tid:0] Free IQ: 64, Free ROB: 192, Free LQ: 32, Free SQ: 32, FreeRM 1(223 224 255 510 31 1 0) 650000: system.cpu.rename: [tid:0] 0 instructions not yet in ROB 650000: system.cpu.rename: calcFreeLQEntries: free lqEntries: 32, loadsInProgress: 0, loads dispatchedToLQ: 0 650000: system.cpu.rename: [tid:0] Not blocked, so attempting to run stage. 650000: system.cpu.rename: [tid:0] Nothing to do, breaking out early. 650000: system.cpu.iew: Issue: Processing [tid:0] 650000: system.cpu.iew: [tid:0] Not blocked, so attempting to run dispatch. 650000: system.cpu.iew: Processing [tid:0] 650000: system.cpu.iew: [tid:0], Dispatch dispatched 0 instructions. 650000: system.cpu.iew: IQ has 64 free entries (Can schedule: 0). LQ has 32 free entries. SQ has 32 free entries. 650000: system.cpu.commit: Getting instructions from Rename stage. 650000: system.cpu.commit: Trying to commit instructions in the ROB. 650000: system.cpu.commit: [tid:0] ROB has 0 insts & 192 free entries. 692000: system.cpu.fetch: [tid:0] Waking up from cache miss. 692000: system.cpu.fetch: Running stage. 692000: system.cpu.fetch: Attempting to fetch from [tid:0] 692000: system.cpu.fetch: [tid:0] Icache miss is complete. 692000: system.cpu.fetch: [tid:0] Adding instructions to queue to decode. 692000: system.cpu.decoder: Requesting bytes 0xb3038082 from address 0x1035c 692000: system.cpu.decoder: Requesting bytes 0x711d7581 from address 0x10360 692000: system.cpu.decoder: Decoding instruction 0x7581b303 at address 0x1035e 692000: system.cpu.decoder: Decode: Decoded ld instruction: 0x400000007581b303 692000: system.cpu.fetch: [tid:0] Instruction PC (0x1035e=>0x10362).(0=>1) created [sn:552]. 692000: system.cpu.fetch: [tid:0] Instruction is: ld t1, 1880(gp) 692000: system.cpu.fetch: [tid:0] Fetch queue entry created (1/32).
What is the reason for this?

Later I found the following configuration in the config.ini file of m5out:
[system.mem_ctrls] type=MemCtrl children=dram power_state clk_domain=system.clk_domain command_window=10000 disable_sanity_check=false dram=system.mem_ctrls.dram eventq_index=0 mem_sched_policy=frfcfs min_reads_per_switch=16 min_writes_per_switch=16 power_model= power_state=system.mem_ctrls.power_state qos_policy=Null qos_priorities=1 qos_priority_escalation=false qos_q_policy=fifo qos_requestors= qos_syncro_scheduler=false qos_turnaround_policy=Null static_backend_latency=10000 static_frontend_latency=10000 system=system write_high_thresh_perc=85 write_low_thresh_perc=50 port=system.membus.mem_side_ports[0]

My guess is probably "static_backend_latency=10000.
static_frontend_latency=10000 "impact, how can I modify these two value validation guesses